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alt_uart.h @ 2afb22b

Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

The make preinstall step itself needs time and disk space.

Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.

There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.

The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.

An introduction of a new build system is difficult.

Include paths specified by the -B option are system headers. This may suppress warnings.

The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

cpukit/include

cpukit/score/cpu/@RTEMS_CPU@/include

cpukit/libnetworking

The new BSP include directories are:

bsps/include

bsps/@RTEMS_CPU@/include

bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

Property mode set to 100644

File size: 211.2 KB

Line
1	/*******************************************************************************
2	* *
3	* Copyright 2013 Altera Corporation. All Rights Reserved. *
4	* *
5	* Redistribution and use in source and binary forms, with or without *
6	* modification, are permitted provided that the following conditions are met: *
7	* *
8	* 1. Redistributions of source code must retain the above copyright notice, *
9	* this list of conditions and the following disclaimer. *
10	* *
11	* 2. Redistributions in binary form must reproduce the above copyright notice, *
12	* this list of conditions and the following disclaimer in the documentation *
13	* and/or other materials provided with the distribution. *
14	* *
15	* 3. The name of the author may not be used to endorse or promote products *
16	* derived from this software without specific prior written permission. *
17	* *
18	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
20	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
21	* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
22	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
23	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
24	* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
25	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
26	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
27	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
28	* *
29	*******************************************************************************/
30
31	/* Altera - ALT_UART */
32
33	#ifndef __ALTERA_ALT_UART_H__
34	#define __ALTERA_ALT_UART_H__
35
36	#ifdef __cplusplus
37	extern "C"
38	{
39	#endif /* __cplusplus */
40
41	/*
42	* Component : UART Module - ALT_UART
43	* UART Module
44	*
45	* Registers in the UART module
46	*
47	*/
48	/*
49	* Register : Rx Buffer, Tx Holding, and Divisor Latch Low - rbr_thr_dll
50	*
51	* This is a multi-function register. This register holds receives and transmit
52	* data and controls the least-signficant 8 bits of the baud rate divisor.
53	*
54	* Register Layout
55	*
56	* Bits \| Access \| Reset \| Description
57	* :-------\|:-------\|:------\|:------------
58	* [7:0] \| RW \| 0x0 \| Value
59	* [31:8] \| ??? \| 0x0 \| UNDEFINED
60	*
61	*/
62	/*
63	* Field : Value - value
64	*
65	* Receive Buffer Register:
66	*
67	* This register contains the data byte received on the serial input port
68	* (uart_rxd). The data in this register is valid only if the Data Ready ( bit [0]
69	* in the Line Status Register(LSR)) is set to 1. If FIFOs are disabled(bit[0] of
70	* Register FCR is set to 0) the data in the RBR must be read before the next data
71	* arrives, otherwise it will be overwritten, resulting in an overrun error. If
72	* FIFOs are enabled(bit [0] of Register FCR is set to 1) this register accesses
73	* the head of the receive FIFO. If the receive FIFO is full, and this register is
74	* not read before the next data character arrives, then the data already in the
75	* FIFO will be preserved but any incoming data will be lost. An overrun error will
76	* also occur.
77	*
78	* Transmit Holding Register:
79	*
80	* This register contains data to be transmitted on the serial output port. Data
81	* should only be written to the THR when the THR Empty bit [5] of the LSR Register
82	* is set to 1. If FIFOs are disabled (bit [0] of Register FCR) is set to 0 and
83	* THRE is set to 1, writing a single character to the THR clears the THRE. Any
84	* additional writes to the THR before the THRE is set again causes the THR data to
85	* be overwritten. If FIFO's are enabled bit [0] of Register FCR is set to 1 and
86	* THRE is set up to 128 characters of data may be written to the THR before the
87	* FIFO is full. Any attempt to write data when the FIFO is full results in the
88	* write data being lost.
89	*
90	* Divisor Latch Low:
91	*
92	* This register makes up the lower 8-bits of a 16-bit, Read/write, Divisor Latch
93	* register that contains the baud rate divisor for the UART. This register may
94	* only be accessed when the DLAB bit [7] of the LCR Register is set to 1. The
95	* output baud rate is equal to the serial clock l4_sp_clk frequency divided by
96	* sixteen times the value of the baud rate divisor, as follows:
97	*
98	* baud rate = (serial clock freq) / (16 * divisor)
99	*
100	* Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud
101	* clock is disabled and no serial communications will occur. Also, once the DLL is
102	* set, at least 8 l4_sp_clk clock cycles should be allowed to pass before
103	* transmitting or receiving data.
104	*
105	* Field Access Macros:
106	*
107	*/
108	/* The Least Significant Bit (LSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */
109	#define ALT_UART_RBR_THR_DLL_VALUE_LSB 0
110	/* The Most Significant Bit (MSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */
111	#define ALT_UART_RBR_THR_DLL_VALUE_MSB 7
112	/* The width in bits of the ALT_UART_RBR_THR_DLL_VALUE register field. */
113	#define ALT_UART_RBR_THR_DLL_VALUE_WIDTH 8
114	/* The mask used to set the ALT_UART_RBR_THR_DLL_VALUE register field value. */
115	#define ALT_UART_RBR_THR_DLL_VALUE_SET_MSK 0x000000ff
116	/* The mask used to clear the ALT_UART_RBR_THR_DLL_VALUE register field value. */
117	#define ALT_UART_RBR_THR_DLL_VALUE_CLR_MSK 0xffffff00
118	/* The reset value of the ALT_UART_RBR_THR_DLL_VALUE register field. */
119	#define ALT_UART_RBR_THR_DLL_VALUE_RESET 0x0
120	/* Extracts the ALT_UART_RBR_THR_DLL_VALUE field value from a register. */
121	#define ALT_UART_RBR_THR_DLL_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
122	/* Produces a ALT_UART_RBR_THR_DLL_VALUE register field value suitable for setting the register. */
123	#define ALT_UART_RBR_THR_DLL_VALUE_SET(value) (((value) << 0) & 0x000000ff)
124
125	#ifndef __ASSEMBLY__
126	/*
127	* WARNING: The C register and register group struct declarations are provided for
128	* convenience and illustrative purposes. They should, however, be used with
129	* caution as the C language standard provides no guarantees about the alignment or
130	* atomicity of device memory accesses. The recommended practice for writing
131	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
132	* alt_write_word() functions.
133	*
134	* The struct declaration for register ALT_UART_RBR_THR_DLL.
135	*/
136	struct ALT_UART_RBR_THR_DLL_s
137	{
138	uint32_t value : 8; /* Value */
139	uint32_t : 24; /* UNDEFINED */
140	};
141
142	/* The typedef declaration for register ALT_UART_RBR_THR_DLL. */
143	typedef volatile struct ALT_UART_RBR_THR_DLL_s ALT_UART_RBR_THR_DLL_t;
144	#endif /* __ASSEMBLY__ */
145
146	/* The byte offset of the ALT_UART_RBR_THR_DLL register from the beginning of the component. */
147	#define ALT_UART_RBR_THR_DLL_OFST 0x0
148	/* The address of the ALT_UART_RBR_THR_DLL register. */
149	#define ALT_UART_RBR_THR_DLL_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_RBR_THR_DLL_OFST))
150
151	/*
152	* Register : Interrupt Enable and Divisor Latch High - ier_dlh
153	*
154	* This is a multi-function register. This register enables/disables receive and
155	* transmit interrupts and also controls the most-significant 8-bits of the baud
156	* rate divisor.
157	*
158	* Divisor Latch High Register:
159	*
160	* This register is accessed when the DLAB bit [7] of the LCR Register is set to
161	* 1.Bits[7:0] contain the high order 8-bits of the baud rate divisor.The output
162	* baud rate is equal to the serial clock l4_sp_clk frequency divided by sixteen
163	* times the value of the baud rate divisor, as follows:
164	*
165	* baud rate = (serial clock freq) / (16 * divisor):
166	*
167	* Note that with the Divisor Latch Registers (DLLand DLH) set to zero, the baud
168	* clock is disabled and no serial communications will occur. Also, once the DLL is
169	* set, at least 8 l4_sp_clk clock cycles should be allowed to pass before
170	* transmitting or receiving data.
171	*
172	* Interrupt Enable Register:
173	*
174	* This register may only be accessed when the DLAB bit [7] of the LCR Register is
175	* set to 0.Allows control of the Interrupt Enables for transmit and receive
176	* functions.
177	*
178	* Register Layout
179	*
180	* Bits \| Access \| Reset \| Description
181	* :-------\|:-------\|:------\|:--------------------------------------------
182	* [0] \| RW \| 0x0 \| DLH[0] and Receive Data Interrupt Enable
183	* [1] \| RW \| 0x0 \| DLH[1] and Transmit Data Interrupt Control
184	* [2] \| RW \| 0x0 \| DLH[2] and Enable Receiver Line Status
185	* [3] \| RW \| 0x0 \| DLH[3] and Enable Modem Status Interrupt
186	* [4] \| RW \| 0x0 \| DLH[4]
187	* [5] \| RW \| 0x0 \| DLH[5]
188	* [6] \| RW \| 0x0 \| DLH[6]
189	* [7] \| RW \| 0x0 \| DLH[7] and PTIME THRE Interrupt Mode Enable
190	* [31:8] \| ??? \| 0x0 \| UNDEFINED
191	*
192	*/
193	/*
194	* Field : DLH[0] and Receive Data Interrupt Enable - erbfi_dlh0
195	*
196	* Divisor Latch High Register:
197	*
198	* Bit 0 of DLH value.
199	*
200	* Interrupt Enable Register:
201	*
202	* Used to enable/disable the generation of the Receive Data Available Interrupt
203	* and the Character Timeout Interrupt(if FIFO's enabled). These are the second
204	* highest priority interrupts.
205	*
206	* Field Enumeration Values:
207	*
208	* Enum \| Value \| Description
209	* :-----------------------------------\|:------\|:------------------
210	* ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD \| 0x0 \| Interrupt Disable
211	* ALT_UART_IER_DLH_ERBFI_DLH0_E_END \| 0x1 \| Interrupt Enable
212	*
213	* Field Access Macros:
214	*
215	*/
216	/*
217	* Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0
218	*
219	* Interrupt Disable
220	*/
221	#define ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD 0x0
222	/*
223	* Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0
224	*
225	* Interrupt Enable
226	*/
227	#define ALT_UART_IER_DLH_ERBFI_DLH0_E_END 0x1
228
229	/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
230	#define ALT_UART_IER_DLH_ERBFI_DLH0_LSB 0
231	/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
232	#define ALT_UART_IER_DLH_ERBFI_DLH0_MSB 0
233	/* The width in bits of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
234	#define ALT_UART_IER_DLH_ERBFI_DLH0_WIDTH 1
235	/* The mask used to set the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */
236	#define ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK 0x00000001
237	/* The mask used to clear the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */
238	#define ALT_UART_IER_DLH_ERBFI_DLH0_CLR_MSK 0xfffffffe
239	/* The reset value of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
240	#define ALT_UART_IER_DLH_ERBFI_DLH0_RESET 0x0
241	/* Extracts the ALT_UART_IER_DLH_ERBFI_DLH0 field value from a register. */
242	#define ALT_UART_IER_DLH_ERBFI_DLH0_GET(value) (((value) & 0x00000001) >> 0)
243	/* Produces a ALT_UART_IER_DLH_ERBFI_DLH0 register field value suitable for setting the register. */
244	#define ALT_UART_IER_DLH_ERBFI_DLH0_SET(value) (((value) << 0) & 0x00000001)
245
246	/*
247	* Field : DLH[1] and Transmit Data Interrupt Control - etbei_dlhl
248	*
249	* Divisor Latch High Register:
250	*
251	* Bit 1 of DLH value.
252	*
253	* Interrupt Enable Register:
254	*
255	* Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable
256	* the generation of Transmitter Holding Register Empty Interrupt. This is the
257	* third highest priority interrupt.
258	*
259	* Field Enumeration Values:
260	*
261	* Enum \| Value \| Description
262	* :-----------------------------------\|:------\|:------------
263	* ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD \| 0x0 \| Tx disable
264	* ALT_UART_IER_DLH_ETBEI_DLHL_E_END \| 0x1 \| Tx enable
265	*
266	* Field Access Macros:
267	*
268	*/
269	/*
270	* Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL
271	*
272	* Tx disable
273	*/
274	#define ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD 0x0
275	/*
276	* Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL
277	*
278	* Tx enable
279	*/
280	#define ALT_UART_IER_DLH_ETBEI_DLHL_E_END 0x1
281
282	/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
283	#define ALT_UART_IER_DLH_ETBEI_DLHL_LSB 1
284	/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
285	#define ALT_UART_IER_DLH_ETBEI_DLHL_MSB 1
286	/* The width in bits of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
287	#define ALT_UART_IER_DLH_ETBEI_DLHL_WIDTH 1
288	/* The mask used to set the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */
289	#define ALT_UART_IER_DLH_ETBEI_DLHL_SET_MSK 0x00000002
290	/* The mask used to clear the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */
291	#define ALT_UART_IER_DLH_ETBEI_DLHL_CLR_MSK 0xfffffffd
292	/* The reset value of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
293	#define ALT_UART_IER_DLH_ETBEI_DLHL_RESET 0x0
294	/* Extracts the ALT_UART_IER_DLH_ETBEI_DLHL field value from a register. */
295	#define ALT_UART_IER_DLH_ETBEI_DLHL_GET(value) (((value) & 0x00000002) >> 1)
296	/* Produces a ALT_UART_IER_DLH_ETBEI_DLHL register field value suitable for setting the register. */
297	#define ALT_UART_IER_DLH_ETBEI_DLHL_SET(value) (((value) << 1) & 0x00000002)
298
299	/*
300	* Field : DLH[2] and Enable Receiver Line Status - elsi_dhl2
301	*
302	* Divisor Latch High Register:
303	*
304	* Bit 2 of DLH value.
305	*
306	* Interrupt Enable Register:
307	*
308	* This is used to enable/disable the generation of Receiver Line Status Interrupt.
309	* This is the highest priority interrupt.
310	*
311	* Field Enumeration Values:
312	*
313	* Enum \| Value \| Description
314	* :----------------------------------\|:------\|:----------------------------
315	* ALT_UART_IER_DLH_ELSI_DHL2_E_DISD \| 0x0 \| Disable interrupt line stat
316	* ALT_UART_IER_DLH_ELSI_DHL2_E_END \| 0x1 \| Enable interrupt line stat
317	*
318	* Field Access Macros:
319	*
320	*/
321	/*
322	* Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2
323	*
324	* Disable interrupt line stat
325	*/
326	#define ALT_UART_IER_DLH_ELSI_DHL2_E_DISD 0x0
327	/*
328	* Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2
329	*
330	* Enable interrupt line stat
331	*/
332	#define ALT_UART_IER_DLH_ELSI_DHL2_E_END 0x1
333
334	/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
335	#define ALT_UART_IER_DLH_ELSI_DHL2_LSB 2
336	/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
337	#define ALT_UART_IER_DLH_ELSI_DHL2_MSB 2
338	/* The width in bits of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
339	#define ALT_UART_IER_DLH_ELSI_DHL2_WIDTH 1
340	/* The mask used to set the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */
341	#define ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK 0x00000004
342	/* The mask used to clear the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */
343	#define ALT_UART_IER_DLH_ELSI_DHL2_CLR_MSK 0xfffffffb
344	/* The reset value of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
345	#define ALT_UART_IER_DLH_ELSI_DHL2_RESET 0x0
346	/* Extracts the ALT_UART_IER_DLH_ELSI_DHL2 field value from a register. */
347	#define ALT_UART_IER_DLH_ELSI_DHL2_GET(value) (((value) & 0x00000004) >> 2)
348	/* Produces a ALT_UART_IER_DLH_ELSI_DHL2 register field value suitable for setting the register. */
349	#define ALT_UART_IER_DLH_ELSI_DHL2_SET(value) (((value) << 2) & 0x00000004)
350
351	/*
352	* Field : DLH[3] and Enable Modem Status Interrupt - edssi_dhl3
353	*
354	* Divisor Latch High Register:
355	*
356	* Bit 3 of DLH value.
357	*
358	* Interrupt Enable Register:
359	*
360	* This is used to enable/disable the generation of Modem Status Interrupts. This
361	* is the fourth highest priority interrupt.
362	*
363	* Field Enumeration Values:
364	*
365	* Enum \| Value \| Description
366	* :-----------------------------------\|:------\|:-------------------------------
367	* ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD \| 0x0 \| disable modem status interrupt
368	* ALT_UART_IER_DLH_EDSSI_DHL3_E_END \| 0x1 \| enable modem status interrupt
369	*
370	* Field Access Macros:
371	*
372	*/
373	/*
374	* Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3
375	*
376	* disable modem status interrupt
377	*/
378	#define ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD 0x0
379	/*
380	* Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3
381	*
382	* enable modem status interrupt
383	*/
384	#define ALT_UART_IER_DLH_EDSSI_DHL3_E_END 0x1
385
386	/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
387	#define ALT_UART_IER_DLH_EDSSI_DHL3_LSB 3
388	/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
389	#define ALT_UART_IER_DLH_EDSSI_DHL3_MSB 3
390	/* The width in bits of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
391	#define ALT_UART_IER_DLH_EDSSI_DHL3_WIDTH 1
392	/* The mask used to set the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */
393	#define ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK 0x00000008
394	/* The mask used to clear the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */
395	#define ALT_UART_IER_DLH_EDSSI_DHL3_CLR_MSK 0xfffffff7
396	/* The reset value of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
397	#define ALT_UART_IER_DLH_EDSSI_DHL3_RESET 0x0
398	/* Extracts the ALT_UART_IER_DLH_EDSSI_DHL3 field value from a register. */
399	#define ALT_UART_IER_DLH_EDSSI_DHL3_GET(value) (((value) & 0x00000008) >> 3)
400	/* Produces a ALT_UART_IER_DLH_EDSSI_DHL3 register field value suitable for setting the register. */
401	#define ALT_UART_IER_DLH_EDSSI_DHL3_SET(value) (((value) << 3) & 0x00000008)
402
403	/*
404	* Field : DLH[4] - dlh4
405	*
406	* Bit 4 of DLH value.
407	*
408	* Field Access Macros:
409	*
410	*/
411	/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH4 register field. */
412	#define ALT_UART_IER_DLH_DLH4_LSB 4
413	/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH4 register field. */
414	#define ALT_UART_IER_DLH_DLH4_MSB 4
415	/* The width in bits of the ALT_UART_IER_DLH_DLH4 register field. */
416	#define ALT_UART_IER_DLH_DLH4_WIDTH 1
417	/* The mask used to set the ALT_UART_IER_DLH_DLH4 register field value. */
418	#define ALT_UART_IER_DLH_DLH4_SET_MSK 0x00000010
419	/* The mask used to clear the ALT_UART_IER_DLH_DLH4 register field value. */
420	#define ALT_UART_IER_DLH_DLH4_CLR_MSK 0xffffffef
421	/* The reset value of the ALT_UART_IER_DLH_DLH4 register field. */
422	#define ALT_UART_IER_DLH_DLH4_RESET 0x0
423	/* Extracts the ALT_UART_IER_DLH_DLH4 field value from a register. */
424	#define ALT_UART_IER_DLH_DLH4_GET(value) (((value) & 0x00000010) >> 4)
425	/* Produces a ALT_UART_IER_DLH_DLH4 register field value suitable for setting the register. */
426	#define ALT_UART_IER_DLH_DLH4_SET(value) (((value) << 4) & 0x00000010)
427
428	/*
429	* Field : DLH[5] - dlh5
430	*
431	* Bit 5 of DLH value.
432	*
433	* Field Access Macros:
434	*
435	*/
436	/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH5 register field. */
437	#define ALT_UART_IER_DLH_DLH5_LSB 5
438	/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH5 register field. */
439	#define ALT_UART_IER_DLH_DLH5_MSB 5
440	/* The width in bits of the ALT_UART_IER_DLH_DLH5 register field. */
441	#define ALT_UART_IER_DLH_DLH5_WIDTH 1
442	/* The mask used to set the ALT_UART_IER_DLH_DLH5 register field value. */
443	#define ALT_UART_IER_DLH_DLH5_SET_MSK 0x00000020
444	/* The mask used to clear the ALT_UART_IER_DLH_DLH5 register field value. */
445	#define ALT_UART_IER_DLH_DLH5_CLR_MSK 0xffffffdf
446	/* The reset value of the ALT_UART_IER_DLH_DLH5 register field. */
447	#define ALT_UART_IER_DLH_DLH5_RESET 0x0
448	/* Extracts the ALT_UART_IER_DLH_DLH5 field value from a register. */
449	#define ALT_UART_IER_DLH_DLH5_GET(value) (((value) & 0x00000020) >> 5)
450	/* Produces a ALT_UART_IER_DLH_DLH5 register field value suitable for setting the register. */
451	#define ALT_UART_IER_DLH_DLH5_SET(value) (((value) << 5) & 0x00000020)
452
453	/*
454	* Field : DLH[6] - dlh6
455	*
456	* Bit 6 of DLH value.
457	*
458	* Field Access Macros:
459	*
460	*/
461	/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH6 register field. */
462	#define ALT_UART_IER_DLH_DLH6_LSB 6
463	/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH6 register field. */
464	#define ALT_UART_IER_DLH_DLH6_MSB 6
465	/* The width in bits of the ALT_UART_IER_DLH_DLH6 register field. */
466	#define ALT_UART_IER_DLH_DLH6_WIDTH 1
467	/* The mask used to set the ALT_UART_IER_DLH_DLH6 register field value. */
468	#define ALT_UART_IER_DLH_DLH6_SET_MSK 0x00000040
469	/* The mask used to clear the ALT_UART_IER_DLH_DLH6 register field value. */
470	#define ALT_UART_IER_DLH_DLH6_CLR_MSK 0xffffffbf
471	/* The reset value of the ALT_UART_IER_DLH_DLH6 register field. */
472	#define ALT_UART_IER_DLH_DLH6_RESET 0x0
473	/* Extracts the ALT_UART_IER_DLH_DLH6 field value from a register. */
474	#define ALT_UART_IER_DLH_DLH6_GET(value) (((value) & 0x00000040) >> 6)
475	/* Produces a ALT_UART_IER_DLH_DLH6 register field value suitable for setting the register. */
476	#define ALT_UART_IER_DLH_DLH6_SET(value) (((value) << 6) & 0x00000040)
477
478	/*
479	* Field : DLH[7] and PTIME THRE Interrupt Mode Enable - ptime_dlh7
480	*
481	* Divisor Latch High Register:
482	*
483	* Bit 7 of DLH value.
484	*
485	* Interrupt Enable Register:
486	*
487	* This is used to enable/disable the generation of THRE Interrupt.
488	*
489	* Field Enumeration Values:
490	*
491	* Enum \| Value \| Description
492	* :-----------------------------------\|:------\|:------------------------------------
493	* ALT_UART_IER_DLH_PTIME_DLH7_E_DISD \| 0x0 \| disable tx-hold-reg-empty interrupt
494	* ALT_UART_IER_DLH_PTIME_DLH7_E_END \| 0x1 \| enable tx-hold-reg-empty interrupt
495	*
496	* Field Access Macros:
497	*
498	*/
499	/*
500	* Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7
501	*
502	* disable tx-hold-reg-empty interrupt
503	*/
504	#define ALT_UART_IER_DLH_PTIME_DLH7_E_DISD 0x0
505	/*
506	* Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7
507	*
508	* enable tx-hold-reg-empty interrupt
509	*/
510	#define ALT_UART_IER_DLH_PTIME_DLH7_E_END 0x1
511
512	/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
513	#define ALT_UART_IER_DLH_PTIME_DLH7_LSB 7
514	/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
515	#define ALT_UART_IER_DLH_PTIME_DLH7_MSB 7
516	/* The width in bits of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
517	#define ALT_UART_IER_DLH_PTIME_DLH7_WIDTH 1
518	/* The mask used to set the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */
519	#define ALT_UART_IER_DLH_PTIME_DLH7_SET_MSK 0x00000080
520	/* The mask used to clear the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */
521	#define ALT_UART_IER_DLH_PTIME_DLH7_CLR_MSK 0xffffff7f
522	/* The reset value of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
523	#define ALT_UART_IER_DLH_PTIME_DLH7_RESET 0x0
524	/* Extracts the ALT_UART_IER_DLH_PTIME_DLH7 field value from a register. */
525	#define ALT_UART_IER_DLH_PTIME_DLH7_GET(value) (((value) & 0x00000080) >> 7)
526	/* Produces a ALT_UART_IER_DLH_PTIME_DLH7 register field value suitable for setting the register. */
527	#define ALT_UART_IER_DLH_PTIME_DLH7_SET(value) (((value) << 7) & 0x00000080)
528
529	#ifndef __ASSEMBLY__
530	/*
531	* WARNING: The C register and register group struct declarations are provided for
532	* convenience and illustrative purposes. They should, however, be used with
533	* caution as the C language standard provides no guarantees about the alignment or
534	* atomicity of device memory accesses. The recommended practice for writing
535	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
536	* alt_write_word() functions.
537	*
538	* The struct declaration for register ALT_UART_IER_DLH.
539	*/
540	struct ALT_UART_IER_DLH_s
541	{
542	uint32_t erbfi_dlh0 : 1; /* DLH[0] and Receive Data Interrupt Enable */
543	uint32_t etbei_dlhl : 1; /* DLH[1] and Transmit Data Interrupt Control */
544	uint32_t elsi_dhl2 : 1; /* DLH[2] and Enable Receiver Line Status */
545	uint32_t edssi_dhl3 : 1; /* DLH[3] and Enable Modem Status Interrupt */
546	uint32_t dlh4 : 1; /* DLH[4] */
547	uint32_t dlh5 : 1; /* DLH[5] */
548	uint32_t dlh6 : 1; /* DLH[6] */
549	uint32_t ptime_dlh7 : 1; /* DLH[7] and PTIME THRE Interrupt Mode Enable */
550	uint32_t : 24; /* UNDEFINED */
551	};
552
553	/* The typedef declaration for register ALT_UART_IER_DLH. */
554	typedef volatile struct ALT_UART_IER_DLH_s ALT_UART_IER_DLH_t;
555	#endif /* __ASSEMBLY__ */
556
557	/* The byte offset of the ALT_UART_IER_DLH register from the beginning of the component. */
558	#define ALT_UART_IER_DLH_OFST 0x4
559	/* The address of the ALT_UART_IER_DLH register. */
560	#define ALT_UART_IER_DLH_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_IER_DLH_OFST))
561
562	/*
563	* Register : Interrupt Identity Register (when read) - iir
564	*
565	* Returns interrupt identification and FIFO enable/disable when read.
566	*
567	* Register Layout
568	*
569	* Bits \| Access \| Reset \| Description
570	* :-------\|:-------\|:------\|:-------------
571	* [3:0] \| R \| 0x1 \| Interrupt ID
572	* [5:4] \| ??? \| 0x0 \| UNDEFINED
573	* [7:6] \| R \| 0x0 \| FIFO Enabled
574	* [31:8] \| ??? \| 0x0 \| UNDEFINED
575	*
576	*/
577	/*
578	* Field : Interrupt ID - id
579	*
580	* This indicates the highest priority pending interrupt.
581	*
582	* Field Enumeration Values:
583	*
584	* Enum \| Value \| Description
585	* :---------------------------------\|:------\|:-----------------------
586	* ALT_UART_IIR_ID_E_MODMSTAT \| 0x0 \| Modem status
587	* ALT_UART_IIR_ID_E_NOINTRPENDING \| 0x1 \| No Interrupt pending
588	* ALT_UART_IIR_ID_E_THREMPTY \| 0x2 \| THR empty
589	* ALT_UART_IIR_ID_E_RXDATAVAILABLE \| 0x4 \| Receive data available
590	* ALT_UART_IIR_ID_E_RXLINESTAT \| 0x6 \| Receive line status
591	* ALT_UART_IIR_ID_E_CHARTMO \| 0xc \| Character timeout
592	*
593	* Field Access Macros:
594	*
595	*/
596	/*
597	* Enumerated value for register field ALT_UART_IIR_ID
598	*
599	* Modem status
600	*/
601	#define ALT_UART_IIR_ID_E_MODMSTAT 0x0
602	/*
603	* Enumerated value for register field ALT_UART_IIR_ID
604	*
605	* No Interrupt pending
606	*/
607	#define ALT_UART_IIR_ID_E_NOINTRPENDING 0x1
608	/*
609	* Enumerated value for register field ALT_UART_IIR_ID
610	*
611	* THR empty
612	*/
613	#define ALT_UART_IIR_ID_E_THREMPTY 0x2
614	/*
615	* Enumerated value for register field ALT_UART_IIR_ID
616	*
617	* Receive data available
618	*/
619	#define ALT_UART_IIR_ID_E_RXDATAVAILABLE 0x4
620	/*
621	* Enumerated value for register field ALT_UART_IIR_ID
622	*
623	* Receive line status
624	*/
625	#define ALT_UART_IIR_ID_E_RXLINESTAT 0x6
626	/*
627	* Enumerated value for register field ALT_UART_IIR_ID
628	*
629	* Character timeout
630	*/
631	#define ALT_UART_IIR_ID_E_CHARTMO 0xc
632
633	/* The Least Significant Bit (LSB) position of the ALT_UART_IIR_ID register field. */
634	#define ALT_UART_IIR_ID_LSB 0
635	/* The Most Significant Bit (MSB) position of the ALT_UART_IIR_ID register field. */
636	#define ALT_UART_IIR_ID_MSB 3
637	/* The width in bits of the ALT_UART_IIR_ID register field. */
638	#define ALT_UART_IIR_ID_WIDTH 4
639	/* The mask used to set the ALT_UART_IIR_ID register field value. */
640	#define ALT_UART_IIR_ID_SET_MSK 0x0000000f
641	/* The mask used to clear the ALT_UART_IIR_ID register field value. */
642	#define ALT_UART_IIR_ID_CLR_MSK 0xfffffff0
643	/* The reset value of the ALT_UART_IIR_ID register field. */
644	#define ALT_UART_IIR_ID_RESET 0x1
645	/* Extracts the ALT_UART_IIR_ID field value from a register. */
646	#define ALT_UART_IIR_ID_GET(value) (((value) & 0x0000000f) >> 0)
647	/* Produces a ALT_UART_IIR_ID register field value suitable for setting the register. */
648	#define ALT_UART_IIR_ID_SET(value) (((value) << 0) & 0x0000000f)
649
650	/*
651	* Field : FIFO Enabled - fifoen
652	*
653	* This is used to indicate whether the FIFO's are enabled or disabled.
654	*
655	* Field Enumeration Values:
656	*
657	* Enum \| Value \| Description
658	* :---------------------------\|:------\|:--------------
659	* ALT_UART_IIR_FIFOEN_E_DISD \| 0x0 \| FIFO disabled
660	* ALT_UART_IIR_FIFOEN_E_END \| 0x3 \| FIFO enabled
661	*
662	* Field Access Macros:
663	*
664	*/
665	/*
666	* Enumerated value for register field ALT_UART_IIR_FIFOEN
667	*
668	* FIFO disabled
669	*/
670	#define ALT_UART_IIR_FIFOEN_E_DISD 0x0
671	/*
672	* Enumerated value for register field ALT_UART_IIR_FIFOEN
673	*
674	* FIFO enabled
675	*/
676	#define ALT_UART_IIR_FIFOEN_E_END 0x3
677
678	/* The Least Significant Bit (LSB) position of the ALT_UART_IIR_FIFOEN register field. */
679	#define ALT_UART_IIR_FIFOEN_LSB 6
680	/* The Most Significant Bit (MSB) position of the ALT_UART_IIR_FIFOEN register field. */
681	#define ALT_UART_IIR_FIFOEN_MSB 7
682	/* The width in bits of the ALT_UART_IIR_FIFOEN register field. */
683	#define ALT_UART_IIR_FIFOEN_WIDTH 2
684	/* The mask used to set the ALT_UART_IIR_FIFOEN register field value. */
685	#define ALT_UART_IIR_FIFOEN_SET_MSK 0x000000c0
686	/* The mask used to clear the ALT_UART_IIR_FIFOEN register field value. */
687	#define ALT_UART_IIR_FIFOEN_CLR_MSK 0xffffff3f
688	/* The reset value of the ALT_UART_IIR_FIFOEN register field. */
689	#define ALT_UART_IIR_FIFOEN_RESET 0x0
690	/* Extracts the ALT_UART_IIR_FIFOEN field value from a register. */
691	#define ALT_UART_IIR_FIFOEN_GET(value) (((value) & 0x000000c0) >> 6)
692	/* Produces a ALT_UART_IIR_FIFOEN register field value suitable for setting the register. */
693	#define ALT_UART_IIR_FIFOEN_SET(value) (((value) << 6) & 0x000000c0)
694
695	#ifndef __ASSEMBLY__
696	/*
697	* WARNING: The C register and register group struct declarations are provided for
698	* convenience and illustrative purposes. They should, however, be used with
699	* caution as the C language standard provides no guarantees about the alignment or
700	* atomicity of device memory accesses. The recommended practice for writing
701	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
702	* alt_write_word() functions.
703	*
704	* The struct declaration for register ALT_UART_IIR.
705	*/
706	struct ALT_UART_IIR_s
707	{
708	const uint32_t id : 4; /* Interrupt ID */
709	uint32_t : 2; /* UNDEFINED */
710	const uint32_t fifoen : 2; /* FIFO Enabled */
711	uint32_t : 24; /* UNDEFINED */
712	};
713
714	/* The typedef declaration for register ALT_UART_IIR. */
715	typedef volatile struct ALT_UART_IIR_s ALT_UART_IIR_t;
716	#endif /* __ASSEMBLY__ */
717
718	/* The byte offset of the ALT_UART_IIR register from the beginning of the component. */
719	#define ALT_UART_IIR_OFST 0x8
720	/* The address of the ALT_UART_IIR register. */
721	#define ALT_UART_IIR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_IIR_OFST))
722
723	/*
724	* Register : FIFO Control (when written) - fcr
725	*
726	* Controls FIFO Operations when written.
727	*
728	* Register Layout
729	*
730	* Bits \| Access \| Reset \| Description
731	* :-------\|:-------\|:--------\|:-----------------------
732	* [0] \| W \| Unknown \| FIFO Enable
733	* [1] \| W \| Unknown \| Rx FIFO Reset
734	* [2] \| W \| Unknown \| Tx FIFO Reset
735	* [3] \| W \| Unknown \| DMA Mode
736	* [5:4] \| W \| Unknown \| Tx Empty Trigger Level
737	* [7:6] \| W \| Unknown \| Rx Trigger Level
738	* [31:8] \| ??? \| 0x0 \| UNDEFINED
739	*
740	*/
741	/*
742	* Field : FIFO Enable - fifoe
743	*
744	* Enables/disables the transmit (Tx) and receive (Rx ) FIFO's. Whenever the value
745	* of this bit is changed both the Tx and Rx controller portion of FIFO's will be
746	* reset.
747	*
748	* Field Enumeration Values:
749	*
750	* Enum \| Value \| Description
751	* :--------------------------\|:------\|:---------------
752	* ALT_UART_FCR_FIFOE_E_DISD \| 0x0 \| FIFOs disabled
753	* ALT_UART_FCR_FIFOE_E_END \| 0x1 \| FIFOs enabled
754	*
755	* Field Access Macros:
756	*
757	*/
758	/*
759	* Enumerated value for register field ALT_UART_FCR_FIFOE
760	*
761	* FIFOs disabled
762	*/
763	#define ALT_UART_FCR_FIFOE_E_DISD 0x0
764	/*
765	* Enumerated value for register field ALT_UART_FCR_FIFOE
766	*
767	* FIFOs enabled
768	*/
769	#define ALT_UART_FCR_FIFOE_E_END 0x1
770
771	/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_FIFOE register field. */
772	#define ALT_UART_FCR_FIFOE_LSB 0
773	/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_FIFOE register field. */
774	#define ALT_UART_FCR_FIFOE_MSB 0
775	/* The width in bits of the ALT_UART_FCR_FIFOE register field. */
776	#define ALT_UART_FCR_FIFOE_WIDTH 1
777	/* The mask used to set the ALT_UART_FCR_FIFOE register field value. */
778	#define ALT_UART_FCR_FIFOE_SET_MSK 0x00000001
779	/* The mask used to clear the ALT_UART_FCR_FIFOE register field value. */
780	#define ALT_UART_FCR_FIFOE_CLR_MSK 0xfffffffe
781	/* The reset value of the ALT_UART_FCR_FIFOE register field is UNKNOWN. */
782	#define ALT_UART_FCR_FIFOE_RESET 0x0
783	/* Extracts the ALT_UART_FCR_FIFOE field value from a register. */
784	#define ALT_UART_FCR_FIFOE_GET(value) (((value) & 0x00000001) >> 0)
785	/* Produces a ALT_UART_FCR_FIFOE register field value suitable for setting the register. */
786	#define ALT_UART_FCR_FIFOE_SET(value) (((value) << 0) & 0x00000001)
787
788	/*
789	* Field : Rx FIFO Reset - rfifor
790	*
791	* Resets the control portion of the receive FIFO and treats the FIFO as empty.
792	* This will also de-assert the DMA Rxrequest and single signals. Note that this
793	* bit is self-clearing' and it is not necessary to clear this bit.
794	*
795	* Field Enumeration Values:
796	*
797	* Enum \| Value \| Description
798	* :----------------------------\|:------\|:----------------------------
799	* ALT_UART_FCR_RFIFOR_E_NORST \| 0x0 \| No Reset of Rx FIFO Control
800	* ALT_UART_FCR_RFIFOR_E_RST \| 0x1 \| Resets of Rx FIFO Control
801	*
802	* Field Access Macros:
803	*
804	*/
805	/*
806	* Enumerated value for register field ALT_UART_FCR_RFIFOR
807	*
808	* No Reset of Rx FIFO Control
809	*/
810	#define ALT_UART_FCR_RFIFOR_E_NORST 0x0
811	/*
812	* Enumerated value for register field ALT_UART_FCR_RFIFOR
813	*
814	* Resets of Rx FIFO Control
815	*/
816	#define ALT_UART_FCR_RFIFOR_E_RST 0x1
817
818	/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RFIFOR register field. */
819	#define ALT_UART_FCR_RFIFOR_LSB 1
820	/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RFIFOR register field. */
821	#define ALT_UART_FCR_RFIFOR_MSB 1
822	/* The width in bits of the ALT_UART_FCR_RFIFOR register field. */
823	#define ALT_UART_FCR_RFIFOR_WIDTH 1
824	/* The mask used to set the ALT_UART_FCR_RFIFOR register field value. */
825	#define ALT_UART_FCR_RFIFOR_SET_MSK 0x00000002
826	/* The mask used to clear the ALT_UART_FCR_RFIFOR register field value. */
827	#define ALT_UART_FCR_RFIFOR_CLR_MSK 0xfffffffd
828	/* The reset value of the ALT_UART_FCR_RFIFOR register field is UNKNOWN. */
829	#define ALT_UART_FCR_RFIFOR_RESET 0x0
830	/* Extracts the ALT_UART_FCR_RFIFOR field value from a register. */
831	#define ALT_UART_FCR_RFIFOR_GET(value) (((value) & 0x00000002) >> 1)
832	/* Produces a ALT_UART_FCR_RFIFOR register field value suitable for setting the register. */
833	#define ALT_UART_FCR_RFIFOR_SET(value) (((value) << 1) & 0x00000002)
834
835	/*
836	* Field : Tx FIFO Reset - xfifor
837	*
838	* Resets the control portion of the transmit FIFO and treats the FIFO as empty.
839	* This will also de-assert the DMA Tx request and single signals when additional
840	* DMA handshaking is used.
841	*
842	* Note that this bit is 'self-clearing' and it is not necessary to clear this bit.
843	*
844	* Field Enumeration Values:
845	*
846	* Enum \| Value \| Description
847	* :----------------------------\|:------\|:----------------------------
848	* ALT_UART_FCR_XFIFOR_E_NORST \| 0x0 \| No Reset of Tx FIFO Control
849	* ALT_UART_FCR_XFIFOR_E_RST \| 0x1 \| Resets Tx FIFO Control
850	*
851	* Field Access Macros:
852	*
853	*/
854	/*
855	* Enumerated value for register field ALT_UART_FCR_XFIFOR
856	*
857	* No Reset of Tx FIFO Control
858	*/
859	#define ALT_UART_FCR_XFIFOR_E_NORST 0x0
860	/*
861	* Enumerated value for register field ALT_UART_FCR_XFIFOR
862	*
863	* Resets Tx FIFO Control
864	*/
865	#define ALT_UART_FCR_XFIFOR_E_RST 0x1
866
867	/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_XFIFOR register field. */
868	#define ALT_UART_FCR_XFIFOR_LSB 2
869	/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_XFIFOR register field. */
870	#define ALT_UART_FCR_XFIFOR_MSB 2
871	/* The width in bits of the ALT_UART_FCR_XFIFOR register field. */
872	#define ALT_UART_FCR_XFIFOR_WIDTH 1
873	/* The mask used to set the ALT_UART_FCR_XFIFOR register field value. */
874	#define ALT_UART_FCR_XFIFOR_SET_MSK 0x00000004
875	/* The mask used to clear the ALT_UART_FCR_XFIFOR register field value. */
876	#define ALT_UART_FCR_XFIFOR_CLR_MSK 0xfffffffb
877	/* The reset value of the ALT_UART_FCR_XFIFOR register field is UNKNOWN. */
878	#define ALT_UART_FCR_XFIFOR_RESET 0x0
879	/* Extracts the ALT_UART_FCR_XFIFOR field value from a register. */
880	#define ALT_UART_FCR_XFIFOR_GET(value) (((value) & 0x00000004) >> 2)
881	/* Produces a ALT_UART_FCR_XFIFOR register field value suitable for setting the register. */
882	#define ALT_UART_FCR_XFIFOR_SET(value) (((value) << 2) & 0x00000004)
883
884	/*
885	* Field : DMA Mode - dmam
886	*
887	* This determines the DMA signalling mode used for the uart_dma_tx_req_n and
888	* uart_dma_rx_req_n output signals when additional DMA handshaking signals are not
889	* selected. DMA mode 0 supports single DMA data transfers at a time. In mode 0,
890	* the uart_dma_tx_req_n signal goes active low under the following conditions:
891	*
892	* * When the Transmitter Holding Register is empty in non-FIFO mode.
893	*
894	* * When the transmitter FIFO is empty in FIFO mode with Programmable THRE
895	* interrupt mode disabled.
896	*
897	* * When the transmitter FIFO is at or below the programmed threshold with
898	* Programmable THRE interrupt mode enabled.
899	*
900	* It goes inactive under the following conditions
901	*
902	* * When a single character has been written into the Transmitter Holding
903	* Register or transmitter FIFO with Programmable THRE interrupt mode disabled.
904	*
905	* * When the transmitter FIFO is above the threshold with Programmable THRE
906	* interrupt mode enabled.
907	*
908	* DMA mode 1 supports multi-DMA data transfers, where multiple transfers are made
909	* continuously until the receiver FIFO has been emptied or the transmit FIFO has
910	* been filled. In mode 1 the uart_dma_tx_req_n signal is asserted under the
911	* following conditions:
912	*
913	* * When the transmitter FIFO is empty with Programmable THRE interrupt mode
914	* disabled.
915	*
916	* * When the transmitter FIFO is at or below the programmed threshold with
917	* Programmable THRE interrupt mode enabled.
918	*
919	* Field Enumeration Values:
920	*
921	* Enum \| Value \| Description
922	* :---------------------------\|:------\|:---------------------------
923	* ALT_UART_FCR_DMAM_E_SINGLE \| 0x0 \| Single DMA Transfer Mode
924	* ALT_UART_FCR_DMAM_E_MULT \| 0x1 \| Multiple DMA Transfer Mode
925	*
926	* Field Access Macros:
927	*
928	*/
929	/*
930	* Enumerated value for register field ALT_UART_FCR_DMAM
931	*
932	* Single DMA Transfer Mode
933	*/
934	#define ALT_UART_FCR_DMAM_E_SINGLE 0x0
935	/*
936	* Enumerated value for register field ALT_UART_FCR_DMAM
937	*
938	* Multiple DMA Transfer Mode
939	*/
940	#define ALT_UART_FCR_DMAM_E_MULT 0x1
941
942	/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_DMAM register field. */
943	#define ALT_UART_FCR_DMAM_LSB 3
944	/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_DMAM register field. */
945	#define ALT_UART_FCR_DMAM_MSB 3
946	/* The width in bits of the ALT_UART_FCR_DMAM register field. */
947	#define ALT_UART_FCR_DMAM_WIDTH 1
948	/* The mask used to set the ALT_UART_FCR_DMAM register field value. */
949	#define ALT_UART_FCR_DMAM_SET_MSK 0x00000008
950	/* The mask used to clear the ALT_UART_FCR_DMAM register field value. */
951	#define ALT_UART_FCR_DMAM_CLR_MSK 0xfffffff7
952	/* The reset value of the ALT_UART_FCR_DMAM register field is UNKNOWN. */
953	#define ALT_UART_FCR_DMAM_RESET 0x0
954	/* Extracts the ALT_UART_FCR_DMAM field value from a register. */
955	#define ALT_UART_FCR_DMAM_GET(value) (((value) & 0x00000008) >> 3)
956	/* Produces a ALT_UART_FCR_DMAM register field value suitable for setting the register. */
957	#define ALT_UART_FCR_DMAM_SET(value) (((value) << 3) & 0x00000008)
958
959	/*
960	* Field : Tx Empty Trigger Level - tet
961	*
962	* This is used to select the empty threshold level at which the THRE Interrupts
963	* will be generated when the mode is active. It also determines when the uart DMA
964	* transmit request signal uart_dma_tx_req_n will be asserted when in certain modes
965	* of operation.
966	*
967	* Field Enumeration Values:
968	*
969	* Enum \| Value \| Description
970	* :-------------------------------\|:------\|:-----------------------
971	* ALT_UART_FCR_TET_E_FIFOEMPTY \| 0x0 \| FIFO empty
972	* ALT_UART_FCR_TET_E_TWOCHARS \| 0x1 \| Two characters in FIFO
973	* ALT_UART_FCR_TET_E_QUARTERFULL \| 0x2 \| FIFO 1/4 full
974	* ALT_UART_FCR_TET_E_HALFFULL \| 0x3 \| FIFO 1/2 full
975	*
976	* Field Access Macros:
977	*
978	*/
979	/*
980	* Enumerated value for register field ALT_UART_FCR_TET
981	*
982	* FIFO empty
983	*/
984	#define ALT_UART_FCR_TET_E_FIFOEMPTY 0x0
985	/*
986	* Enumerated value for register field ALT_UART_FCR_TET
987	*
988	* Two characters in FIFO
989	*/
990	#define ALT_UART_FCR_TET_E_TWOCHARS 0x1
991	/*
992	* Enumerated value for register field ALT_UART_FCR_TET
993	*
994	* FIFO 1/4 full
995	*/
996	#define ALT_UART_FCR_TET_E_QUARTERFULL 0x2
997	/*
998	* Enumerated value for register field ALT_UART_FCR_TET
999	*
1000	* FIFO 1/2 full
1001	*/
1002	#define ALT_UART_FCR_TET_E_HALFFULL 0x3
1003
1004	/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_TET register field. */
1005	#define ALT_UART_FCR_TET_LSB 4
1006	/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_TET register field. */
1007	#define ALT_UART_FCR_TET_MSB 5
1008	/* The width in bits of the ALT_UART_FCR_TET register field. */
1009	#define ALT_UART_FCR_TET_WIDTH 2
1010	/* The mask used to set the ALT_UART_FCR_TET register field value. */
1011	#define ALT_UART_FCR_TET_SET_MSK 0x00000030
1012	/* The mask used to clear the ALT_UART_FCR_TET register field value. */
1013	#define ALT_UART_FCR_TET_CLR_MSK 0xffffffcf
1014	/* The reset value of the ALT_UART_FCR_TET register field is UNKNOWN. */
1015	#define ALT_UART_FCR_TET_RESET 0x0
1016	/* Extracts the ALT_UART_FCR_TET field value from a register. */
1017	#define ALT_UART_FCR_TET_GET(value) (((value) & 0x00000030) >> 4)
1018	/* Produces a ALT_UART_FCR_TET register field value suitable for setting the register. */
1019	#define ALT_UART_FCR_TET_SET(value) (((value) << 4) & 0x00000030)
1020
1021	/*
1022	* Field : Rx Trigger Level - rt
1023	*
1024	* This register is configured to implement FIFOs. Bits[7:6], Rx Trigger (or RT):
1025	* This is used to select the trigger level in the receiver FIFO at which the
1026	* Received Data Available Interrupt will be generated. In auto flow control mode
1027	* it is used to determine when the uart_rts_n signal will be de-asserted. It also
1028	* determines when the uart_dma_rx_req_n signal will be asserted when in certain
1029	* modes of operation.
1030	*
1031	* Field Enumeration Values:
1032	*
1033	* Enum \| Value \| Description
1034	* :------------------------------\|:------\|:----------------------
1035	* ALT_UART_FCR_RT_E_ONECHAR \| 0x0 \| one character in fifo
1036	* ALT_UART_FCR_RT_E_QUARTERFULL \| 0x1 \| FIFO 1/4 full
1037	* ALT_UART_FCR_RT_E_HALFFULL \| 0x2 \| FIFO 1/2 full
1038	* ALT_UART_FCR_RT_E_FULLLESS2 \| 0x3 \| FIFO 2 less than full
1039	*
1040	* Field Access Macros:
1041	*
1042	*/
1043	/*
1044	* Enumerated value for register field ALT_UART_FCR_RT
1045	*
1046	* one character in fifo
1047	*/
1048	#define ALT_UART_FCR_RT_E_ONECHAR 0x0
1049	/*
1050	* Enumerated value for register field ALT_UART_FCR_RT
1051	*
1052	* FIFO 1/4 full
1053	*/
1054	#define ALT_UART_FCR_RT_E_QUARTERFULL 0x1
1055	/*
1056	* Enumerated value for register field ALT_UART_FCR_RT
1057	*
1058	* FIFO 1/2 full
1059	*/
1060	#define ALT_UART_FCR_RT_E_HALFFULL 0x2
1061	/*
1062	* Enumerated value for register field ALT_UART_FCR_RT
1063	*
1064	* FIFO 2 less than full
1065	*/
1066	#define ALT_UART_FCR_RT_E_FULLLESS2 0x3
1067
1068	/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RT register field. */
1069	#define ALT_UART_FCR_RT_LSB 6
1070	/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RT register field. */
1071	#define ALT_UART_FCR_RT_MSB 7
1072	/* The width in bits of the ALT_UART_FCR_RT register field. */
1073	#define ALT_UART_FCR_RT_WIDTH 2
1074	/* The mask used to set the ALT_UART_FCR_RT register field value. */
1075	#define ALT_UART_FCR_RT_SET_MSK 0x000000c0
1076	/* The mask used to clear the ALT_UART_FCR_RT register field value. */
1077	#define ALT_UART_FCR_RT_CLR_MSK 0xffffff3f
1078	/* The reset value of the ALT_UART_FCR_RT register field is UNKNOWN. */
1079	#define ALT_UART_FCR_RT_RESET 0x0
1080	/* Extracts the ALT_UART_FCR_RT field value from a register. */
1081	#define ALT_UART_FCR_RT_GET(value) (((value) & 0x000000c0) >> 6)
1082	/* Produces a ALT_UART_FCR_RT register field value suitable for setting the register. */
1083	#define ALT_UART_FCR_RT_SET(value) (((value) << 6) & 0x000000c0)
1084
1085	#ifndef __ASSEMBLY__
1086	/*
1087	* WARNING: The C register and register group struct declarations are provided for
1088	* convenience and illustrative purposes. They should, however, be used with
1089	* caution as the C language standard provides no guarantees about the alignment or
1090	* atomicity of device memory accesses. The recommended practice for writing
1091	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1092	* alt_write_word() functions.
1093	*
1094	* The struct declaration for register ALT_UART_FCR.
1095	*/
1096	struct ALT_UART_FCR_s
1097	{
1098	uint32_t fifoe : 1; /* FIFO Enable */
1099	uint32_t rfifor : 1; /* Rx FIFO Reset */
1100	uint32_t xfifor : 1; /* Tx FIFO Reset */
1101	uint32_t dmam : 1; /* DMA Mode */
1102	uint32_t tet : 2; /* Tx Empty Trigger Level */
1103	uint32_t rt : 2; /* Rx Trigger Level */
1104	uint32_t : 24; /* UNDEFINED */
1105	};
1106
1107	/* The typedef declaration for register ALT_UART_FCR. */
1108	typedef volatile struct ALT_UART_FCR_s ALT_UART_FCR_t;
1109	#endif /* __ASSEMBLY__ */
1110
1111	/* The byte offset of the ALT_UART_FCR register from the beginning of the component. */
1112	#define ALT_UART_FCR_OFST 0x8
1113	/* The address of the ALT_UART_FCR register. */
1114	#define ALT_UART_FCR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_FCR_OFST))
1115
1116	/*
1117	* Register : Line Control Register (When Written) - lcr
1118	*
1119	* Formats serial data.
1120	*
1121	* Register Layout
1122	*
1123	* Bits \| Access \| Reset \| Description
1124	* :-------\|:-------\|:------\|:-------------------------
1125	* [1:0] \| RW \| 0x0 \| Data Length Select
1126	* [2] \| RW \| 0x0 \| Stop Bits
1127	* [3] \| RW \| 0x0 \| Parity Enable
1128	* [4] \| RW \| 0x0 \| Even Parity Select
1129	* [5] \| ??? \| 0x0 \| UNDEFINED
1130	* [6] \| RW \| 0x0 \| Break Control Bit
1131	* [7] \| RW \| 0x0 \| Divisor Latch Access Bit
1132	* [31:8] \| ??? \| 0x0 \| UNDEFINED
1133	*
1134	*/
1135	/*
1136	* Field : Data Length Select - dls
1137	*
1138	* Data Length Select.Selects the number of data bits per character that the
1139	* peripheral will transmit and receive.
1140	*
1141	* Field Enumeration Values:
1142	*
1143	* Enum \| Value \| Description
1144	* :------------------------\|:------\|:------------
1145	* ALT_UART_LCR_DLS_E_LEN5 \| 0x0 \| 5 bits
1146	* ALT_UART_LCR_DLS_E_LEN6 \| 0x1 \| 6 bits
1147	* ALT_UART_LCR_DLS_E_LEN7 \| 0x2 \| 7 bits
1148	* ALT_UART_LCR_DLS_E_LEN8 \| 0x3 \| 8 bits
1149	*
1150	* Field Access Macros:
1151	*
1152	*/
1153	/*
1154	* Enumerated value for register field ALT_UART_LCR_DLS
1155	*
1156	* 5 bits
1157	*/
1158	#define ALT_UART_LCR_DLS_E_LEN5 0x0
1159	/*
1160	* Enumerated value for register field ALT_UART_LCR_DLS
1161	*
1162	* 6 bits
1163	*/
1164	#define ALT_UART_LCR_DLS_E_LEN6 0x1
1165	/*
1166	* Enumerated value for register field ALT_UART_LCR_DLS
1167	*
1168	* 7 bits
1169	*/
1170	#define ALT_UART_LCR_DLS_E_LEN7 0x2
1171	/*
1172	* Enumerated value for register field ALT_UART_LCR_DLS
1173	*
1174	* 8 bits
1175	*/
1176	#define ALT_UART_LCR_DLS_E_LEN8 0x3
1177
1178	/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLS register field. */
1179	#define ALT_UART_LCR_DLS_LSB 0
1180	/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLS register field. */
1181	#define ALT_UART_LCR_DLS_MSB 1
1182	/* The width in bits of the ALT_UART_LCR_DLS register field. */
1183	#define ALT_UART_LCR_DLS_WIDTH 2
1184	/* The mask used to set the ALT_UART_LCR_DLS register field value. */
1185	#define ALT_UART_LCR_DLS_SET_MSK 0x00000003
1186	/* The mask used to clear the ALT_UART_LCR_DLS register field value. */
1187	#define ALT_UART_LCR_DLS_CLR_MSK 0xfffffffc
1188	/* The reset value of the ALT_UART_LCR_DLS register field. */
1189	#define ALT_UART_LCR_DLS_RESET 0x0
1190	/* Extracts the ALT_UART_LCR_DLS field value from a register. */
1191	#define ALT_UART_LCR_DLS_GET(value) (((value) & 0x00000003) >> 0)
1192	/* Produces a ALT_UART_LCR_DLS register field value suitable for setting the register. */
1193	#define ALT_UART_LCR_DLS_SET(value) (((value) << 0) & 0x00000003)
1194
1195	/*
1196	* Field : Stop Bits - stop
1197	*
1198	* Number of stop bits. Used to select the number of stop bits per character that
1199	* the peripheral will transmit and receive.Note that regardless of the number of
1200	* stop bits selected the receiver will only check the first stop bit.
1201	*
1202	* Field Enumeration Values:
1203	*
1204	* Enum \| Value \| Description
1205	* :----------------------------------\|:------\|:------------------------------------------
1206	* ALT_UART_LCR_STOP_E_ONESTOP \| 0x0 \| one stop bit
1207	* ALT_UART_LCR_STOP_E_ONEPOINT5STOP \| 0x1 \| 1.5 stop bits when DLS (LCR[1:0]) is zero
1208	*
1209	* Field Access Macros:
1210	*
1211	*/
1212	/*
1213	* Enumerated value for register field ALT_UART_LCR_STOP
1214	*
1215	* one stop bit
1216	*/
1217	#define ALT_UART_LCR_STOP_E_ONESTOP 0x0
1218	/*
1219	* Enumerated value for register field ALT_UART_LCR_STOP
1220	*
1221	* 1.5 stop bits when DLS (LCR[1:0]) is zero
1222	*/
1223	#define ALT_UART_LCR_STOP_E_ONEPOINT5STOP 0x1
1224
1225	/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_STOP register field. */
1226	#define ALT_UART_LCR_STOP_LSB 2
1227	/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_STOP register field. */
1228	#define ALT_UART_LCR_STOP_MSB 2
1229	/* The width in bits of the ALT_UART_LCR_STOP register field. */
1230	#define ALT_UART_LCR_STOP_WIDTH 1
1231	/* The mask used to set the ALT_UART_LCR_STOP register field value. */
1232	#define ALT_UART_LCR_STOP_SET_MSK 0x00000004
1233	/* The mask used to clear the ALT_UART_LCR_STOP register field value. */
1234	#define ALT_UART_LCR_STOP_CLR_MSK 0xfffffffb
1235	/* The reset value of the ALT_UART_LCR_STOP register field. */
1236	#define ALT_UART_LCR_STOP_RESET 0x0
1237	/* Extracts the ALT_UART_LCR_STOP field value from a register. */
1238	#define ALT_UART_LCR_STOP_GET(value) (((value) & 0x00000004) >> 2)
1239	/* Produces a ALT_UART_LCR_STOP register field value suitable for setting the register. */
1240	#define ALT_UART_LCR_STOP_SET(value) (((value) << 2) & 0x00000004)
1241
1242	/*
1243	* Field : Parity Enable - pen
1244	*
1245	* This bit is used to enable and disable parity generation and detection in a
1246	* transmitted and received data character.
1247	*
1248	* Field Enumeration Values:
1249	*
1250	* Enum \| Value \| Description
1251	* :------------------------\|:------\|:----------------
1252	* ALT_UART_LCR_PEN_E_DISD \| 0x0 \| parity disabled
1253	* ALT_UART_LCR_PEN_E_END \| 0x1 \| parity enabled
1254	*
1255	* Field Access Macros:
1256	*
1257	*/
1258	/*
1259	* Enumerated value for register field ALT_UART_LCR_PEN
1260	*
1261	* parity disabled
1262	*/
1263	#define ALT_UART_LCR_PEN_E_DISD 0x0
1264	/*
1265	* Enumerated value for register field ALT_UART_LCR_PEN
1266	*
1267	* parity enabled
1268	*/
1269	#define ALT_UART_LCR_PEN_E_END 0x1
1270
1271	/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_PEN register field. */
1272	#define ALT_UART_LCR_PEN_LSB 3
1273	/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_PEN register field. */
1274	#define ALT_UART_LCR_PEN_MSB 3
1275	/* The width in bits of the ALT_UART_LCR_PEN register field. */
1276	#define ALT_UART_LCR_PEN_WIDTH 1
1277	/* The mask used to set the ALT_UART_LCR_PEN register field value. */
1278	#define ALT_UART_LCR_PEN_SET_MSK 0x00000008
1279	/* The mask used to clear the ALT_UART_LCR_PEN register field value. */
1280	#define ALT_UART_LCR_PEN_CLR_MSK 0xfffffff7
1281	/* The reset value of the ALT_UART_LCR_PEN register field. */
1282	#define ALT_UART_LCR_PEN_RESET 0x0
1283	/* Extracts the ALT_UART_LCR_PEN field value from a register. */
1284	#define ALT_UART_LCR_PEN_GET(value) (((value) & 0x00000008) >> 3)
1285	/* Produces a ALT_UART_LCR_PEN register field value suitable for setting the register. */
1286	#define ALT_UART_LCR_PEN_SET(value) (((value) << 3) & 0x00000008)
1287
1288	/*
1289	* Field : Even Parity Select - eps
1290	*
1291	* This is used to select between even and odd parity, when parity is enabled (PEN
1292	* set to one). If set to one, an even number of logic '1's is transmitted or
1293	* checked. If set to zero, an odd number of logic '1's is transmitted or checked.
1294	*
1295	* Field Enumeration Values:
1296	*
1297	* Enum \| Value \| Description
1298	* :---------------------------\|:------\|:------------
1299	* ALT_UART_LCR_EPS_E_ODDPAR \| 0x0 \| odd parity
1300	* ALT_UART_LCR_EPS_E_EVENPAR \| 0x1 \| even parity
1301	*
1302	* Field Access Macros:
1303	*
1304	*/
1305	/*
1306	* Enumerated value for register field ALT_UART_LCR_EPS
1307	*
1308	* odd parity
1309	*/
1310	#define ALT_UART_LCR_EPS_E_ODDPAR 0x0
1311	/*
1312	* Enumerated value for register field ALT_UART_LCR_EPS
1313	*
1314	* even parity
1315	*/
1316	#define ALT_UART_LCR_EPS_E_EVENPAR 0x1
1317
1318	/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_EPS register field. */
1319	#define ALT_UART_LCR_EPS_LSB 4
1320	/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_EPS register field. */
1321	#define ALT_UART_LCR_EPS_MSB 4
1322	/* The width in bits of the ALT_UART_LCR_EPS register field. */
1323	#define ALT_UART_LCR_EPS_WIDTH 1
1324	/* The mask used to set the ALT_UART_LCR_EPS register field value. */
1325	#define ALT_UART_LCR_EPS_SET_MSK 0x00000010
1326	/* The mask used to clear the ALT_UART_LCR_EPS register field value. */
1327	#define ALT_UART_LCR_EPS_CLR_MSK 0xffffffef
1328	/* The reset value of the ALT_UART_LCR_EPS register field. */
1329	#define ALT_UART_LCR_EPS_RESET 0x0
1330	/* Extracts the ALT_UART_LCR_EPS field value from a register. */
1331	#define ALT_UART_LCR_EPS_GET(value) (((value) & 0x00000010) >> 4)
1332	/* Produces a ALT_UART_LCR_EPS register field value suitable for setting the register. */
1333	#define ALT_UART_LCR_EPS_SET(value) (((value) << 4) & 0x00000010)
1334
1335	/*
1336	* Field : Break Control Bit - break
1337	*
1338	* This is used to cause a break condition to be transmitted to the receiving
1339	* device. If set to one the serial output is forced to the spacing (logic 0)
1340	* state. When not in Loopback Mode, as determined by MCR[4], the sout line is
1341	* forced low until the Break bit is cleared. When in Loopback Mode, the break
1342	* condition is internally looped back to the receiver and the sir_out_n line is
1343	* forced low.
1344	*
1345	* Field Access Macros:
1346	*
1347	*/
1348	/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_BREAK register field. */
1349	#define ALT_UART_LCR_BREAK_LSB 6
1350	/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_BREAK register field. */
1351	#define ALT_UART_LCR_BREAK_MSB 6
1352	/* The width in bits of the ALT_UART_LCR_BREAK register field. */
1353	#define ALT_UART_LCR_BREAK_WIDTH 1
1354	/* The mask used to set the ALT_UART_LCR_BREAK register field value. */
1355	#define ALT_UART_LCR_BREAK_SET_MSK 0x00000040
1356	/* The mask used to clear the ALT_UART_LCR_BREAK register field value. */
1357	#define ALT_UART_LCR_BREAK_CLR_MSK 0xffffffbf
1358	/* The reset value of the ALT_UART_LCR_BREAK register field. */
1359	#define ALT_UART_LCR_BREAK_RESET 0x0
1360	/* Extracts the ALT_UART_LCR_BREAK field value from a register. */
1361	#define ALT_UART_LCR_BREAK_GET(value) (((value) & 0x00000040) >> 6)
1362	/* Produces a ALT_UART_LCR_BREAK register field value suitable for setting the register. */
1363	#define ALT_UART_LCR_BREAK_SET(value) (((value) << 6) & 0x00000040)
1364
1365	/*
1366	* Field : Divisor Latch Access Bit - dlab
1367	*
1368	* Used to enable reading and writing of the Divisor Latch register (DLL and DLH)
1369	* to set the baud rate of the UART. This bit must be cleared after initial baud
1370	* rate setup in order to access other registers.
1371	*
1372	* Field Access Macros:
1373	*
1374	*/
1375	/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLAB register field. */
1376	#define ALT_UART_LCR_DLAB_LSB 7
1377	/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLAB register field. */
1378	#define ALT_UART_LCR_DLAB_MSB 7
1379	/* The width in bits of the ALT_UART_LCR_DLAB register field. */
1380	#define ALT_UART_LCR_DLAB_WIDTH 1
1381	/* The mask used to set the ALT_UART_LCR_DLAB register field value. */
1382	#define ALT_UART_LCR_DLAB_SET_MSK 0x00000080
1383	/* The mask used to clear the ALT_UART_LCR_DLAB register field value. */
1384	#define ALT_UART_LCR_DLAB_CLR_MSK 0xffffff7f
1385	/* The reset value of the ALT_UART_LCR_DLAB register field. */
1386	#define ALT_UART_LCR_DLAB_RESET 0x0
1387	/* Extracts the ALT_UART_LCR_DLAB field value from a register. */
1388	#define ALT_UART_LCR_DLAB_GET(value) (((value) & 0x00000080) >> 7)
1389	/* Produces a ALT_UART_LCR_DLAB register field value suitable for setting the register. */
1390	#define ALT_UART_LCR_DLAB_SET(value) (((value) << 7) & 0x00000080)
1391
1392	#ifndef __ASSEMBLY__
1393	/*
1394	* WARNING: The C register and register group struct declarations are provided for
1395	* convenience and illustrative purposes. They should, however, be used with
1396	* caution as the C language standard provides no guarantees about the alignment or
1397	* atomicity of device memory accesses. The recommended practice for writing
1398	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1399	* alt_write_word() functions.
1400	*
1401	* The struct declaration for register ALT_UART_LCR.
1402	*/
1403	struct ALT_UART_LCR_s
1404	{
1405	uint32_t dls : 2; /* Data Length Select */
1406	uint32_t stop : 1; /* Stop Bits */
1407	uint32_t pen : 1; /* Parity Enable */
1408	uint32_t eps : 1; /* Even Parity Select */
1409	uint32_t : 1; /* UNDEFINED */
1410	uint32_t break_ : 1; /* Break Control Bit */
1411	uint32_t dlab : 1; /* Divisor Latch Access Bit */
1412	uint32_t : 24; /* UNDEFINED */
1413	};
1414
1415	/* The typedef declaration for register ALT_UART_LCR. */
1416	typedef volatile struct ALT_UART_LCR_s ALT_UART_LCR_t;
1417	#endif /* __ASSEMBLY__ */
1418
1419	/* The byte offset of the ALT_UART_LCR register from the beginning of the component. */
1420	#define ALT_UART_LCR_OFST 0xc
1421	/* The address of the ALT_UART_LCR register. */
1422	#define ALT_UART_LCR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_LCR_OFST))
1423
1424	/*
1425	* Register : Modem Control Register - mcr
1426	*
1427	* Reports various operations of the modem signals
1428	*
1429	* Register Layout
1430	*
1431	* Bits \| Access \| Reset \| Description
1432	* :-------\|:-------\|:------\|:-------------------------
1433	* [0] \| RW \| 0x0 \| Data Terminal Ready
1434	* [1] \| RW \| 0x0 \| Request to Send
1435	* [2] \| RW \| 0x0 \| Out1
1436	* [3] \| RW \| 0x0 \| out2
1437	* [4] \| RW \| 0x0 \| LoopBack Bit
1438	* [5] \| RW \| 0x0 \| Auto Flow Control Enable
1439	* [31:6] \| ??? \| 0x0 \| UNDEFINED
1440	*
1441	*/
1442	/*
1443	* Field : Data Terminal Ready - dtr
1444	*
1445	* This is used to directly control the Data Terminal Ready output. The value
1446	* written to this location is inverted and driven out on uart_dtr_n, that is: The
1447	* Data Terminal Ready output is used to inform the modem or data set that the UART
1448	* is ready to establish communications.
1449	*
1450	* Note that Loopback mode bit [4] of MCR is set to one, the uart_dtr_n output is
1451	* held inactive high while the value of this location is internally looped back
1452	* to an input.
1453	*
1454	* Field Enumeration Values:
1455	*
1456	* Enum \| Value \| Description
1457	* :--------------------------\|:------\|:---------------------------------
1458	* ALT_UART_MCR_DTR_E_LOGIC1 \| 0x0 \| uart_dtr_n de-asserted (logic 1)
1459	* ALT_UART_MCR_DTR_E_LOGIC0 \| 0x1 \| uart_dtr_n asserted (logic 0)
1460	*
1461	* Field Access Macros:
1462	*
1463	*/
1464	/*
1465	* Enumerated value for register field ALT_UART_MCR_DTR
1466	*
1467	* uart_dtr_n de-asserted (logic 1)
1468	*/
1469	#define ALT_UART_MCR_DTR_E_LOGIC1 0x0
1470	/*
1471	* Enumerated value for register field ALT_UART_MCR_DTR
1472	*
1473	* uart_dtr_n asserted (logic 0)
1474	*/
1475	#define ALT_UART_MCR_DTR_E_LOGIC0 0x1
1476
1477	/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_DTR register field. */
1478	#define ALT_UART_MCR_DTR_LSB 0
1479	/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_DTR register field. */
1480	#define ALT_UART_MCR_DTR_MSB 0
1481	/* The width in bits of the ALT_UART_MCR_DTR register field. */
1482	#define ALT_UART_MCR_DTR_WIDTH 1
1483	/* The mask used to set the ALT_UART_MCR_DTR register field value. */
1484	#define ALT_UART_MCR_DTR_SET_MSK 0x00000001
1485	/* The mask used to clear the ALT_UART_MCR_DTR register field value. */
1486	#define ALT_UART_MCR_DTR_CLR_MSK 0xfffffffe
1487	/* The reset value of the ALT_UART_MCR_DTR register field. */
1488	#define ALT_UART_MCR_DTR_RESET 0x0
1489	/* Extracts the ALT_UART_MCR_DTR field value from a register. */
1490	#define ALT_UART_MCR_DTR_GET(value) (((value) & 0x00000001) >> 0)
1491	/* Produces a ALT_UART_MCR_DTR register field value suitable for setting the register. */
1492	#define ALT_UART_MCR_DTR_SET(value) (((value) << 0) & 0x00000001)
1493
1494	/*
1495	* Field : Request to Send - rts
1496	*
1497	* This is used to directly control the Request to Send (uart_rts_n) output. The
1498	* Request to Send (uart_rts_n) output is used to inform the modem or data set that
1499	* the UART is ready to exchange data. When Auto RTS Flow Control is not enabled
1500	* (MCR[5] set to zero), the uart_rts_n signal is set low by programming MCR[1]
1501	* (RTS) to a high. If Auto Flow Control is active (MCR[5] set to one) and FIFO's
1502	* enable (FCR[0] set to one), the uart_rts_n output is controlled in the same way,
1503	* but is also gated with the receiver FIFO threshold trigger (uart_rts_n is
1504	* inactive high when above the threshold). The uart_rts_n signal will be de-
1505	* asserted when MCR[1] is set low.
1506	*
1507	* Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held
1508	* inactive high while the value of this location is internally looped back to an
1509	* input.
1510	*
1511	* Field Enumeration Values:
1512	*
1513	* Enum \| Value \| Description
1514	* :--------------------------\|:------\|:---------------------------------
1515	* ALT_UART_MCR_RTS_E_LOGIC1 \| 0x0 \| uart_rts_n de-asserted (logic 1)
1516	* ALT_UART_MCR_RTS_E_LOGIC0 \| 0x1 \| uart_rts_n asserted (logic 0)
1517	*
1518	* Field Access Macros:
1519	*
1520	*/
1521	/*
1522	* Enumerated value for register field ALT_UART_MCR_RTS
1523	*
1524	* uart_rts_n de-asserted (logic 1)
1525	*/
1526	#define ALT_UART_MCR_RTS_E_LOGIC1 0x0
1527	/*
1528	* Enumerated value for register field ALT_UART_MCR_RTS
1529	*
1530	* uart_rts_n asserted (logic 0)
1531	*/
1532	#define ALT_UART_MCR_RTS_E_LOGIC0 0x1
1533
1534	/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_RTS register field. */
1535	#define ALT_UART_MCR_RTS_LSB 1
1536	/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_RTS register field. */
1537	#define ALT_UART_MCR_RTS_MSB 1
1538	/* The width in bits of the ALT_UART_MCR_RTS register field. */
1539	#define ALT_UART_MCR_RTS_WIDTH 1
1540	/* The mask used to set the ALT_UART_MCR_RTS register field value. */
1541	#define ALT_UART_MCR_RTS_SET_MSK 0x00000002
1542	/* The mask used to clear the ALT_UART_MCR_RTS register field value. */
1543	#define ALT_UART_MCR_RTS_CLR_MSK 0xfffffffd
1544	/* The reset value of the ALT_UART_MCR_RTS register field. */
1545	#define ALT_UART_MCR_RTS_RESET 0x0
1546	/* Extracts the ALT_UART_MCR_RTS field value from a register. */
1547	#define ALT_UART_MCR_RTS_GET(value) (((value) & 0x00000002) >> 1)
1548	/* Produces a ALT_UART_MCR_RTS register field value suitable for setting the register. */
1549	#define ALT_UART_MCR_RTS_SET(value) (((value) << 1) & 0x00000002)
1550
1551	/*
1552	* Field : Out1 - out1
1553	*
1554	* The value written to this location is inverted and driven out on uart_out1_n
1555	* pin.
1556	*
1557	* Note that in Loopback mode (MCR[4] set to one), the uart_out1_n output is held
1558	* inactive high while the value of this location is internally looped back to an
1559	* input.
1560	*
1561	* Field Enumeration Values:
1562	*
1563	* Enum \| Value \| Description
1564	* :---------------------------\|:------\|:----------------------------------
1565	* ALT_UART_MCR_OUT1_E_LOGIC1 \| 0x0 \| uart_out1_n de-asserted (logic 1)
1566	* ALT_UART_MCR_OUT1_E_LOGIC0 \| 0x1 \| uart_out1_n asserted (logic 0)
1567	*
1568	* Field Access Macros:
1569	*
1570	*/
1571	/*
1572	* Enumerated value for register field ALT_UART_MCR_OUT1
1573	*
1574	* uart_out1_n de-asserted (logic 1)
1575	*/
1576	#define ALT_UART_MCR_OUT1_E_LOGIC1 0x0
1577	/*
1578	* Enumerated value for register field ALT_UART_MCR_OUT1
1579	*
1580	* uart_out1_n asserted (logic 0)
1581	*/
1582	#define ALT_UART_MCR_OUT1_E_LOGIC0 0x1
1583
1584	/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT1 register field. */
1585	#define ALT_UART_MCR_OUT1_LSB 2
1586	/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT1 register field. */
1587	#define ALT_UART_MCR_OUT1_MSB 2
1588	/* The width in bits of the ALT_UART_MCR_OUT1 register field. */
1589	#define ALT_UART_MCR_OUT1_WIDTH 1
1590	/* The mask used to set the ALT_UART_MCR_OUT1 register field value. */
1591	#define ALT_UART_MCR_OUT1_SET_MSK 0x00000004
1592	/* The mask used to clear the ALT_UART_MCR_OUT1 register field value. */
1593	#define ALT_UART_MCR_OUT1_CLR_MSK 0xfffffffb
1594	/* The reset value of the ALT_UART_MCR_OUT1 register field. */
1595	#define ALT_UART_MCR_OUT1_RESET 0x0
1596	/* Extracts the ALT_UART_MCR_OUT1 field value from a register. */
1597	#define ALT_UART_MCR_OUT1_GET(value) (((value) & 0x00000004) >> 2)
1598	/* Produces a ALT_UART_MCR_OUT1 register field value suitable for setting the register. */
1599	#define ALT_UART_MCR_OUT1_SET(value) (((value) << 2) & 0x00000004)
1600
1601	/*
1602	* Field : out2 - out2
1603	*
1604	* This is used to directly control the user-designated uart_out2_n output. The
1605	* value written to this location is inverted and driven out on uart_out2_n
1606	*
1607	* Note: In Loopback mode bit 4 of the modem control register (MCR) is set to one,
1608	* the uart_out2_n output is held inactive high while the value of this location is
1609	* internally looped back to an input.
1610	*
1611	* Field Enumeration Values:
1612	*
1613	* Enum \| Value \| Description
1614	* :---------------------------\|:------\|:----------------------------------
1615	* ALT_UART_MCR_OUT2_E_LOGIC1 \| 0x0 \| uart_out2_n de-asserted (logic 1)
1616	* ALT_UART_MCR_OUT2_E_LOGIC0 \| 0x1 \| uart_out2_n asserted (logic 0)
1617	*
1618	* Field Access Macros:
1619	*
1620	*/
1621	/*
1622	* Enumerated value for register field ALT_UART_MCR_OUT2
1623	*
1624	* uart_out2_n de-asserted (logic 1)
1625	*/
1626	#define ALT_UART_MCR_OUT2_E_LOGIC1 0x0
1627	/*
1628	* Enumerated value for register field ALT_UART_MCR_OUT2
1629	*
1630	* uart_out2_n asserted (logic 0)
1631	*/
1632	#define ALT_UART_MCR_OUT2_E_LOGIC0 0x1
1633
1634	/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT2 register field. */
1635	#define ALT_UART_MCR_OUT2_LSB 3
1636	/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT2 register field. */
1637	#define ALT_UART_MCR_OUT2_MSB 3
1638	/* The width in bits of the ALT_UART_MCR_OUT2 register field. */
1639	#define ALT_UART_MCR_OUT2_WIDTH 1
1640	/* The mask used to set the ALT_UART_MCR_OUT2 register field value. */
1641	#define ALT_UART_MCR_OUT2_SET_MSK 0x00000008
1642	/* The mask used to clear the ALT_UART_MCR_OUT2 register field value. */
1643	#define ALT_UART_MCR_OUT2_CLR_MSK 0xfffffff7
1644	/* The reset value of the ALT_UART_MCR_OUT2 register field. */
1645	#define ALT_UART_MCR_OUT2_RESET 0x0
1646	/* Extracts the ALT_UART_MCR_OUT2 field value from a register. */
1647	#define ALT_UART_MCR_OUT2_GET(value) (((value) & 0x00000008) >> 3)
1648	/* Produces a ALT_UART_MCR_OUT2 register field value suitable for setting the register. */
1649	#define ALT_UART_MCR_OUT2_SET(value) (((value) << 3) & 0x00000008)
1650
1651	/*
1652	* Field : LoopBack Bit - loopback
1653	*
1654	* This is used to put the UART into a diagnostic mode for test purposes. If UART
1655	* mode is NOT active, bit [6] of the modem control register MCR is set to zero,
1656	* data on the sout line is held high, while serial data output is looped back to
1657	* the sin line, internally. In this mode all the interrupts are fully functional.
1658	* Also, in loopback mode, the modem control inputs (uart_dsr_n, uart_cts_n,
1659	* uart_ri_n, uart_dcd_n) are disconnected and the modem control outputs
1660	* (uart_dtr_n, uart_rts_n, uart_out1_n, uart_out2_n) are loopedback to the inputs,
1661	* internally.
1662	*
1663	* Field Access Macros:
1664	*
1665	*/
1666	/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_LOOPBACK register field. */
1667	#define ALT_UART_MCR_LOOPBACK_LSB 4
1668	/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_LOOPBACK register field. */
1669	#define ALT_UART_MCR_LOOPBACK_MSB 4
1670	/* The width in bits of the ALT_UART_MCR_LOOPBACK register field. */
1671	#define ALT_UART_MCR_LOOPBACK_WIDTH 1
1672	/* The mask used to set the ALT_UART_MCR_LOOPBACK register field value. */
1673	#define ALT_UART_MCR_LOOPBACK_SET_MSK 0x00000010
1674	/* The mask used to clear the ALT_UART_MCR_LOOPBACK register field value. */
1675	#define ALT_UART_MCR_LOOPBACK_CLR_MSK 0xffffffef
1676	/* The reset value of the ALT_UART_MCR_LOOPBACK register field. */
1677	#define ALT_UART_MCR_LOOPBACK_RESET 0x0
1678	/* Extracts the ALT_UART_MCR_LOOPBACK field value from a register. */
1679	#define ALT_UART_MCR_LOOPBACK_GET(value) (((value) & 0x00000010) >> 4)
1680	/* Produces a ALT_UART_MCR_LOOPBACK register field value suitable for setting the register. */
1681	#define ALT_UART_MCR_LOOPBACK_SET(value) (((value) << 4) & 0x00000010)
1682
1683	/*
1684	* Field : Auto Flow Control Enable - afce
1685	*
1686	* When FIFOs are enabled, the Auto Flow Control enable bits are active.
1687	*
1688	* Field Enumeration Values:
1689	*
1690	* Enum \| Value \| Description
1691	* :-------------------------\|:------\|:--------------------------------
1692	* ALT_UART_MCR_AFCE_E_DISD \| 0x0 \| Auto Flow Control Mode disabled
1693	* ALT_UART_MCR_AFCE_E_END \| 0x1 \| Auto Flow Control Mode enabled
1694	*
1695	* Field Access Macros:
1696	*
1697	*/
1698	/*
1699	* Enumerated value for register field ALT_UART_MCR_AFCE
1700	*
1701	* Auto Flow Control Mode disabled
1702	*/
1703	#define ALT_UART_MCR_AFCE_E_DISD 0x0
1704	/*
1705	* Enumerated value for register field ALT_UART_MCR_AFCE
1706	*
1707	* Auto Flow Control Mode enabled
1708	*/
1709	#define ALT_UART_MCR_AFCE_E_END 0x1
1710
1711	/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_AFCE register field. */
1712	#define ALT_UART_MCR_AFCE_LSB 5
1713	/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_AFCE register field. */
1714	#define ALT_UART_MCR_AFCE_MSB 5
1715	/* The width in bits of the ALT_UART_MCR_AFCE register field. */
1716	#define ALT_UART_MCR_AFCE_WIDTH 1
1717	/* The mask used to set the ALT_UART_MCR_AFCE register field value. */
1718	#define ALT_UART_MCR_AFCE_SET_MSK 0x00000020
1719	/* The mask used to clear the ALT_UART_MCR_AFCE register field value. */
1720	#define ALT_UART_MCR_AFCE_CLR_MSK 0xffffffdf
1721	/* The reset value of the ALT_UART_MCR_AFCE register field. */
1722	#define ALT_UART_MCR_AFCE_RESET 0x0
1723	/* Extracts the ALT_UART_MCR_AFCE field value from a register. */
1724	#define ALT_UART_MCR_AFCE_GET(value) (((value) & 0x00000020) >> 5)
1725	/* Produces a ALT_UART_MCR_AFCE register field value suitable for setting the register. */
1726	#define ALT_UART_MCR_AFCE_SET(value) (((value) << 5) & 0x00000020)
1727
1728	#ifndef __ASSEMBLY__
1729	/*
1730	* WARNING: The C register and register group struct declarations are provided for
1731	* convenience and illustrative purposes. They should, however, be used with
1732	* caution as the C language standard provides no guarantees about the alignment or
1733	* atomicity of device memory accesses. The recommended practice for writing
1734	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1735	* alt_write_word() functions.
1736	*
1737	* The struct declaration for register ALT_UART_MCR.
1738	*/
1739	struct ALT_UART_MCR_s
1740	{
1741	uint32_t dtr : 1; /* Data Terminal Ready */
1742	uint32_t rts : 1; /* Request to Send */
1743	uint32_t out1 : 1; /* Out1 */
1744	uint32_t out2 : 1; /* out2 */
1745	uint32_t loopback : 1; /* LoopBack Bit */
1746	uint32_t afce : 1; /* Auto Flow Control Enable */
1747	uint32_t : 26; /* UNDEFINED */
1748	};
1749
1750	/* The typedef declaration for register ALT_UART_MCR. */
1751	typedef volatile struct ALT_UART_MCR_s ALT_UART_MCR_t;
1752	#endif /* __ASSEMBLY__ */
1753
1754	/* The byte offset of the ALT_UART_MCR register from the beginning of the component. */
1755	#define ALT_UART_MCR_OFST 0x10
1756	/* The address of the ALT_UART_MCR register. */
1757	#define ALT_UART_MCR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_MCR_OFST))
1758
1759	/*
1760	* Register : Line Status Register - lsr
1761	*
1762	* Reports status of transmit and receive.
1763	*
1764	* Register Layout
1765	*
1766	* Bits \| Access \| Reset \| Description
1767	* :-------\|:-------\|:------\|:------------------------------------
1768	* [0] \| R \| 0x0 \| Data Ready bit
1769	* [1] \| R \| 0x0 \| Overrun error
1770	* [2] \| R \| 0x0 \| Parity Error
1771	* [3] \| R \| 0x0 \| Framing Error
1772	* [4] \| R \| 0x0 \| Break Interrupt
1773	* [5] \| R \| 0x1 \| Transmit Holding Register Empty bit
1774	* [6] \| R \| 0x1 \| Transmitter Empty bit
1775	* [7] \| R \| 0x0 \| Receiver FIFO Error bit
1776	* [31:8] \| ??? \| 0x0 \| UNDEFINED
1777	*
1778	*/
1779	/*
1780	* Field : Data Ready bit - dr
1781	*
1782	* This is used to indicate that the receiver contains at least one character in
1783	* the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the
1784	* non-FIFO mode, or when the receiver FIFO is empty, in the FIFO mode.
1785	*
1786	* Field Enumeration Values:
1787	*
1788	* Enum \| Value \| Description
1789	* :----------------------------\|:------\|:--------------
1790	* ALT_UART_LSR_DR_E_NODATARDY \| 0x0 \| no data ready
1791	* ALT_UART_LSR_DR_E_DATARDY \| 0x1 \| data ready
1792	*
1793	* Field Access Macros:
1794	*
1795	*/
1796	/*
1797	* Enumerated value for register field ALT_UART_LSR_DR
1798	*
1799	* no data ready
1800	*/
1801	#define ALT_UART_LSR_DR_E_NODATARDY 0x0
1802	/*
1803	* Enumerated value for register field ALT_UART_LSR_DR
1804	*
1805	* data ready
1806	*/
1807	#define ALT_UART_LSR_DR_E_DATARDY 0x1
1808
1809	/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_DR register field. */
1810	#define ALT_UART_LSR_DR_LSB 0
1811	/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_DR register field. */
1812	#define ALT_UART_LSR_DR_MSB 0
1813	/* The width in bits of the ALT_UART_LSR_DR register field. */
1814	#define ALT_UART_LSR_DR_WIDTH 1
1815	/* The mask used to set the ALT_UART_LSR_DR register field value. */
1816	#define ALT_UART_LSR_DR_SET_MSK 0x00000001
1817	/* The mask used to clear the ALT_UART_LSR_DR register field value. */
1818	#define ALT_UART_LSR_DR_CLR_MSK 0xfffffffe
1819	/* The reset value of the ALT_UART_LSR_DR register field. */
1820	#define ALT_UART_LSR_DR_RESET 0x0
1821	/* Extracts the ALT_UART_LSR_DR field value from a register. */
1822	#define ALT_UART_LSR_DR_GET(value) (((value) & 0x00000001) >> 0)
1823	/* Produces a ALT_UART_LSR_DR register field value suitable for setting the register. */
1824	#define ALT_UART_LSR_DR_SET(value) (((value) << 0) & 0x00000001)
1825
1826	/*
1827	* Field : Overrun error - oe
1828	*
1829	* This is used to indicate the occurrence of an overrun error. This occurs if a
1830	* new data character was received before the previous data was read. In the non-
1831	* FIFO mode, the OE bit is set when a new character arrives in the receiver before
1832	* the previous character was read from the RBR. When this happens, the data in the
1833	* RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is
1834	* full and new character arrives at the receiver. The data in the FIFO is retained
1835	* and the data in the receive shift register is lost.Reading the LSR clears the OE
1836	* bit.
1837	*
1838	* Field Enumeration Values:
1839	*
1840	* Enum \| Value \| Description
1841	* :----------------------------\|:------\|:-----------------
1842	* ALT_UART_LSR_OE_E_NOOVERRUN \| 0x0 \| no overrun error
1843	* ALT_UART_LSR_OE_E_OVERRUN \| 0x1 \| overrun error
1844	*
1845	* Field Access Macros:
1846	*
1847	*/
1848	/*
1849	* Enumerated value for register field ALT_UART_LSR_OE
1850	*
1851	* no overrun error
1852	*/
1853	#define ALT_UART_LSR_OE_E_NOOVERRUN 0x0
1854	/*
1855	* Enumerated value for register field ALT_UART_LSR_OE
1856	*
1857	* overrun error
1858	*/
1859	#define ALT_UART_LSR_OE_E_OVERRUN 0x1
1860
1861	/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_OE register field. */
1862	#define ALT_UART_LSR_OE_LSB 1
1863	/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_OE register field. */
1864	#define ALT_UART_LSR_OE_MSB 1
1865	/* The width in bits of the ALT_UART_LSR_OE register field. */
1866	#define ALT_UART_LSR_OE_WIDTH 1
1867	/* The mask used to set the ALT_UART_LSR_OE register field value. */
1868	#define ALT_UART_LSR_OE_SET_MSK 0x00000002
1869	/* The mask used to clear the ALT_UART_LSR_OE register field value. */
1870	#define ALT_UART_LSR_OE_CLR_MSK 0xfffffffd
1871	/* The reset value of the ALT_UART_LSR_OE register field. */
1872	#define ALT_UART_LSR_OE_RESET 0x0
1873	/* Extracts the ALT_UART_LSR_OE field value from a register. */
1874	#define ALT_UART_LSR_OE_GET(value) (((value) & 0x00000002) >> 1)
1875	/* Produces a ALT_UART_LSR_OE register field value suitable for setting the register. */
1876	#define ALT_UART_LSR_OE_SET(value) (((value) << 1) & 0x00000002)
1877
1878	/*
1879	* Field : Parity Error - pe
1880	*
1881	* This is used to indicate the occurrence of a parity error in the receiver if the
1882	* Parity Enable (PEN) bit (LCR[3]) is set. Since the parity error is associated
1883	* with a character received, it is revealed when the character with the parity
1884	* error arrives at the top of the FIFO. It should be noted that the Parity Error
1885	* (PE) bit (LSR[2]) will be set if a break interrupt has occurred, as indicated by
1886	* Break Interrupt (BI) bit (LSR[4]). Reading the LSR clears the PE bit.
1887	*
1888	* Field Enumeration Values:
1889	*
1890	* Enum \| Value \| Description
1891	* :------------------------------\|:------\|:----------------
1892	* ALT_UART_LSR_PE_E_NOPARITYERR \| 0x0 \| no parity error
1893	* ALT_UART_LSR_PE_E_PARITYERR \| 0x1 \| no parity error
1894	*
1895	* Field Access Macros:
1896	*
1897	*/
1898	/*
1899	* Enumerated value for register field ALT_UART_LSR_PE
1900	*
1901	* no parity error
1902	*/
1903	#define ALT_UART_LSR_PE_E_NOPARITYERR 0x0
1904	/*
1905	* Enumerated value for register field ALT_UART_LSR_PE
1906	*
1907	* no parity error
1908	*/
1909	#define ALT_UART_LSR_PE_E_PARITYERR 0x1
1910
1911	/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_PE register field. */
1912	#define ALT_UART_LSR_PE_LSB 2
1913	/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_PE register field. */
1914	#define ALT_UART_LSR_PE_MSB 2
1915	/* The width in bits of the ALT_UART_LSR_PE register field. */
1916	#define ALT_UART_LSR_PE_WIDTH 1
1917	/* The mask used to set the ALT_UART_LSR_PE register field value. */
1918	#define ALT_UART_LSR_PE_SET_MSK 0x00000004
1919	/* The mask used to clear the ALT_UART_LSR_PE register field value. */
1920	#define ALT_UART_LSR_PE_CLR_MSK 0xfffffffb
1921	/* The reset value of the ALT_UART_LSR_PE register field. */
1922	#define ALT_UART_LSR_PE_RESET 0x0
1923	/* Extracts the ALT_UART_LSR_PE field value from a register. */
1924	#define ALT_UART_LSR_PE_GET(value) (((value) & 0x00000004) >> 2)
1925	/* Produces a ALT_UART_LSR_PE register field value suitable for setting the register. */
1926	#define ALT_UART_LSR_PE_SET(value) (((value) << 2) & 0x00000004)
1927
1928	/*
1929	* Field : Framing Error - fe
1930	*
1931	* This is used to indicate the occurrence of a framing error in the receiver. A
1932	* framing error occurs when the receiver does not detect a valid STOP bit in the
1933	* received data. In the FIFO mode, since the framing error is associated with a
1934	* character received, it is revealed when the character with the framing error is
1935	* at the top of the FIFO. When a framing error occurs the UART will try to
1936	* resynchronize. It does this by assuming that the error was due to the start bit
1937	* of the next character and then continues receiving the other bit i.e. data,
1938	* and/or parity and stop. It should be noted that the Framing Error (FE)
1939	* bit(LSR[3]) will be set if a break interrupt has occurred, as indicated by a
1940	* Break Interrupt BIT bit (LSR[4]). Reading the LSR clears the FE bit.
1941	*
1942	* Field Enumeration Values:
1943	*
1944	* Enum \| Value \| Description
1945	* :---------------------------\|:------\|:-----------------
1946	* ALT_UART_LSR_FE_E_NOFRMERR \| 0x0 \| no framing error
1947	* ALT_UART_LSR_FE_E_FRMERR \| 0x1 \| framing error
1948	*
1949	* Field Access Macros:
1950	*
1951	*/
1952	/*
1953	* Enumerated value for register field ALT_UART_LSR_FE
1954	*
1955	* no framing error
1956	*/
1957	#define ALT_UART_LSR_FE_E_NOFRMERR 0x0
1958	/*
1959	* Enumerated value for register field ALT_UART_LSR_FE
1960	*
1961	* framing error
1962	*/
1963	#define ALT_UART_LSR_FE_E_FRMERR 0x1
1964
1965	/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_FE register field. */
1966	#define ALT_UART_LSR_FE_LSB 3
1967	/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_FE register field. */
1968	#define ALT_UART_LSR_FE_MSB 3
1969	/* The width in bits of the ALT_UART_LSR_FE register field. */
1970	#define ALT_UART_LSR_FE_WIDTH 1
1971	/* The mask used to set the ALT_UART_LSR_FE register field value. */
1972	#define ALT_UART_LSR_FE_SET_MSK 0x00000008
1973	/* The mask used to clear the ALT_UART_LSR_FE register field value. */
1974	#define ALT_UART_LSR_FE_CLR_MSK 0xfffffff7
1975	/* The reset value of the ALT_UART_LSR_FE register field. */
1976	#define ALT_UART_LSR_FE_RESET 0x0
1977	/* Extracts the ALT_UART_LSR_FE field value from a register. */
1978	#define ALT_UART_LSR_FE_GET(value) (((value) & 0x00000008) >> 3)
1979	/* Produces a ALT_UART_LSR_FE register field value suitable for setting the register. */
1980	#define ALT_UART_LSR_FE_SET(value) (((value) << 3) & 0x00000008)
1981
1982	/*
1983	* Field : Break Interrupt - bi
1984	*
1985	* This is used to indicate the detection of a break sequence on the serial input
1986	* data. Set whenever the serial input, sin, is held in a logic 0 state for longer
1987	* than the sum of start time + data bits + parity + stop bits. A break condition
1988	* on serial input causes one and only one character, consisting of all zeros, to
1989	* be received by the UART. The character associated with the break condition is
1990	* carried through the FIFO and is revealed when the character is at the top of the
1991	* FIFO. Reading the LSR clears the BI bit.
1992	*
1993	* Field Access Macros:
1994	*
1995	*/
1996	/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_BI register field. */
1997	#define ALT_UART_LSR_BI_LSB 4
1998	/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_BI register field. */
1999	#define ALT_UART_LSR_BI_MSB 4
2000	/* The width in bits of the ALT_UART_LSR_BI register field. */
2001	#define ALT_UART_LSR_BI_WIDTH 1
2002	/* The mask used to set the ALT_UART_LSR_BI register field value. */
2003	#define ALT_UART_LSR_BI_SET_MSK 0x00000010
2004	/* The mask used to clear the ALT_UART_LSR_BI register field value. */
2005	#define ALT_UART_LSR_BI_CLR_MSK 0xffffffef
2006	/* The reset value of the ALT_UART_LSR_BI register field. */
2007	#define ALT_UART_LSR_BI_RESET 0x0
2008	/* Extracts the ALT_UART_LSR_BI field value from a register. */
2009	#define ALT_UART_LSR_BI_GET(value) (((value) & 0x00000010) >> 4)
2010	/* Produces a ALT_UART_LSR_BI register field value suitable for setting the register. */
2011	#define ALT_UART_LSR_BI_SET(value) (((value) << 4) & 0x00000010)
2012
2013	/*
2014	* Field : Transmit Holding Register Empty bit - thre
2015	*
2016	* If THRE mode is disabled (IER[7] set to zero) this bit indicates that the THR or
2017	* Tx FIFO is empty. This bit is set whenever data is transferred from the THR or
2018	* Tx FIFO to the transmitter shift register and no new data has been written to
2019	* the THR or Tx FIFO. This also causes a THRE Interrupt to occur, if the THRE
2020	* Interrupt is enabled. If both THRE and FIFOs are enabled, both (IER[7] set to
2021	* one and FCR[0] set to one respectively), the functionality will indicate the
2022	* transmitter FIFO is full, and no longer controls THRE interrupts, which are then
2023	* controlled by the FCR[5:4] thresholdsetting.
2024	*
2025	* Field Access Macros:
2026	*
2027	*/
2028	/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_THRE register field. */
2029	#define ALT_UART_LSR_THRE_LSB 5
2030	/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_THRE register field. */
2031	#define ALT_UART_LSR_THRE_MSB 5
2032	/* The width in bits of the ALT_UART_LSR_THRE register field. */
2033	#define ALT_UART_LSR_THRE_WIDTH 1
2034	/* The mask used to set the ALT_UART_LSR_THRE register field value. */
2035	#define ALT_UART_LSR_THRE_SET_MSK 0x00000020
2036	/* The mask used to clear the ALT_UART_LSR_THRE register field value. */
2037	#define ALT_UART_LSR_THRE_CLR_MSK 0xffffffdf
2038	/* The reset value of the ALT_UART_LSR_THRE register field. */
2039	#define ALT_UART_LSR_THRE_RESET 0x1
2040	/* Extracts the ALT_UART_LSR_THRE field value from a register. */
2041	#define ALT_UART_LSR_THRE_GET(value) (((value) & 0x00000020) >> 5)
2042	/* Produces a ALT_UART_LSR_THRE register field value suitable for setting the register. */
2043	#define ALT_UART_LSR_THRE_SET(value) (((value) << 5) & 0x00000020)
2044
2045	/*
2046	* Field : Transmitter Empty bit - temt
2047	*
2048	* If in FIFO mode and FIFO's enabled (FCR[0] set to one), this bit is set whenever
2049	* the Transmitter Shift Register and the FIFO are both empty. If FIFO's are
2050	* disabled, this bit is set whenever the Transmitter Holding Register and the
2051	* Transmitter Shift Register are both empty.
2052	*
2053	* Field Enumeration Values:
2054	*
2055	* Enum \| Value \| Description
2056	* :-----------------------------\|:------\|:-----------------------
2057	* ALT_UART_LSR_TEMT_E_NOTEMPTY \| 0x0 \| Transmit Empty not set
2058	* ALT_UART_LSR_TEMT_E_EMPTY \| 0x1 \| Transmit Empty set
2059	*
2060	* Field Access Macros:
2061	*
2062	*/
2063	/*
2064	* Enumerated value for register field ALT_UART_LSR_TEMT
2065	*
2066	* Transmit Empty not set
2067	*/
2068	#define ALT_UART_LSR_TEMT_E_NOTEMPTY 0x0
2069	/*
2070	* Enumerated value for register field ALT_UART_LSR_TEMT
2071	*
2072	* Transmit Empty set
2073	*/
2074	#define ALT_UART_LSR_TEMT_E_EMPTY 0x1
2075
2076	/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_TEMT register field. */
2077	#define ALT_UART_LSR_TEMT_LSB 6
2078	/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_TEMT register field. */
2079	#define ALT_UART_LSR_TEMT_MSB 6
2080	/* The width in bits of the ALT_UART_LSR_TEMT register field. */
2081	#define ALT_UART_LSR_TEMT_WIDTH 1
2082	/* The mask used to set the ALT_UART_LSR_TEMT register field value. */
2083	#define ALT_UART_LSR_TEMT_SET_MSK 0x00000040
2084	/* The mask used to clear the ALT_UART_LSR_TEMT register field value. */
2085	#define ALT_UART_LSR_TEMT_CLR_MSK 0xffffffbf
2086	/* The reset value of the ALT_UART_LSR_TEMT register field. */
2087	#define ALT_UART_LSR_TEMT_RESET 0x1
2088	/* Extracts the ALT_UART_LSR_TEMT field value from a register. */
2089	#define ALT_UART_LSR_TEMT_GET(value) (((value) & 0x00000040) >> 6)
2090	/* Produces a ALT_UART_LSR_TEMT register field value suitable for setting the register. */
2091	#define ALT_UART_LSR_TEMT_SET(value) (((value) << 6) & 0x00000040)
2092
2093	/*
2094	* Field : Receiver FIFO Error bit - rfe
2095	*
2096	* This bit is only relevant when FIFO's are enabled (FCR[0] set to one). This is
2097	* used to indicate if there is at least one parity error, framing error, or break
2098	* indication in the FIFO. This bit is cleared when the LSR is read and the
2099	* character with the error is at the top of the receiver FIFO and there are no
2100	* subsequent errors in the FIFO.
2101	*
2102	* Field Enumeration Values:
2103	*
2104	* Enum \| Value \| Description
2105	* :-------------------------\|:------\|:--------------------
2106	* ALT_UART_LSR_RFE_E_NOERR \| 0x0 \| no error in Rx FIFO
2107	* ALT_UART_LSR_RFE_E_ERR \| 0x1 \| error in Rx FIFO
2108	*
2109	* Field Access Macros:
2110	*
2111	*/
2112	/*
2113	* Enumerated value for register field ALT_UART_LSR_RFE
2114	*
2115	* no error in Rx FIFO
2116	*/
2117	#define ALT_UART_LSR_RFE_E_NOERR 0x0
2118	/*
2119	* Enumerated value for register field ALT_UART_LSR_RFE
2120	*
2121	* error in Rx FIFO
2122	*/
2123	#define ALT_UART_LSR_RFE_E_ERR 0x1
2124
2125	/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_RFE register field. */
2126	#define ALT_UART_LSR_RFE_LSB 7
2127	/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_RFE register field. */
2128	#define ALT_UART_LSR_RFE_MSB 7
2129	/* The width in bits of the ALT_UART_LSR_RFE register field. */
2130	#define ALT_UART_LSR_RFE_WIDTH 1
2131	/* The mask used to set the ALT_UART_LSR_RFE register field value. */
2132	#define ALT_UART_LSR_RFE_SET_MSK 0x00000080
2133	/* The mask used to clear the ALT_UART_LSR_RFE register field value. */
2134	#define ALT_UART_LSR_RFE_CLR_MSK 0xffffff7f
2135	/* The reset value of the ALT_UART_LSR_RFE register field. */
2136	#define ALT_UART_LSR_RFE_RESET 0x0
2137	/* Extracts the ALT_UART_LSR_RFE field value from a register. */
2138	#define ALT_UART_LSR_RFE_GET(value) (((value) & 0x00000080) >> 7)
2139	/* Produces a ALT_UART_LSR_RFE register field value suitable for setting the register. */
2140	#define ALT_UART_LSR_RFE_SET(value) (((value) << 7) & 0x00000080)
2141
2142	#ifndef __ASSEMBLY__
2143	/*
2144	* WARNING: The C register and register group struct declarations are provided for
2145	* convenience and illustrative purposes. They should, however, be used with
2146	* caution as the C language standard provides no guarantees about the alignment or
2147	* atomicity of device memory accesses. The recommended practice for writing
2148	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
2149	* alt_write_word() functions.
2150	*
2151	* The struct declaration for register ALT_UART_LSR.
2152	*/
2153	struct ALT_UART_LSR_s
2154	{
2155	const uint32_t dr : 1; /* Data Ready bit */
2156	const uint32_t oe : 1; /* Overrun error */
2157	const uint32_t pe : 1; /* Parity Error */
2158	const uint32_t fe : 1; /* Framing Error */
2159	const uint32_t bi : 1; /* Break Interrupt */
2160	const uint32_t thre : 1; /* Transmit Holding Register Empty bit */
2161	const uint32_t temt : 1; /* Transmitter Empty bit */
2162	const uint32_t rfe : 1; /* Receiver FIFO Error bit */
2163	uint32_t : 24; /* UNDEFINED */
2164	};
2165
2166	/* The typedef declaration for register ALT_UART_LSR. */
2167	typedef volatile struct ALT_UART_LSR_s ALT_UART_LSR_t;
2168	#endif /* __ASSEMBLY__ */
2169
2170	/* The byte offset of the ALT_UART_LSR register from the beginning of the component. */
2171	#define ALT_UART_LSR_OFST 0x14
2172	/* The address of the ALT_UART_LSR register. */
2173	#define ALT_UART_LSR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_LSR_OFST))
2174
2175	/*
2176	* Register : Modem Status Register - msr
2177	*
2178	* It should be noted that whenever bits 0, 1, 2 or 3 are set to logic one, to
2179	* indicate a change on the modem control inputs, a modem status interrupt will be
2180	* generated if enabled via the IER regardless of when the change occurred. Since
2181	* the delta bits (bits 0, 1, 3) can get set after a reset if their respective
2182	* modem signals are active (see individual bits for details), a read of the MSR
2183	* after reset can be performed to prevent unwanted interrupts.
2184	*
2185	* Register Layout
2186	*
2187	* Bits \| Access \| Reset \| Description
2188	* :-------\|:-------\|:------\|:--------------------------------
2189	* [0] \| R \| 0x0 \| Delta Clear to Send
2190	* [1] \| R \| 0x0 \| Delta Data Set Ready
2191	* [2] \| R \| 0x0 \| Trailing Edge of Ring Indicator
2192	* [3] \| R \| 0x0 \| Delta Data Carrier Detect
2193	* [4] \| R \| 0x0 \| Clear to Send
2194	* [5] \| R \| 0x0 \| Data Set Ready
2195	* [6] \| R \| 0x0 \| Ring Indicator
2196	* [7] \| R \| 0x0 \| Data Carrier Detect
2197	* [31:8] \| ??? \| 0x0 \| UNDEFINED
2198	*
2199	*/
2200	/*
2201	* Field : Delta Clear to Send - dcts
2202	*
2203	* This is used to indicate that the modem control line uart_cts_n has changed
2204	* since the last time the MSR was read. That is: Reading the MSR clears the DCTS
2205	* bit. In Loopback Mode bit [4] of MCR set to one, DCTS reflects changes on bit
2206	* [1] RTS of register MCR.
2207	*
2208	* Note: If the DCTS bit is not set and the uart_cts_n signal is asserted (low) and
2209	* a reset occurs (software or otherwise), then the DCTS bit will get set when the
2210	* reset is removed if the uart_cts_n signal remains asserted.
2211	*
2212	* Field Enumeration Values:
2213	*
2214	* Enum \| Value \| Description
2215	* :--------------------------\|:------\|:-----------------------------------------------
2216	* ALT_UART_MSR_DCTS_E_NOCHG \| 0x0 \| no change on uart_cts_n since last read of MSR
2217	* ALT_UART_MSR_DCTS_E_CHG \| 0x1 \| change on uart_cts_n since last read of MSR
2218	*
2219	* Field Access Macros:
2220	*
2221	*/
2222	/*
2223	* Enumerated value for register field ALT_UART_MSR_DCTS
2224	*
2225	* no change on uart_cts_n since last read of MSR
2226	*/
2227	#define ALT_UART_MSR_DCTS_E_NOCHG 0x0
2228	/*
2229	* Enumerated value for register field ALT_UART_MSR_DCTS
2230	*
2231	* change on uart_cts_n since last read of MSR
2232	*/
2233	#define ALT_UART_MSR_DCTS_E_CHG 0x1
2234
2235	/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCTS register field. */
2236	#define ALT_UART_MSR_DCTS_LSB 0
2237	/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCTS register field. */
2238	#define ALT_UART_MSR_DCTS_MSB 0
2239	/* The width in bits of the ALT_UART_MSR_DCTS register field. */
2240	#define ALT_UART_MSR_DCTS_WIDTH 1
2241	/* The mask used to set the ALT_UART_MSR_DCTS register field value. */
2242	#define ALT_UART_MSR_DCTS_SET_MSK 0x00000001
2243	/* The mask used to clear the ALT_UART_MSR_DCTS register field value. */
2244	#define ALT_UART_MSR_DCTS_CLR_MSK 0xfffffffe
2245	/* The reset value of the ALT_UART_MSR_DCTS register field. */
2246	#define ALT_UART_MSR_DCTS_RESET 0x0
2247	/* Extracts the ALT_UART_MSR_DCTS field value from a register. */
2248	#define ALT_UART_MSR_DCTS_GET(value) (((value) & 0x00000001) >> 0)
2249	/* Produces a ALT_UART_MSR_DCTS register field value suitable for setting the register. */
2250	#define ALT_UART_MSR_DCTS_SET(value) (((value) << 0) & 0x00000001)
2251
2252	/*
2253	* Field : Delta Data Set Ready - ddsr
2254	*
2255	* This is used to indicate that the modem control line uart_dsr_n has changed
2256	* since the last time the MSR was read. Reading the MSR clears the DDSR bit.In
2257	* Loopback Mode (MCR[4] set to one), DDSR reflects changes on bit [0] DTR of
2258	* register MCR .
2259	*
2260	* Note, if the DDSR bit is not set and the uart_dsr_n signal is asserted (low) and
2261	* a reset occurs (software or otherwise), then the DDSR bit will get set when the
2262	* reset is removed if the uart_dsr_n signal remains asserted.
2263	*
2264	* Field Enumeration Values:
2265	*
2266	* Enum \| Value \| Description
2267	* :--------------------------\|:------\|:-----------------------------------------------
2268	* ALT_UART_MSR_DDSR_E_NOCHG \| 0x0 \| no change on uart_dsr_n since last read of MSR
2269	* ALT_UART_MSR_DDSR_E_CHG \| 0x1 \| change on uart_dsr_n since last read of MSR
2270	*
2271	* Field Access Macros:
2272	*
2273	*/
2274	/*
2275	* Enumerated value for register field ALT_UART_MSR_DDSR
2276	*
2277	* no change on uart_dsr_n since last read of MSR
2278	*/
2279	#define ALT_UART_MSR_DDSR_E_NOCHG 0x0
2280	/*
2281	* Enumerated value for register field ALT_UART_MSR_DDSR
2282	*
2283	* change on uart_dsr_n since last read of MSR
2284	*/
2285	#define ALT_UART_MSR_DDSR_E_CHG 0x1
2286
2287	/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDSR register field. */
2288	#define ALT_UART_MSR_DDSR_LSB 1
2289	/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDSR register field. */
2290	#define ALT_UART_MSR_DDSR_MSB 1
2291	/* The width in bits of the ALT_UART_MSR_DDSR register field. */
2292	#define ALT_UART_MSR_DDSR_WIDTH 1
2293	/* The mask used to set the ALT_UART_MSR_DDSR register field value. */
2294	#define ALT_UART_MSR_DDSR_SET_MSK 0x00000002
2295	/* The mask used to clear the ALT_UART_MSR_DDSR register field value. */
2296	#define ALT_UART_MSR_DDSR_CLR_MSK 0xfffffffd
2297	/* The reset value of the ALT_UART_MSR_DDSR register field. */
2298	#define ALT_UART_MSR_DDSR_RESET 0x0
2299	/* Extracts the ALT_UART_MSR_DDSR field value from a register. */
2300	#define ALT_UART_MSR_DDSR_GET(value) (((value) & 0x00000002) >> 1)
2301	/* Produces a ALT_UART_MSR_DDSR register field value suitable for setting the register. */
2302	#define ALT_UART_MSR_DDSR_SET(value) (((value) << 1) & 0x00000002)
2303
2304	/*
2305	* Field : Trailing Edge of Ring Indicator - teri
2306	*
2307	* This is used to indicate that a change on the input uart_ri_n (from an active
2308	* low, to an inactive high state) has occurred since the last time the MSR was
2309	* read. Reading the MSR clears the TERI bit. In Loopback Mode bit [4] of register
2310	* MCR is set to one, TERI reflects when bit [2] of register MCR has changed state
2311	* from a high to a low.
2312	*
2313	* Field Enumeration Values:
2314	*
2315	* Enum \| Value \| Description
2316	* :--------------------------\|:------\|:----------------------------------------------
2317	* ALT_UART_MSR_TERI_E_NOCHG \| 0x0 \| no change on uart_ri_n since last read of MSR
2318	* ALT_UART_MSR_TERI_E_CHG \| 0x1 \| change on uart_ri_n since last read of MSR
2319	*
2320	* Field Access Macros:
2321	*
2322	*/
2323	/*
2324	* Enumerated value for register field ALT_UART_MSR_TERI
2325	*
2326	* no change on uart_ri_n since last read of MSR
2327	*/
2328	#define ALT_UART_MSR_TERI_E_NOCHG 0x0
2329	/*
2330	* Enumerated value for register field ALT_UART_MSR_TERI
2331	*
2332	* change on uart_ri_n since last read of MSR
2333	*/
2334	#define ALT_UART_MSR_TERI_E_CHG 0x1
2335
2336	/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_TERI register field. */
2337	#define ALT_UART_MSR_TERI_LSB 2
2338	/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_TERI register field. */
2339	#define ALT_UART_MSR_TERI_MSB 2
2340	/* The width in bits of the ALT_UART_MSR_TERI register field. */
2341	#define ALT_UART_MSR_TERI_WIDTH 1
2342	/* The mask used to set the ALT_UART_MSR_TERI register field value. */
2343	#define ALT_UART_MSR_TERI_SET_MSK 0x00000004
2344	/* The mask used to clear the ALT_UART_MSR_TERI register field value. */
2345	#define ALT_UART_MSR_TERI_CLR_MSK 0xfffffffb
2346	/* The reset value of the ALT_UART_MSR_TERI register field. */
2347	#define ALT_UART_MSR_TERI_RESET 0x0
2348	/* Extracts the ALT_UART_MSR_TERI field value from a register. */
2349	#define ALT_UART_MSR_TERI_GET(value) (((value) & 0x00000004) >> 2)
2350	/* Produces a ALT_UART_MSR_TERI register field value suitable for setting the register. */
2351	#define ALT_UART_MSR_TERI_SET(value) (((value) << 2) & 0x00000004)
2352
2353	/*
2354	* Field : Delta Data Carrier Detect - ddcd
2355	*
2356	* This is used to indicate that the modem control line dcd_n has changed since the
2357	* last time the MSR was read. Reading the MSR clears the DDCD bit. In Loopback
2358	* Mode bit [4] of register MCR is set to one, DDCD reflects changes bit [3]
2359	* uart_out2 of register MCR.
2360	*
2361	* Note: If the DDCD bit is not set and the uart_dcd_n signal is asserted (low) and
2362	* a reset occurs (software or otherwise), then the DDCD bit will get set when the
2363	* reset is removed if the uart_dcd_n signal remains asserted.
2364	*
2365	* Field Enumeration Values:
2366	*
2367	* Enum \| Value \| Description
2368	* :--------------------------\|:------\|:-----------------------------------------------
2369	* ALT_UART_MSR_DDCD_E_NOCHG \| 0x0 \| no change on uart_dcd_n since last read of MSR
2370	* ALT_UART_MSR_DDCD_E_CHG \| 0x1 \| change on uart_dcd_n since last read of MSR
2371	*
2372	* Field Access Macros:
2373	*
2374	*/
2375	/*
2376	* Enumerated value for register field ALT_UART_MSR_DDCD
2377	*
2378	* no change on uart_dcd_n since last read of MSR
2379	*/
2380	#define ALT_UART_MSR_DDCD_E_NOCHG 0x0
2381	/*
2382	* Enumerated value for register field ALT_UART_MSR_DDCD
2383	*
2384	* change on uart_dcd_n since last read of MSR
2385	*/
2386	#define ALT_UART_MSR_DDCD_E_CHG 0x1
2387
2388	/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDCD register field. */
2389	#define ALT_UART_MSR_DDCD_LSB 3
2390	/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDCD register field. */
2391	#define ALT_UART_MSR_DDCD_MSB 3
2392	/* The width in bits of the ALT_UART_MSR_DDCD register field. */
2393	#define ALT_UART_MSR_DDCD_WIDTH 1
2394	/* The mask used to set the ALT_UART_MSR_DDCD register field value. */
2395	#define ALT_UART_MSR_DDCD_SET_MSK 0x00000008
2396	/* The mask used to clear the ALT_UART_MSR_DDCD register field value. */
2397	#define ALT_UART_MSR_DDCD_CLR_MSK 0xfffffff7
2398	/* The reset value of the ALT_UART_MSR_DDCD register field. */
2399	#define ALT_UART_MSR_DDCD_RESET 0x0
2400	/* Extracts the ALT_UART_MSR_DDCD field value from a register. */
2401	#define ALT_UART_MSR_DDCD_GET(value) (((value) & 0x00000008) >> 3)
2402	/* Produces a ALT_UART_MSR_DDCD register field value suitable for setting the register. */
2403	#define ALT_UART_MSR_DDCD_SET(value) (((value) << 3) & 0x00000008)
2404
2405	/*
2406	* Field : Clear to Send - cts
2407	*
2408	* This is used to indicate the current state of the modem control line uart_cts_n.
2409	* That is, this bit is the complement uart_cts_n. When the Clear to Send input
2410	* (uart_cts_n) is asserted it is an indication that the modem or data set is ready
2411	* to exchange data with the uart. In Loopback Mode bit [4] of register MCR is set
2412	* to one, CTS is the same as bit [1] RTS of register MCR.
2413	*
2414	* Field Enumeration Values:
2415	*
2416	* Enum \| Value \| Description
2417	* :--------------------------\|:------\|:------------------------------------------
2418	* ALT_UART_MSR_CTS_E_LOGIC1 \| 0x0 \| uart_cts_n input is de-asserted (logic 1)
2419	* ALT_UART_MSR_CTS_E_LOGIC0 \| 0x1 \| uart_cts_n input is asserted (logic 0)
2420	*
2421	* Field Access Macros:
2422	*
2423	*/
2424	/*
2425	* Enumerated value for register field ALT_UART_MSR_CTS
2426	*
2427	* uart_cts_n input is de-asserted (logic 1)
2428	*/
2429	#define ALT_UART_MSR_CTS_E_LOGIC1 0x0
2430	/*
2431	* Enumerated value for register field ALT_UART_MSR_CTS
2432	*
2433	* uart_cts_n input is asserted (logic 0)
2434	*/
2435	#define ALT_UART_MSR_CTS_E_LOGIC0 0x1
2436
2437	/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_CTS register field. */
2438	#define ALT_UART_MSR_CTS_LSB 4
2439	/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_CTS register field. */
2440	#define ALT_UART_MSR_CTS_MSB 4
2441	/* The width in bits of the ALT_UART_MSR_CTS register field. */
2442	#define ALT_UART_MSR_CTS_WIDTH 1
2443	/* The mask used to set the ALT_UART_MSR_CTS register field value. */
2444	#define ALT_UART_MSR_CTS_SET_MSK 0x00000010
2445	/* The mask used to clear the ALT_UART_MSR_CTS register field value. */
2446	#define ALT_UART_MSR_CTS_CLR_MSK 0xffffffef
2447	/* The reset value of the ALT_UART_MSR_CTS register field. */
2448	#define ALT_UART_MSR_CTS_RESET 0x0
2449	/* Extracts the ALT_UART_MSR_CTS field value from a register. */
2450	#define ALT_UART_MSR_CTS_GET(value) (((value) & 0x00000010) >> 4)
2451	/* Produces a ALT_UART_MSR_CTS register field value suitable for setting the register. */
2452	#define ALT_UART_MSR_CTS_SET(value) (((value) << 4) & 0x00000010)
2453
2454	/*
2455	* Field : Data Set Ready - dsr
2456	*
2457	* This is used to indicate the current state of the modem control line uart_dsr_n.
2458	* That is this bit is the complement f uart_dsr_n. When the Data Set Ready input
2459	* (uart_dsr_n) is asserted it is an indication that the modem or data set is ready
2460	* to establish communications with the uart. In Loopback Mode bit [4] of register
2461	* MCR is set to one, DSR is the same as bit [0] (DTR) of register MCR.
2462	*
2463	* Field Enumeration Values:
2464	*
2465	* Enum \| Value \| Description
2466	* :--------------------------\|:------\|:------------------------------------------
2467	* ALT_UART_MSR_DSR_E_LOGIC1 \| 0x0 \| uart_dsr_n input is de-asserted (logic 1)
2468	* ALT_UART_MSR_DSR_E_LOGIC0 \| 0x1 \| uart_dsr_n input is asserted (logic 0)
2469	*
2470	* Field Access Macros:
2471	*
2472	*/
2473	/*
2474	* Enumerated value for register field ALT_UART_MSR_DSR
2475	*
2476	* uart_dsr_n input is de-asserted (logic 1)
2477	*/
2478	#define ALT_UART_MSR_DSR_E_LOGIC1 0x0
2479	/*
2480	* Enumerated value for register field ALT_UART_MSR_DSR
2481	*
2482	* uart_dsr_n input is asserted (logic 0)
2483	*/
2484	#define ALT_UART_MSR_DSR_E_LOGIC0 0x1
2485
2486	/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DSR register field. */
2487	#define ALT_UART_MSR_DSR_LSB 5
2488	/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DSR register field. */
2489	#define ALT_UART_MSR_DSR_MSB 5
2490	/* The width in bits of the ALT_UART_MSR_DSR register field. */
2491	#define ALT_UART_MSR_DSR_WIDTH 1
2492	/* The mask used to set the ALT_UART_MSR_DSR register field value. */
2493	#define ALT_UART_MSR_DSR_SET_MSK 0x00000020
2494	/* The mask used to clear the ALT_UART_MSR_DSR register field value. */
2495	#define ALT_UART_MSR_DSR_CLR_MSK 0xffffffdf
2496	/* The reset value of the ALT_UART_MSR_DSR register field. */
2497	#define ALT_UART_MSR_DSR_RESET 0x0
2498	/* Extracts the ALT_UART_MSR_DSR field value from a register. */
2499	#define ALT_UART_MSR_DSR_GET(value) (((value) & 0x00000020) >> 5)
2500	/* Produces a ALT_UART_MSR_DSR register field value suitable for setting the register. */
2501	#define ALT_UART_MSR_DSR_SET(value) (((value) << 5) & 0x00000020)
2502
2503	/*
2504	* Field : Ring Indicator - ri
2505	*
2506	* This bit is used to indicate the current state of the modem control line
2507	* uart_ri_n. That is this bit is the complement uart_ri_n. When the Ring Indicator
2508	* input (uart_ri_n) is asserted it is an indication that a telephone ringing
2509	* signal has been received by the modem or data set. In Loopback Mode bit [4] of
2510	* register MCR set to one, RI is the same as bit [2] uart_out1_n of register MCR.
2511	*
2512	* Field Enumeration Values:
2513	*
2514	* Enum \| Value \| Description
2515	* :-------------------------\|:------\|:-----------------------------------------
2516	* ALT_UART_MSR_RI_E_LOGIC1 \| 0x0 \| uart_ri_n input is de-asserted (logic 1)
2517	* ALT_UART_MSR_RI_E_LOGIC0 \| 0x1 \| uart_ri_n input is asserted (logic 0)
2518	*
2519	* Field Access Macros:
2520	*
2521	*/
2522	/*
2523	* Enumerated value for register field ALT_UART_MSR_RI
2524	*
2525	* uart_ri_n input is de-asserted (logic 1)
2526	*/
2527	#define ALT_UART_MSR_RI_E_LOGIC1 0x0
2528	/*
2529	* Enumerated value for register field ALT_UART_MSR_RI
2530	*
2531	* uart_ri_n input is asserted (logic 0)
2532	*/
2533	#define ALT_UART_MSR_RI_E_LOGIC0 0x1
2534
2535	/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_RI register field. */
2536	#define ALT_UART_MSR_RI_LSB 6
2537	/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_RI register field. */
2538	#define ALT_UART_MSR_RI_MSB 6
2539	/* The width in bits of the ALT_UART_MSR_RI register field. */
2540	#define ALT_UART_MSR_RI_WIDTH 1
2541	/* The mask used to set the ALT_UART_MSR_RI register field value. */
2542	#define ALT_UART_MSR_RI_SET_MSK 0x00000040
2543	/* The mask used to clear the ALT_UART_MSR_RI register field value. */
2544	#define ALT_UART_MSR_RI_CLR_MSK 0xffffffbf
2545	/* The reset value of the ALT_UART_MSR_RI register field. */
2546	#define ALT_UART_MSR_RI_RESET 0x0
2547	/* Extracts the ALT_UART_MSR_RI field value from a register. */
2548	#define ALT_UART_MSR_RI_GET(value) (((value) & 0x00000040) >> 6)
2549	/* Produces a ALT_UART_MSR_RI register field value suitable for setting the register. */
2550	#define ALT_UART_MSR_RI_SET(value) (((value) << 6) & 0x00000040)
2551
2552	/*
2553	* Field : Data Carrier Detect - dcd
2554	*
2555	* This is used to indicate the current state of the modem control line uart_dcd_n.
2556	* That is this bit is the complement uart_dcd_n. When the Data Carrier Detect
2557	* input (uart_dcd_n) is asserted it is an indication that the carrier has been
2558	* detected by the modem or data set. In Loopback Mode (MCR[4] set to one), DCD is
2559	* the same as MCR[3] (uart_out2).
2560	*
2561	* Field Enumeration Values:
2562	*
2563	* Enum \| Value \| Description
2564	* :--------------------------\|:------\|:------------------------------------------
2565	* ALT_UART_MSR_DCD_E_LOGIC1 \| 0x0 \| uart_dcd_n input is de-asserted (logic 1)
2566	* ALT_UART_MSR_DCD_E_LOGIC0 \| 0x1 \| uart_dcd_n input is asserted (logic 0)
2567	*
2568	* Field Access Macros:
2569	*
2570	*/
2571	/*
2572	* Enumerated value for register field ALT_UART_MSR_DCD
2573	*
2574	* uart_dcd_n input is de-asserted (logic 1)
2575	*/
2576	#define ALT_UART_MSR_DCD_E_LOGIC1 0x0
2577	/*
2578	* Enumerated value for register field ALT_UART_MSR_DCD
2579	*
2580	* uart_dcd_n input is asserted (logic 0)
2581	*/
2582	#define ALT_UART_MSR_DCD_E_LOGIC0 0x1
2583
2584	/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCD register field. */
2585	#define ALT_UART_MSR_DCD_LSB 7
2586	/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCD register field. */
2587	#define ALT_UART_MSR_DCD_MSB 7
2588	/* The width in bits of the ALT_UART_MSR_DCD register field. */
2589	#define ALT_UART_MSR_DCD_WIDTH 1
2590	/* The mask used to set the ALT_UART_MSR_DCD register field value. */
2591	#define ALT_UART_MSR_DCD_SET_MSK 0x00000080
2592	/* The mask used to clear the ALT_UART_MSR_DCD register field value. */
2593	#define ALT_UART_MSR_DCD_CLR_MSK 0xffffff7f
2594	/* The reset value of the ALT_UART_MSR_DCD register field. */
2595	#define ALT_UART_MSR_DCD_RESET 0x0
2596	/* Extracts the ALT_UART_MSR_DCD field value from a register. */
2597	#define ALT_UART_MSR_DCD_GET(value) (((value) & 0x00000080) >> 7)
2598	/* Produces a ALT_UART_MSR_DCD register field value suitable for setting the register. */
2599	#define ALT_UART_MSR_DCD_SET(value) (((value) << 7) & 0x00000080)
2600
2601	#ifndef __ASSEMBLY__
2602	/*
2603	* WARNING: The C register and register group struct declarations are provided for
2604	* convenience and illustrative purposes. They should, however, be used with
2605	* caution as the C language standard provides no guarantees about the alignment or
2606	* atomicity of device memory accesses. The recommended practice for writing
2607	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
2608	* alt_write_word() functions.
2609	*
2610	* The struct declaration for register ALT_UART_MSR.
2611	*/
2612	struct ALT_UART_MSR_s
2613	{
2614	const uint32_t dcts : 1; /* Delta Clear to Send */
2615	const uint32_t ddsr : 1; /* Delta Data Set Ready */
2616	const uint32_t teri : 1; /* Trailing Edge of Ring Indicator */
2617	const uint32_t ddcd : 1; /* Delta Data Carrier Detect */
2618	const uint32_t cts : 1; /* Clear to Send */
2619	const uint32_t dsr : 1; /* Data Set Ready */
2620	const uint32_t ri : 1; /* Ring Indicator */
2621	const uint32_t dcd : 1; /* Data Carrier Detect */
2622	uint32_t : 24; /* UNDEFINED */
2623	};
2624
2625	/* The typedef declaration for register ALT_UART_MSR. */
2626	typedef volatile struct ALT_UART_MSR_s ALT_UART_MSR_t;
2627	#endif /* __ASSEMBLY__ */
2628
2629	/* The byte offset of the ALT_UART_MSR register from the beginning of the component. */
2630	#define ALT_UART_MSR_OFST 0x18
2631	/* The address of the ALT_UART_MSR register. */
2632	#define ALT_UART_MSR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_MSR_OFST))
2633
2634	/*
2635	* Register : Scratchpad Register - scr
2636	*
2637	* Scratchpad Register
2638	*
2639	* Register Layout
2640	*
2641	* Bits \| Access \| Reset \| Description
2642	* :-------\|:-------\|:------\|:--------------------
2643	* [7:0] \| RW \| 0x0 \| Scratchpad Register
2644	* [31:8] \| ??? \| 0x0 \| UNDEFINED
2645	*
2646	*/
2647	/*
2648	* Field : Scratchpad Register - scr
2649	*
2650	* This register is for programmers to use as a temporary storage space.
2651	*
2652	* Field Access Macros:
2653	*
2654	*/
2655	/* The Least Significant Bit (LSB) position of the ALT_UART_SCR_SCR register field. */
2656	#define ALT_UART_SCR_SCR_LSB 0
2657	/* The Most Significant Bit (MSB) position of the ALT_UART_SCR_SCR register field. */
2658	#define ALT_UART_SCR_SCR_MSB 7
2659	/* The width in bits of the ALT_UART_SCR_SCR register field. */
2660	#define ALT_UART_SCR_SCR_WIDTH 8
2661	/* The mask used to set the ALT_UART_SCR_SCR register field value. */
2662	#define ALT_UART_SCR_SCR_SET_MSK 0x000000ff
2663	/* The mask used to clear the ALT_UART_SCR_SCR register field value. */
2664	#define ALT_UART_SCR_SCR_CLR_MSK 0xffffff00
2665	/* The reset value of the ALT_UART_SCR_SCR register field. */
2666	#define ALT_UART_SCR_SCR_RESET 0x0
2667	/* Extracts the ALT_UART_SCR_SCR field value from a register. */
2668	#define ALT_UART_SCR_SCR_GET(value) (((value) & 0x000000ff) >> 0)
2669	/* Produces a ALT_UART_SCR_SCR register field value suitable for setting the register. */
2670	#define ALT_UART_SCR_SCR_SET(value) (((value) << 0) & 0x000000ff)
2671
2672	#ifndef __ASSEMBLY__
2673	/*
2674	* WARNING: The C register and register group struct declarations are provided for
2675	* convenience and illustrative purposes. They should, however, be used with
2676	* caution as the C language standard provides no guarantees about the alignment or
2677	* atomicity of device memory accesses. The recommended practice for writing
2678	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
2679	* alt_write_word() functions.
2680	*
2681	* The struct declaration for register ALT_UART_SCR.
2682	*/
2683	struct ALT_UART_SCR_s
2684	{
2685	uint32_t scr : 8; /* Scratchpad Register */
2686	uint32_t : 24; /* UNDEFINED */
2687	};
2688
2689	/* The typedef declaration for register ALT_UART_SCR. */
2690	typedef volatile struct ALT_UART_SCR_s ALT_UART_SCR_t;
2691	#endif /* __ASSEMBLY__ */
2692
2693	/* The byte offset of the ALT_UART_SCR register from the beginning of the component. */
2694	#define ALT_UART_SCR_OFST 0x1c
2695	/* The address of the ALT_UART_SCR register. */
2696	#define ALT_UART_SCR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_SCR_OFST))
2697
2698	/*
2699	* Register : Shadow Receive Buffer Register - srbr
2700	*
2701	* Used to accomadate burst accesses from the master.
2702	*
2703	* Register Layout
2704	*
2705	* Bits \| Access \| Reset \| Description
2706	* :-------\|:-------\|:------\|:----------------------
2707	* [7:0] \| RW \| 0x0 \| Shadow Receive Buffer
2708	* [31:8] \| ??? \| 0x0 \| UNDEFINED
2709	*
2710	*/
2711	/*
2712	* Field : Shadow Receive Buffer - srbr
2713	*
2714	* This is a shadow register for the RBR and has been allocated one 32-bit location
2715	* so as to accommodate burst accesses from the master.This register contains the
2716	* data byte received on the serial input port (sin). The data in this register is
2717	* valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set.
2718	* If FIFOs are disabled, bit [0] of register FCR set to zero, the data in the RBR
2719	* must be read before the next data arrives, otherwise it will be overwritten,
2720	* resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this
2721	* register accesses the head of the receive FIFO. If the receive FIFO is full and
2722	* this register is not read before the next data character arrives, then the data
2723	* already in the FIFO will be preserved but any incoming data will be lost. An
2724	* overrun error will also occur.
2725	*
2726	* Field Access Macros:
2727	*
2728	*/
2729	/* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_SRBR register field. */
2730	#define ALT_UART_SRBR_SRBR_LSB 0
2731	/* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_SRBR register field. */
2732	#define ALT_UART_SRBR_SRBR_MSB 7
2733	/* The width in bits of the ALT_UART_SRBR_SRBR register field. */
2734	#define ALT_UART_SRBR_SRBR_WIDTH 8
2735	/* The mask used to set the ALT_UART_SRBR_SRBR register field value. */
2736	#define ALT_UART_SRBR_SRBR_SET_MSK 0x000000ff
2737	/* The mask used to clear the ALT_UART_SRBR_SRBR register field value. */
2738	#define ALT_UART_SRBR_SRBR_CLR_MSK 0xffffff00
2739	/* The reset value of the ALT_UART_SRBR_SRBR register field. */
2740	#define ALT_UART_SRBR_SRBR_RESET 0x0
2741	/* Extracts the ALT_UART_SRBR_SRBR field value from a register. */
2742	#define ALT_UART_SRBR_SRBR_GET(value) (((value) & 0x000000ff) >> 0)
2743	/* Produces a ALT_UART_SRBR_SRBR register field value suitable for setting the register. */
2744	#define ALT_UART_SRBR_SRBR_SET(value) (((value) << 0) & 0x000000ff)
2745
2746	#ifndef __ASSEMBLY__
2747	/*
2748	* WARNING: The C register and register group struct declarations are provided for
2749	* convenience and illustrative purposes. They should, however, be used with
2750	* caution as the C language standard provides no guarantees about the alignment or
2751	* atomicity of device memory accesses. The recommended practice for writing
2752	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
2753	* alt_write_word() functions.
2754	*
2755	* The struct declaration for register ALT_UART_SRBR.
2756	*/
2757	struct ALT_UART_SRBR_s
2758	{
2759	uint32_t srbr : 8; /* Shadow Receive Buffer */
2760	uint32_t : 24; /* UNDEFINED */
2761	};
2762
2763	/* The typedef declaration for register ALT_UART_SRBR. */
2764	typedef volatile struct ALT_UART_SRBR_s ALT_UART_SRBR_t;
2765	#endif /* __ASSEMBLY__ */
2766
2767	/* The byte offset of the ALT_UART_SRBR register from the beginning of the component. */
2768	#define ALT_UART_SRBR_OFST 0x30
2769	/* The address of the ALT_UART_SRBR register. */
2770	#define ALT_UART_SRBR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_SRBR_OFST))
2771
2772	/*
2773	* Register : Shadow Transmit Buffer Register - sthr
2774	*
2775	* Used to accomadate burst accesses from the master.
2776	*
2777	* Register Layout
2778	*
2779	* Bits \| Access \| Reset \| Description
2780	* :-------\|:-------\|:------\|:-----------------------
2781	* [7:0] \| RW \| 0x0 \| Shadow Transmit Buffer
2782	* [31:8] \| ??? \| 0x0 \| UNDEFINED
2783	*
2784	*/
2785	/*
2786	* Field : Shadow Transmit Buffer - sthr
2787	*
2788	* This is a shadow register for the THR and has been allocated sixteen 32-bit
2789	* locations so as to accommodate burst accesses from the master. This register
2790	* contains data to be transmitted on the serial output port (sout). Data should
2791	* only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If
2792	* FIFO's are disabled bit [0] of register FCR set to zero and THRE is set, writing
2793	* a single character to the THR clears the THRE. Any additional writes to the THR
2794	* before the THRE is set again causes the THR data to be overwritten. If FIFO's
2795	* are enabled bit [0] of register FCR set to one and THRE is set, 128 characters
2796	* of data may be written to the THR before the FIFO is full. The UART FIFO depth
2797	* is configured for 128 characters. Any attempt to write data when the FIFO is
2798	* full results in the write data being lost.
2799	*
2800	* Field Access Macros:
2801	*
2802	*/
2803	/* The Least Significant Bit (LSB) position of the ALT_UART_STHR_STHR register field. */
2804	#define ALT_UART_STHR_STHR_LSB 0
2805	/* The Most Significant Bit (MSB) position of the ALT_UART_STHR_STHR register field. */
2806	#define ALT_UART_STHR_STHR_MSB 7
2807	/* The width in bits of the ALT_UART_STHR_STHR register field. */
2808	#define ALT_UART_STHR_STHR_WIDTH 8
2809	/* The mask used to set the ALT_UART_STHR_STHR register field value. */
2810	#define ALT_UART_STHR_STHR_SET_MSK 0x000000ff
2811	/* The mask used to clear the ALT_UART_STHR_STHR register field value. */
2812	#define ALT_UART_STHR_STHR_CLR_MSK 0xffffff00
2813	/* The reset value of the ALT_UART_STHR_STHR register field. */
2814	#define ALT_UART_STHR_STHR_RESET 0x0
2815	/* Extracts the ALT_UART_STHR_STHR field value from a register. */
2816	#define ALT_UART_STHR_STHR_GET(value) (((value) & 0x000000ff) >> 0)
2817	/* Produces a ALT_UART_STHR_STHR register field value suitable for setting the register. */
2818	#define ALT_UART_STHR_STHR_SET(value) (((value) << 0) & 0x000000ff)
2819
2820	#ifndef __ASSEMBLY__
2821	/*
2822	* WARNING: The C register and register group struct declarations are provided for
2823	* convenience and illustrative purposes. They should, however, be used with
2824	* caution as the C language standard provides no guarantees about the alignment or
2825	* atomicity of device memory accesses. The recommended practice for writing
2826	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
2827	* alt_write_word() functions.
2828	*
2829	* The struct declaration for register ALT_UART_STHR.
2830	*/
2831	struct ALT_UART_STHR_s
2832	{
2833	uint32_t sthr : 8; /* Shadow Transmit Buffer */
2834	uint32_t : 24; /* UNDEFINED */
2835	};
2836
2837	/* The typedef declaration for register ALT_UART_STHR. */
2838	typedef volatile struct ALT_UART_STHR_s ALT_UART_STHR_t;
2839	#endif /* __ASSEMBLY__ */
2840
2841	/* The byte offset of the ALT_UART_STHR register from the beginning of the component. */
2842	#define ALT_UART_STHR_OFST 0x34
2843	/* The address of the ALT_UART_STHR register. */
2844	#define ALT_UART_STHR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_STHR_OFST))
2845
2846	/*
2847	* Register : FIFO Access Register - far
2848	*
2849	* This register is used in FIFO access testing.
2850	*
2851	* Register Layout
2852	*
2853	* Bits \| Access \| Reset \| Description
2854	* :-------\|:-------\|:------\|:----------------
2855	* [0] \| RW \| 0x0 \| FIFO ACCESS Bit
2856	* [31:1] \| ??? \| 0x0 \| UNDEFINED
2857	*
2858	*/
2859	/*
2860	* Field : FIFO ACCESS Bit - srbr_sthr
2861	*
2862	* This register is used to enable a FIFO access mode for testing, so that the
2863	* receive FIFO can be written by the master and the transmit FIFO can be read by
2864	* the master when FIFO's are enabled. When FIFO's are not enabled it allows the
2865	* RBR to be written by the master and the THR to be read by the master
2866	*
2867	* Note: That when the FIFO access mode is enabled/disabled, the control portion of
2868	* the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty.
2869	*
2870	* Field Enumeration Values:
2871	*
2872	* Enum \| Value \| Description
2873	* :------------------------------\|:------\|:--------------------------
2874	* ALT_UART_FAR_SRBR_STHR_E_DISD \| 0x0 \| FIFO access mode disabled
2875	* ALT_UART_FAR_SRBR_STHR_E_END \| 0x1 \| FIFO access mode enabled
2876	*
2877	* Field Access Macros:
2878	*
2879	*/
2880	/*
2881	* Enumerated value for register field ALT_UART_FAR_SRBR_STHR
2882	*
2883	* FIFO access mode disabled
2884	*/
2885	#define ALT_UART_FAR_SRBR_STHR_E_DISD 0x0
2886	/*
2887	* Enumerated value for register field ALT_UART_FAR_SRBR_STHR
2888	*
2889	* FIFO access mode enabled
2890	*/
2891	#define ALT_UART_FAR_SRBR_STHR_E_END 0x1
2892
2893	/* The Least Significant Bit (LSB) position of the ALT_UART_FAR_SRBR_STHR register field. */
2894	#define ALT_UART_FAR_SRBR_STHR_LSB 0
2895	/* The Most Significant Bit (MSB) position of the ALT_UART_FAR_SRBR_STHR register field. */
2896	#define ALT_UART_FAR_SRBR_STHR_MSB 0
2897	/* The width in bits of the ALT_UART_FAR_SRBR_STHR register field. */
2898	#define ALT_UART_FAR_SRBR_STHR_WIDTH 1
2899	/* The mask used to set the ALT_UART_FAR_SRBR_STHR register field value. */
2900	#define ALT_UART_FAR_SRBR_STHR_SET_MSK 0x00000001
2901	/* The mask used to clear the ALT_UART_FAR_SRBR_STHR register field value. */
2902	#define ALT_UART_FAR_SRBR_STHR_CLR_MSK 0xfffffffe
2903	/* The reset value of the ALT_UART_FAR_SRBR_STHR register field. */
2904	#define ALT_UART_FAR_SRBR_STHR_RESET 0x0
2905	/* Extracts the ALT_UART_FAR_SRBR_STHR field value from a register. */
2906	#define ALT_UART_FAR_SRBR_STHR_GET(value) (((value) & 0x00000001) >> 0)
2907	/* Produces a ALT_UART_FAR_SRBR_STHR register field value suitable for setting the register. */
2908	#define ALT_UART_FAR_SRBR_STHR_SET(value) (((value) << 0) & 0x00000001)
2909
2910	#ifndef __ASSEMBLY__
2911	/*
2912	* WARNING: The C register and register group struct declarations are provided for
2913	* convenience and illustrative purposes. They should, however, be used with
2914	* caution as the C language standard provides no guarantees about the alignment or
2915	* atomicity of device memory accesses. The recommended practice for writing
2916	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
2917	* alt_write_word() functions.
2918	*
2919	* The struct declaration for register ALT_UART_FAR.
2920	*/
2921	struct ALT_UART_FAR_s
2922	{
2923	uint32_t srbr_sthr : 1; /* FIFO ACCESS Bit */
2924	uint32_t : 31; /* UNDEFINED */
2925	};
2926
2927	/* The typedef declaration for register ALT_UART_FAR. */
2928	typedef volatile struct ALT_UART_FAR_s ALT_UART_FAR_t;
2929	#endif /* __ASSEMBLY__ */
2930
2931	/* The byte offset of the ALT_UART_FAR register from the beginning of the component. */
2932	#define ALT_UART_FAR_OFST 0x70
2933	/* The address of the ALT_UART_FAR register. */
2934	#define ALT_UART_FAR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_FAR_OFST))
2935
2936	/*
2937	* Register : Transmit FIFO Read Register - tfr
2938	*
2939	* Used in FIFO Access test mode.
2940	*
2941	* Register Layout
2942	*
2943	* Bits \| Access \| Reset \| Description
2944	* :-------\|:-------\|:------\|:-------------------
2945	* [7:0] \| R \| 0x0 \| Transmit FIFO Read
2946	* [31:8] \| ??? \| 0x0 \| UNDEFINED
2947	*
2948	*/
2949	/*
2950	* Field : Transmit FIFO Read - tfr
2951	*
2952	* These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
2953	* one). When FIFO's are enabled, reading this register gives the data at the top
2954	* of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the
2955	* next data value that is currently at the top of the FIFO. When FIFO's are not
2956	* enabled, reading this register gives the data in the THR.
2957	*
2958	* Field Access Macros:
2959	*
2960	*/
2961	/* The Least Significant Bit (LSB) position of the ALT_UART_TFR_TFR register field. */
2962	#define ALT_UART_TFR_TFR_LSB 0
2963	/* The Most Significant Bit (MSB) position of the ALT_UART_TFR_TFR register field. */
2964	#define ALT_UART_TFR_TFR_MSB 7
2965	/* The width in bits of the ALT_UART_TFR_TFR register field. */
2966	#define ALT_UART_TFR_TFR_WIDTH 8
2967	/* The mask used to set the ALT_UART_TFR_TFR register field value. */
2968	#define ALT_UART_TFR_TFR_SET_MSK 0x000000ff
2969	/* The mask used to clear the ALT_UART_TFR_TFR register field value. */
2970	#define ALT_UART_TFR_TFR_CLR_MSK 0xffffff00
2971	/* The reset value of the ALT_UART_TFR_TFR register field. */
2972	#define ALT_UART_TFR_TFR_RESET 0x0
2973	/* Extracts the ALT_UART_TFR_TFR field value from a register. */
2974	#define ALT_UART_TFR_TFR_GET(value) (((value) & 0x000000ff) >> 0)
2975	/* Produces a ALT_UART_TFR_TFR register field value suitable for setting the register. */
2976	#define ALT_UART_TFR_TFR_SET(value) (((value) << 0) & 0x000000ff)
2977
2978	#ifndef __ASSEMBLY__
2979	/*
2980	* WARNING: The C register and register group struct declarations are provided for
2981	* convenience and illustrative purposes. They should, however, be used with
2982	* caution as the C language standard provides no guarantees about the alignment or
2983	* atomicity of device memory accesses. The recommended practice for writing
2984	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
2985	* alt_write_word() functions.
2986	*
2987	* The struct declaration for register ALT_UART_TFR.
2988	*/
2989	struct ALT_UART_TFR_s
2990	{
2991	const uint32_t tfr : 8; /* Transmit FIFO Read */
2992	uint32_t : 24; /* UNDEFINED */
2993	};
2994
2995	/* The typedef declaration for register ALT_UART_TFR. */
2996	typedef volatile struct ALT_UART_TFR_s ALT_UART_TFR_t;
2997	#endif /* __ASSEMBLY__ */
2998
2999	/* The byte offset of the ALT_UART_TFR register from the beginning of the component. */
3000	#define ALT_UART_TFR_OFST 0x74
3001	/* The address of the ALT_UART_TFR register. */
3002	#define ALT_UART_TFR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_TFR_OFST))
3003
3004	/*
3005	* Register : Receive FIFO Write - RFW
3006	*
3007	* Used only with FIFO access test mode.
3008	*
3009	* Register Layout
3010	*
3011	* Bits \| Access \| Reset \| Description
3012	* :--------\|:-------\|:------\|:---------------------------
3013	* [7:0] \| W \| 0x0 \| Receive FIFO Write Field
3014	* [8] \| W \| 0x0 \| Receive FIFO Parity Error
3015	* [9] \| W \| 0x0 \| Receive FIFO Framing Error
3016	* [31:10] \| ??? \| 0x0 \| UNDEFINED
3017	*
3018	*/
3019	/*
3020	* Field : Receive FIFO Write Field - rfwd
3021	*
3022	* These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
3023	* one). When FIFO's are enabled, the data that is written to the RFWD is pushed
3024	* into the receive FIFO. Each consecutive write pushes the new data to the next
3025	* write location in the receive FIFO. When FIFO's are not enabled, the data that
3026	* is written to the RFWD is pushed into the RBR.
3027	*
3028	* Field Access Macros:
3029	*
3030	*/
3031	/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFWD register field. */
3032	#define ALT_UART_RFW_RFWD_LSB 0
3033	/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFWD register field. */
3034	#define ALT_UART_RFW_RFWD_MSB 7
3035	/* The width in bits of the ALT_UART_RFW_RFWD register field. */
3036	#define ALT_UART_RFW_RFWD_WIDTH 8
3037	/* The mask used to set the ALT_UART_RFW_RFWD register field value. */
3038	#define ALT_UART_RFW_RFWD_SET_MSK 0x000000ff
3039	/* The mask used to clear the ALT_UART_RFW_RFWD register field value. */
3040	#define ALT_UART_RFW_RFWD_CLR_MSK 0xffffff00
3041	/* The reset value of the ALT_UART_RFW_RFWD register field. */
3042	#define ALT_UART_RFW_RFWD_RESET 0x0
3043	/* Extracts the ALT_UART_RFW_RFWD field value from a register. */
3044	#define ALT_UART_RFW_RFWD_GET(value) (((value) & 0x000000ff) >> 0)
3045	/* Produces a ALT_UART_RFW_RFWD register field value suitable for setting the register. */
3046	#define ALT_UART_RFW_RFWD_SET(value) (((value) << 0) & 0x000000ff)
3047
3048	/*
3049	* Field : Receive FIFO Parity Error - rfpe
3050	*
3051	* These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
3052	* one). When FIFO's are enabled, this bit is used to write parity error detection
3053	* information to the receive FIFO. When FIFO's are not enabled, this bit is used
3054	* to write parity error detection information to the RBR.
3055	*
3056	* Field Access Macros:
3057	*
3058	*/
3059	/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFPE register field. */
3060	#define ALT_UART_RFW_RFPE_LSB 8
3061	/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFPE register field. */
3062	#define ALT_UART_RFW_RFPE_MSB 8
3063	/* The width in bits of the ALT_UART_RFW_RFPE register field. */
3064	#define ALT_UART_RFW_RFPE_WIDTH 1
3065	/* The mask used to set the ALT_UART_RFW_RFPE register field value. */
3066	#define ALT_UART_RFW_RFPE_SET_MSK 0x00000100
3067	/* The mask used to clear the ALT_UART_RFW_RFPE register field value. */
3068	#define ALT_UART_RFW_RFPE_CLR_MSK 0xfffffeff
3069	/* The reset value of the ALT_UART_RFW_RFPE register field. */
3070	#define ALT_UART_RFW_RFPE_RESET 0x0
3071	/* Extracts the ALT_UART_RFW_RFPE field value from a register. */
3072	#define ALT_UART_RFW_RFPE_GET(value) (((value) & 0x00000100) >> 8)
3073	/* Produces a ALT_UART_RFW_RFPE register field value suitable for setting the register. */
3074	#define ALT_UART_RFW_RFPE_SET(value) (((value) << 8) & 0x00000100)
3075
3076	/*
3077	* Field : Receive FIFO Framing Error - RFFE
3078	*
3079	* These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
3080	* one). When FIFO's are enabled, this bit is used to write framing error detection
3081	* information to the receive FIFO. When FIFO's are not enabled, this bit is used
3082	* to write framing error detection information to the RBR.
3083	*
3084	* Field Access Macros:
3085	*
3086	*/
3087	/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFFE register field. */
3088	#define ALT_UART_RFW_RFFE_LSB 9
3089	/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFFE register field. */
3090	#define ALT_UART_RFW_RFFE_MSB 9
3091	/* The width in bits of the ALT_UART_RFW_RFFE register field. */
3092	#define ALT_UART_RFW_RFFE_WIDTH 1
3093	/* The mask used to set the ALT_UART_RFW_RFFE register field value. */
3094	#define ALT_UART_RFW_RFFE_SET_MSK 0x00000200
3095	/* The mask used to clear the ALT_UART_RFW_RFFE register field value. */
3096	#define ALT_UART_RFW_RFFE_CLR_MSK 0xfffffdff
3097	/* The reset value of the ALT_UART_RFW_RFFE register field. */
3098	#define ALT_UART_RFW_RFFE_RESET 0x0
3099	/* Extracts the ALT_UART_RFW_RFFE field value from a register. */
3100	#define ALT_UART_RFW_RFFE_GET(value) (((value) & 0x00000200) >> 9)
3101	/* Produces a ALT_UART_RFW_RFFE register field value suitable for setting the register. */
3102	#define ALT_UART_RFW_RFFE_SET(value) (((value) << 9) & 0x00000200)
3103
3104	#ifndef __ASSEMBLY__
3105	/*
3106	* WARNING: The C register and register group struct declarations are provided for
3107	* convenience and illustrative purposes. They should, however, be used with
3108	* caution as the C language standard provides no guarantees about the alignment or
3109	* atomicity of device memory accesses. The recommended practice for writing
3110	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
3111	* alt_write_word() functions.
3112	*
3113	* The struct declaration for register ALT_UART_RFW.
3114	*/
3115	struct ALT_UART_RFW_s
3116	{
3117	uint32_t rfwd : 8; /* Receive FIFO Write Field */
3118	uint32_t rfpe : 1; /* Receive FIFO Parity Error */
3119	uint32_t RFFE : 1; /* Receive FIFO Framing Error */
3120	uint32_t : 22; /* UNDEFINED */
3121	};
3122
3123	/* The typedef declaration for register ALT_UART_RFW. */
3124	typedef volatile struct ALT_UART_RFW_s ALT_UART_RFW_t;
3125	#endif /* __ASSEMBLY__ */
3126
3127	/* The byte offset of the ALT_UART_RFW register from the beginning of the component. */
3128	#define ALT_UART_RFW_OFST 0x78
3129	/* The address of the ALT_UART_RFW register. */
3130	#define ALT_UART_RFW_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_RFW_OFST))
3131
3132	/*
3133	* Register : UART Status Register - usr
3134	*
3135	* Status of FIFO Operations.
3136	*
3137	* Register Layout
3138	*
3139	* Bits \| Access \| Reset \| Description
3140	* :-------\|:-------\|:------\|:-----------------------
3141	* [0] \| ??? \| 0x0 \| UNDEFINED
3142	* [1] \| R \| 0x1 \| Transmit FIFO Not Full
3143	* [2] \| R \| 0x1 \| Transmit FIFO Empty
3144	* [3] \| R \| 0x0 \| Receive FIFO Not Empty
3145	* [4] \| R \| 0x0 \| Receive FIFO Full
3146	* [31:5] \| ??? \| 0x0 \| UNDEFINED
3147	*
3148	*/
3149	/*
3150	* Field : Transmit FIFO Not Full - tfnf
3151	*
3152	* This Bit is used to indicate that the transmit FIFO in not full. This bit is
3153	* cleared when the Tx FIFO is full.
3154	*
3155	* Field Enumeration Values:
3156	*
3157	* Enum \| Value \| Description
3158	* :----------------------------\|:------\|:--------------------------
3159	* ALT_UART_USR_TFNF_E_FULL \| 0x0 \| Transmit FIFO is full
3160	* ALT_UART_USR_TFNF_E_NOTFULL \| 0x1 \| Transmit FIFO is not full
3161	*
3162	* Field Access Macros:
3163	*
3164	*/
3165	/*
3166	* Enumerated value for register field ALT_UART_USR_TFNF
3167	*
3168	* Transmit FIFO is full
3169	*/
3170	#define ALT_UART_USR_TFNF_E_FULL 0x0
3171	/*
3172	* Enumerated value for register field ALT_UART_USR_TFNF
3173	*
3174	* Transmit FIFO is not full
3175	*/
3176	#define ALT_UART_USR_TFNF_E_NOTFULL 0x1
3177
3178	/* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFNF register field. */
3179	#define ALT_UART_USR_TFNF_LSB 1
3180	/* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFNF register field. */
3181	#define ALT_UART_USR_TFNF_MSB 1
3182	/* The width in bits of the ALT_UART_USR_TFNF register field. */
3183	#define ALT_UART_USR_TFNF_WIDTH 1
3184	/* The mask used to set the ALT_UART_USR_TFNF register field value. */
3185	#define ALT_UART_USR_TFNF_SET_MSK 0x00000002
3186	/* The mask used to clear the ALT_UART_USR_TFNF register field value. */
3187	#define ALT_UART_USR_TFNF_CLR_MSK 0xfffffffd
3188	/* The reset value of the ALT_UART_USR_TFNF register field. */
3189	#define ALT_UART_USR_TFNF_RESET 0x1
3190	/* Extracts the ALT_UART_USR_TFNF field value from a register. */
3191	#define ALT_UART_USR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
3192	/* Produces a ALT_UART_USR_TFNF register field value suitable for setting the register. */
3193	#define ALT_UART_USR_TFNF_SET(value) (((value) << 1) & 0x00000002)
3194
3195	/*
3196	* Field : Transmit FIFO Empty - tfe
3197	*
3198	* This is used to indicate that the transmit FIFO is completely empty. This bit is
3199	* cleared when the Tx FIFO is no longer empty.
3200	*
3201	* Field Enumeration Values:
3202	*
3203	* Enum \| Value \| Description
3204	* :----------------------------\|:------\|:---------------------------
3205	* ALT_UART_USR_TFE_E_NOTEMPTY \| 0x0 \| Transmit FIFO is not empty
3206	* ALT_UART_USR_TFE_E_EMPTY \| 0x1 \| Transmit FIFO is empty
3207	*
3208	* Field Access Macros:
3209	*
3210	*/
3211	/*
3212	* Enumerated value for register field ALT_UART_USR_TFE
3213	*
3214	* Transmit FIFO is not empty
3215	*/
3216	#define ALT_UART_USR_TFE_E_NOTEMPTY 0x0
3217	/*
3218	* Enumerated value for register field ALT_UART_USR_TFE
3219	*
3220	* Transmit FIFO is empty
3221	*/
3222	#define ALT_UART_USR_TFE_E_EMPTY 0x1
3223
3224	/* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFE register field. */
3225	#define ALT_UART_USR_TFE_LSB 2
3226	/* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFE register field. */
3227	#define ALT_UART_USR_TFE_MSB 2
3228	/* The width in bits of the ALT_UART_USR_TFE register field. */
3229	#define ALT_UART_USR_TFE_WIDTH 1
3230	/* The mask used to set the ALT_UART_USR_TFE register field value. */
3231	#define ALT_UART_USR_TFE_SET_MSK 0x00000004
3232	/* The mask used to clear the ALT_UART_USR_TFE register field value. */
3233	#define ALT_UART_USR_TFE_CLR_MSK 0xfffffffb
3234	/* The reset value of the ALT_UART_USR_TFE register field. */
3235	#define ALT_UART_USR_TFE_RESET 0x1
3236	/* Extracts the ALT_UART_USR_TFE field value from a register. */
3237	#define ALT_UART_USR_TFE_GET(value) (((value) & 0x00000004) >> 2)
3238	/* Produces a ALT_UART_USR_TFE register field value suitable for setting the register. */
3239	#define ALT_UART_USR_TFE_SET(value) (((value) << 2) & 0x00000004)
3240
3241	/*
3242	* Field : Receive FIFO Not Empty - rfne
3243	*
3244	* This Bit is used to indicate that the receive FIFO contains one or more entries.
3245	* This bit is cleared when the Rx FIFO is empty.
3246	*
3247	* Field Enumeration Values:
3248	*
3249	* Enum \| Value \| Description
3250	* :-----------------------------\|:------\|:--------------------------
3251	* ALT_UART_USR_RFNE_E_EMPTY \| 0x0 \| Receiive FIFO is empty
3252	* ALT_UART_USR_RFNE_E_NOTEMPTY \| 0x1 \| Receive FIFO is not empty
3253	*
3254	* Field Access Macros:
3255	*
3256	*/
3257	/*
3258	* Enumerated value for register field ALT_UART_USR_RFNE
3259	*
3260	* Receiive FIFO is empty
3261	*/
3262	#define ALT_UART_USR_RFNE_E_EMPTY 0x0
3263	/*
3264	* Enumerated value for register field ALT_UART_USR_RFNE
3265	*
3266	* Receive FIFO is not empty
3267	*/
3268	#define ALT_UART_USR_RFNE_E_NOTEMPTY 0x1
3269
3270	/* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFNE register field. */
3271	#define ALT_UART_USR_RFNE_LSB 3
3272	/* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFNE register field. */
3273	#define ALT_UART_USR_RFNE_MSB 3
3274	/* The width in bits of the ALT_UART_USR_RFNE register field. */
3275	#define ALT_UART_USR_RFNE_WIDTH 1
3276	/* The mask used to set the ALT_UART_USR_RFNE register field value. */
3277	#define ALT_UART_USR_RFNE_SET_MSK 0x00000008
3278	/* The mask used to clear the ALT_UART_USR_RFNE register field value. */
3279	#define ALT_UART_USR_RFNE_CLR_MSK 0xfffffff7
3280	/* The reset value of the ALT_UART_USR_RFNE register field. */
3281	#define ALT_UART_USR_RFNE_RESET 0x0
3282	/* Extracts the ALT_UART_USR_RFNE field value from a register. */
3283	#define ALT_UART_USR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
3284	/* Produces a ALT_UART_USR_RFNE register field value suitable for setting the register. */
3285	#define ALT_UART_USR_RFNE_SET(value) (((value) << 3) & 0x00000008)
3286
3287	/*
3288	* Field : Receive FIFO Full - rff
3289	*
3290	* This Bit is used to indicate that the receive FIFO is completely full. This bit
3291	* is cleared when the Rx FIFO is no longer full.
3292	*
3293	* Field Enumeration Values:
3294	*
3295	* Enum \| Value \| Description
3296	* :---------------------------\|:------\|:-----------------------
3297	* ALT_UART_USR_RFF_E_NOTFULL \| 0x0 \| Receiive FIFO not full
3298	* ALT_UART_USR_RFF_E_FULL \| 0x1 \| Transmit FIFO is full
3299	*
3300	* Field Access Macros:
3301	*
3302	*/
3303	/*
3304	* Enumerated value for register field ALT_UART_USR_RFF
3305	*
3306	* Receiive FIFO not full
3307	*/
3308	#define ALT_UART_USR_RFF_E_NOTFULL 0x0
3309	/*
3310	* Enumerated value for register field ALT_UART_USR_RFF
3311	*
3312	* Transmit FIFO is full
3313	*/
3314	#define ALT_UART_USR_RFF_E_FULL 0x1
3315
3316	/* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFF register field. */
3317	#define ALT_UART_USR_RFF_LSB 4
3318	/* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFF register field. */
3319	#define ALT_UART_USR_RFF_MSB 4
3320	/* The width in bits of the ALT_UART_USR_RFF register field. */
3321	#define ALT_UART_USR_RFF_WIDTH 1
3322	/* The mask used to set the ALT_UART_USR_RFF register field value. */
3323	#define ALT_UART_USR_RFF_SET_MSK 0x00000010
3324	/* The mask used to clear the ALT_UART_USR_RFF register field value. */
3325	#define ALT_UART_USR_RFF_CLR_MSK 0xffffffef
3326	/* The reset value of the ALT_UART_USR_RFF register field. */
3327	#define ALT_UART_USR_RFF_RESET 0x0
3328	/* Extracts the ALT_UART_USR_RFF field value from a register. */
3329	#define ALT_UART_USR_RFF_GET(value) (((value) & 0x00000010) >> 4)
3330	/* Produces a ALT_UART_USR_RFF register field value suitable for setting the register. */
3331	#define ALT_UART_USR_RFF_SET(value) (((value) << 4) & 0x00000010)
3332
3333	#ifndef __ASSEMBLY__
3334	/*
3335	* WARNING: The C register and register group struct declarations are provided for
3336	* convenience and illustrative purposes. They should, however, be used with
3337	* caution as the C language standard provides no guarantees about the alignment or
3338	* atomicity of device memory accesses. The recommended practice for writing
3339	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
3340	* alt_write_word() functions.
3341	*
3342	* The struct declaration for register ALT_UART_USR.
3343	*/
3344	struct ALT_UART_USR_s
3345	{
3346	uint32_t : 1; /* UNDEFINED */
3347	const uint32_t tfnf : 1; /* Transmit FIFO Not Full */
3348	const uint32_t tfe : 1; /* Transmit FIFO Empty */
3349	const uint32_t rfne : 1; /* Receive FIFO Not Empty */
3350	const uint32_t rff : 1; /* Receive FIFO Full */
3351	uint32_t : 27; /* UNDEFINED */
3352	};
3353
3354	/* The typedef declaration for register ALT_UART_USR. */
3355	typedef volatile struct ALT_UART_USR_s ALT_UART_USR_t;
3356	#endif /* __ASSEMBLY__ */
3357
3358	/* The byte offset of the ALT_UART_USR register from the beginning of the component. */
3359	#define ALT_UART_USR_OFST 0x7c
3360	/* The address of the ALT_UART_USR register. */
3361	#define ALT_UART_USR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_USR_OFST))
3362
3363	/*
3364	* Register : Transmit FIFO Level - tfl
3365	*
3366	* This register is used to specify the number of data entries in the Tx FIFO.
3367	* Status Bits in USR register monitor the FIFO state.
3368	*
3369	* Register Layout
3370	*
3371	* Bits \| Access \| Reset \| Description
3372	* :-------\|:-------\|:------\|:--------------------
3373	* [4:0] \| R \| 0x0 \| Transmit FIFO Level
3374	* [31:5] \| ??? \| 0x0 \| UNDEFINED
3375	*
3376	*/
3377	/*
3378	* Field : Transmit FIFO Level - tfl
3379	*
3380	* This indicates the number of data entries in the transmit FIFO.
3381	*
3382	* Field Access Macros:
3383	*
3384	*/
3385	/* The Least Significant Bit (LSB) position of the ALT_UART_TFL_TFL register field. */
3386	#define ALT_UART_TFL_TFL_LSB 0
3387	/* The Most Significant Bit (MSB) position of the ALT_UART_TFL_TFL register field. */
3388	#define ALT_UART_TFL_TFL_MSB 4
3389	/* The width in bits of the ALT_UART_TFL_TFL register field. */
3390	#define ALT_UART_TFL_TFL_WIDTH 5
3391	/* The mask used to set the ALT_UART_TFL_TFL register field value. */
3392	#define ALT_UART_TFL_TFL_SET_MSK 0x0000001f
3393	/* The mask used to clear the ALT_UART_TFL_TFL register field value. */
3394	#define ALT_UART_TFL_TFL_CLR_MSK 0xffffffe0
3395	/* The reset value of the ALT_UART_TFL_TFL register field. */
3396	#define ALT_UART_TFL_TFL_RESET 0x0
3397	/* Extracts the ALT_UART_TFL_TFL field value from a register. */
3398	#define ALT_UART_TFL_TFL_GET(value) (((value) & 0x0000001f) >> 0)
3399	/* Produces a ALT_UART_TFL_TFL register field value suitable for setting the register. */
3400	#define ALT_UART_TFL_TFL_SET(value) (((value) << 0) & 0x0000001f)
3401
3402	#ifndef __ASSEMBLY__
3403	/*
3404	* WARNING: The C register and register group struct declarations are provided for
3405	* convenience and illustrative purposes. They should, however, be used with
3406	* caution as the C language standard provides no guarantees about the alignment or
3407	* atomicity of device memory accesses. The recommended practice for writing
3408	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
3409	* alt_write_word() functions.
3410	*
3411	* The struct declaration for register ALT_UART_TFL.
3412	*/
3413	struct ALT_UART_TFL_s
3414	{
3415	const uint32_t tfl : 5; /* Transmit FIFO Level */
3416	uint32_t : 27; /* UNDEFINED */
3417	};
3418
3419	/* The typedef declaration for register ALT_UART_TFL. */
3420	typedef volatile struct ALT_UART_TFL_s ALT_UART_TFL_t;
3421	#endif /* __ASSEMBLY__ */
3422
3423	/* The byte offset of the ALT_UART_TFL register from the beginning of the component. */
3424	#define ALT_UART_TFL_OFST 0x80
3425	/* The address of the ALT_UART_TFL register. */
3426	#define ALT_UART_TFL_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_TFL_OFST))
3427
3428	/*
3429	* Register : Receive FIFO Level Write - rfl
3430	*
3431	* This register is used to specify the number of data entries in the Tx FIFO.
3432	* Status Bits in USR register monitor the FIFO state.
3433	*
3434	* Register Layout
3435	*
3436	* Bits \| Access \| Reset \| Description
3437	* :-------\|:-------\|:------\|:--------------------------
3438	* [4:0] \| R \| 0x0 \| Receive FIFO Level Status
3439	* [31:5] \| ??? \| 0x0 \| UNDEFINED
3440	*
3441	*/
3442	/*
3443	* Field : Receive FIFO Level Status - rfl
3444	*
3445	* This indicates the number of data entries in the receive FIFO.
3446	*
3447	* Field Access Macros:
3448	*
3449	*/
3450	/* The Least Significant Bit (LSB) position of the ALT_UART_RFL_RFL register field. */
3451	#define ALT_UART_RFL_RFL_LSB 0
3452	/* The Most Significant Bit (MSB) position of the ALT_UART_RFL_RFL register field. */
3453	#define ALT_UART_RFL_RFL_MSB 4
3454	/* The width in bits of the ALT_UART_RFL_RFL register field. */
3455	#define ALT_UART_RFL_RFL_WIDTH 5
3456	/* The mask used to set the ALT_UART_RFL_RFL register field value. */
3457	#define ALT_UART_RFL_RFL_SET_MSK 0x0000001f
3458	/* The mask used to clear the ALT_UART_RFL_RFL register field value. */
3459	#define ALT_UART_RFL_RFL_CLR_MSK 0xffffffe0
3460	/* The reset value of the ALT_UART_RFL_RFL register field. */
3461	#define ALT_UART_RFL_RFL_RESET 0x0
3462	/* Extracts the ALT_UART_RFL_RFL field value from a register. */
3463	#define ALT_UART_RFL_RFL_GET(value) (((value) & 0x0000001f) >> 0)
3464	/* Produces a ALT_UART_RFL_RFL register field value suitable for setting the register. */
3465	#define ALT_UART_RFL_RFL_SET(value) (((value) << 0) & 0x0000001f)
3466
3467	#ifndef __ASSEMBLY__
3468	/*
3469	* WARNING: The C register and register group struct declarations are provided for
3470	* convenience and illustrative purposes. They should, however, be used with
3471	* caution as the C language standard provides no guarantees about the alignment or
3472	* atomicity of device memory accesses. The recommended practice for writing
3473	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
3474	* alt_write_word() functions.
3475	*
3476	* The struct declaration for register ALT_UART_RFL.
3477	*/
3478	struct ALT_UART_RFL_s
3479	{
3480	const uint32_t rfl : 5; /* Receive FIFO Level Status */
3481	uint32_t : 27; /* UNDEFINED */
3482	};
3483
3484	/* The typedef declaration for register ALT_UART_RFL. */
3485	typedef volatile struct ALT_UART_RFL_s ALT_UART_RFL_t;
3486	#endif /* __ASSEMBLY__ */
3487
3488	/* The byte offset of the ALT_UART_RFL register from the beginning of the component. */
3489	#define ALT_UART_RFL_OFST 0x84
3490	/* The address of the ALT_UART_RFL register. */
3491	#define ALT_UART_RFL_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_RFL_OFST))
3492
3493	/*
3494	* Register : Software Reset Register - srr
3495	*
3496	* Provides Software Resets for Tx/Rx FIFO's and the uart.
3497	*
3498	* Register Layout
3499	*
3500	* Bits \| Access \| Reset \| Description
3501	* :-------\|:-------\|:------\|:--------------
3502	* [0] \| W \| 0x0 \| UART Reset
3503	* [1] \| W \| 0x0 \| Rx FIFO Reset
3504	* [2] \| W \| 0x0 \| Tx FIFO Reset
3505	* [31:3] \| ??? \| 0x0 \| UNDEFINED
3506	*
3507	*/
3508	/*
3509	* Field : UART Reset - ur
3510	*
3511	* This asynchronously resets the UART and synchronously removes the reset
3512	* assertion.
3513	*
3514	* Field Enumeration Values:
3515	*
3516	* Enum \| Value \| Description
3517	* :------------------------\|:------\|:--------------
3518	* ALT_UART_SRR_UR_E_NORST \| 0x0 \| No reset Uart
3519	* ALT_UART_SRR_UR_E_RST \| 0x1 \| Reset Uart
3520	*
3521	* Field Access Macros:
3522	*
3523	*/
3524	/*
3525	* Enumerated value for register field ALT_UART_SRR_UR
3526	*
3527	* No reset Uart
3528	*/
3529	#define ALT_UART_SRR_UR_E_NORST 0x0
3530	/*
3531	* Enumerated value for register field ALT_UART_SRR_UR
3532	*
3533	* Reset Uart
3534	*/
3535	#define ALT_UART_SRR_UR_E_RST 0x1
3536
3537	/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_UR register field. */
3538	#define ALT_UART_SRR_UR_LSB 0
3539	/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_UR register field. */
3540	#define ALT_UART_SRR_UR_MSB 0
3541	/* The width in bits of the ALT_UART_SRR_UR register field. */
3542	#define ALT_UART_SRR_UR_WIDTH 1
3543	/* The mask used to set the ALT_UART_SRR_UR register field value. */
3544	#define ALT_UART_SRR_UR_SET_MSK 0x00000001
3545	/* The mask used to clear the ALT_UART_SRR_UR register field value. */
3546	#define ALT_UART_SRR_UR_CLR_MSK 0xfffffffe
3547	/* The reset value of the ALT_UART_SRR_UR register field. */
3548	#define ALT_UART_SRR_UR_RESET 0x0
3549	/* Extracts the ALT_UART_SRR_UR field value from a register. */
3550	#define ALT_UART_SRR_UR_GET(value) (((value) & 0x00000001) >> 0)
3551	/* Produces a ALT_UART_SRR_UR register field value suitable for setting the register. */
3552	#define ALT_UART_SRR_UR_SET(value) (((value) << 0) & 0x00000001)
3553
3554	/*
3555	* Field : Rx FIFO Reset - rfr
3556	*
3557	* This is a shadow register for the Rx FIFO Reset bit (FCR[1]). This can be used
3558	* to remove the burden on software having to store previously written FCR values
3559	* (which are pretty static) just to reset the receive FIFO. This resets the
3560	* control portion of the receive FIFO and treats the FIFO as empty. This will also
3561	* de-assert the DMA Rx request and single signals. Note that this bit is 'self-
3562	* clearing' and it is not necessary to clear this bit.
3563	*
3564	* Field Enumeration Values:
3565	*
3566	* Enum \| Value \| Description
3567	* :-------------------------\|:------\|:-----------------
3568	* ALT_UART_SRR_RFR_E_NORST \| 0x0 \| No reset Rx FIFO
3569	* ALT_UART_SRR_RFR_E_RST \| 0x1 \| Reset Rx FIFO
3570	*
3571	* Field Access Macros:
3572	*
3573	*/
3574	/*
3575	* Enumerated value for register field ALT_UART_SRR_RFR
3576	*
3577	* No reset Rx FIFO
3578	*/
3579	#define ALT_UART_SRR_RFR_E_NORST 0x0
3580	/*
3581	* Enumerated value for register field ALT_UART_SRR_RFR
3582	*
3583	* Reset Rx FIFO
3584	*/
3585	#define ALT_UART_SRR_RFR_E_RST 0x1
3586
3587	/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_RFR register field. */
3588	#define ALT_UART_SRR_RFR_LSB 1
3589	/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_RFR register field. */
3590	#define ALT_UART_SRR_RFR_MSB 1
3591	/* The width in bits of the ALT_UART_SRR_RFR register field. */
3592	#define ALT_UART_SRR_RFR_WIDTH 1
3593	/* The mask used to set the ALT_UART_SRR_RFR register field value. */
3594	#define ALT_UART_SRR_RFR_SET_MSK 0x00000002
3595	/* The mask used to clear the ALT_UART_SRR_RFR register field value. */
3596	#define ALT_UART_SRR_RFR_CLR_MSK 0xfffffffd
3597	/* The reset value of the ALT_UART_SRR_RFR register field. */
3598	#define ALT_UART_SRR_RFR_RESET 0x0
3599	/* Extracts the ALT_UART_SRR_RFR field value from a register. */
3600	#define ALT_UART_SRR_RFR_GET(value) (((value) & 0x00000002) >> 1)
3601	/* Produces a ALT_UART_SRR_RFR register field value suitable for setting the register. */
3602	#define ALT_UART_SRR_RFR_SET(value) (((value) << 1) & 0x00000002)
3603
3604	/*
3605	* Field : Tx FIFO Reset - xfr
3606	*
3607	* This is a shadow register forthe Tx FIFO Reset bit (FCR[2]). This can be used
3608	* to remove the burden on software having to store previously written FCR values
3609	* (which are pretty static) just to reset the transmit FIFO.This resets the
3610	* control portion of the transmit FIFO and treats the FIFO as empty. This will
3611	* also de-assert the DMA Tx request and single signals.
3612	*
3613	* Field Enumeration Values:
3614	*
3615	* Enum \| Value \| Description
3616	* :-------------------------\|:------\|:-----------------
3617	* ALT_UART_SRR_XFR_E_NORST \| 0x0 \| No reset Tx FIFO
3618	* ALT_UART_SRR_XFR_E_RST \| 0x1 \| Reset Tx FIFO
3619	*
3620	* Field Access Macros:
3621	*
3622	*/
3623	/*
3624	* Enumerated value for register field ALT_UART_SRR_XFR
3625	*
3626	* No reset Tx FIFO
3627	*/
3628	#define ALT_UART_SRR_XFR_E_NORST 0x0
3629	/*
3630	* Enumerated value for register field ALT_UART_SRR_XFR
3631	*
3632	* Reset Tx FIFO
3633	*/
3634	#define ALT_UART_SRR_XFR_E_RST 0x1
3635
3636	/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_XFR register field. */
3637	#define ALT_UART_SRR_XFR_LSB 2
3638	/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_XFR register field. */
3639	#define ALT_UART_SRR_XFR_MSB 2
3640	/* The width in bits of the ALT_UART_SRR_XFR register field. */
3641	#define ALT_UART_SRR_XFR_WIDTH 1
3642	/* The mask used to set the ALT_UART_SRR_XFR register field value. */
3643	#define ALT_UART_SRR_XFR_SET_MSK 0x00000004
3644	/* The mask used to clear the ALT_UART_SRR_XFR register field value. */
3645	#define ALT_UART_SRR_XFR_CLR_MSK 0xfffffffb
3646	/* The reset value of the ALT_UART_SRR_XFR register field. */
3647	#define ALT_UART_SRR_XFR_RESET 0x0
3648	/* Extracts the ALT_UART_SRR_XFR field value from a register. */
3649	#define ALT_UART_SRR_XFR_GET(value) (((value) & 0x00000004) >> 2)
3650	/* Produces a ALT_UART_SRR_XFR register field value suitable for setting the register. */
3651	#define ALT_UART_SRR_XFR_SET(value) (((value) << 2) & 0x00000004)
3652
3653	#ifndef __ASSEMBLY__
3654	/*
3655	* WARNING: The C register and register group struct declarations are provided for
3656	* convenience and illustrative purposes. They should, however, be used with
3657	* caution as the C language standard provides no guarantees about the alignment or
3658	* atomicity of device memory accesses. The recommended practice for writing
3659	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
3660	* alt_write_word() functions.
3661	*
3662	* The struct declaration for register ALT_UART_SRR.
3663	*/
3664	struct ALT_UART_SRR_s
3665	{
3666	uint32_t ur : 1; /* UART Reset */
3667	uint32_t rfr : 1; /* Rx FIFO Reset */
3668	uint32_t xfr : 1; /* Tx FIFO Reset */
3669	uint32_t : 29; /* UNDEFINED */
3670	};
3671
3672	/* The typedef declaration for register ALT_UART_SRR. */
3673	typedef volatile struct ALT_UART_SRR_s ALT_UART_SRR_t;
3674	#endif /* __ASSEMBLY__ */
3675
3676	/* The byte offset of the ALT_UART_SRR register from the beginning of the component. */
3677	#define ALT_UART_SRR_OFST 0x88
3678	/* The address of the ALT_UART_SRR register. */
3679	#define ALT_UART_SRR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_SRR_OFST))
3680
3681	/*
3682	* Register : Shadow Request to Send - srts
3683	*
3684	* This is a shadow register for the RTS status (MCR[1]), this can be used to
3685	* remove the burden of having to performing a read modify write on the MCR.
3686	*
3687	* Register Layout
3688	*
3689	* Bits \| Access \| Reset \| Description
3690	* :-------\|:-------\|:------\|:-----------------------
3691	* [0] \| RW \| 0x0 \| Shadow Request to Send
3692	* [31:1] \| ??? \| 0x0 \| UNDEFINED
3693	*
3694	*/
3695	/*
3696	* Field : Shadow Request to Send - srts
3697	*
3698	* This is used to directly control the Request to Send (uart_rts_n) output. The
3699	* Request to Send (uart_rts_n) output is used to inform the modem or data set that
3700	* the UART is read to exchange data. The uart_rts_n signal is set low by
3701	* programming MCR[1] (RTS) to a high. In Auto Flow Control, (MCR[5] set to one)
3702	* and FIFO's are enabled (FCR[0] set to one), the uart_rts_n output is controlled
3703	* in the same way, but is also gated with the receiver FIFO threshold trigger
3704	* (uart_rts_n is inactive high when above the threshold).
3705	*
3706	* Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held
3707	* inactive high while the value of this location is internally looped back to an
3708	* input.
3709	*
3710	* Field Enumeration Values:
3711	*
3712	* Enum \| Value \| Description
3713	* :----------------------------\|:------\|:------------------
3714	* ALT_UART_SRTS_SRTS_E_LOGIC0 \| 0x1 \| uart_rts_n logic0
3715	* ALT_UART_SRTS_SRTS_E_LOGIC1 \| 0x0 \| uart_rts_n logic1
3716	*
3717	* Field Access Macros:
3718	*
3719	*/
3720	/*
3721	* Enumerated value for register field ALT_UART_SRTS_SRTS
3722	*
3723	* uart_rts_n logic0
3724	*/
3725	#define ALT_UART_SRTS_SRTS_E_LOGIC0 0x1
3726	/*
3727	* Enumerated value for register field ALT_UART_SRTS_SRTS
3728	*
3729	* uart_rts_n logic1
3730	*/
3731	#define ALT_UART_SRTS_SRTS_E_LOGIC1 0x0
3732
3733	/* The Least Significant Bit (LSB) position of the ALT_UART_SRTS_SRTS register field. */
3734	#define ALT_UART_SRTS_SRTS_LSB 0
3735	/* The Most Significant Bit (MSB) position of the ALT_UART_SRTS_SRTS register field. */
3736	#define ALT_UART_SRTS_SRTS_MSB 0
3737	/* The width in bits of the ALT_UART_SRTS_SRTS register field. */
3738	#define ALT_UART_SRTS_SRTS_WIDTH 1
3739	/* The mask used to set the ALT_UART_SRTS_SRTS register field value. */
3740	#define ALT_UART_SRTS_SRTS_SET_MSK 0x00000001
3741	/* The mask used to clear the ALT_UART_SRTS_SRTS register field value. */
3742	#define ALT_UART_SRTS_SRTS_CLR_MSK 0xfffffffe
3743	/* The reset value of the ALT_UART_SRTS_SRTS register field. */
3744	#define ALT_UART_SRTS_SRTS_RESET 0x0
3745	/* Extracts the ALT_UART_SRTS_SRTS field value from a register. */
3746	#define ALT_UART_SRTS_SRTS_GET(value) (((value) & 0x00000001) >> 0)
3747	/* Produces a ALT_UART_SRTS_SRTS register field value suitable for setting the register. */
3748	#define ALT_UART_SRTS_SRTS_SET(value) (((value) << 0) & 0x00000001)
3749
3750	#ifndef __ASSEMBLY__
3751	/*
3752	* WARNING: The C register and register group struct declarations are provided for
3753	* convenience and illustrative purposes. They should, however, be used with
3754	* caution as the C language standard provides no guarantees about the alignment or
3755	* atomicity of device memory accesses. The recommended practice for writing
3756	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
3757	* alt_write_word() functions.
3758	*
3759	* The struct declaration for register ALT_UART_SRTS.
3760	*/
3761	struct ALT_UART_SRTS_s
3762	{
3763	uint32_t srts : 1; /* Shadow Request to Send */
3764	uint32_t : 31; /* UNDEFINED */
3765	};
3766
3767	/* The typedef declaration for register ALT_UART_SRTS. */
3768	typedef volatile struct ALT_UART_SRTS_s ALT_UART_SRTS_t;
3769	#endif /* __ASSEMBLY__ */
3770
3771	/* The byte offset of the ALT_UART_SRTS register from the beginning of the component. */
3772	#define ALT_UART_SRTS_OFST 0x8c
3773	/* The address of the ALT_UART_SRTS register. */
3774	#define ALT_UART_SRTS_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_SRTS_OFST))
3775
3776	/*
3777	* Register : Shadow Break Control Register - sbcr
3778	*
3779	* This is a shadow register for the Break bit [6] of the register LCR. This can be
3780	* used to remove the burden of having to performing a read modify write on the
3781	* LCR.
3782	*
3783	* Register Layout
3784	*
3785	* Bits \| Access \| Reset \| Description
3786	* :-------\|:-------\|:------\|:---------------------
3787	* [0] \| RW \| 0x0 \| Shadow Break Control
3788	* [31:1] \| ??? \| 0x0 \| UNDEFINED
3789	*
3790	*/
3791	/*
3792	* Field : Shadow Break Control - sbcr
3793	*
3794	* This is used to cause a break condition to be transmitted to the receiving
3795	* device. If set to one the serial output is forced to the spacing (logic 0)
3796	* state. When not in Loopback Mode, as determined by MCR[4], the uart_txd line is
3797	* forced low until the Break bit is cleared. When in Loopback Mode, the break
3798	* condition is internally looped back to the receiver.
3799	*
3800	* Field Enumeration Values:
3801	*
3802	* Enum \| Value \| Description
3803	* :--------------------------\|:------\|:----------------------------
3804	* ALT_UART_SBCR_SBCR_E_DISD \| 0x0 \| no break
3805	* ALT_UART_SBCR_SBCR_E_END \| 0x1 \| break serial output spacing
3806	*
3807	* Field Access Macros:
3808	*
3809	*/
3810	/*
3811	* Enumerated value for register field ALT_UART_SBCR_SBCR
3812	*
3813	* no break
3814	*/
3815	#define ALT_UART_SBCR_SBCR_E_DISD 0x0
3816	/*
3817	* Enumerated value for register field ALT_UART_SBCR_SBCR
3818	*
3819	* break serial output spacing
3820	*/
3821	#define ALT_UART_SBCR_SBCR_E_END 0x1
3822
3823	/* The Least Significant Bit (LSB) position of the ALT_UART_SBCR_SBCR register field. */
3824	#define ALT_UART_SBCR_SBCR_LSB 0
3825	/* The Most Significant Bit (MSB) position of the ALT_UART_SBCR_SBCR register field. */
3826	#define ALT_UART_SBCR_SBCR_MSB 0
3827	/* The width in bits of the ALT_UART_SBCR_SBCR register field. */
3828	#define ALT_UART_SBCR_SBCR_WIDTH 1
3829	/* The mask used to set the ALT_UART_SBCR_SBCR register field value. */
3830	#define ALT_UART_SBCR_SBCR_SET_MSK 0x00000001
3831	/* The mask used to clear the ALT_UART_SBCR_SBCR register field value. */
3832	#define ALT_UART_SBCR_SBCR_CLR_MSK 0xfffffffe
3833	/* The reset value of the ALT_UART_SBCR_SBCR register field. */
3834	#define ALT_UART_SBCR_SBCR_RESET 0x0
3835	/* Extracts the ALT_UART_SBCR_SBCR field value from a register. */
3836	#define ALT_UART_SBCR_SBCR_GET(value) (((value) & 0x00000001) >> 0)
3837	/* Produces a ALT_UART_SBCR_SBCR register field value suitable for setting the register. */
3838	#define ALT_UART_SBCR_SBCR_SET(value) (((value) << 0) & 0x00000001)
3839
3840	#ifndef __ASSEMBLY__
3841	/*
3842	* WARNING: The C register and register group struct declarations are provided for
3843	* convenience and illustrative purposes. They should, however, be used with
3844	* caution as the C language standard provides no guarantees about the alignment or
3845	* atomicity of device memory accesses. The recommended practice for writing
3846	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
3847	* alt_write_word() functions.
3848	*
3849	* The struct declaration for register ALT_UART_SBCR.
3850	*/
3851	struct ALT_UART_SBCR_s
3852	{
3853	uint32_t sbcr : 1; /* Shadow Break Control */
3854	uint32_t : 31; /* UNDEFINED */
3855	};
3856
3857	/* The typedef declaration for register ALT_UART_SBCR. */
3858	typedef volatile struct ALT_UART_SBCR_s ALT_UART_SBCR_t;
3859	#endif /* __ASSEMBLY__ */
3860
3861	/* The byte offset of the ALT_UART_SBCR register from the beginning of the component. */
3862	#define ALT_UART_SBCR_OFST 0x90
3863	/* The address of the ALT_UART_SBCR register. */
3864	#define ALT_UART_SBCR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_SBCR_OFST))
3865
3866	/*
3867	* Register : Shadow DMA Mode - sdmam
3868	*
3869	* This is a shadow register for the DMA mode bit (FCR[3]).
3870	*
3871	* Register Layout
3872	*
3873	* Bits \| Access \| Reset \| Description
3874	* :-------\|:-------\|:------\|:----------------
3875	* [0] \| RW \| 0x0 \| Shadow DMA Mode
3876	* [31:1] \| ??? \| 0x0 \| UNDEFINED
3877	*
3878	*/
3879	/*
3880	* Field : Shadow DMA Mode - sdmam
3881	*
3882	* This can be used to remove the burden of having to store the previously written
3883	* value to the FCR in memory and having to mask this value so that only the DMA
3884	* Mode bit gets updated.
3885	*
3886	* Field Enumeration Values:
3887	*
3888	* Enum \| Value \| Description
3889	* :------------------------------\|:------\|:---------------------------
3890	* ALT_UART_SDMAM_SDMAM_E_SINGLE \| 0x0 \| Single DMA Transfer Mode
3891	* ALT_UART_SDMAM_SDMAM_E_MULT \| 0x1 \| Multiple DMA Transfer Mode
3892	*
3893	* Field Access Macros:
3894	*
3895	*/
3896	/*
3897	* Enumerated value for register field ALT_UART_SDMAM_SDMAM
3898	*
3899	* Single DMA Transfer Mode
3900	*/
3901	#define ALT_UART_SDMAM_SDMAM_E_SINGLE 0x0
3902	/*
3903	* Enumerated value for register field ALT_UART_SDMAM_SDMAM
3904	*
3905	* Multiple DMA Transfer Mode
3906	*/
3907	#define ALT_UART_SDMAM_SDMAM_E_MULT 0x1
3908
3909	/* The Least Significant Bit (LSB) position of the ALT_UART_SDMAM_SDMAM register field. */
3910	#define ALT_UART_SDMAM_SDMAM_LSB 0
3911	/* The Most Significant Bit (MSB) position of the ALT_UART_SDMAM_SDMAM register field. */
3912	#define ALT_UART_SDMAM_SDMAM_MSB 0
3913	/* The width in bits of the ALT_UART_SDMAM_SDMAM register field. */
3914	#define ALT_UART_SDMAM_SDMAM_WIDTH 1
3915	/* The mask used to set the ALT_UART_SDMAM_SDMAM register field value. */
3916	#define ALT_UART_SDMAM_SDMAM_SET_MSK 0x00000001
3917	/* The mask used to clear the ALT_UART_SDMAM_SDMAM register field value. */
3918	#define ALT_UART_SDMAM_SDMAM_CLR_MSK 0xfffffffe
3919	/* The reset value of the ALT_UART_SDMAM_SDMAM register field. */
3920	#define ALT_UART_SDMAM_SDMAM_RESET 0x0
3921	/* Extracts the ALT_UART_SDMAM_SDMAM field value from a register. */
3922	#define ALT_UART_SDMAM_SDMAM_GET(value) (((value) & 0x00000001) >> 0)
3923	/* Produces a ALT_UART_SDMAM_SDMAM register field value suitable for setting the register. */
3924	#define ALT_UART_SDMAM_SDMAM_SET(value) (((value) << 0) & 0x00000001)
3925
3926	#ifndef __ASSEMBLY__
3927	/*
3928	* WARNING: The C register and register group struct declarations are provided for
3929	* convenience and illustrative purposes. They should, however, be used with
3930	* caution as the C language standard provides no guarantees about the alignment or
3931	* atomicity of device memory accesses. The recommended practice for writing
3932	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
3933	* alt_write_word() functions.
3934	*
3935	* The struct declaration for register ALT_UART_SDMAM.
3936	*/
3937	struct ALT_UART_SDMAM_s
3938	{
3939	uint32_t sdmam : 1; /* Shadow DMA Mode */
3940	uint32_t : 31; /* UNDEFINED */
3941	};
3942
3943	/* The typedef declaration for register ALT_UART_SDMAM. */
3944	typedef volatile struct ALT_UART_SDMAM_s ALT_UART_SDMAM_t;
3945	#endif /* __ASSEMBLY__ */
3946
3947	/* The byte offset of the ALT_UART_SDMAM register from the beginning of the component. */
3948	#define ALT_UART_SDMAM_OFST 0x94
3949	/* The address of the ALT_UART_SDMAM register. */
3950	#define ALT_UART_SDMAM_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_SDMAM_OFST))
3951
3952	/*
3953	* Register : Shadow FIFO Enable - sfe
3954	*
3955	* This is a shadow register for the FIFO enable bit [0] of register FCR.
3956	*
3957	* Register Layout
3958	*
3959	* Bits \| Access \| Reset \| Description
3960	* :-------\|:-------\|:------\|:-------------------
3961	* [0] \| RW \| 0x0 \| Shadow FIFO Enable
3962	* [31:1] \| ??? \| 0x0 \| UNDEFINED
3963	*
3964	*/
3965	/*
3966	* Field : Shadow FIFO Enable - sfe
3967	*
3968	* This can be used to remove the burden of having to store the previously written
3969	* value to the FCR in memory and having to mask this value so that only the FIFO
3970	* enable bit gets updated. This enables/disables the transmit (Tx) and receive (Rx
3971	* ) FIFO's. If this bit is set to zero (disabled) after being enabled then both
3972	* the Tx and Rx controller portion of FIFO's will be reset.
3973	*
3974	* Field Enumeration Values:
3975	*
3976	* Enum \| Value \| Description
3977	* :------------------------\|:------\|:--------------
3978	* ALT_UART_SFE_SFE_E_DISD \| 0x0 \| Disable Rx/Tx
3979	* ALT_UART_SFE_SFE_E_END \| 0x1 \| Enable Rx/Tx
3980	*
3981	* Field Access Macros:
3982	*
3983	*/
3984	/*
3985	* Enumerated value for register field ALT_UART_SFE_SFE
3986	*
3987	* Disable Rx/Tx
3988	*/
3989	#define ALT_UART_SFE_SFE_E_DISD 0x0
3990	/*
3991	* Enumerated value for register field ALT_UART_SFE_SFE
3992	*
3993	* Enable Rx/Tx
3994	*/
3995	#define ALT_UART_SFE_SFE_E_END 0x1
3996
3997	/* The Least Significant Bit (LSB) position of the ALT_UART_SFE_SFE register field. */
3998	#define ALT_UART_SFE_SFE_LSB 0
3999	/* The Most Significant Bit (MSB) position of the ALT_UART_SFE_SFE register field. */
4000	#define ALT_UART_SFE_SFE_MSB 0
4001	/* The width in bits of the ALT_UART_SFE_SFE register field. */
4002	#define ALT_UART_SFE_SFE_WIDTH 1
4003	/* The mask used to set the ALT_UART_SFE_SFE register field value. */
4004	#define ALT_UART_SFE_SFE_SET_MSK 0x00000001
4005	/* The mask used to clear the ALT_UART_SFE_SFE register field value. */
4006	#define ALT_UART_SFE_SFE_CLR_MSK 0xfffffffe
4007	/* The reset value of the ALT_UART_SFE_SFE register field. */
4008	#define ALT_UART_SFE_SFE_RESET 0x0
4009	/* Extracts the ALT_UART_SFE_SFE field value from a register. */
4010	#define ALT_UART_SFE_SFE_GET(value) (((value) & 0x00000001) >> 0)
4011	/* Produces a ALT_UART_SFE_SFE register field value suitable for setting the register. */
4012	#define ALT_UART_SFE_SFE_SET(value) (((value) << 0) & 0x00000001)
4013
4014	#ifndef __ASSEMBLY__
4015	/*
4016	* WARNING: The C register and register group struct declarations are provided for
4017	* convenience and illustrative purposes. They should, however, be used with
4018	* caution as the C language standard provides no guarantees about the alignment or
4019	* atomicity of device memory accesses. The recommended practice for writing
4020	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
4021	* alt_write_word() functions.
4022	*
4023	* The struct declaration for register ALT_UART_SFE.
4024	*/
4025	struct ALT_UART_SFE_s
4026	{
4027	uint32_t sfe : 1; /* Shadow FIFO Enable */
4028	uint32_t : 31; /* UNDEFINED */
4029	};
4030
4031	/* The typedef declaration for register ALT_UART_SFE. */
4032	typedef volatile struct ALT_UART_SFE_s ALT_UART_SFE_t;
4033	#endif /* __ASSEMBLY__ */
4034
4035	/* The byte offset of the ALT_UART_SFE register from the beginning of the component. */
4036	#define ALT_UART_SFE_OFST 0x98
4037	/* The address of the ALT_UART_SFE register. */
4038	#define ALT_UART_SFE_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_SFE_OFST))
4039
4040	/*
4041	* Register : Shadow Rx Trigger - srt
4042	*
4043	* This is a shadow register for the Rx trigger bits (FCR[7:6]).
4044	*
4045	* Register Layout
4046	*
4047	* Bits \| Access \| Reset \| Description
4048	* :-------\|:-------\|:------\|:------------------------
4049	* [1:0] \| RW \| 0x0 \| Shadow Rx Trigger Bits
4050	* [31:2] \| ??? \| 0x0 \| UNDEFINED
4051	*
4052	*/
4053	/*
4054	* Field : Shadow Rx Trigger Bits - srt
4055	*
4056	* This can be used to remove the burden of having to store the previously written
4057	* value to the FCR in memory and having to mask this value so that only the Rx
4058	* trigger bit gets updated. This is used to select the trigger level in the
4059	* receiver FIFO at which the Received Data Available Interrupt will be generated.
4060	* It also determines when the uart_dma_rx_req_n signal will be asserted when DMA
4061	* Mode (FCR[3]) is set to one. The enum below shows trigger levels that are
4062	* supported.
4063	*
4064	* Field Enumeration Values:
4065	*
4066	* Enum \| Value \| Description
4067	* :-------------------------------\|:------\|:----------------------
4068	* ALT_UART_SRT_SRT_E_ONECHAR \| 0x0 \| one character in fifo
4069	* ALT_UART_SRT_SRT_E_QUARTERFULL \| 0x1 \| FIFO 1/4 full
4070	* ALT_UART_SRT_SRT_E_HALFFULL \| 0x2 \| FIFO 1/2 full
4071	* ALT_UART_SRT_SRT_E_FULLLESS2 \| 0x3 \| FIFO 2 less than full
4072	*
4073	* Field Access Macros:
4074	*
4075	*/
4076	/*
4077	* Enumerated value for register field ALT_UART_SRT_SRT
4078	*
4079	* one character in fifo
4080	*/
4081	#define ALT_UART_SRT_SRT_E_ONECHAR 0x0
4082	/*
4083	* Enumerated value for register field ALT_UART_SRT_SRT
4084	*
4085	* FIFO 1/4 full
4086	*/
4087	#define ALT_UART_SRT_SRT_E_QUARTERFULL 0x1
4088	/*
4089	* Enumerated value for register field ALT_UART_SRT_SRT
4090	*
4091	* FIFO 1/2 full
4092	*/
4093	#define ALT_UART_SRT_SRT_E_HALFFULL 0x2
4094	/*
4095	* Enumerated value for register field ALT_UART_SRT_SRT
4096	*
4097	* FIFO 2 less than full
4098	*/
4099	#define ALT_UART_SRT_SRT_E_FULLLESS2 0x3
4100
4101	/* The Least Significant Bit (LSB) position of the ALT_UART_SRT_SRT register field. */
4102	#define ALT_UART_SRT_SRT_LSB 0
4103	/* The Most Significant Bit (MSB) position of the ALT_UART_SRT_SRT register field. */
4104	#define ALT_UART_SRT_SRT_MSB 1
4105	/* The width in bits of the ALT_UART_SRT_SRT register field. */
4106	#define ALT_UART_SRT_SRT_WIDTH 2
4107	/* The mask used to set the ALT_UART_SRT_SRT register field value. */
4108	#define ALT_UART_SRT_SRT_SET_MSK 0x00000003
4109	/* The mask used to clear the ALT_UART_SRT_SRT register field value. */
4110	#define ALT_UART_SRT_SRT_CLR_MSK 0xfffffffc
4111	/* The reset value of the ALT_UART_SRT_SRT register field. */
4112	#define ALT_UART_SRT_SRT_RESET 0x0
4113	/* Extracts the ALT_UART_SRT_SRT field value from a register. */
4114	#define ALT_UART_SRT_SRT_GET(value) (((value) & 0x00000003) >> 0)
4115	/* Produces a ALT_UART_SRT_SRT register field value suitable for setting the register. */
4116	#define ALT_UART_SRT_SRT_SET(value) (((value) << 0) & 0x00000003)
4117
4118	#ifndef __ASSEMBLY__
4119	/*
4120	* WARNING: The C register and register group struct declarations are provided for
4121	* convenience and illustrative purposes. They should, however, be used with
4122	* caution as the C language standard provides no guarantees about the alignment or
4123	* atomicity of device memory accesses. The recommended practice for writing
4124	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
4125	* alt_write_word() functions.
4126	*
4127	* The struct declaration for register ALT_UART_SRT.
4128	*/
4129	struct ALT_UART_SRT_s
4130	{
4131	uint32_t srt : 2; /* Shadow Rx Trigger Bits */
4132	uint32_t : 30; /* UNDEFINED */
4133	};
4134
4135	/* The typedef declaration for register ALT_UART_SRT. */
4136	typedef volatile struct ALT_UART_SRT_s ALT_UART_SRT_t;
4137	#endif /* __ASSEMBLY__ */
4138
4139	/* The byte offset of the ALT_UART_SRT register from the beginning of the component. */
4140	#define ALT_UART_SRT_OFST 0x9c
4141	/* The address of the ALT_UART_SRT register. */
4142	#define ALT_UART_SRT_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_SRT_OFST))
4143
4144	/*
4145	* Register : Shadow Tx Empty Trigger - stet
4146	*
4147	* This is a shadow register for the Tx empty trigger bits (FCR[5:4]).
4148	*
4149	* Register Layout
4150	*
4151	* Bits \| Access \| Reset \| Description
4152	* :-------\|:-------\|:------\|:-----------------------------
4153	* [1:0] \| RW \| 0x0 \| Shadow Tx Empty Trigger Bits
4154	* [31:2] \| ??? \| 0x0 \| UNDEFINED
4155	*
4156	*/
4157	/*
4158	* Field : Shadow Tx Empty Trigger Bits - stet
4159	*
4160	* This can be used to remove the burden of having to store the previously written
4161	* value to the FCR in memory and having to mask this value so that only the Tx
4162	* empty trigger bit gets updated. This is used to select the empty threshold level
4163	* at which the THRE Interrupts will be generated when the mode is active. These
4164	* threshold levels are also described in. The enum trigger levels are supported.
4165	*
4166	* Field Enumeration Values:
4167	*
4168	* Enum \| Value \| Description
4169	* :---------------------------------\|:------\|:-----------------------
4170	* ALT_UART_STET_STET_E_FIFOEMPTY \| 0x0 \| FIFO empty
4171	* ALT_UART_STET_STET_E_TWOCHARS \| 0x1 \| Two characters in FIFO
4172	* ALT_UART_STET_STET_E_QUARTERFULL \| 0x2 \| FIFO quarter full
4173	* ALT_UART_STET_STET_E_HALFFULL \| 0x3 \| FIFO half full
4174	*
4175	* Field Access Macros:
4176	*
4177	*/
4178	/*
4179	* Enumerated value for register field ALT_UART_STET_STET
4180	*
4181	* FIFO empty
4182	*/
4183	#define ALT_UART_STET_STET_E_FIFOEMPTY 0x0
4184	/*
4185	* Enumerated value for register field ALT_UART_STET_STET
4186	*
4187	* Two characters in FIFO
4188	*/
4189	#define ALT_UART_STET_STET_E_TWOCHARS 0x1
4190	/*
4191	* Enumerated value for register field ALT_UART_STET_STET
4192	*
4193	* FIFO quarter full
4194	*/
4195	#define ALT_UART_STET_STET_E_QUARTERFULL 0x2
4196	/*
4197	* Enumerated value for register field ALT_UART_STET_STET
4198	*
4199	* FIFO half full
4200	*/
4201	#define ALT_UART_STET_STET_E_HALFFULL 0x3
4202
4203	/* The Least Significant Bit (LSB) position of the ALT_UART_STET_STET register field. */
4204	#define ALT_UART_STET_STET_LSB 0
4205	/* The Most Significant Bit (MSB) position of the ALT_UART_STET_STET register field. */
4206	#define ALT_UART_STET_STET_MSB 1
4207	/* The width in bits of the ALT_UART_STET_STET register field. */
4208	#define ALT_UART_STET_STET_WIDTH 2
4209	/* The mask used to set the ALT_UART_STET_STET register field value. */
4210	#define ALT_UART_STET_STET_SET_MSK 0x00000003
4211	/* The mask used to clear the ALT_UART_STET_STET register field value. */
4212	#define ALT_UART_STET_STET_CLR_MSK 0xfffffffc
4213	/* The reset value of the ALT_UART_STET_STET register field. */
4214	#define ALT_UART_STET_STET_RESET 0x0
4215	/* Extracts the ALT_UART_STET_STET field value from a register. */
4216	#define ALT_UART_STET_STET_GET(value) (((value) & 0x00000003) >> 0)
4217	/* Produces a ALT_UART_STET_STET register field value suitable for setting the register. */
4218	#define ALT_UART_STET_STET_SET(value) (((value) << 0) & 0x00000003)
4219
4220	#ifndef __ASSEMBLY__
4221	/*
4222	* WARNING: The C register and register group struct declarations are provided for
4223	* convenience and illustrative purposes. They should, however, be used with
4224	* caution as the C language standard provides no guarantees about the alignment or
4225	* atomicity of device memory accesses. The recommended practice for writing
4226	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
4227	* alt_write_word() functions.
4228	*
4229	* The struct declaration for register ALT_UART_STET.
4230	*/
4231	struct ALT_UART_STET_s
4232	{
4233	uint32_t stet : 2; /* Shadow Tx Empty Trigger Bits */
4234	uint32_t : 30; /* UNDEFINED */
4235	};
4236
4237	/* The typedef declaration for register ALT_UART_STET. */
4238	typedef volatile struct ALT_UART_STET_s ALT_UART_STET_t;
4239	#endif /* __ASSEMBLY__ */
4240
4241	/* The byte offset of the ALT_UART_STET register from the beginning of the component. */
4242	#define ALT_UART_STET_OFST 0xa0
4243	/* The address of the ALT_UART_STET register. */
4244	#define ALT_UART_STET_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_STET_OFST))
4245
4246	/*
4247	* Register : Halt Tx - htx
4248	*
4249	* Used to halt transmission for testing.
4250	*
4251	* Register Layout
4252	*
4253	* Bits \| Access \| Reset \| Description
4254	* :-------\|:-------\|:------\|:-------------
4255	* [0] \| RW \| 0x0 \| Halt Tx Bits
4256	* [31:1] \| ??? \| 0x0 \| UNDEFINED
4257	*
4258	*/
4259	/*
4260	* Field : Halt Tx Bits - htx
4261	*
4262	* This register is use to halt transmissions for testing, so that the transmit
4263	* FIFO can be filled by the master when FIFO's are enabled.
4264	*
4265	* Note, if FIFO's are not enabled, the setting of the halt Tx register will have
4266	* no effect on operation.
4267	*
4268	* Field Enumeration Values:
4269	*
4270	* Enum \| Value \| Description
4271	* :------------------------\|:------\|:-----------------
4272	* ALT_UART_HTX_HTX_E_DISD \| 0x0 \| Halt Tx disabled
4273	* ALT_UART_HTX_HTX_E_END \| 0x1 \| Halt Tx enabled
4274	*
4275	* Field Access Macros:
4276	*
4277	*/
4278	/*
4279	* Enumerated value for register field ALT_UART_HTX_HTX
4280	*
4281	* Halt Tx disabled
4282	*/
4283	#define ALT_UART_HTX_HTX_E_DISD 0x0
4284	/*
4285	* Enumerated value for register field ALT_UART_HTX_HTX
4286	*
4287	* Halt Tx enabled
4288	*/
4289	#define ALT_UART_HTX_HTX_E_END 0x1
4290
4291	/* The Least Significant Bit (LSB) position of the ALT_UART_HTX_HTX register field. */
4292	#define ALT_UART_HTX_HTX_LSB 0
4293	/* The Most Significant Bit (MSB) position of the ALT_UART_HTX_HTX register field. */
4294	#define ALT_UART_HTX_HTX_MSB 0
4295	/* The width in bits of the ALT_UART_HTX_HTX register field. */
4296	#define ALT_UART_HTX_HTX_WIDTH 1
4297	/* The mask used to set the ALT_UART_HTX_HTX register field value. */
4298	#define ALT_UART_HTX_HTX_SET_MSK 0x00000001
4299	/* The mask used to clear the ALT_UART_HTX_HTX register field value. */
4300	#define ALT_UART_HTX_HTX_CLR_MSK 0xfffffffe
4301	/* The reset value of the ALT_UART_HTX_HTX register field. */
4302	#define ALT_UART_HTX_HTX_RESET 0x0
4303	/* Extracts the ALT_UART_HTX_HTX field value from a register. */
4304	#define ALT_UART_HTX_HTX_GET(value) (((value) & 0x00000001) >> 0)
4305	/* Produces a ALT_UART_HTX_HTX register field value suitable for setting the register. */
4306	#define ALT_UART_HTX_HTX_SET(value) (((value) << 0) & 0x00000001)
4307
4308	#ifndef __ASSEMBLY__
4309	/*
4310	* WARNING: The C register and register group struct declarations are provided for
4311	* convenience and illustrative purposes. They should, however, be used with
4312	* caution as the C language standard provides no guarantees about the alignment or
4313	* atomicity of device memory accesses. The recommended practice for writing
4314	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
4315	* alt_write_word() functions.
4316	*
4317	* The struct declaration for register ALT_UART_HTX.
4318	*/
4319	struct ALT_UART_HTX_s
4320	{
4321	uint32_t htx : 1; /* Halt Tx Bits */
4322	uint32_t : 31; /* UNDEFINED */
4323	};
4324
4325	/* The typedef declaration for register ALT_UART_HTX. */
4326	typedef volatile struct ALT_UART_HTX_s ALT_UART_HTX_t;
4327	#endif /* __ASSEMBLY__ */
4328
4329	/* The byte offset of the ALT_UART_HTX register from the beginning of the component. */
4330	#define ALT_UART_HTX_OFST 0xa4
4331	/* The address of the ALT_UART_HTX register. */
4332	#define ALT_UART_HTX_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_HTX_OFST))
4333
4334	/*
4335	* Register : DMA Software Acknowledge - dmasa
4336	*
4337	* DMA Operation Control
4338	*
4339	* Register Layout
4340	*
4341	* Bits \| Access \| Reset \| Description
4342	* :-------\|:-------\|:------\|:------------------------------
4343	* [0] \| W \| 0x0 \| DMA Software Acknowledge Bits
4344	* [31:1] \| ??? \| 0x0 \| UNDEFINED
4345	*
4346	*/
4347	/*
4348	* Field : DMA Software Acknowledge Bits - dmasa
4349	*
4350	* This register is used to perform DMA software acknowledge if a transfer needs to
4351	* be terminated due to an error condition. For example, if the DMA disables the
4352	* channel, then the uart should clear its request. This will cause the Tx request,
4353	* Tx single, Rx request and Rx single signals to de-assert. Note that this bit is
4354	* 'self-clearing' and it is not necessary to clear this bit.
4355	*
4356	* Field Access Macros:
4357	*
4358	*/
4359	/* The Least Significant Bit (LSB) position of the ALT_UART_DMASA_DMASA register field. */
4360	#define ALT_UART_DMASA_DMASA_LSB 0
4361	/* The Most Significant Bit (MSB) position of the ALT_UART_DMASA_DMASA register field. */
4362	#define ALT_UART_DMASA_DMASA_MSB 0
4363	/* The width in bits of the ALT_UART_DMASA_DMASA register field. */
4364	#define ALT_UART_DMASA_DMASA_WIDTH 1
4365	/* The mask used to set the ALT_UART_DMASA_DMASA register field value. */
4366	#define ALT_UART_DMASA_DMASA_SET_MSK 0x00000001
4367	/* The mask used to clear the ALT_UART_DMASA_DMASA register field value. */
4368	#define ALT_UART_DMASA_DMASA_CLR_MSK 0xfffffffe
4369	/* The reset value of the ALT_UART_DMASA_DMASA register field. */
4370	#define ALT_UART_DMASA_DMASA_RESET 0x0
4371	/* Extracts the ALT_UART_DMASA_DMASA field value from a register. */
4372	#define ALT_UART_DMASA_DMASA_GET(value) (((value) & 0x00000001) >> 0)
4373	/* Produces a ALT_UART_DMASA_DMASA register field value suitable for setting the register. */
4374	#define ALT_UART_DMASA_DMASA_SET(value) (((value) << 0) & 0x00000001)
4375
4376	#ifndef __ASSEMBLY__
4377	/*
4378	* WARNING: The C register and register group struct declarations are provided for
4379	* convenience and illustrative purposes. They should, however, be used with
4380	* caution as the C language standard provides no guarantees about the alignment or
4381	* atomicity of device memory accesses. The recommended practice for writing
4382	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
4383	* alt_write_word() functions.
4384	*
4385	* The struct declaration for register ALT_UART_DMASA.
4386	*/
4387	struct ALT_UART_DMASA_s
4388	{
4389	uint32_t dmasa : 1; /* DMA Software Acknowledge Bits */
4390	uint32_t : 31; /* UNDEFINED */
4391	};
4392
4393	/* The typedef declaration for register ALT_UART_DMASA. */
4394	typedef volatile struct ALT_UART_DMASA_s ALT_UART_DMASA_t;
4395	#endif /* __ASSEMBLY__ */
4396
4397	/* The byte offset of the ALT_UART_DMASA register from the beginning of the component. */
4398	#define ALT_UART_DMASA_OFST 0xa8
4399	/* The address of the ALT_UART_DMASA register. */
4400	#define ALT_UART_DMASA_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_DMASA_OFST))
4401
4402	/*
4403	* Register : Component Parameter Register - cpr
4404	*
4405	* Describes various fixed hardware setups states.
4406	*
4407	* Register Layout
4408	*
4409	* Bits \| Access \| Reset \| Description
4410	* :--------\|:-------\|:------\|:----------------------------------
4411	* [1:0] \| R \| 0x2 \| APB DATA WIDTH
4412	* [3:2] \| ??? \| 0x0 \| UNDEFINED
4413	* [4] \| R \| 0x1 \| Auto Flow Control
4414	* [5] \| R \| 0x1 \| THRE MODE
4415	* [6] \| R \| 0x0 \| SIR MODE Unsupported
4416	* [7] \| R \| 0x0 \| SIR LP MODE Unsupported
4417	* [8] \| R \| 0x1 \| ADDITIONAL FEATURES Supported
4418	* [9] \| R \| 0x1 \| FIFO ACCESS Supported
4419	* [10] \| R \| 0x1 \| FIFO STAT Supported
4420	* [11] \| R \| 0x1 \| SHADOW Supported
4421	* [12] \| R \| 0x1 \| Configuartion ID Register Present
4422	* [13] \| R \| 0x1 \| DMA EXTRA Supported
4423	* [15:14] \| ??? \| 0x0 \| UNDEFINED
4424	* [23:16] \| R \| 0x37 \| FIFO Depth
4425	* [31:24] \| ??? \| 0x0 \| UNDEFINED
4426	*
4427	*/
4428	/*
4429	* Field : APB DATA WIDTH - apbdatawidth
4430	*
4431	* Fixed to support an ABP data bus width of 32-bits.
4432	*
4433	* Field Enumeration Values:
4434	*
4435	* Enum \| Value \| Description
4436	* :----------------------------------------\|:------\|:-------------------------
4437	* ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS \| 0x2 \| APB Data Width = 32-bits
4438	*
4439	* Field Access Macros:
4440	*
4441	*/
4442	/*
4443	* Enumerated value for register field ALT_UART_CPR_APBDATAWIDTH
4444	*
4445	* APB Data Width = 32-bits
4446	*/
4447	#define ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS 0x2
4448
4449	/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */
4450	#define ALT_UART_CPR_APBDATAWIDTH_LSB 0
4451	/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */
4452	#define ALT_UART_CPR_APBDATAWIDTH_MSB 1
4453	/* The width in bits of the ALT_UART_CPR_APBDATAWIDTH register field. */
4454	#define ALT_UART_CPR_APBDATAWIDTH_WIDTH 2
4455	/* The mask used to set the ALT_UART_CPR_APBDATAWIDTH register field value. */
4456	#define ALT_UART_CPR_APBDATAWIDTH_SET_MSK 0x00000003
4457	/* The mask used to clear the ALT_UART_CPR_APBDATAWIDTH register field value. */
4458	#define ALT_UART_CPR_APBDATAWIDTH_CLR_MSK 0xfffffffc
4459	/* The reset value of the ALT_UART_CPR_APBDATAWIDTH register field. */
4460	#define ALT_UART_CPR_APBDATAWIDTH_RESET 0x2
4461	/* Extracts the ALT_UART_CPR_APBDATAWIDTH field value from a register. */
4462	#define ALT_UART_CPR_APBDATAWIDTH_GET(value) (((value) & 0x00000003) >> 0)
4463	/* Produces a ALT_UART_CPR_APBDATAWIDTH register field value suitable for setting the register. */
4464	#define ALT_UART_CPR_APBDATAWIDTH_SET(value) (((value) << 0) & 0x00000003)
4465
4466	/*
4467	* Field : Auto Flow Control - afce_mode
4468	*
4469	* Allows auto flow control.
4470	*
4471	* Field Enumeration Values:
4472	*
4473	* Enum \| Value \| Description
4474	* :----------------------------\|:------\|:------------
4475	* ALT_UART_CPR_AFCE_MOD_E_END \| 0x1 \| Auto Flow
4476	*
4477	* Field Access Macros:
4478	*
4479	*/
4480	/*
4481	* Enumerated value for register field ALT_UART_CPR_AFCE_MOD
4482	*
4483	* Auto Flow
4484	*/
4485	#define ALT_UART_CPR_AFCE_MOD_E_END 0x1
4486
4487	/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_AFCE_MOD register field. */
4488	#define ALT_UART_CPR_AFCE_MOD_LSB 4
4489	/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_AFCE_MOD register field. */
4490	#define ALT_UART_CPR_AFCE_MOD_MSB 4
4491	/* The width in bits of the ALT_UART_CPR_AFCE_MOD register field. */
4492	#define ALT_UART_CPR_AFCE_MOD_WIDTH 1
4493	/* The mask used to set the ALT_UART_CPR_AFCE_MOD register field value. */
4494	#define ALT_UART_CPR_AFCE_MOD_SET_MSK 0x00000010
4495	/* The mask used to clear the ALT_UART_CPR_AFCE_MOD register field value. */
4496	#define ALT_UART_CPR_AFCE_MOD_CLR_MSK 0xffffffef
4497	/* The reset value of the ALT_UART_CPR_AFCE_MOD register field. */
4498	#define ALT_UART_CPR_AFCE_MOD_RESET 0x1
4499	/* Extracts the ALT_UART_CPR_AFCE_MOD field value from a register. */
4500	#define ALT_UART_CPR_AFCE_MOD_GET(value) (((value) & 0x00000010) >> 4)
4501	/* Produces a ALT_UART_CPR_AFCE_MOD register field value suitable for setting the register. */
4502	#define ALT_UART_CPR_AFCE_MOD_SET(value) (((value) << 4) & 0x00000010)
4503
4504	/*
4505	* Field : THRE MODE - thre_mode
4506	*
4507	* Programmable Transmitter Hold Register Empty interrupt
4508	*
4509	* Field Enumeration Values:
4510	*
4511	* Enum \| Value \| Description
4512	* :----------------------------\|:------\|:------------------------------------------
4513	* ALT_UART_CPR_THRE_MOD_E_END \| 0x1 \| Programmable Tx Hold Reg. Empty interrupt
4514	* : \| \| present
4515	*
4516	* Field Access Macros:
4517	*
4518	*/
4519	/*
4520	* Enumerated value for register field ALT_UART_CPR_THRE_MOD
4521	*
4522	* Programmable Tx Hold Reg. Empty interrupt present
4523	*/
4524	#define ALT_UART_CPR_THRE_MOD_E_END 0x1
4525
4526	/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_THRE_MOD register field. */
4527	#define ALT_UART_CPR_THRE_MOD_LSB 5
4528	/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_THRE_MOD register field. */
4529	#define ALT_UART_CPR_THRE_MOD_MSB 5
4530	/* The width in bits of the ALT_UART_CPR_THRE_MOD register field. */
4531	#define ALT_UART_CPR_THRE_MOD_WIDTH 1
4532	/* The mask used to set the ALT_UART_CPR_THRE_MOD register field value. */
4533	#define ALT_UART_CPR_THRE_MOD_SET_MSK 0x00000020
4534	/* The mask used to clear the ALT_UART_CPR_THRE_MOD register field value. */
4535	#define ALT_UART_CPR_THRE_MOD_CLR_MSK 0xffffffdf
4536	/* The reset value of the ALT_UART_CPR_THRE_MOD register field. */
4537	#define ALT_UART_CPR_THRE_MOD_RESET 0x1
4538	/* Extracts the ALT_UART_CPR_THRE_MOD field value from a register. */
4539	#define ALT_UART_CPR_THRE_MOD_GET(value) (((value) & 0x00000020) >> 5)
4540	/* Produces a ALT_UART_CPR_THRE_MOD register field value suitable for setting the register. */
4541	#define ALT_UART_CPR_THRE_MOD_SET(value) (((value) << 5) & 0x00000020)
4542
4543	/*
4544	* Field : SIR MODE Unsupported - sir_mode
4545	*
4546	* Sir mode not used in this application.
4547	*
4548	* Field Enumeration Values:
4549	*
4550	* Enum \| Value \| Description
4551	* :----------------------------\|:------\|:-----------------------
4552	* ALT_UART_CPR_SIR_MOD_E_DISD \| 0x0 \| Sir Mode Not Supported
4553	*
4554	* Field Access Macros:
4555	*
4556	*/
4557	/*
4558	* Enumerated value for register field ALT_UART_CPR_SIR_MOD
4559	*
4560	* Sir Mode Not Supported
4561	*/
4562	#define ALT_UART_CPR_SIR_MOD_E_DISD 0x0
4563
4564	/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_MOD register field. */
4565	#define ALT_UART_CPR_SIR_MOD_LSB 6
4566	/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_MOD register field. */
4567	#define ALT_UART_CPR_SIR_MOD_MSB 6
4568	/* The width in bits of the ALT_UART_CPR_SIR_MOD register field. */
4569	#define ALT_UART_CPR_SIR_MOD_WIDTH 1
4570	/* The mask used to set the ALT_UART_CPR_SIR_MOD register field value. */
4571	#define ALT_UART_CPR_SIR_MOD_SET_MSK 0x00000040
4572	/* The mask used to clear the ALT_UART_CPR_SIR_MOD register field value. */
4573	#define ALT_UART_CPR_SIR_MOD_CLR_MSK 0xffffffbf
4574	/* The reset value of the ALT_UART_CPR_SIR_MOD register field. */
4575	#define ALT_UART_CPR_SIR_MOD_RESET 0x0
4576	/* Extracts the ALT_UART_CPR_SIR_MOD field value from a register. */
4577	#define ALT_UART_CPR_SIR_MOD_GET(value) (((value) & 0x00000040) >> 6)
4578	/* Produces a ALT_UART_CPR_SIR_MOD register field value suitable for setting the register. */
4579	#define ALT_UART_CPR_SIR_MOD_SET(value) (((value) << 6) & 0x00000040)
4580
4581	/*
4582	* Field : SIR LP MODE Unsupported - sir_lp_mode
4583	*
4584	* LP Sir Mode not used in this application.
4585	*
4586	* Field Enumeration Values:
4587	*
4588	* Enum \| Value \| Description
4589	* :-------------------------------\|:------\|:--------------------------
4590	* ALT_UART_CPR_SIR_LP_MOD_E_DISD \| 0x0 \| LP Sir Mode Not Supported
4591	*
4592	* Field Access Macros:
4593	*
4594	*/
4595	/*
4596	* Enumerated value for register field ALT_UART_CPR_SIR_LP_MOD
4597	*
4598	* LP Sir Mode Not Supported
4599	*/
4600	#define ALT_UART_CPR_SIR_LP_MOD_E_DISD 0x0
4601
4602	/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */
4603	#define ALT_UART_CPR_SIR_LP_MOD_LSB 7
4604	/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */
4605	#define ALT_UART_CPR_SIR_LP_MOD_MSB 7
4606	/* The width in bits of the ALT_UART_CPR_SIR_LP_MOD register field. */
4607	#define ALT_UART_CPR_SIR_LP_MOD_WIDTH 1
4608	/* The mask used to set the ALT_UART_CPR_SIR_LP_MOD register field value. */
4609	#define ALT_UART_CPR_SIR_LP_MOD_SET_MSK 0x00000080
4610	/* The mask used to clear the ALT_UART_CPR_SIR_LP_MOD register field value. */
4611	#define ALT_UART_CPR_SIR_LP_MOD_CLR_MSK 0xffffff7f
4612	/* The reset value of the ALT_UART_CPR_SIR_LP_MOD register field. */
4613	#define ALT_UART_CPR_SIR_LP_MOD_RESET 0x0
4614	/* Extracts the ALT_UART_CPR_SIR_LP_MOD field value from a register. */
4615	#define ALT_UART_CPR_SIR_LP_MOD_GET(value) (((value) & 0x00000080) >> 7)
4616	/* Produces a ALT_UART_CPR_SIR_LP_MOD register field value suitable for setting the register. */
4617	#define ALT_UART_CPR_SIR_LP_MOD_SET(value) (((value) << 7) & 0x00000080)
4618
4619	/*
4620	* Field : ADDITIONAL FEATURES Supported - additional_feat
4621	*
4622	* Configures the uart to include fifo status register, shadow registers and
4623	* encoded parameter register.
4624	*
4625	* Field Enumeration Values:
4626	*
4627	* Enum \| Value \| Description
4628	* :-----------------------------------\|:------\|:------------------------------
4629	* ALT_UART_CPR_ADDITIONAL_FEAT_E_END \| 0x1 \| Additional Features Supported
4630	*
4631	* Field Access Macros:
4632	*
4633	*/
4634	/*
4635	* Enumerated value for register field ALT_UART_CPR_ADDITIONAL_FEAT
4636	*
4637	* Additional Features Supported
4638	*/
4639	#define ALT_UART_CPR_ADDITIONAL_FEAT_E_END 0x1
4640
4641	/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
4642	#define ALT_UART_CPR_ADDITIONAL_FEAT_LSB 8
4643	/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
4644	#define ALT_UART_CPR_ADDITIONAL_FEAT_MSB 8
4645	/* The width in bits of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
4646	#define ALT_UART_CPR_ADDITIONAL_FEAT_WIDTH 1
4647	/* The mask used to set the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */
4648	#define ALT_UART_CPR_ADDITIONAL_FEAT_SET_MSK 0x00000100
4649	/* The mask used to clear the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */
4650	#define ALT_UART_CPR_ADDITIONAL_FEAT_CLR_MSK 0xfffffeff
4651	/* The reset value of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
4652	#define ALT_UART_CPR_ADDITIONAL_FEAT_RESET 0x1
4653	/* Extracts the ALT_UART_CPR_ADDITIONAL_FEAT field value from a register. */
4654	#define ALT_UART_CPR_ADDITIONAL_FEAT_GET(value) (((value) & 0x00000100) >> 8)
4655	/* Produces a ALT_UART_CPR_ADDITIONAL_FEAT register field value suitable for setting the register. */
4656	#define ALT_UART_CPR_ADDITIONAL_FEAT_SET(value) (((value) << 8) & 0x00000100)
4657
4658	/*
4659	* Field : FIFO ACCESS Supported - fifo_access
4660	*
4661	* Configures the peripheral to have a programmable FIFO access mode. This is used
4662	* for test purposes, to allow the receiver FIFO to be written and the transmit
4663	* FIFO to be read when FIFOs are implemented and enabled.
4664	*
4665	* Field Enumeration Values:
4666	*
4667	* Enum \| Value \| Description
4668	* :-------------------------------\|:------\|:----------------------
4669	* ALT_UART_CPR_FIFO_ACCESS_E_END \| 0x1 \| FIFO Access Supported
4670	*
4671	* Field Access Macros:
4672	*
4673	*/
4674	/*
4675	* Enumerated value for register field ALT_UART_CPR_FIFO_ACCESS
4676	*
4677	* FIFO Access Supported
4678	*/
4679	#define ALT_UART_CPR_FIFO_ACCESS_E_END 0x1
4680
4681	/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */
4682	#define ALT_UART_CPR_FIFO_ACCESS_LSB 9
4683	/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */
4684	#define ALT_UART_CPR_FIFO_ACCESS_MSB 9
4685	/* The width in bits of the ALT_UART_CPR_FIFO_ACCESS register field. */
4686	#define ALT_UART_CPR_FIFO_ACCESS_WIDTH 1
4687	/* The mask used to set the ALT_UART_CPR_FIFO_ACCESS register field value. */
4688	#define ALT_UART_CPR_FIFO_ACCESS_SET_MSK 0x00000200
4689	/* The mask used to clear the ALT_UART_CPR_FIFO_ACCESS register field value. */
4690	#define ALT_UART_CPR_FIFO_ACCESS_CLR_MSK 0xfffffdff
4691	/* The reset value of the ALT_UART_CPR_FIFO_ACCESS register field. */
4692	#define ALT_UART_CPR_FIFO_ACCESS_RESET 0x1
4693	/* Extracts the ALT_UART_CPR_FIFO_ACCESS field value from a register. */
4694	#define ALT_UART_CPR_FIFO_ACCESS_GET(value) (((value) & 0x00000200) >> 9)
4695	/* Produces a ALT_UART_CPR_FIFO_ACCESS register field value suitable for setting the register. */
4696	#define ALT_UART_CPR_FIFO_ACCESS_SET(value) (((value) << 9) & 0x00000200)
4697
4698	/*
4699	* Field : FIFO STAT Supported - fifo_stat
4700	*
4701	* Configures the peripheral to have three additional FIFO status registers.
4702	*
4703	* Field Enumeration Values:
4704	*
4705	* Enum \| Value \| Description
4706	* :-----------------------------\|:------\|:--------------------
4707	* ALT_UART_CPR_FIFO_STAT_E_END \| 0x1 \| FIFO Stat Supported
4708	*
4709	* Field Access Macros:
4710	*
4711	*/
4712	/*
4713	* Enumerated value for register field ALT_UART_CPR_FIFO_STAT
4714	*
4715	* FIFO Stat Supported
4716	*/
4717	#define ALT_UART_CPR_FIFO_STAT_E_END 0x1
4718
4719	/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_STAT register field. */
4720	#define ALT_UART_CPR_FIFO_STAT_LSB 10
4721	/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_STAT register field. */
4722	#define ALT_UART_CPR_FIFO_STAT_MSB 10
4723	/* The width in bits of the ALT_UART_CPR_FIFO_STAT register field. */
4724	#define ALT_UART_CPR_FIFO_STAT_WIDTH 1
4725	/* The mask used to set the ALT_UART_CPR_FIFO_STAT register field value. */
4726	#define ALT_UART_CPR_FIFO_STAT_SET_MSK 0x00000400
4727	/* The mask used to clear the ALT_UART_CPR_FIFO_STAT register field value. */
4728	#define ALT_UART_CPR_FIFO_STAT_CLR_MSK 0xfffffbff
4729	/* The reset value of the ALT_UART_CPR_FIFO_STAT register field. */
4730	#define ALT_UART_CPR_FIFO_STAT_RESET 0x1
4731	/* Extracts the ALT_UART_CPR_FIFO_STAT field value from a register. */
4732	#define ALT_UART_CPR_FIFO_STAT_GET(value) (((value) & 0x00000400) >> 10)
4733	/* Produces a ALT_UART_CPR_FIFO_STAT register field value suitable for setting the register. */
4734	#define ALT_UART_CPR_FIFO_STAT_SET(value) (((value) << 10) & 0x00000400)
4735
4736	/*
4737	* Field : SHADOW Supported - shadow
4738	*
4739	* Configures the peripheral to have seven additional registers that shadow some of
4740	* the existing register bits that are regularly modified by software. These can be
4741	* used to reduce the software overhead that is introduced by having to perform
4742	* read-modify writes.
4743	*
4744	* Field Enumeration Values:
4745	*
4746	* Enum \| Value \| Description
4747	* :--------------------------\|:------\|:-----------------
4748	* ALT_UART_CPR_SHADOW_E_END \| 0x1 \| Shadow Supported
4749	*
4750	* Field Access Macros:
4751	*
4752	*/
4753	/*
4754	* Enumerated value for register field ALT_UART_CPR_SHADOW
4755	*
4756	* Shadow Supported
4757	*/
4758	#define ALT_UART_CPR_SHADOW_E_END 0x1
4759
4760	/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SHADOW register field. */
4761	#define ALT_UART_CPR_SHADOW_LSB 11
4762	/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SHADOW register field. */
4763	#define ALT_UART_CPR_SHADOW_MSB 11
4764	/* The width in bits of the ALT_UART_CPR_SHADOW register field. */
4765	#define ALT_UART_CPR_SHADOW_WIDTH 1
4766	/* The mask used to set the ALT_UART_CPR_SHADOW register field value. */
4767	#define ALT_UART_CPR_SHADOW_SET_MSK 0x00000800
4768	/* The mask used to clear the ALT_UART_CPR_SHADOW register field value. */
4769	#define ALT_UART_CPR_SHADOW_CLR_MSK 0xfffff7ff
4770	/* The reset value of the ALT_UART_CPR_SHADOW register field. */
4771	#define ALT_UART_CPR_SHADOW_RESET 0x1
4772	/* Extracts the ALT_UART_CPR_SHADOW field value from a register. */
4773	#define ALT_UART_CPR_SHADOW_GET(value) (((value) & 0x00000800) >> 11)
4774	/* Produces a ALT_UART_CPR_SHADOW register field value suitable for setting the register. */
4775	#define ALT_UART_CPR_SHADOW_SET(value) (((value) << 11) & 0x00000800)
4776
4777	/*
4778	* Field : Configuartion ID Register Present - uart_add_encoded_param
4779	*
4780	* Configures the peripheral to have a configuration identification register.
4781	*
4782	* Field Enumeration Values:
4783	*
4784	* Enum \| Value \| Description
4785	* :--------------------------------------\|:------\|:--------------------
4786	* ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END \| 0x1 \| ID register present
4787	*
4788	* Field Access Macros:
4789	*
4790	*/
4791	/*
4792	* Enumerated value for register field ALT_UART_CPR_UART_ADD_ENC_PARAM
4793	*
4794	* ID register present
4795	*/
4796	#define ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END 0x1
4797
4798	/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
4799	#define ALT_UART_CPR_UART_ADD_ENC_PARAM_LSB 12
4800	/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
4801	#define ALT_UART_CPR_UART_ADD_ENC_PARAM_MSB 12
4802	/* The width in bits of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
4803	#define ALT_UART_CPR_UART_ADD_ENC_PARAM_WIDTH 1
4804	/* The mask used to set the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */
4805	#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET_MSK 0x00001000
4806	/* The mask used to clear the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */
4807	#define ALT_UART_CPR_UART_ADD_ENC_PARAM_CLR_MSK 0xffffefff
4808	/* The reset value of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
4809	#define ALT_UART_CPR_UART_ADD_ENC_PARAM_RESET 0x1
4810	/* Extracts the ALT_UART_CPR_UART_ADD_ENC_PARAM field value from a register. */
4811	#define ALT_UART_CPR_UART_ADD_ENC_PARAM_GET(value) (((value) & 0x00001000) >> 12)
4812	/* Produces a ALT_UART_CPR_UART_ADD_ENC_PARAM register field value suitable for setting the register. */
4813	#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET(value) (((value) << 12) & 0x00001000)
4814
4815	/*
4816	* Field : DMA EXTRA Supported - dma_extra
4817	*
4818	* Configures the peripheral to have four additional DMA signals on the interface.
4819	*
4820	* Field Enumeration Values:
4821	*
4822	* Enum \| Value \| Description
4823	* :-----------------------------\|:------\|:--------------------
4824	* ALT_UART_CPR_DMA_EXTRA_E_END \| 0x1 \| DMA Extra Supported
4825	*
4826	* Field Access Macros:
4827	*
4828	*/
4829	/*
4830	* Enumerated value for register field ALT_UART_CPR_DMA_EXTRA
4831	*
4832	* DMA Extra Supported
4833	*/
4834	#define ALT_UART_CPR_DMA_EXTRA_E_END 0x1
4835
4836	/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */
4837	#define ALT_UART_CPR_DMA_EXTRA_LSB 13
4838	/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */
4839	#define ALT_UART_CPR_DMA_EXTRA_MSB 13
4840	/* The width in bits of the ALT_UART_CPR_DMA_EXTRA register field. */
4841	#define ALT_UART_CPR_DMA_EXTRA_WIDTH 1
4842	/* The mask used to set the ALT_UART_CPR_DMA_EXTRA register field value. */
4843	#define ALT_UART_CPR_DMA_EXTRA_SET_MSK 0x00002000
4844	/* The mask used to clear the ALT_UART_CPR_DMA_EXTRA register field value. */
4845	#define ALT_UART_CPR_DMA_EXTRA_CLR_MSK 0xffffdfff
4846	/* The reset value of the ALT_UART_CPR_DMA_EXTRA register field. */
4847	#define ALT_UART_CPR_DMA_EXTRA_RESET 0x1
4848	/* Extracts the ALT_UART_CPR_DMA_EXTRA field value from a register. */
4849	#define ALT_UART_CPR_DMA_EXTRA_GET(value) (((value) & 0x00002000) >> 13)
4850	/* Produces a ALT_UART_CPR_DMA_EXTRA register field value suitable for setting the register. */
4851	#define ALT_UART_CPR_DMA_EXTRA_SET(value) (((value) << 13) & 0x00002000)
4852
4853	/*
4854	* Field : FIFO Depth - fifo_mode
4855	*
4856	* Receiver and Transmitter FIFO depth in bytes.
4857	*
4858	* Field Enumeration Values:
4859	*
4860	* Enum \| Value \| Description
4861	* :-------------------------------------\|:------\|:---------------------
4862	* ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES \| 0x80 \| FIFO Depth 128 bytes
4863	*
4864	* Field Access Macros:
4865	*
4866	*/
4867	/*
4868	* Enumerated value for register field ALT_UART_CPR_FIFO_MOD
4869	*
4870	* FIFO Depth 128 bytes
4871	*/
4872	#define ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES 0x80
4873
4874	/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_MOD register field. */
4875	#define ALT_UART_CPR_FIFO_MOD_LSB 16
4876	/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_MOD register field. */
4877	#define ALT_UART_CPR_FIFO_MOD_MSB 23
4878	/* The width in bits of the ALT_UART_CPR_FIFO_MOD register field. */
4879	#define ALT_UART_CPR_FIFO_MOD_WIDTH 8
4880	/* The mask used to set the ALT_UART_CPR_FIFO_MOD register field value. */
4881	#define ALT_UART_CPR_FIFO_MOD_SET_MSK 0x00ff0000
4882	/* The mask used to clear the ALT_UART_CPR_FIFO_MOD register field value. */
4883	#define ALT_UART_CPR_FIFO_MOD_CLR_MSK 0xff00ffff
4884	/* The reset value of the ALT_UART_CPR_FIFO_MOD register field. */
4885	#define ALT_UART_CPR_FIFO_MOD_RESET 0x37
4886	/* Extracts the ALT_UART_CPR_FIFO_MOD field value from a register. */
4887	#define ALT_UART_CPR_FIFO_MOD_GET(value) (((value) & 0x00ff0000) >> 16)
4888	/* Produces a ALT_UART_CPR_FIFO_MOD register field value suitable for setting the register. */
4889	#define ALT_UART_CPR_FIFO_MOD_SET(value) (((value) << 16) & 0x00ff0000)
4890
4891	#ifndef __ASSEMBLY__
4892	/*
4893	* WARNING: The C register and register group struct declarations are provided for
4894	* convenience and illustrative purposes. They should, however, be used with
4895	* caution as the C language standard provides no guarantees about the alignment or
4896	* atomicity of device memory accesses. The recommended practice for writing
4897	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
4898	* alt_write_word() functions.
4899	*
4900	* The struct declaration for register ALT_UART_CPR.
4901	*/
4902	struct ALT_UART_CPR_s
4903	{
4904	const uint32_t apbdatawidth : 2; /* APB DATA WIDTH */
4905	uint32_t : 2; /* UNDEFINED */
4906	const uint32_t afce_mode : 1; /* Auto Flow Control */
4907	const uint32_t thre_mode : 1; /* THRE MODE */
4908	const uint32_t sir_mode : 1; /* SIR MODE Unsupported */
4909	const uint32_t sir_lp_mode : 1; /* SIR LP MODE Unsupported */
4910	const uint32_t additional_feat : 1; /* ADDITIONAL FEATURES Supported */
4911	const uint32_t fifo_access : 1; /* FIFO ACCESS Supported */
4912	const uint32_t fifo_stat : 1; /* FIFO STAT Supported */
4913	const uint32_t shadow : 1; /* SHADOW Supported */
4914	const uint32_t uart_add_encoded_param : 1; /* Configuartion ID Register Present */
4915	const uint32_t dma_extra : 1; /* DMA EXTRA Supported */
4916	uint32_t : 2; /* UNDEFINED */
4917	const uint32_t fifo_mode : 8; /* FIFO Depth */
4918	uint32_t : 8; /* UNDEFINED */
4919	};
4920
4921	/* The typedef declaration for register ALT_UART_CPR. */
4922	typedef volatile struct ALT_UART_CPR_s ALT_UART_CPR_t;
4923	#endif /* __ASSEMBLY__ */
4924
4925	/* The byte offset of the ALT_UART_CPR register from the beginning of the component. */
4926	#define ALT_UART_CPR_OFST 0xf4
4927	/* The address of the ALT_UART_CPR register. */
4928	#define ALT_UART_CPR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_CPR_OFST))
4929
4930	/*
4931	* Register : Component Version - ucv
4932	*
4933	* Used only with Additional Features
4934	*
4935	* Register Layout
4936	*
4937	* Bits \| Access \| Reset \| Description
4938	* :-------\|:-------\|:-----------\|:--------------
4939	* [31:0] \| R \| 0x3331312a \| ASCII version
4940	*
4941	*/
4942	/*
4943	* Field : ASCII version - uart_component_version
4944	*
4945	* ASCII value for each number in the version, followed by *For example 32_30_31_2A
4946	* represents the version 2.01a
4947	*
4948	* Field Access Macros:
4949	*
4950	*/
4951	/* The Least Significant Bit (LSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
4952	#define ALT_UART_UCV_UART_COMPONENT_VER_LSB 0
4953	/* The Most Significant Bit (MSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
4954	#define ALT_UART_UCV_UART_COMPONENT_VER_MSB 31
4955	/* The width in bits of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
4956	#define ALT_UART_UCV_UART_COMPONENT_VER_WIDTH 32
4957	/* The mask used to set the ALT_UART_UCV_UART_COMPONENT_VER register field value. */
4958	#define ALT_UART_UCV_UART_COMPONENT_VER_SET_MSK 0xffffffff
4959	/* The mask used to clear the ALT_UART_UCV_UART_COMPONENT_VER register field value. */
4960	#define ALT_UART_UCV_UART_COMPONENT_VER_CLR_MSK 0x00000000
4961	/* The reset value of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
4962	#define ALT_UART_UCV_UART_COMPONENT_VER_RESET 0x3331312a
4963	/* Extracts the ALT_UART_UCV_UART_COMPONENT_VER field value from a register. */
4964	#define ALT_UART_UCV_UART_COMPONENT_VER_GET(value) (((value) & 0xffffffff) >> 0)
4965	/* Produces a ALT_UART_UCV_UART_COMPONENT_VER register field value suitable for setting the register. */
4966	#define ALT_UART_UCV_UART_COMPONENT_VER_SET(value) (((value) << 0) & 0xffffffff)
4967
4968	#ifndef __ASSEMBLY__
4969	/*
4970	* WARNING: The C register and register group struct declarations are provided for
4971	* convenience and illustrative purposes. They should, however, be used with
4972	* caution as the C language standard provides no guarantees about the alignment or
4973	* atomicity of device memory accesses. The recommended practice for writing
4974	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
4975	* alt_write_word() functions.
4976	*
4977	* The struct declaration for register ALT_UART_UCV.
4978	*/
4979	struct ALT_UART_UCV_s
4980	{
4981	const uint32_t uart_component_version : 32; /* ASCII version */
4982	};
4983
4984	/* The typedef declaration for register ALT_UART_UCV. */
4985	typedef volatile struct ALT_UART_UCV_s ALT_UART_UCV_t;
4986	#endif /* __ASSEMBLY__ */
4987
4988	/* The byte offset of the ALT_UART_UCV register from the beginning of the component. */
4989	#define ALT_UART_UCV_OFST 0xf8
4990	/* The address of the ALT_UART_UCV register. */
4991	#define ALT_UART_UCV_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_UCV_OFST))
4992
4993	/*
4994	* Register : Component Type Register - ctr
4995	*
4996	* Describes a hex value associated with the component.
4997	*
4998	* Register Layout
4999	*
5000	* Bits \| Access \| Reset \| Description
5001	* :-------\|:-------\|:-----------\|:--------------
5002	* [31:0] \| R \| 0x44570110 \| Peripheral ID
5003	*
5004	*/
5005	/*
5006	* Field : Peripheral ID - peripheral_id
5007	*
5008	* This register contains the peripherals identification code.
5009	*
5010	* Field Access Macros:
5011	*
5012	*/
5013	/* The Least Significant Bit (LSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */
5014	#define ALT_UART_CTR_PERIPHERAL_ID_LSB 0
5015	/* The Most Significant Bit (MSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */
5016	#define ALT_UART_CTR_PERIPHERAL_ID_MSB 31
5017	/* The width in bits of the ALT_UART_CTR_PERIPHERAL_ID register field. */
5018	#define ALT_UART_CTR_PERIPHERAL_ID_WIDTH 32
5019	/* The mask used to set the ALT_UART_CTR_PERIPHERAL_ID register field value. */
5020	#define ALT_UART_CTR_PERIPHERAL_ID_SET_MSK 0xffffffff
5021	/* The mask used to clear the ALT_UART_CTR_PERIPHERAL_ID register field value. */
5022	#define ALT_UART_CTR_PERIPHERAL_ID_CLR_MSK 0x00000000
5023	/* The reset value of the ALT_UART_CTR_PERIPHERAL_ID register field. */
5024	#define ALT_UART_CTR_PERIPHERAL_ID_RESET 0x44570110
5025	/* Extracts the ALT_UART_CTR_PERIPHERAL_ID field value from a register. */
5026	#define ALT_UART_CTR_PERIPHERAL_ID_GET(value) (((value) & 0xffffffff) >> 0)
5027	/* Produces a ALT_UART_CTR_PERIPHERAL_ID register field value suitable for setting the register. */
5028	#define ALT_UART_CTR_PERIPHERAL_ID_SET(value) (((value) << 0) & 0xffffffff)
5029
5030	#ifndef __ASSEMBLY__
5031	/*
5032	* WARNING: The C register and register group struct declarations are provided for
5033	* convenience and illustrative purposes. They should, however, be used with
5034	* caution as the C language standard provides no guarantees about the alignment or
5035	* atomicity of device memory accesses. The recommended practice for writing
5036	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
5037	* alt_write_word() functions.
5038	*
5039	* The struct declaration for register ALT_UART_CTR.
5040	*/
5041	struct ALT_UART_CTR_s
5042	{
5043	const uint32_t peripheral_id : 32; /* Peripheral ID */
5044	};
5045
5046	/* The typedef declaration for register ALT_UART_CTR. */
5047	typedef volatile struct ALT_UART_CTR_s ALT_UART_CTR_t;
5048	#endif /* __ASSEMBLY__ */
5049
5050	/* The byte offset of the ALT_UART_CTR register from the beginning of the component. */
5051	#define ALT_UART_CTR_OFST 0xfc
5052	/* The address of the ALT_UART_CTR register. */
5053	#define ALT_UART_CTR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_UART_CTR_OFST))
5054
5055	#ifndef __ASSEMBLY__
5056	/*
5057	* WARNING: The C register and register group struct declarations are provided for
5058	* convenience and illustrative purposes. They should, however, be used with
5059	* caution as the C language standard provides no guarantees about the alignment or
5060	* atomicity of device memory accesses. The recommended practice for writing
5061	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
5062	* alt_write_word() functions.
5063	*
5064	* The struct declaration for register group ALT_UART.
5065	*/
5066	struct ALT_UART_s
5067	{
5068	volatile ALT_UART_RBR_THR_DLL_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */
5069	volatile ALT_UART_IER_DLH_t ier_dlh; /* ALT_UART_IER_DLH */
5070	/* Union for registers colocated at base address offset #0x. */
5071	union
5072	{
5073	volatile ALT_UART_IIR_t iir; /* ALT_UART_IIR */
5074	volatile ALT_UART_FCR_t fcr; /* ALT_UART_FCR */
5075	} _u_0x8;
5076	volatile ALT_UART_LCR_t lcr; /* ALT_UART_LCR */
5077	volatile ALT_UART_MCR_t mcr; /* ALT_UART_MCR */
5078	volatile ALT_UART_LSR_t lsr; /* ALT_UART_LSR */
5079	volatile ALT_UART_MSR_t msr; /* ALT_UART_MSR */
5080	volatile ALT_UART_SCR_t scr; /* ALT_UART_SCR */
5081	volatile uint32_t _pad_0x20_0x2f[4]; /* UNDEFINED */
5082	volatile ALT_UART_SRBR_t srbr; /* ALT_UART_SRBR */
5083	volatile ALT_UART_STHR_t sthr; /* ALT_UART_STHR */
5084	volatile uint32_t _pad_0x38_0x6f[14]; /* UNDEFINED */
5085	volatile ALT_UART_FAR_t far; /* ALT_UART_FAR */
5086	volatile ALT_UART_TFR_t tfr; /* ALT_UART_TFR */
5087	volatile ALT_UART_RFW_t RFW; /* ALT_UART_RFW */
5088	volatile ALT_UART_USR_t usr; /* ALT_UART_USR */
5089	volatile ALT_UART_TFL_t tfl; /* ALT_UART_TFL */
5090	volatile ALT_UART_RFL_t rfl; /* ALT_UART_RFL */
5091	volatile ALT_UART_SRR_t srr; /* ALT_UART_SRR */
5092	volatile ALT_UART_SRTS_t srts; /* ALT_UART_SRTS */
5093	volatile ALT_UART_SBCR_t sbcr; /* ALT_UART_SBCR */
5094	volatile ALT_UART_SDMAM_t sdmam; /* ALT_UART_SDMAM */
5095	volatile ALT_UART_SFE_t sfe; /* ALT_UART_SFE */
5096	volatile ALT_UART_SRT_t srt; /* ALT_UART_SRT */
5097	volatile ALT_UART_STET_t stet; /* ALT_UART_STET */
5098	volatile ALT_UART_HTX_t htx; /* ALT_UART_HTX */
5099	volatile ALT_UART_DMASA_t dmasa; /* ALT_UART_DMASA */
5100	volatile uint32_t _pad_0xac_0xf3[18]; /* UNDEFINED */
5101	volatile ALT_UART_CPR_t cpr; /* ALT_UART_CPR */
5102	volatile ALT_UART_UCV_t ucv; /* ALT_UART_UCV */
5103	volatile ALT_UART_CTR_t ctr; /* ALT_UART_CTR */
5104	};
5105
5106	/* The typedef declaration for register group ALT_UART. */
5107	typedef volatile struct ALT_UART_s ALT_UART_t;
5108	/* The struct declaration for the raw register contents of register group ALT_UART. */
5109	struct ALT_UART_raw_s
5110	{
5111	volatile uint32_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */
5112	volatile uint32_t ier_dlh; /* ALT_UART_IER_DLH */
5113	/* Union for registers colocated at base address offset #0x. */
5114	union
5115	{
5116	volatile uint32_t iir; /* ALT_UART_IIR */
5117	volatile uint32_t fcr; /* ALT_UART_FCR */
5118	} _u_0x8;
5119	volatile uint32_t lcr; /* ALT_UART_LCR */
5120	volatile uint32_t mcr; /* ALT_UART_MCR */
5121	volatile uint32_t lsr; /* ALT_UART_LSR */
5122	volatile uint32_t msr; /* ALT_UART_MSR */
5123	volatile uint32_t scr; /* ALT_UART_SCR */
5124	volatile uint32_t _pad_0x20_0x2f[4]; /* UNDEFINED */
5125	volatile uint32_t srbr; /* ALT_UART_SRBR */
5126	volatile uint32_t sthr; /* ALT_UART_STHR */
5127	volatile uint32_t _pad_0x38_0x6f[14]; /* UNDEFINED */
5128	volatile uint32_t far; /* ALT_UART_FAR */
5129	volatile uint32_t tfr; /* ALT_UART_TFR */
5130	volatile uint32_t RFW; /* ALT_UART_RFW */
5131	volatile uint32_t usr; /* ALT_UART_USR */
5132	volatile uint32_t tfl; /* ALT_UART_TFL */
5133	volatile uint32_t rfl; /* ALT_UART_RFL */
5134	volatile uint32_t srr; /* ALT_UART_SRR */
5135	volatile uint32_t srts; /* ALT_UART_SRTS */
5136	volatile uint32_t sbcr; /* ALT_UART_SBCR */
5137	volatile uint32_t sdmam; /* ALT_UART_SDMAM */
5138	volatile uint32_t sfe; /* ALT_UART_SFE */
5139	volatile uint32_t srt; /* ALT_UART_SRT */
5140	volatile uint32_t stet; /* ALT_UART_STET */
5141	volatile uint32_t htx; /* ALT_UART_HTX */
5142	volatile uint32_t dmasa; /* ALT_UART_DMASA */
5143	volatile uint32_t _pad_0xac_0xf3[18]; /* UNDEFINED */
5144	volatile uint32_t cpr; /* ALT_UART_CPR */
5145	volatile uint32_t ucv; /* ALT_UART_UCV */
5146	volatile uint32_t ctr; /* ALT_UART_CTR */
5147	};
5148
5149	/* The typedef declaration for the raw register contents of register group ALT_UART. */
5150	typedef volatile struct ALT_UART_raw_s ALT_UART_raw_t;
5151	#endif /* __ASSEMBLY__ */
5152
5153
5154	#ifdef __cplusplus
5155	}
5156	#endif /* __cplusplus */
5157	#endif /* __ALTERA_ALT_UART_H__ */
5158

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source: rtems/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h @ 2afb22b

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