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alt_rstmgr.h @ 2afb22b

Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

The make preinstall step itself needs time and disk space.

Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.

There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.

The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.

An introduction of a new build system is difficult.

Include paths specified by the -B option are system headers. This may suppress warnings.

The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

cpukit/include

cpukit/score/cpu/@RTEMS_CPU@/include

cpukit/libnetworking

The new BSP include directories are:

bsps/include

bsps/@RTEMS_CPU@/include

bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

Property mode set to 100644

File size: 168.5 KB

Line
1	/*******************************************************************************
2	* *
3	* Copyright 2013 Altera Corporation. All Rights Reserved. *
4	* *
5	* Redistribution and use in source and binary forms, with or without *
6	* modification, are permitted provided that the following conditions are met: *
7	* *
8	* 1. Redistributions of source code must retain the above copyright notice, *
9	* this list of conditions and the following disclaimer. *
10	* *
11	* 2. Redistributions in binary form must reproduce the above copyright notice, *
12	* this list of conditions and the following disclaimer in the documentation *
13	* and/or other materials provided with the distribution. *
14	* *
15	* 3. The name of the author may not be used to endorse or promote products *
16	* derived from this software without specific prior written permission. *
17	* *
18	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
20	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
21	* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
22	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
23	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
24	* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
25	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
26	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
27	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
28	* *
29	*******************************************************************************/
30
31	/* Altera - ALT_RSTMGR */
32
33	#ifndef __ALTERA_ALT_RSTMGR_H__
34	#define __ALTERA_ALT_RSTMGR_H__
35
36	#ifdef __cplusplus
37	extern "C"
38	{
39	#endif /* __cplusplus */
40
41	/*
42	* Component : Reset Manager Module - ALT_RSTMGR
43	* Reset Manager Module
44	*
45	* Registers in the Reset Manager module
46	*
47	*/
48	/*
49	* Register : Status Register - stat
50	*
51	* The STAT register contains bits that indicate the reset source or a timeout
52	* event. For reset sources, a field is 1 if its associated reset requester caused
53	* the reset. For timeout events, a field is 1 if its associated timeout occured as
54	* part of a hardware sequenced warm/debug reset.
55	*
56	* Software clears bits by writing them with a value of 1. Writes to bits with a
57	* value of 0 are ignored.
58	*
59	* After a cold reset is complete, all bits are reset to their reset value except
60	* for the bit(s) that indicate the source of the cold reset. If multiple cold
61	* reset requests overlap with each other, the source de-asserts the request last
62	* will be logged. The other reset request source(s) de-assert the request in the
63	* same cycle will also be logged, the rest of the fields are reset to default
64	* value of 0.
65	*
66	* After a warm reset is complete, the bit(s) that indicate the source of the warm
67	* reset are set to 1. A warm reset doesn't clear any of the bits in the STAT
68	* register; these bits must be cleared by software writing the STAT register.
69	*
70	* Register Layout
71	*
72	* Bits \| Access \| Reset \| Description
73	* :--------\|:-------\|:------\|:-------------------------------------
74	* [0] \| RW \| 0x0 \| Power-On Voltage Detector Cold Reset
75	* [1] \| RW \| 0x0 \| nPOR Pin Cold Reset
76	* [2] \| RW \| 0x0 \| FPGA Core Cold Reset
77	* [3] \| RW \| 0x0 \| CONFIG_IO Cold Reset
78	* [4] \| RW \| 0x0 \| Software Cold Reset
79	* [7:5] \| ??? \| 0x0 \| UNDEFINED
80	* [8] \| RW \| 0x0 \| nRST Pin Warm Reset
81	* [9] \| RW \| 0x0 \| FPGA Core Warm Reset
82	* [10] \| RW \| 0x0 \| Software Warm Reset
83	* [11] \| ??? \| 0x0 \| UNDEFINED
84	* [12] \| RW \| 0x0 \| MPU Watchdog 0 Warm Reset
85	* [13] \| RW \| 0x0 \| MPU Watchdog 1 Warm Reset
86	* [14] \| RW \| 0x0 \| L4 Watchdog 0 Warm Reset
87	* [15] \| RW \| 0x0 \| L4 Watchdog 1 Warm Reset
88	* [17:16] \| ??? \| 0x0 \| UNDEFINED
89	* [18] \| RW \| 0x0 \| FPGA Core Debug Reset
90	* [19] \| RW \| 0x0 \| DAP Debug Reset
91	* [23:20] \| ??? \| 0x0 \| UNDEFINED
92	* [24] \| RW \| 0x0 \| SDRAM Self-Refresh Timeout
93	* [25] \| RW \| 0x0 \| FPGA manager handshake Timeout
94	* [26] \| RW \| 0x0 \| SCAN manager handshake Timeout
95	* [27] \| RW \| 0x0 \| FPGA handshake Timeout
96	* [28] \| RW \| 0x0 \| ETR Stall Timeout
97	* [31:29] \| ??? \| 0x0 \| UNDEFINED
98	*
99	*/
100	/*
101	* Field : Power-On Voltage Detector Cold Reset - porvoltrst
102	*
103	* Built-in POR voltage detector triggered a cold reset (por_voltage_req = 1)
104	*
105	* Field Access Macros:
106	*
107	*/
108	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
109	#define ALT_RSTMGR_STAT_PORVOLTRST_LSB 0
110	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
111	#define ALT_RSTMGR_STAT_PORVOLTRST_MSB 0
112	/* The width in bits of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
113	#define ALT_RSTMGR_STAT_PORVOLTRST_WIDTH 1
114	/* The mask used to set the ALT_RSTMGR_STAT_PORVOLTRST register field value. */
115	#define ALT_RSTMGR_STAT_PORVOLTRST_SET_MSK 0x00000001
116	/* The mask used to clear the ALT_RSTMGR_STAT_PORVOLTRST register field value. */
117	#define ALT_RSTMGR_STAT_PORVOLTRST_CLR_MSK 0xfffffffe
118	/* The reset value of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
119	#define ALT_RSTMGR_STAT_PORVOLTRST_RESET 0x0
120	/* Extracts the ALT_RSTMGR_STAT_PORVOLTRST field value from a register. */
121	#define ALT_RSTMGR_STAT_PORVOLTRST_GET(value) (((value) & 0x00000001) >> 0)
122	/* Produces a ALT_RSTMGR_STAT_PORVOLTRST register field value suitable for setting the register. */
123	#define ALT_RSTMGR_STAT_PORVOLTRST_SET(value) (((value) << 0) & 0x00000001)
124
125	/*
126	* Field : nPOR Pin Cold Reset - nporpinrst
127	*
128	* nPOR pin triggered a cold reset (por_pin_req = 1)
129	*
130	* Field Access Macros:
131	*
132	*/
133	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */
134	#define ALT_RSTMGR_STAT_NPORPINRST_LSB 1
135	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */
136	#define ALT_RSTMGR_STAT_NPORPINRST_MSB 1
137	/* The width in bits of the ALT_RSTMGR_STAT_NPORPINRST register field. */
138	#define ALT_RSTMGR_STAT_NPORPINRST_WIDTH 1
139	/* The mask used to set the ALT_RSTMGR_STAT_NPORPINRST register field value. */
140	#define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK 0x00000002
141	/* The mask used to clear the ALT_RSTMGR_STAT_NPORPINRST register field value. */
142	#define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK 0xfffffffd
143	/* The reset value of the ALT_RSTMGR_STAT_NPORPINRST register field. */
144	#define ALT_RSTMGR_STAT_NPORPINRST_RESET 0x0
145	/* Extracts the ALT_RSTMGR_STAT_NPORPINRST field value from a register. */
146	#define ALT_RSTMGR_STAT_NPORPINRST_GET(value) (((value) & 0x00000002) >> 1)
147	/* Produces a ALT_RSTMGR_STAT_NPORPINRST register field value suitable for setting the register. */
148	#define ALT_RSTMGR_STAT_NPORPINRST_SET(value) (((value) << 1) & 0x00000002)
149
150	/*
151	* Field : FPGA Core Cold Reset - fpgacoldrst
152	*
153	* FPGA core triggered a cold reset (f2h_cold_rst_req_n = 1)
154	*
155	* Field Access Macros:
156	*
157	*/
158	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
159	#define ALT_RSTMGR_STAT_FPGACOLDRST_LSB 2
160	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
161	#define ALT_RSTMGR_STAT_FPGACOLDRST_MSB 2
162	/* The width in bits of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
163	#define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH 1
164	/* The mask used to set the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */
165	#define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK 0x00000004
166	/* The mask used to clear the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */
167	#define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK 0xfffffffb
168	/* The reset value of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
169	#define ALT_RSTMGR_STAT_FPGACOLDRST_RESET 0x0
170	/* Extracts the ALT_RSTMGR_STAT_FPGACOLDRST field value from a register. */
171	#define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value) (((value) & 0x00000004) >> 2)
172	/* Produces a ALT_RSTMGR_STAT_FPGACOLDRST register field value suitable for setting the register. */
173	#define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value) (((value) << 2) & 0x00000004)
174
175	/*
176	* Field : CONFIG_IO Cold Reset - configiocoldrst
177	*
178	* FPGA entered CONFIG_IO mode and a triggered a cold reset
179	*
180	* Field Access Macros:
181	*
182	*/
183	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
184	#define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB 3
185	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
186	#define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB 3
187	/* The width in bits of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
188	#define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH 1
189	/* The mask used to set the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */
190	#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK 0x00000008
191	/* The mask used to clear the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */
192	#define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK 0xfffffff7
193	/* The reset value of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
194	#define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET 0x0
195	/* Extracts the ALT_RSTMGR_STAT_CFGIOCOLDRST field value from a register. */
196	#define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value) (((value) & 0x00000008) >> 3)
197	/* Produces a ALT_RSTMGR_STAT_CFGIOCOLDRST register field value suitable for setting the register. */
198	#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value) (((value) << 3) & 0x00000008)
199
200	/*
201	* Field : Software Cold Reset - swcoldrst
202	*
203	* Software wrote CTRL.SWCOLDRSTREQ to 1 and triggered a cold reset
204	*
205	* Field Access Macros:
206	*
207	*/
208	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
209	#define ALT_RSTMGR_STAT_SWCOLDRST_LSB 4
210	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
211	#define ALT_RSTMGR_STAT_SWCOLDRST_MSB 4
212	/* The width in bits of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
213	#define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH 1
214	/* The mask used to set the ALT_RSTMGR_STAT_SWCOLDRST register field value. */
215	#define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK 0x00000010
216	/* The mask used to clear the ALT_RSTMGR_STAT_SWCOLDRST register field value. */
217	#define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK 0xffffffef
218	/* The reset value of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
219	#define ALT_RSTMGR_STAT_SWCOLDRST_RESET 0x0
220	/* Extracts the ALT_RSTMGR_STAT_SWCOLDRST field value from a register. */
221	#define ALT_RSTMGR_STAT_SWCOLDRST_GET(value) (((value) & 0x00000010) >> 4)
222	/* Produces a ALT_RSTMGR_STAT_SWCOLDRST register field value suitable for setting the register. */
223	#define ALT_RSTMGR_STAT_SWCOLDRST_SET(value) (((value) << 4) & 0x00000010)
224
225	/*
226	* Field : nRST Pin Warm Reset - nrstpinrst
227	*
228	* nRST pin triggered a hardware sequenced warm reset
229	*
230	* Field Access Macros:
231	*
232	*/
233	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
234	#define ALT_RSTMGR_STAT_NRSTPINRST_LSB 8
235	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
236	#define ALT_RSTMGR_STAT_NRSTPINRST_MSB 8
237	/* The width in bits of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
238	#define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH 1
239	/* The mask used to set the ALT_RSTMGR_STAT_NRSTPINRST register field value. */
240	#define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK 0x00000100
241	/* The mask used to clear the ALT_RSTMGR_STAT_NRSTPINRST register field value. */
242	#define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK 0xfffffeff
243	/* The reset value of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
244	#define ALT_RSTMGR_STAT_NRSTPINRST_RESET 0x0
245	/* Extracts the ALT_RSTMGR_STAT_NRSTPINRST field value from a register. */
246	#define ALT_RSTMGR_STAT_NRSTPINRST_GET(value) (((value) & 0x00000100) >> 8)
247	/* Produces a ALT_RSTMGR_STAT_NRSTPINRST register field value suitable for setting the register. */
248	#define ALT_RSTMGR_STAT_NRSTPINRST_SET(value) (((value) << 8) & 0x00000100)
249
250	/*
251	* Field : FPGA Core Warm Reset - fpgawarmrst
252	*
253	* FPGA core triggered a hardware sequenced warm reset (f2h_warm_rst_req_n = 1)
254	*
255	* Field Access Macros:
256	*
257	*/
258	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
259	#define ALT_RSTMGR_STAT_FPGAWARMRST_LSB 9
260	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
261	#define ALT_RSTMGR_STAT_FPGAWARMRST_MSB 9
262	/* The width in bits of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
263	#define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH 1
264	/* The mask used to set the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */
265	#define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK 0x00000200
266	/* The mask used to clear the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */
267	#define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK 0xfffffdff
268	/* The reset value of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
269	#define ALT_RSTMGR_STAT_FPGAWARMRST_RESET 0x0
270	/* Extracts the ALT_RSTMGR_STAT_FPGAWARMRST field value from a register. */
271	#define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value) (((value) & 0x00000200) >> 9)
272	/* Produces a ALT_RSTMGR_STAT_FPGAWARMRST register field value suitable for setting the register. */
273	#define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value) (((value) << 9) & 0x00000200)
274
275	/*
276	* Field : Software Warm Reset - swwarmrst
277	*
278	* Software wrote CTRL.SWWARMRSTREQ to 1 and triggered a hardware sequenced warm
279	* reset
280	*
281	* Field Access Macros:
282	*
283	*/
284	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */
285	#define ALT_RSTMGR_STAT_SWWARMRST_LSB 10
286	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */
287	#define ALT_RSTMGR_STAT_SWWARMRST_MSB 10
288	/* The width in bits of the ALT_RSTMGR_STAT_SWWARMRST register field. */
289	#define ALT_RSTMGR_STAT_SWWARMRST_WIDTH 1
290	/* The mask used to set the ALT_RSTMGR_STAT_SWWARMRST register field value. */
291	#define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK 0x00000400
292	/* The mask used to clear the ALT_RSTMGR_STAT_SWWARMRST register field value. */
293	#define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK 0xfffffbff
294	/* The reset value of the ALT_RSTMGR_STAT_SWWARMRST register field. */
295	#define ALT_RSTMGR_STAT_SWWARMRST_RESET 0x0
296	/* Extracts the ALT_RSTMGR_STAT_SWWARMRST field value from a register. */
297	#define ALT_RSTMGR_STAT_SWWARMRST_GET(value) (((value) & 0x00000400) >> 10)
298	/* Produces a ALT_RSTMGR_STAT_SWWARMRST register field value suitable for setting the register. */
299	#define ALT_RSTMGR_STAT_SWWARMRST_SET(value) (((value) << 10) & 0x00000400)
300
301	/*
302	* Field : MPU Watchdog 0 Warm Reset - mpuwd0rst
303	*
304	* MPU Watchdog 0 triggered a hardware sequenced warm reset
305	*
306	* Field Access Macros:
307	*
308	*/
309	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
310	#define ALT_RSTMGR_STAT_MPUWD0RST_LSB 12
311	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
312	#define ALT_RSTMGR_STAT_MPUWD0RST_MSB 12
313	/* The width in bits of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
314	#define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH 1
315	/* The mask used to set the ALT_RSTMGR_STAT_MPUWD0RST register field value. */
316	#define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK 0x00001000
317	/* The mask used to clear the ALT_RSTMGR_STAT_MPUWD0RST register field value. */
318	#define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK 0xffffefff
319	/* The reset value of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
320	#define ALT_RSTMGR_STAT_MPUWD0RST_RESET 0x0
321	/* Extracts the ALT_RSTMGR_STAT_MPUWD0RST field value from a register. */
322	#define ALT_RSTMGR_STAT_MPUWD0RST_GET(value) (((value) & 0x00001000) >> 12)
323	/* Produces a ALT_RSTMGR_STAT_MPUWD0RST register field value suitable for setting the register. */
324	#define ALT_RSTMGR_STAT_MPUWD0RST_SET(value) (((value) << 12) & 0x00001000)
325
326	/*
327	* Field : MPU Watchdog 1 Warm Reset - mpuwd1rst
328	*
329	* MPU Watchdog 1 triggered a hardware sequenced warm reset
330	*
331	* Field Access Macros:
332	*
333	*/
334	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
335	#define ALT_RSTMGR_STAT_MPUWD1RST_LSB 13
336	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
337	#define ALT_RSTMGR_STAT_MPUWD1RST_MSB 13
338	/* The width in bits of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
339	#define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH 1
340	/* The mask used to set the ALT_RSTMGR_STAT_MPUWD1RST register field value. */
341	#define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK 0x00002000
342	/* The mask used to clear the ALT_RSTMGR_STAT_MPUWD1RST register field value. */
343	#define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK 0xffffdfff
344	/* The reset value of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
345	#define ALT_RSTMGR_STAT_MPUWD1RST_RESET 0x0
346	/* Extracts the ALT_RSTMGR_STAT_MPUWD1RST field value from a register. */
347	#define ALT_RSTMGR_STAT_MPUWD1RST_GET(value) (((value) & 0x00002000) >> 13)
348	/* Produces a ALT_RSTMGR_STAT_MPUWD1RST register field value suitable for setting the register. */
349	#define ALT_RSTMGR_STAT_MPUWD1RST_SET(value) (((value) << 13) & 0x00002000)
350
351	/*
352	* Field : L4 Watchdog 0 Warm Reset - l4wd0rst
353	*
354	* L4 Watchdog 0 triggered a hardware sequenced warm reset
355	*
356	* Field Access Macros:
357	*
358	*/
359	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */
360	#define ALT_RSTMGR_STAT_L4WD0RST_LSB 14
361	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */
362	#define ALT_RSTMGR_STAT_L4WD0RST_MSB 14
363	/* The width in bits of the ALT_RSTMGR_STAT_L4WD0RST register field. */
364	#define ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1
365	/* The mask used to set the ALT_RSTMGR_STAT_L4WD0RST register field value. */
366	#define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00004000
367	/* The mask used to clear the ALT_RSTMGR_STAT_L4WD0RST register field value. */
368	#define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xffffbfff
369	/* The reset value of the ALT_RSTMGR_STAT_L4WD0RST register field. */
370	#define ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0
371	/* Extracts the ALT_RSTMGR_STAT_L4WD0RST field value from a register. */
372	#define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00004000) >> 14)
373	/* Produces a ALT_RSTMGR_STAT_L4WD0RST register field value suitable for setting the register. */
374	#define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 14) & 0x00004000)
375
376	/*
377	* Field : L4 Watchdog 1 Warm Reset - l4wd1rst
378	*
379	* L4 Watchdog 1 triggered a hardware sequenced warm reset
380	*
381	* Field Access Macros:
382	*
383	*/
384	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */
385	#define ALT_RSTMGR_STAT_L4WD1RST_LSB 15
386	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */
387	#define ALT_RSTMGR_STAT_L4WD1RST_MSB 15
388	/* The width in bits of the ALT_RSTMGR_STAT_L4WD1RST register field. */
389	#define ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1
390	/* The mask used to set the ALT_RSTMGR_STAT_L4WD1RST register field value. */
391	#define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00008000
392	/* The mask used to clear the ALT_RSTMGR_STAT_L4WD1RST register field value. */
393	#define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xffff7fff
394	/* The reset value of the ALT_RSTMGR_STAT_L4WD1RST register field. */
395	#define ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0
396	/* Extracts the ALT_RSTMGR_STAT_L4WD1RST field value from a register. */
397	#define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00008000) >> 15)
398	/* Produces a ALT_RSTMGR_STAT_L4WD1RST register field value suitable for setting the register. */
399	#define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 15) & 0x00008000)
400
401	/*
402	* Field : FPGA Core Debug Reset - fpgadbgrst
403	*
404	* FPGA triggered debug reset (f2h_dbg_rst_req_n = 1)
405	*
406	* Field Access Macros:
407	*
408	*/
409	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
410	#define ALT_RSTMGR_STAT_FPGADBGRST_LSB 18
411	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
412	#define ALT_RSTMGR_STAT_FPGADBGRST_MSB 18
413	/* The width in bits of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
414	#define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH 1
415	/* The mask used to set the ALT_RSTMGR_STAT_FPGADBGRST register field value. */
416	#define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK 0x00040000
417	/* The mask used to clear the ALT_RSTMGR_STAT_FPGADBGRST register field value. */
418	#define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK 0xfffbffff
419	/* The reset value of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
420	#define ALT_RSTMGR_STAT_FPGADBGRST_RESET 0x0
421	/* Extracts the ALT_RSTMGR_STAT_FPGADBGRST field value from a register. */
422	#define ALT_RSTMGR_STAT_FPGADBGRST_GET(value) (((value) & 0x00040000) >> 18)
423	/* Produces a ALT_RSTMGR_STAT_FPGADBGRST register field value suitable for setting the register. */
424	#define ALT_RSTMGR_STAT_FPGADBGRST_SET(value) (((value) << 18) & 0x00040000)
425
426	/*
427	* Field : DAP Debug Reset - cdbgreqrst
428	*
429	* DAP triggered debug reset
430	*
431	* Field Access Macros:
432	*
433	*/
434	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
435	#define ALT_RSTMGR_STAT_CDBGREQRST_LSB 19
436	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
437	#define ALT_RSTMGR_STAT_CDBGREQRST_MSB 19
438	/* The width in bits of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
439	#define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH 1
440	/* The mask used to set the ALT_RSTMGR_STAT_CDBGREQRST register field value. */
441	#define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK 0x00080000
442	/* The mask used to clear the ALT_RSTMGR_STAT_CDBGREQRST register field value. */
443	#define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK 0xfff7ffff
444	/* The reset value of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
445	#define ALT_RSTMGR_STAT_CDBGREQRST_RESET 0x0
446	/* Extracts the ALT_RSTMGR_STAT_CDBGREQRST field value from a register. */
447	#define ALT_RSTMGR_STAT_CDBGREQRST_GET(value) (((value) & 0x00080000) >> 19)
448	/* Produces a ALT_RSTMGR_STAT_CDBGREQRST register field value suitable for setting the register. */
449	#define ALT_RSTMGR_STAT_CDBGREQRST_SET(value) (((value) << 19) & 0x00080000)
450
451	/*
452	* Field : SDRAM Self-Refresh Timeout - sdrselfreftimeout
453	*
454	* A 1 indicates that Reset Manager's request to the SDRAM Controller Subsystem to
455	* put the SDRAM devices into self-refresh mode before starting a hardware
456	* sequenced warm reset timed-out and the Reset Manager had to proceed with the
457	* warm reset anyway.
458	*
459	* Field Access Macros:
460	*
461	*/
462	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
463	#define ALT_RSTMGR_STAT_SDRSELFREFTMO_LSB 24
464	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
465	#define ALT_RSTMGR_STAT_SDRSELFREFTMO_MSB 24
466	/* The width in bits of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
467	#define ALT_RSTMGR_STAT_SDRSELFREFTMO_WIDTH 1
468	/* The mask used to set the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */
469	#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET_MSK 0x01000000
470	/* The mask used to clear the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */
471	#define ALT_RSTMGR_STAT_SDRSELFREFTMO_CLR_MSK 0xfeffffff
472	/* The reset value of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
473	#define ALT_RSTMGR_STAT_SDRSELFREFTMO_RESET 0x0
474	/* Extracts the ALT_RSTMGR_STAT_SDRSELFREFTMO field value from a register. */
475	#define ALT_RSTMGR_STAT_SDRSELFREFTMO_GET(value) (((value) & 0x01000000) >> 24)
476	/* Produces a ALT_RSTMGR_STAT_SDRSELFREFTMO register field value suitable for setting the register. */
477	#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET(value) (((value) << 24) & 0x01000000)
478
479	/*
480	* Field : FPGA manager handshake Timeout - fpgamgrhstimeout
481	*
482	* A 1 indicates that Reset Manager's request to the FPGA manager to stop driving
483	* configuration clock to FPGA CB before starting a hardware sequenced warm reset
484	* timed-out and the Reset Manager had to proceed with the warm reset anyway.
485	*
486	* Field Access Macros:
487	*
488	*/
489	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
490	#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_LSB 25
491	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
492	#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_MSB 25
493	/* The width in bits of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
494	#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_WIDTH 1
495	/* The mask used to set the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */
496	#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET_MSK 0x02000000
497	/* The mask used to clear the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */
498	#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_CLR_MSK 0xfdffffff
499	/* The reset value of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
500	#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_RESET 0x0
501	/* Extracts the ALT_RSTMGR_STAT_FPGAMGRHSTMO field value from a register. */
502	#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_GET(value) (((value) & 0x02000000) >> 25)
503	/* Produces a ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value suitable for setting the register. */
504	#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET(value) (((value) << 25) & 0x02000000)
505
506	/*
507	* Field : SCAN manager handshake Timeout - scanhstimeout
508	*
509	* A 1 indicates that Reset Manager's request to the SCAN manager to stop driving
510	* JTAG clock to FPGA CB before starting a hardware sequenced warm reset timed-out
511	* and the Reset Manager had to proceed with the warm reset anyway.
512	*
513	* Field Access Macros:
514	*
515	*/
516	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
517	#define ALT_RSTMGR_STAT_SCANHSTMO_LSB 26
518	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
519	#define ALT_RSTMGR_STAT_SCANHSTMO_MSB 26
520	/* The width in bits of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
521	#define ALT_RSTMGR_STAT_SCANHSTMO_WIDTH 1
522	/* The mask used to set the ALT_RSTMGR_STAT_SCANHSTMO register field value. */
523	#define ALT_RSTMGR_STAT_SCANHSTMO_SET_MSK 0x04000000
524	/* The mask used to clear the ALT_RSTMGR_STAT_SCANHSTMO register field value. */
525	#define ALT_RSTMGR_STAT_SCANHSTMO_CLR_MSK 0xfbffffff
526	/* The reset value of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
527	#define ALT_RSTMGR_STAT_SCANHSTMO_RESET 0x0
528	/* Extracts the ALT_RSTMGR_STAT_SCANHSTMO field value from a register. */
529	#define ALT_RSTMGR_STAT_SCANHSTMO_GET(value) (((value) & 0x04000000) >> 26)
530	/* Produces a ALT_RSTMGR_STAT_SCANHSTMO register field value suitable for setting the register. */
531	#define ALT_RSTMGR_STAT_SCANHSTMO_SET(value) (((value) << 26) & 0x04000000)
532
533	/*
534	* Field : FPGA handshake Timeout - fpgahstimeout
535	*
536	* A 1 indicates that Reset Manager's handshake request to FPGA before starting a
537	* hardware sequenced warm reset timed-out and the Reset Manager had to proceed
538	* with the warm reset anyway.
539	*
540	* Field Access Macros:
541	*
542	*/
543	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
544	#define ALT_RSTMGR_STAT_FPGAHSTMO_LSB 27
545	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
546	#define ALT_RSTMGR_STAT_FPGAHSTMO_MSB 27
547	/* The width in bits of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
548	#define ALT_RSTMGR_STAT_FPGAHSTMO_WIDTH 1
549	/* The mask used to set the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */
550	#define ALT_RSTMGR_STAT_FPGAHSTMO_SET_MSK 0x08000000
551	/* The mask used to clear the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */
552	#define ALT_RSTMGR_STAT_FPGAHSTMO_CLR_MSK 0xf7ffffff
553	/* The reset value of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
554	#define ALT_RSTMGR_STAT_FPGAHSTMO_RESET 0x0
555	/* Extracts the ALT_RSTMGR_STAT_FPGAHSTMO field value from a register. */
556	#define ALT_RSTMGR_STAT_FPGAHSTMO_GET(value) (((value) & 0x08000000) >> 27)
557	/* Produces a ALT_RSTMGR_STAT_FPGAHSTMO register field value suitable for setting the register. */
558	#define ALT_RSTMGR_STAT_FPGAHSTMO_SET(value) (((value) << 27) & 0x08000000)
559
560	/*
561	* Field : ETR Stall Timeout - etrstalltimeout
562	*
563	* A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to
564	* stall its AXI master port before starting a hardware sequenced warm reset timed-
565	* out and the Reset Manager had to proceed with the warm reset anyway.
566	*
567	* Field Access Macros:
568	*
569	*/
570	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
571	#define ALT_RSTMGR_STAT_ETRSTALLTMO_LSB 28
572	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
573	#define ALT_RSTMGR_STAT_ETRSTALLTMO_MSB 28
574	/* The width in bits of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
575	#define ALT_RSTMGR_STAT_ETRSTALLTMO_WIDTH 1
576	/* The mask used to set the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */
577	#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET_MSK 0x10000000
578	/* The mask used to clear the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */
579	#define ALT_RSTMGR_STAT_ETRSTALLTMO_CLR_MSK 0xefffffff
580	/* The reset value of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
581	#define ALT_RSTMGR_STAT_ETRSTALLTMO_RESET 0x0
582	/* Extracts the ALT_RSTMGR_STAT_ETRSTALLTMO field value from a register. */
583	#define ALT_RSTMGR_STAT_ETRSTALLTMO_GET(value) (((value) & 0x10000000) >> 28)
584	/* Produces a ALT_RSTMGR_STAT_ETRSTALLTMO register field value suitable for setting the register. */
585	#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET(value) (((value) << 28) & 0x10000000)
586
587	#ifndef __ASSEMBLY__
588	/*
589	* WARNING: The C register and register group struct declarations are provided for
590	* convenience and illustrative purposes. They should, however, be used with
591	* caution as the C language standard provides no guarantees about the alignment or
592	* atomicity of device memory accesses. The recommended practice for writing
593	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
594	* alt_write_word() functions.
595	*
596	* The struct declaration for register ALT_RSTMGR_STAT.
597	*/
598	struct ALT_RSTMGR_STAT_s
599	{
600	uint32_t porvoltrst : 1; /* Power-On Voltage Detector Cold Reset */
601	uint32_t nporpinrst : 1; /* nPOR Pin Cold Reset */
602	uint32_t fpgacoldrst : 1; /* FPGA Core Cold Reset */
603	uint32_t configiocoldrst : 1; /* CONFIG_IO Cold Reset */
604	uint32_t swcoldrst : 1; /* Software Cold Reset */
605	uint32_t : 3; /* UNDEFINED */
606	uint32_t nrstpinrst : 1; /* nRST Pin Warm Reset */
607	uint32_t fpgawarmrst : 1; /* FPGA Core Warm Reset */
608	uint32_t swwarmrst : 1; /* Software Warm Reset */
609	uint32_t : 1; /* UNDEFINED */
610	uint32_t mpuwd0rst : 1; /* MPU Watchdog 0 Warm Reset */
611	uint32_t mpuwd1rst : 1; /* MPU Watchdog 1 Warm Reset */
612	uint32_t l4wd0rst : 1; /* L4 Watchdog 0 Warm Reset */
613	uint32_t l4wd1rst : 1; /* L4 Watchdog 1 Warm Reset */
614	uint32_t : 2; /* UNDEFINED */
615	uint32_t fpgadbgrst : 1; /* FPGA Core Debug Reset */
616	uint32_t cdbgreqrst : 1; /* DAP Debug Reset */
617	uint32_t : 4; /* UNDEFINED */
618	uint32_t sdrselfreftimeout : 1; /* SDRAM Self-Refresh Timeout */
619	uint32_t fpgamgrhstimeout : 1; /* FPGA manager handshake Timeout */
620	uint32_t scanhstimeout : 1; /* SCAN manager handshake Timeout */
621	uint32_t fpgahstimeout : 1; /* FPGA handshake Timeout */
622	uint32_t etrstalltimeout : 1; /* ETR Stall Timeout */
623	uint32_t : 3; /* UNDEFINED */
624	};
625
626	/* The typedef declaration for register ALT_RSTMGR_STAT. */
627	typedef volatile struct ALT_RSTMGR_STAT_s ALT_RSTMGR_STAT_t;
628	#endif /* __ASSEMBLY__ */
629
630	/* The byte offset of the ALT_RSTMGR_STAT register from the beginning of the component. */
631	#define ALT_RSTMGR_STAT_OFST 0x0
632
633	/*
634	* Register : Control Register - ctrl
635	*
636	* The CTRL register is used by software to control reset behavior.It includes
637	* fields for software to initiate the cold and warm reset, enable hardware
638	* handshake with other modules before warm reset, and perform software handshake.
639	* The software handshake sequence must match the hardware sequence. Software
640	* mustde-assert the handshake request after asserting warm reset and before de-
641	* assert the warm reset.
642	*
643	* Fields are only reset by a cold reset.
644	*
645	* Register Layout
646	*
647	* Bits \| Access \| Reset \| Description
648	* :--------\|:-------\|:--------\|:---------------------------------------------------
649	* [0] \| RW \| 0x0 \| Software Cold Reset Request
650	* [1] \| RW \| 0x0 \| Software Warm Reset Request
651	* [3:2] \| ??? \| 0x0 \| UNDEFINED
652	* [4] \| RW \| 0x0 \| SDRAM Self-Refresh Enable
653	* [5] \| RW \| 0x0 \| SDRAM Self-Refresh Request
654	* [6] \| R \| 0x0 \| SDRAM Self-Refresh Acknowledge
655	* [7] \| ??? \| 0x0 \| UNDEFINED
656	* [8] \| RW \| 0x0 \| FPGA Manager Handshake Enable
657	* [9] \| RW \| 0x0 \| FPGA Manager Handshake Request
658	* [10] \| R \| Unknown \| FPGA Manager Handshake Acknowledge
659	* [11] \| ??? \| 0x0 \| UNDEFINED
660	* [12] \| RW \| 0x0 \| SCAN Manager Handshake Enable
661	* [13] \| RW \| 0x0 \| SCAN Manager Handshake Request
662	* [14] \| R \| Unknown \| SCAN Manager Handshake Acknowledge
663	* [15] \| ??? \| 0x0 \| UNDEFINED
664	* [16] \| RW \| 0x0 \| FPGA Handshake Enable
665	* [17] \| RW \| 0x0 \| FPGA Handshake Request
666	* [18] \| R \| Unknown \| FPGA Handshake Acknowledge
667	* [19] \| ??? \| 0x0 \| UNDEFINED
668	* [20] \| RW \| 0x1 \| ETR (Embedded Trace Router) Stall Enable
669	* [21] \| RW \| 0x0 \| ETR (Embedded Trace Router) Stall Request
670	* [22] \| R \| 0x0 \| ETR (Embedded Trace Router) Stall Acknowledge
671	* [23] \| RW \| 0x0 \| ETR (Embedded Trace Router) Stall After Warm Reset
672	* [31:24] \| ??? \| 0x0 \| UNDEFINED
673	*
674	*/
675	/*
676	* Field : Software Cold Reset Request - swcoldrstreq
677	*
678	* This is a one-shot bit written by software to 1 to trigger a cold reset. It
679	* always reads the value 0.
680	*
681	* Field Access Macros:
682	*
683	*/
684	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
685	#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB 0
686	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
687	#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB 0
688	/* The width in bits of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
689	#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH 1
690	/* The mask used to set the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */
691	#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK 0x00000001
692	/* The mask used to clear the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */
693	#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK 0xfffffffe
694	/* The reset value of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
695	#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET 0x0
696	/* Extracts the ALT_RSTMGR_CTL_SWCOLDRSTREQ field value from a register. */
697	#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value) (((value) & 0x00000001) >> 0)
698	/* Produces a ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value suitable for setting the register. */
699	#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value) (((value) << 0) & 0x00000001)
700
701	/*
702	* Field : Software Warm Reset Request - swwarmrstreq
703	*
704	* This is a one-shot bit written by software to 1 to trigger a hardware sequenced
705	* warm reset. It always reads the value 0.
706	*
707	* Field Access Macros:
708	*
709	*/
710	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
711	#define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB 1
712	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
713	#define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB 1
714	/* The width in bits of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
715	#define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH 1
716	/* The mask used to set the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */
717	#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002
718	/* The mask used to clear the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */
719	#define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK 0xfffffffd
720	/* The reset value of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
721	#define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET 0x0
722	/* Extracts the ALT_RSTMGR_CTL_SWWARMRSTREQ field value from a register. */
723	#define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value) (((value) & 0x00000002) >> 1)
724	/* Produces a ALT_RSTMGR_CTL_SWWARMRSTREQ register field value suitable for setting the register. */
725	#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value) (((value) << 1) & 0x00000002)
726
727	/*
728	* Field : SDRAM Self-Refresh Enable - sdrselfrefen
729	*
730	* This field controls whether the contents of SDRAM devices survive a hardware
731	* sequenced warm reset. If set to 1, the Reset Manager makes a request to the
732	* SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode
733	* before asserting warm reset signals. However, if SDRAM is already in warm reset,
734	* Handshake with SDRAM is not performed.
735	*
736	* Field Access Macros:
737	*
738	*/
739	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
740	#define ALT_RSTMGR_CTL_SDRSELFREFEN_LSB 4
741	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
742	#define ALT_RSTMGR_CTL_SDRSELFREFEN_MSB 4
743	/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
744	#define ALT_RSTMGR_CTL_SDRSELFREFEN_WIDTH 1
745	/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */
746	#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK 0x00000010
747	/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */
748	#define ALT_RSTMGR_CTL_SDRSELFREFEN_CLR_MSK 0xffffffef
749	/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
750	#define ALT_RSTMGR_CTL_SDRSELFREFEN_RESET 0x0
751	/* Extracts the ALT_RSTMGR_CTL_SDRSELFREFEN field value from a register. */
752	#define ALT_RSTMGR_CTL_SDRSELFREFEN_GET(value) (((value) & 0x00000010) >> 4)
753	/* Produces a ALT_RSTMGR_CTL_SDRSELFREFEN register field value suitable for setting the register. */
754	#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET(value) (((value) << 4) & 0x00000010)
755
756	/*
757	* Field : SDRAM Self-Refresh Request - sdrselfrefreq
758	*
759	* Software writes this field 1 to request to the SDRAM Controller Subsystem that
760	* it puts the SDRAM devices into self-refresh mode. This is done to preserve SDRAM
761	* contents across a software warm reset.
762	*
763	* Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0.
764	* Note that it is possible for the SDRAM Controller Subsystem to never assert
765	* SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted.
766	*
767	* Field Access Macros:
768	*
769	*/
770	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
771	#define ALT_RSTMGR_CTL_SDRSELFREFREQ_LSB 5
772	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
773	#define ALT_RSTMGR_CTL_SDRSELFREFREQ_MSB 5
774	/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
775	#define ALT_RSTMGR_CTL_SDRSELFREFREQ_WIDTH 1
776	/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */
777	#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET_MSK 0x00000020
778	/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */
779	#define ALT_RSTMGR_CTL_SDRSELFREFREQ_CLR_MSK 0xffffffdf
780	/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
781	#define ALT_RSTMGR_CTL_SDRSELFREFREQ_RESET 0x0
782	/* Extracts the ALT_RSTMGR_CTL_SDRSELFREFREQ field value from a register. */
783	#define ALT_RSTMGR_CTL_SDRSELFREFREQ_GET(value) (((value) & 0x00000020) >> 5)
784	/* Produces a ALT_RSTMGR_CTL_SDRSELFREFREQ register field value suitable for setting the register. */
785	#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET(value) (((value) << 5) & 0x00000020)
786
787	/*
788	* Field : SDRAM Self-Refresh Acknowledge - sdrselfreqack
789	*
790	* This is the acknowlege for a SDRAM self-refresh mode request initiated by the
791	* SDRSELFREFREQ field. A 1 indicates that the SDRAM Controller Subsystem has put
792	* the SDRAM devices into self-refresh mode.
793	*
794	* Field Access Macros:
795	*
796	*/
797	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
798	#define ALT_RSTMGR_CTL_SDRSELFREQACK_LSB 6
799	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
800	#define ALT_RSTMGR_CTL_SDRSELFREQACK_MSB 6
801	/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
802	#define ALT_RSTMGR_CTL_SDRSELFREQACK_WIDTH 1
803	/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */
804	#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET_MSK 0x00000040
805	/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */
806	#define ALT_RSTMGR_CTL_SDRSELFREQACK_CLR_MSK 0xffffffbf
807	/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
808	#define ALT_RSTMGR_CTL_SDRSELFREQACK_RESET 0x0
809	/* Extracts the ALT_RSTMGR_CTL_SDRSELFREQACK field value from a register. */
810	#define ALT_RSTMGR_CTL_SDRSELFREQACK_GET(value) (((value) & 0x00000040) >> 6)
811	/* Produces a ALT_RSTMGR_CTL_SDRSELFREQACK register field value suitable for setting the register. */
812	#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET(value) (((value) << 6) & 0x00000040)
813
814	/*
815	* Field : FPGA Manager Handshake Enable - fpgamgrhsen
816	*
817	* Enables a handshake between the Reset Manager and FPGA Manager before a warm
818	* reset. The handshake is used to warn the FPGA Manager that a warm reset it
819	* coming so it can prepare for it. When the FPGA Manager receives a warm reset
820	* handshake, the FPGA Manager drives its output clock to a quiescent state to
821	* avoid glitches.
822	*
823	* If set to 1, the Manager makes a request to the FPGA Managerbefore asserting
824	* warm reset signals. However if the FPGA Manager is already in warm reset, the
825	* handshake is skipped.
826	*
827	* If set to 0, the handshake is skipped.
828	*
829	* Field Access Macros:
830	*
831	*/
832	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
833	#define ALT_RSTMGR_CTL_FPGAMGRHSEN_LSB 8
834	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
835	#define ALT_RSTMGR_CTL_FPGAMGRHSEN_MSB 8
836	/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
837	#define ALT_RSTMGR_CTL_FPGAMGRHSEN_WIDTH 1
838	/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */
839	#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK 0x00000100
840	/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */
841	#define ALT_RSTMGR_CTL_FPGAMGRHSEN_CLR_MSK 0xfffffeff
842	/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
843	#define ALT_RSTMGR_CTL_FPGAMGRHSEN_RESET 0x0
844	/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSEN field value from a register. */
845	#define ALT_RSTMGR_CTL_FPGAMGRHSEN_GET(value) (((value) & 0x00000100) >> 8)
846	/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSEN register field value suitable for setting the register. */
847	#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET(value) (((value) << 8) & 0x00000100)
848
849	/*
850	* Field : FPGA Manager Handshake Request - fpgamgrhsreq
851	*
852	* Software writes this field 1 to request to the FPGA Manager to idle its output
853	* clock.
854	*
855	* Software waits for the FPGAMGRHSACK to be 1 and then writes this field to 0.
856	* Note that it is possible for the FPGA Manager to never assert FPGAMGRHSACK so
857	* software should timeout in this case.
858	*
859	* Field Access Macros:
860	*
861	*/
862	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
863	#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_LSB 9
864	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
865	#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_MSB 9
866	/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
867	#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_WIDTH 1
868	/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */
869	#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET_MSK 0x00000200
870	/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */
871	#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_CLR_MSK 0xfffffdff
872	/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
873	#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_RESET 0x0
874	/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSREQ field value from a register. */
875	#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_GET(value) (((value) & 0x00000200) >> 9)
876	/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value suitable for setting the register. */
877	#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET(value) (((value) << 9) & 0x00000200)
878
879	/*
880	* Field : FPGA Manager Handshake Acknowledge - fpgamgrhsack
881	*
882	* This is the acknowlege (high active) that the FPGA manager has successfully
883	* idled its output clock.
884	*
885	* Field Access Macros:
886	*
887	*/
888	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */
889	#define ALT_RSTMGR_CTL_FPGAMGRHSACK_LSB 10
890	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */
891	#define ALT_RSTMGR_CTL_FPGAMGRHSACK_MSB 10
892	/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */
893	#define ALT_RSTMGR_CTL_FPGAMGRHSACK_WIDTH 1
894	/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */
895	#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET_MSK 0x00000400
896	/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */
897	#define ALT_RSTMGR_CTL_FPGAMGRHSACK_CLR_MSK 0xfffffbff
898	/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field is UNKNOWN. */
899	#define ALT_RSTMGR_CTL_FPGAMGRHSACK_RESET 0x0
900	/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSACK field value from a register. */
901	#define ALT_RSTMGR_CTL_FPGAMGRHSACK_GET(value) (((value) & 0x00000400) >> 10)
902	/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSACK register field value suitable for setting the register. */
903	#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET(value) (((value) << 10) & 0x00000400)
904
905	/*
906	* Field : SCAN Manager Handshake Enable - scanmgrhsen
907	*
908	* Enables a handshake between the Reset Manager and Scan Manager before a warm
909	* reset. The handshake is used to warn the Scan Manager that a warm reset it
910	* coming so it can prepare for it. When the Scan Manager receives a warm reset
911	* handshake, the Scan Manager drives its output clocks to a quiescent state to
912	* avoid glitches.
913	*
914	* If set to 1, the Reset Manager makes a request to the Scan Managerbefore
915	* asserting warm reset signals. However if the Scan Manager is already in warm
916	* reset, the handshake is skipped.
917	*
918	* If set to 0, the handshake is skipped.
919	*
920	* Field Access Macros:
921	*
922	*/
923	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
924	#define ALT_RSTMGR_CTL_SCANMGRHSEN_LSB 12
925	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
926	#define ALT_RSTMGR_CTL_SCANMGRHSEN_MSB 12
927	/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
928	#define ALT_RSTMGR_CTL_SCANMGRHSEN_WIDTH 1
929	/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */
930	#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK 0x00001000
931	/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */
932	#define ALT_RSTMGR_CTL_SCANMGRHSEN_CLR_MSK 0xffffefff
933	/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
934	#define ALT_RSTMGR_CTL_SCANMGRHSEN_RESET 0x0
935	/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSEN field value from a register. */
936	#define ALT_RSTMGR_CTL_SCANMGRHSEN_GET(value) (((value) & 0x00001000) >> 12)
937	/* Produces a ALT_RSTMGR_CTL_SCANMGRHSEN register field value suitable for setting the register. */
938	#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET(value) (((value) << 12) & 0x00001000)
939
940	/*
941	* Field : SCAN Manager Handshake Request - scanmgrhsreq
942	*
943	* Software writes this field 1 to request to the SCAN manager to idle its output
944	* clocks.
945	*
946	* Software waits for the SCANMGRHSACK to be 1 and then writes this field to 0.
947	* Note that it is possible for the Scan Manager to never assert SCANMGRHSACK (e.g.
948	* its input clock is disabled) so software should timeout in this case.
949	*
950	* Field Access Macros:
951	*
952	*/
953	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
954	#define ALT_RSTMGR_CTL_SCANMGRHSREQ_LSB 13
955	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
956	#define ALT_RSTMGR_CTL_SCANMGRHSREQ_MSB 13
957	/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
958	#define ALT_RSTMGR_CTL_SCANMGRHSREQ_WIDTH 1
959	/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */
960	#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET_MSK 0x00002000
961	/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */
962	#define ALT_RSTMGR_CTL_SCANMGRHSREQ_CLR_MSK 0xffffdfff
963	/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
964	#define ALT_RSTMGR_CTL_SCANMGRHSREQ_RESET 0x0
965	/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSREQ field value from a register. */
966	#define ALT_RSTMGR_CTL_SCANMGRHSREQ_GET(value) (((value) & 0x00002000) >> 13)
967	/* Produces a ALT_RSTMGR_CTL_SCANMGRHSREQ register field value suitable for setting the register. */
968	#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET(value) (((value) << 13) & 0x00002000)
969
970	/*
971	* Field : SCAN Manager Handshake Acknowledge - scanmgrhsack
972	*
973	* This is the acknowlege (high active) that the SCAN manager has successfully
974	* idled its output clocks.
975	*
976	* Field Access Macros:
977	*
978	*/
979	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */
980	#define ALT_RSTMGR_CTL_SCANMGRHSACK_LSB 14
981	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */
982	#define ALT_RSTMGR_CTL_SCANMGRHSACK_MSB 14
983	/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */
984	#define ALT_RSTMGR_CTL_SCANMGRHSACK_WIDTH 1
985	/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */
986	#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET_MSK 0x00004000
987	/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */
988	#define ALT_RSTMGR_CTL_SCANMGRHSACK_CLR_MSK 0xffffbfff
989	/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSACK register field is UNKNOWN. */
990	#define ALT_RSTMGR_CTL_SCANMGRHSACK_RESET 0x0
991	/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSACK field value from a register. */
992	#define ALT_RSTMGR_CTL_SCANMGRHSACK_GET(value) (((value) & 0x00004000) >> 14)
993	/* Produces a ALT_RSTMGR_CTL_SCANMGRHSACK register field value suitable for setting the register. */
994	#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET(value) (((value) << 14) & 0x00004000)
995
996	/*
997	* Field : FPGA Handshake Enable - fpgahsen
998	*
999	* This field controls whether to perform handshake with FPGA before asserting warm
1000	* reset.
1001	*
1002	* If set to 1, the Reset Manager makes a request to the FPGAbefore asserting warm
1003	* reset signals. However if FPGA is already in warm reset state, the handshake is
1004	* not performed.
1005	*
1006	* If set to 0, the handshake is not performed
1007	*
1008	* Field Access Macros:
1009	*
1010	*/
1011	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
1012	#define ALT_RSTMGR_CTL_FPGAHSEN_LSB 16
1013	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
1014	#define ALT_RSTMGR_CTL_FPGAHSEN_MSB 16
1015	/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
1016	#define ALT_RSTMGR_CTL_FPGAHSEN_WIDTH 1
1017	/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSEN register field value. */
1018	#define ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK 0x00010000
1019	/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSEN register field value. */
1020	#define ALT_RSTMGR_CTL_FPGAHSEN_CLR_MSK 0xfffeffff
1021	/* The reset value of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
1022	#define ALT_RSTMGR_CTL_FPGAHSEN_RESET 0x0
1023	/* Extracts the ALT_RSTMGR_CTL_FPGAHSEN field value from a register. */
1024	#define ALT_RSTMGR_CTL_FPGAHSEN_GET(value) (((value) & 0x00010000) >> 16)
1025	/* Produces a ALT_RSTMGR_CTL_FPGAHSEN register field value suitable for setting the register. */
1026	#define ALT_RSTMGR_CTL_FPGAHSEN_SET(value) (((value) << 16) & 0x00010000)
1027
1028	/*
1029	* Field : FPGA Handshake Request - fpgahsreq
1030	*
1031	* Software writes this field 1 to initiate handshake request to FPGA .
1032	*
1033	* Software waits for the FPGAHSACK to be active and then writes this field to 0.
1034	* Note that it is possible for the FPGA to never assert FPGAHSACK so software
1035	* should timeout in this case.
1036	*
1037	* Field Access Macros:
1038	*
1039	*/
1040	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
1041	#define ALT_RSTMGR_CTL_FPGAHSREQ_LSB 17
1042	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
1043	#define ALT_RSTMGR_CTL_FPGAHSREQ_MSB 17
1044	/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
1045	#define ALT_RSTMGR_CTL_FPGAHSREQ_WIDTH 1
1046	/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */
1047	#define ALT_RSTMGR_CTL_FPGAHSREQ_SET_MSK 0x00020000
1048	/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */
1049	#define ALT_RSTMGR_CTL_FPGAHSREQ_CLR_MSK 0xfffdffff
1050	/* The reset value of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
1051	#define ALT_RSTMGR_CTL_FPGAHSREQ_RESET 0x0
1052	/* Extracts the ALT_RSTMGR_CTL_FPGAHSREQ field value from a register. */
1053	#define ALT_RSTMGR_CTL_FPGAHSREQ_GET(value) (((value) & 0x00020000) >> 17)
1054	/* Produces a ALT_RSTMGR_CTL_FPGAHSREQ register field value suitable for setting the register. */
1055	#define ALT_RSTMGR_CTL_FPGAHSREQ_SET(value) (((value) << 17) & 0x00020000)
1056
1057	/*
1058	* Field : FPGA Handshake Acknowledge - fpgahsack
1059	*
1060	* This is the acknowlege (high active) that the FPGA handshake acknowledge has
1061	* been received by Reset Manager.
1062	*
1063	* Field Access Macros:
1064	*
1065	*/
1066	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */
1067	#define ALT_RSTMGR_CTL_FPGAHSACK_LSB 18
1068	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */
1069	#define ALT_RSTMGR_CTL_FPGAHSACK_MSB 18
1070	/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSACK register field. */
1071	#define ALT_RSTMGR_CTL_FPGAHSACK_WIDTH 1
1072	/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSACK register field value. */
1073	#define ALT_RSTMGR_CTL_FPGAHSACK_SET_MSK 0x00040000
1074	/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSACK register field value. */
1075	#define ALT_RSTMGR_CTL_FPGAHSACK_CLR_MSK 0xfffbffff
1076	/* The reset value of the ALT_RSTMGR_CTL_FPGAHSACK register field is UNKNOWN. */
1077	#define ALT_RSTMGR_CTL_FPGAHSACK_RESET 0x0
1078	/* Extracts the ALT_RSTMGR_CTL_FPGAHSACK field value from a register. */
1079	#define ALT_RSTMGR_CTL_FPGAHSACK_GET(value) (((value) & 0x00040000) >> 18)
1080	/* Produces a ALT_RSTMGR_CTL_FPGAHSACK register field value suitable for setting the register. */
1081	#define ALT_RSTMGR_CTL_FPGAHSACK_SET(value) (((value) << 18) & 0x00040000)
1082
1083	/*
1084	* Field : ETR (Embedded Trace Router) Stall Enable - etrstallen
1085	*
1086	* This field controls whether the ETR is requested to idle its AXI master
1087	* interface (i.e. finish outstanding transactions and not initiate any more) to
1088	* the L3 Interconnect before a warm or debug reset. If set to 1, the Reset Manager
1089	* makes a request to the ETR to stall its AXI master and waits for it to finish
1090	* any outstanding AXI transactions before a warm reset of the L3 Interconnect or a
1091	* debug reset of the ETR. This stalling is required because the debug logic
1092	* (including the ETR) is reset on a debug reset and the ETR AXI master is
1093	* connected to the L3 Interconnect which is reset on a warm reset and these resets
1094	* can happen independently.
1095	*
1096	* Field Access Macros:
1097	*
1098	*/
1099	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
1100	#define ALT_RSTMGR_CTL_ETRSTALLEN_LSB 20
1101	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
1102	#define ALT_RSTMGR_CTL_ETRSTALLEN_MSB 20
1103	/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
1104	#define ALT_RSTMGR_CTL_ETRSTALLEN_WIDTH 1
1105	/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */
1106	#define ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK 0x00100000
1107	/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */
1108	#define ALT_RSTMGR_CTL_ETRSTALLEN_CLR_MSK 0xffefffff
1109	/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
1110	#define ALT_RSTMGR_CTL_ETRSTALLEN_RESET 0x1
1111	/* Extracts the ALT_RSTMGR_CTL_ETRSTALLEN field value from a register. */
1112	#define ALT_RSTMGR_CTL_ETRSTALLEN_GET(value) (((value) & 0x00100000) >> 20)
1113	/* Produces a ALT_RSTMGR_CTL_ETRSTALLEN register field value suitable for setting the register. */
1114	#define ALT_RSTMGR_CTL_ETRSTALLEN_SET(value) (((value) << 20) & 0x00100000)
1115
1116	/*
1117	* Field : ETR (Embedded Trace Router) Stall Request - etrstallreq
1118	*
1119	* Software writes this field 1 to request to the ETR that it stalls its AXI master
1120	* to the L3 Interconnect.
1121	*
1122	* Software waits for the ETRSTALLACK to be 1 and then writes this field to 0.
1123	* Note that it is possible for the ETR to never assert ETRSTALLACK so software
1124	* should timeout if ETRSTALLACK is never asserted.
1125	*
1126	* Field Access Macros:
1127	*
1128	*/
1129	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
1130	#define ALT_RSTMGR_CTL_ETRSTALLREQ_LSB 21
1131	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
1132	#define ALT_RSTMGR_CTL_ETRSTALLREQ_MSB 21
1133	/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
1134	#define ALT_RSTMGR_CTL_ETRSTALLREQ_WIDTH 1
1135	/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */
1136	#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET_MSK 0x00200000
1137	/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */
1138	#define ALT_RSTMGR_CTL_ETRSTALLREQ_CLR_MSK 0xffdfffff
1139	/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
1140	#define ALT_RSTMGR_CTL_ETRSTALLREQ_RESET 0x0
1141	/* Extracts the ALT_RSTMGR_CTL_ETRSTALLREQ field value from a register. */
1142	#define ALT_RSTMGR_CTL_ETRSTALLREQ_GET(value) (((value) & 0x00200000) >> 21)
1143	/* Produces a ALT_RSTMGR_CTL_ETRSTALLREQ register field value suitable for setting the register. */
1144	#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET(value) (((value) << 21) & 0x00200000)
1145
1146	/*
1147	* Field : ETR (Embedded Trace Router) Stall Acknowledge - etrstallack
1148	*
1149	* This is the acknowlege for a ETR AXI master stall initiated by the ETRSTALLREQ
1150	* field. A 1 indicates that the ETR has stalled its AXI master
1151	*
1152	* Field Access Macros:
1153	*
1154	*/
1155	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
1156	#define ALT_RSTMGR_CTL_ETRSTALLACK_LSB 22
1157	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
1158	#define ALT_RSTMGR_CTL_ETRSTALLACK_MSB 22
1159	/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
1160	#define ALT_RSTMGR_CTL_ETRSTALLACK_WIDTH 1
1161	/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */
1162	#define ALT_RSTMGR_CTL_ETRSTALLACK_SET_MSK 0x00400000
1163	/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */
1164	#define ALT_RSTMGR_CTL_ETRSTALLACK_CLR_MSK 0xffbfffff
1165	/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
1166	#define ALT_RSTMGR_CTL_ETRSTALLACK_RESET 0x0
1167	/* Extracts the ALT_RSTMGR_CTL_ETRSTALLACK field value from a register. */
1168	#define ALT_RSTMGR_CTL_ETRSTALLACK_GET(value) (((value) & 0x00400000) >> 22)
1169	/* Produces a ALT_RSTMGR_CTL_ETRSTALLACK register field value suitable for setting the register. */
1170	#define ALT_RSTMGR_CTL_ETRSTALLACK_SET(value) (((value) << 22) & 0x00400000)
1171
1172	/*
1173	* Field : ETR (Embedded Trace Router) Stall After Warm Reset - etrstallwarmrst
1174	*
1175	* If a warm reset occurs and ETRSTALLEN is 1, hardware sets this bit to 1 to
1176	* indicate that the stall of the ETR AXI master is pending. Hardware leaves the
1177	* ETR stalled until software clears this field by writing it with 1. Software must
1178	* only clear this field when it is ready to have the ETR AXI master start making
1179	* AXI requests to write trace data.
1180	*
1181	* Field Access Macros:
1182	*
1183	*/
1184	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
1185	#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_LSB 23
1186	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
1187	#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_MSB 23
1188	/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
1189	#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_WIDTH 1
1190	/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */
1191	#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET_MSK 0x00800000
1192	/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */
1193	#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_CLR_MSK 0xff7fffff
1194	/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
1195	#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_RESET 0x0
1196	/* Extracts the ALT_RSTMGR_CTL_ETRSTALLWARMRST field value from a register. */
1197	#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_GET(value) (((value) & 0x00800000) >> 23)
1198	/* Produces a ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value suitable for setting the register. */
1199	#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET(value) (((value) << 23) & 0x00800000)
1200
1201	#ifndef __ASSEMBLY__
1202	/*
1203	* WARNING: The C register and register group struct declarations are provided for
1204	* convenience and illustrative purposes. They should, however, be used with
1205	* caution as the C language standard provides no guarantees about the alignment or
1206	* atomicity of device memory accesses. The recommended practice for writing
1207	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1208	* alt_write_word() functions.
1209	*
1210	* The struct declaration for register ALT_RSTMGR_CTL.
1211	*/
1212	struct ALT_RSTMGR_CTL_s
1213	{
1214	uint32_t swcoldrstreq : 1; /* Software Cold Reset Request */
1215	uint32_t swwarmrstreq : 1; /* Software Warm Reset Request */
1216	uint32_t : 2; /* UNDEFINED */
1217	uint32_t sdrselfrefen : 1; /* SDRAM Self-Refresh Enable */
1218	uint32_t sdrselfrefreq : 1; /* SDRAM Self-Refresh Request */
1219	const uint32_t sdrselfreqack : 1; /* SDRAM Self-Refresh Acknowledge */
1220	uint32_t : 1; /* UNDEFINED */
1221	uint32_t fpgamgrhsen : 1; /* FPGA Manager Handshake Enable */
1222	uint32_t fpgamgrhsreq : 1; /* FPGA Manager Handshake Request */
1223	const uint32_t fpgamgrhsack : 1; /* FPGA Manager Handshake Acknowledge */
1224	uint32_t : 1; /* UNDEFINED */
1225	uint32_t scanmgrhsen : 1; /* SCAN Manager Handshake Enable */
1226	uint32_t scanmgrhsreq : 1; /* SCAN Manager Handshake Request */
1227	const uint32_t scanmgrhsack : 1; /* SCAN Manager Handshake Acknowledge */
1228	uint32_t : 1; /* UNDEFINED */
1229	uint32_t fpgahsen : 1; /* FPGA Handshake Enable */
1230	uint32_t fpgahsreq : 1; /* FPGA Handshake Request */
1231	const uint32_t fpgahsack : 1; /* FPGA Handshake Acknowledge */
1232	uint32_t : 1; /* UNDEFINED */
1233	uint32_t etrstallen : 1; /* ETR (Embedded Trace Router) Stall Enable */
1234	uint32_t etrstallreq : 1; /* ETR (Embedded Trace Router) Stall Request */
1235	const uint32_t etrstallack : 1; /* ETR (Embedded Trace Router) Stall Acknowledge */
1236	uint32_t etrstallwarmrst : 1; /* ETR (Embedded Trace Router) Stall After Warm Reset */
1237	uint32_t : 8; /* UNDEFINED */
1238	};
1239
1240	/* The typedef declaration for register ALT_RSTMGR_CTL. */
1241	typedef volatile struct ALT_RSTMGR_CTL_s ALT_RSTMGR_CTL_t;
1242	#endif /* __ASSEMBLY__ */
1243
1244	/* The byte offset of the ALT_RSTMGR_CTL register from the beginning of the component. */
1245	#define ALT_RSTMGR_CTL_OFST 0x4
1246
1247	/*
1248	* Register : Reset Cycles Count Register - counts
1249	*
1250	* The COUNTS register is used by software to control reset behavior.It includes
1251	* fields for software to control the behavior of the warm reset and nRST pin.
1252	*
1253	* Fields are only reset by a cold reset.
1254	*
1255	* Register Layout
1256	*
1257	* Bits \| Access \| Reset \| Description
1258	* :--------\|:-------\|:------\|:-------------------------------
1259	* [7:0] \| RW \| 0x80 \| Warm reset release delay count
1260	* [27:8] \| RW \| 0x800 \| nRST Pin Count
1261	* [31:28] \| ??? \| 0x0 \| UNDEFINED
1262	*
1263	*/
1264	/*
1265	* Field : Warm reset release delay count - warmrstcycles
1266	*
1267	* On a warm reset, the Reset Manager releases the reset to the Clock Manager, and
1268	* then waits for the number of cycles specified in this register before releasing
1269	* the rest of the hardware controlled resets. Value must be greater than 16.
1270	*
1271	* Field Access Macros:
1272	*
1273	*/
1274	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1275	#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 0
1276	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1277	#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 7
1278	/* The width in bits of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1279	#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8
1280	/* The mask used to set the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */
1281	#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0x000000ff
1282	/* The mask used to clear the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */
1283	#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0xffffff00
1284	/* The reset value of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1285	#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80
1286	/* Extracts the ALT_RSTMGR_COUNTS_WARMRSTCYCLES field value from a register. */
1287	#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0x000000ff) >> 0)
1288	/* Produces a ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value suitable for setting the register. */
1289	#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 0) & 0x000000ff)
1290
1291	/*
1292	* Field : nRST Pin Count - nrstcnt
1293	*
1294	* The Reset Manager pulls down the nRST pin on a warm reset for the number of
1295	* cycles specified in this register. A value of 0x0 prevents the Reset Manager
1296	* from pulling down the nRST pin.
1297	*
1298	* Field Access Macros:
1299	*
1300	*/
1301	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1302	#define ALT_RSTMGR_COUNTS_NRSTCNT_LSB 8
1303	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1304	#define ALT_RSTMGR_COUNTS_NRSTCNT_MSB 27
1305	/* The width in bits of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1306	#define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20
1307	/* The mask used to set the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */
1308	#define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x0fffff00
1309	/* The mask used to clear the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */
1310	#define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xf00000ff
1311	/* The reset value of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1312	#define ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800
1313	/* Extracts the ALT_RSTMGR_COUNTS_NRSTCNT field value from a register. */
1314	#define ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x0fffff00) >> 8)
1315	/* Produces a ALT_RSTMGR_COUNTS_NRSTCNT register field value suitable for setting the register. */
1316	#define ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 8) & 0x0fffff00)
1317
1318	#ifndef __ASSEMBLY__
1319	/*
1320	* WARNING: The C register and register group struct declarations are provided for
1321	* convenience and illustrative purposes. They should, however, be used with
1322	* caution as the C language standard provides no guarantees about the alignment or
1323	* atomicity of device memory accesses. The recommended practice for writing
1324	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1325	* alt_write_word() functions.
1326	*
1327	* The struct declaration for register ALT_RSTMGR_COUNTS.
1328	*/
1329	struct ALT_RSTMGR_COUNTS_s
1330	{
1331	uint32_t warmrstcycles : 8; /* Warm reset release delay count */
1332	uint32_t nrstcnt : 20; /* nRST Pin Count */
1333	uint32_t : 4; /* UNDEFINED */
1334	};
1335
1336	/* The typedef declaration for register ALT_RSTMGR_COUNTS. */
1337	typedef volatile struct ALT_RSTMGR_COUNTS_s ALT_RSTMGR_COUNTS_t;
1338	#endif /* __ASSEMBLY__ */
1339
1340	/* The byte offset of the ALT_RSTMGR_COUNTS register from the beginning of the component. */
1341	#define ALT_RSTMGR_COUNTS_OFST 0x8
1342
1343	/*
1344	* Register : MPU Module Reset Register - mpumodrst
1345	*
1346	* The MPUMODRST register is used by software to trigger module resets (individual
1347	* module reset signals). Software explicitly asserts and de-asserts module reset
1348	* signals by writing bits in the appropriate *MODRST register. It is up to
1349	* software to ensure module reset signals are asserted for the appropriate length
1350	* of time and are de-asserted in the correct order. It is also up to software to
1351	* not assert a module reset signal that would prevent software from de-asserting
1352	* the module reset signal. For example, software should not assert the module
1353	* reset to the CPU executing the software.
1354	*
1355	* Software writes a bit to 1 to assert the module reset signal and to 0 to de-
1356	* assert the module reset signal.
1357	*
1358	* All fields except CPU1 are only reset by a cold reset. The CPU1 field is reset
1359	* by a cold reset. The CPU1 field is also reset by a warm reset if not masked by
1360	* the corresponding MPUWARMMASK field.
1361	*
1362	* Register Layout
1363	*
1364	* Bits \| Access \| Reset \| Description
1365	* :-------\|:-------\|:------\|:----------------
1366	* [0] \| RW \| 0x0 \| CPU0
1367	* [1] \| RW \| 0x1 \| CPU1
1368	* [2] \| RW \| 0x0 \| Watchdogs
1369	* [3] \| RW \| 0x0 \| SCU/Peripherals
1370	* [4] \| RW \| 0x0 \| L2
1371	* [31:5] \| ??? \| 0x0 \| UNDEFINED
1372	*
1373	*/
1374	/*
1375	* Field : CPU0 - cpu0
1376	*
1377	* Resets Cortex-A9 CPU0 in MPU. Whe software changes this field from 0 to 1,
1378	* ittriggers the following sequence: 1. CPU0 reset is asserted. cpu0 clkoff is
1379	* de-asserted 2. after 32 osc1_clk cycles, cpu0 clkoff is asserted.
1380	*
1381	* When software changes this field from 1 to 0, it triggers the following
1382	* sequence: 1.CPU0 reset is de-asserted. 2. after 32 cycles, cpu0 clkoff is de-
1383	* asserted.
1384	*
1385	* Software needs to wait for at least 64 osc1_clk cycles between each change of
1386	* this field to keep the proper reset/clkoff sequence.
1387	*
1388	* Field Access Macros:
1389	*
1390	*/
1391	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1392	#define ALT_RSTMGR_MPUMODRST_CPU0_LSB 0
1393	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1394	#define ALT_RSTMGR_MPUMODRST_CPU0_MSB 0
1395	/* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1396	#define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH 1
1397	/* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */
1398	#define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK 0x00000001
1399	/* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */
1400	#define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK 0xfffffffe
1401	/* The reset value of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1402	#define ALT_RSTMGR_MPUMODRST_CPU0_RESET 0x0
1403	/* Extracts the ALT_RSTMGR_MPUMODRST_CPU0 field value from a register. */
1404	#define ALT_RSTMGR_MPUMODRST_CPU0_GET(value) (((value) & 0x00000001) >> 0)
1405	/* Produces a ALT_RSTMGR_MPUMODRST_CPU0 register field value suitable for setting the register. */
1406	#define ALT_RSTMGR_MPUMODRST_CPU0_SET(value) (((value) << 0) & 0x00000001)
1407
1408	/*
1409	* Field : CPU1 - cpu1
1410	*
1411	* Resets Cortex-A9 CPU1 in MPU.
1412	*
1413	* It is reset to 1 on a cold or warm reset. This holds CPU1 in reset until
1414	* software is ready to release CPU1 from reset by writing 0 to this field.
1415	*
1416	* On single-core devices, writes to this field are ignored.On dual-core devices,
1417	* writes to this field trigger the same sequence as writes to the CPU0 field
1418	* (except the sequence is performed on CPU1).
1419	*
1420	* Field Access Macros:
1421	*
1422	*/
1423	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
1424	#define ALT_RSTMGR_MPUMODRST_CPU1_LSB 1
1425	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
1426	#define ALT_RSTMGR_MPUMODRST_CPU1_MSB 1
1427	/* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
1428	#define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH 1
1429	/* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */
1430	#define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK 0x00000002
1431	/* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */
1432	#define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK 0xfffffffd
1433	/* The reset value of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
1434	#define ALT_RSTMGR_MPUMODRST_CPU1_RESET 0x1
1435	/* Extracts the ALT_RSTMGR_MPUMODRST_CPU1 field value from a register. */
1436	#define ALT_RSTMGR_MPUMODRST_CPU1_GET(value) (((value) & 0x00000002) >> 1)
1437	/* Produces a ALT_RSTMGR_MPUMODRST_CPU1 register field value suitable for setting the register. */
1438	#define ALT_RSTMGR_MPUMODRST_CPU1_SET(value) (((value) << 1) & 0x00000002)
1439
1440	/*
1441	* Field : Watchdogs - wds
1442	*
1443	* Resets both per-CPU Watchdog Reset Status registers in MPU.
1444	*
1445	* Field Access Macros:
1446	*
1447	*/
1448	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */
1449	#define ALT_RSTMGR_MPUMODRST_WDS_LSB 2
1450	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */
1451	#define ALT_RSTMGR_MPUMODRST_WDS_MSB 2
1452	/* The width in bits of the ALT_RSTMGR_MPUMODRST_WDS register field. */
1453	#define ALT_RSTMGR_MPUMODRST_WDS_WIDTH 1
1454	/* The mask used to set the ALT_RSTMGR_MPUMODRST_WDS register field value. */
1455	#define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK 0x00000004
1456	/* The mask used to clear the ALT_RSTMGR_MPUMODRST_WDS register field value. */
1457	#define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK 0xfffffffb
1458	/* The reset value of the ALT_RSTMGR_MPUMODRST_WDS register field. */
1459	#define ALT_RSTMGR_MPUMODRST_WDS_RESET 0x0
1460	/* Extracts the ALT_RSTMGR_MPUMODRST_WDS field value from a register. */
1461	#define ALT_RSTMGR_MPUMODRST_WDS_GET(value) (((value) & 0x00000004) >> 2)
1462	/* Produces a ALT_RSTMGR_MPUMODRST_WDS register field value suitable for setting the register. */
1463	#define ALT_RSTMGR_MPUMODRST_WDS_SET(value) (((value) << 2) & 0x00000004)
1464
1465	/*
1466	* Field : SCU/Peripherals - scuper
1467	*
1468	* Resets SCU and peripherals. Peripherals consist of the interrupt controller,
1469	* global timer, both per-CPU private timers, and both per-CPU watchdogs (except
1470	* for the Watchdog Reset Status registers).
1471	*
1472	* Field Access Macros:
1473	*
1474	*/
1475	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
1476	#define ALT_RSTMGR_MPUMODRST_SCUPER_LSB 3
1477	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
1478	#define ALT_RSTMGR_MPUMODRST_SCUPER_MSB 3
1479	/* The width in bits of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
1480	#define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH 1
1481	/* The mask used to set the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */
1482	#define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK 0x00000008
1483	/* The mask used to clear the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */
1484	#define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK 0xfffffff7
1485	/* The reset value of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
1486	#define ALT_RSTMGR_MPUMODRST_SCUPER_RESET 0x0
1487	/* Extracts the ALT_RSTMGR_MPUMODRST_SCUPER field value from a register. */
1488	#define ALT_RSTMGR_MPUMODRST_SCUPER_GET(value) (((value) & 0x00000008) >> 3)
1489	/* Produces a ALT_RSTMGR_MPUMODRST_SCUPER register field value suitable for setting the register. */
1490	#define ALT_RSTMGR_MPUMODRST_SCUPER_SET(value) (((value) << 3) & 0x00000008)
1491
1492	/*
1493	* Field : L2 - l2
1494	*
1495	* Resets L2 cache controller
1496	*
1497	* Field Access Macros:
1498	*
1499	*/
1500	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */
1501	#define ALT_RSTMGR_MPUMODRST_L2_LSB 4
1502	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */
1503	#define ALT_RSTMGR_MPUMODRST_L2_MSB 4
1504	/* The width in bits of the ALT_RSTMGR_MPUMODRST_L2 register field. */
1505	#define ALT_RSTMGR_MPUMODRST_L2_WIDTH 1
1506	/* The mask used to set the ALT_RSTMGR_MPUMODRST_L2 register field value. */
1507	#define ALT_RSTMGR_MPUMODRST_L2_SET_MSK 0x00000010
1508	/* The mask used to clear the ALT_RSTMGR_MPUMODRST_L2 register field value. */
1509	#define ALT_RSTMGR_MPUMODRST_L2_CLR_MSK 0xffffffef
1510	/* The reset value of the ALT_RSTMGR_MPUMODRST_L2 register field. */
1511	#define ALT_RSTMGR_MPUMODRST_L2_RESET 0x0
1512	/* Extracts the ALT_RSTMGR_MPUMODRST_L2 field value from a register. */
1513	#define ALT_RSTMGR_MPUMODRST_L2_GET(value) (((value) & 0x00000010) >> 4)
1514	/* Produces a ALT_RSTMGR_MPUMODRST_L2 register field value suitable for setting the register. */
1515	#define ALT_RSTMGR_MPUMODRST_L2_SET(value) (((value) << 4) & 0x00000010)
1516
1517	#ifndef __ASSEMBLY__
1518	/*
1519	* WARNING: The C register and register group struct declarations are provided for
1520	* convenience and illustrative purposes. They should, however, be used with
1521	* caution as the C language standard provides no guarantees about the alignment or
1522	* atomicity of device memory accesses. The recommended practice for writing
1523	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1524	* alt_write_word() functions.
1525	*
1526	* The struct declaration for register ALT_RSTMGR_MPUMODRST.
1527	*/
1528	struct ALT_RSTMGR_MPUMODRST_s
1529	{
1530	uint32_t cpu0 : 1; /* CPU0 */
1531	uint32_t cpu1 : 1; /* CPU1 */
1532	uint32_t wds : 1; /* Watchdogs */
1533	uint32_t scuper : 1; /* SCU/Peripherals */
1534	uint32_t l2 : 1; /* L2 */
1535	uint32_t : 27; /* UNDEFINED */
1536	};
1537
1538	/* The typedef declaration for register ALT_RSTMGR_MPUMODRST. */
1539	typedef volatile struct ALT_RSTMGR_MPUMODRST_s ALT_RSTMGR_MPUMODRST_t;
1540	#endif /* __ASSEMBLY__ */
1541
1542	/* The byte offset of the ALT_RSTMGR_MPUMODRST register from the beginning of the component. */
1543	#define ALT_RSTMGR_MPUMODRST_OFST 0x10
1544
1545	/*
1546	* Register : Peripheral Module Reset Register - permodrst
1547	*
1548	* The PERMODRST register is used by software to trigger module resets (individual
1549	* module reset signals). Software explicitly asserts and de-asserts module reset
1550	* signals by writing bits in the appropriate *MODRST register. It is up to
1551	* software to ensure module reset signals are asserted for the appropriate length
1552	* of time and are de-asserted in the correct order. It is also up to software to
1553	* not assert a module reset signal that would prevent software from de-asserting
1554	* the module reset signal. For example, software should not assert the module
1555	* reset to the CPU executing the software.
1556	*
1557	* Software writes a bit to 1 to assert the module reset signal and to 0 to de-
1558	* assert the module reset signal.
1559	*
1560	* All fields are reset by a cold reset.All fields are also reset by a warm reset
1561	* if not masked by the corresponding PERWARMMASK field.
1562	*
1563	* The reset value of all fields is 1. This holds the corresponding module in reset
1564	* until software is ready to release the module from reset by writing 0 to its
1565	* field.
1566	*
1567	* Register Layout
1568	*
1569	* Bits \| Access \| Reset \| Description
1570	* :--------\|:-------\|:------\|:---------------------------
1571	* [0] \| RW \| 0x1 \| EMAC0
1572	* [1] \| RW \| 0x1 \| EMAC1
1573	* [2] \| RW \| 0x1 \| USB0
1574	* [3] \| RW \| 0x1 \| USB1
1575	* [4] \| RW \| 0x1 \| NAND Flash
1576	* [5] \| RW \| 0x1 \| QSPI Flash
1577	* [6] \| RW \| 0x1 \| L4 Watchdog 0
1578	* [7] \| RW \| 0x1 \| L4 Watchdog 1
1579	* [8] \| RW \| 0x1 \| OSC1 Timer 0
1580	* [9] \| RW \| 0x1 \| OSC1 Timer 1
1581	* [10] \| RW \| 0x1 \| SP Timer 0
1582	* [11] \| RW \| 0x1 \| SP Timer 1
1583	* [12] \| RW \| 0x1 \| I2C0
1584	* [13] \| RW \| 0x1 \| I2C1
1585	* [14] \| RW \| 0x1 \| I2C2
1586	* [15] \| RW \| 0x1 \| I2C3
1587	* [16] \| RW \| 0x1 \| UART0
1588	* [17] \| RW \| 0x1 \| UART1
1589	* [18] \| RW \| 0x1 \| SPIM0
1590	* [19] \| RW \| 0x1 \| SPIM1
1591	* [20] \| RW \| 0x1 \| SPIS0
1592	* [21] \| RW \| 0x1 \| SPIS1
1593	* [22] \| RW \| 0x1 \| SD/MMC
1594	* [23] \| RW \| 0x1 \| CAN0
1595	* [24] \| RW \| 0x1 \| CAN1
1596	* [25] \| RW \| 0x1 \| GPIO0
1597	* [26] \| RW \| 0x1 \| GPIO1
1598	* [27] \| RW \| 0x1 \| GPIO2
1599	* [28] \| RW \| 0x1 \| DMA Controller
1600	* [29] \| RW \| 0x1 \| SDRAM Controller Subsystem
1601	* [31:30] \| ??? \| 0x0 \| UNDEFINED
1602	*
1603	*/
1604	/*
1605	* Field : EMAC0 - emac0
1606	*
1607	* Resets EMAC0
1608	*
1609	* Field Access Macros:
1610	*
1611	*/
1612	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
1613	#define ALT_RSTMGR_PERMODRST_EMAC0_LSB 0
1614	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
1615	#define ALT_RSTMGR_PERMODRST_EMAC0_MSB 0
1616	/* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
1617	#define ALT_RSTMGR_PERMODRST_EMAC0_WIDTH 1
1618	/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */
1619	#define ALT_RSTMGR_PERMODRST_EMAC0_SET_MSK 0x00000001
1620	/* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */
1621	#define ALT_RSTMGR_PERMODRST_EMAC0_CLR_MSK 0xfffffffe
1622	/* The reset value of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
1623	#define ALT_RSTMGR_PERMODRST_EMAC0_RESET 0x1
1624	/* Extracts the ALT_RSTMGR_PERMODRST_EMAC0 field value from a register. */
1625	#define ALT_RSTMGR_PERMODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
1626	/* Produces a ALT_RSTMGR_PERMODRST_EMAC0 register field value suitable for setting the register. */
1627	#define ALT_RSTMGR_PERMODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001)
1628
1629	/*
1630	* Field : EMAC1 - emac1
1631	*
1632	* Resets EMAC1
1633	*
1634	* Field Access Macros:
1635	*
1636	*/
1637	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
1638	#define ALT_RSTMGR_PERMODRST_EMAC1_LSB 1
1639	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
1640	#define ALT_RSTMGR_PERMODRST_EMAC1_MSB 1
1641	/* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
1642	#define ALT_RSTMGR_PERMODRST_EMAC1_WIDTH 1
1643	/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */
1644	#define ALT_RSTMGR_PERMODRST_EMAC1_SET_MSK 0x00000002
1645	/* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */
1646	#define ALT_RSTMGR_PERMODRST_EMAC1_CLR_MSK 0xfffffffd
1647	/* The reset value of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
1648	#define ALT_RSTMGR_PERMODRST_EMAC1_RESET 0x1
1649	/* Extracts the ALT_RSTMGR_PERMODRST_EMAC1 field value from a register. */
1650	#define ALT_RSTMGR_PERMODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
1651	/* Produces a ALT_RSTMGR_PERMODRST_EMAC1 register field value suitable for setting the register. */
1652	#define ALT_RSTMGR_PERMODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002)
1653
1654	/*
1655	* Field : USB0 - usb0
1656	*
1657	* Resets USB0
1658	*
1659	* Field Access Macros:
1660	*
1661	*/
1662	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */
1663	#define ALT_RSTMGR_PERMODRST_USB0_LSB 2
1664	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */
1665	#define ALT_RSTMGR_PERMODRST_USB0_MSB 2
1666	/* The width in bits of the ALT_RSTMGR_PERMODRST_USB0 register field. */
1667	#define ALT_RSTMGR_PERMODRST_USB0_WIDTH 1
1668	/* The mask used to set the ALT_RSTMGR_PERMODRST_USB0 register field value. */
1669	#define ALT_RSTMGR_PERMODRST_USB0_SET_MSK 0x00000004
1670	/* The mask used to clear the ALT_RSTMGR_PERMODRST_USB0 register field value. */
1671	#define ALT_RSTMGR_PERMODRST_USB0_CLR_MSK 0xfffffffb
1672	/* The reset value of the ALT_RSTMGR_PERMODRST_USB0 register field. */
1673	#define ALT_RSTMGR_PERMODRST_USB0_RESET 0x1
1674	/* Extracts the ALT_RSTMGR_PERMODRST_USB0 field value from a register. */
1675	#define ALT_RSTMGR_PERMODRST_USB0_GET(value) (((value) & 0x00000004) >> 2)
1676	/* Produces a ALT_RSTMGR_PERMODRST_USB0 register field value suitable for setting the register. */
1677	#define ALT_RSTMGR_PERMODRST_USB0_SET(value) (((value) << 2) & 0x00000004)
1678
1679	/*
1680	* Field : USB1 - usb1
1681	*
1682	* Resets USB1
1683	*
1684	* Field Access Macros:
1685	*
1686	*/
1687	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */
1688	#define ALT_RSTMGR_PERMODRST_USB1_LSB 3
1689	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */
1690	#define ALT_RSTMGR_PERMODRST_USB1_MSB 3
1691	/* The width in bits of the ALT_RSTMGR_PERMODRST_USB1 register field. */
1692	#define ALT_RSTMGR_PERMODRST_USB1_WIDTH 1
1693	/* The mask used to set the ALT_RSTMGR_PERMODRST_USB1 register field value. */
1694	#define ALT_RSTMGR_PERMODRST_USB1_SET_MSK 0x00000008
1695	/* The mask used to clear the ALT_RSTMGR_PERMODRST_USB1 register field value. */
1696	#define ALT_RSTMGR_PERMODRST_USB1_CLR_MSK 0xfffffff7
1697	/* The reset value of the ALT_RSTMGR_PERMODRST_USB1 register field. */
1698	#define ALT_RSTMGR_PERMODRST_USB1_RESET 0x1
1699	/* Extracts the ALT_RSTMGR_PERMODRST_USB1 field value from a register. */
1700	#define ALT_RSTMGR_PERMODRST_USB1_GET(value) (((value) & 0x00000008) >> 3)
1701	/* Produces a ALT_RSTMGR_PERMODRST_USB1 register field value suitable for setting the register. */
1702	#define ALT_RSTMGR_PERMODRST_USB1_SET(value) (((value) << 3) & 0x00000008)
1703
1704	/*
1705	* Field : NAND Flash - nand
1706	*
1707	* Resets NAND flash controller
1708	*
1709	* Field Access Macros:
1710	*
1711	*/
1712	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */
1713	#define ALT_RSTMGR_PERMODRST_NAND_LSB 4
1714	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */
1715	#define ALT_RSTMGR_PERMODRST_NAND_MSB 4
1716	/* The width in bits of the ALT_RSTMGR_PERMODRST_NAND register field. */
1717	#define ALT_RSTMGR_PERMODRST_NAND_WIDTH 1
1718	/* The mask used to set the ALT_RSTMGR_PERMODRST_NAND register field value. */
1719	#define ALT_RSTMGR_PERMODRST_NAND_SET_MSK 0x00000010
1720	/* The mask used to clear the ALT_RSTMGR_PERMODRST_NAND register field value. */
1721	#define ALT_RSTMGR_PERMODRST_NAND_CLR_MSK 0xffffffef
1722	/* The reset value of the ALT_RSTMGR_PERMODRST_NAND register field. */
1723	#define ALT_RSTMGR_PERMODRST_NAND_RESET 0x1
1724	/* Extracts the ALT_RSTMGR_PERMODRST_NAND field value from a register. */
1725	#define ALT_RSTMGR_PERMODRST_NAND_GET(value) (((value) & 0x00000010) >> 4)
1726	/* Produces a ALT_RSTMGR_PERMODRST_NAND register field value suitable for setting the register. */
1727	#define ALT_RSTMGR_PERMODRST_NAND_SET(value) (((value) << 4) & 0x00000010)
1728
1729	/*
1730	* Field : QSPI Flash - qspi
1731	*
1732	* Resets QSPI flash controller
1733	*
1734	* Field Access Macros:
1735	*
1736	*/
1737	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */
1738	#define ALT_RSTMGR_PERMODRST_QSPI_LSB 5
1739	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */
1740	#define ALT_RSTMGR_PERMODRST_QSPI_MSB 5
1741	/* The width in bits of the ALT_RSTMGR_PERMODRST_QSPI register field. */
1742	#define ALT_RSTMGR_PERMODRST_QSPI_WIDTH 1
1743	/* The mask used to set the ALT_RSTMGR_PERMODRST_QSPI register field value. */
1744	#define ALT_RSTMGR_PERMODRST_QSPI_SET_MSK 0x00000020
1745	/* The mask used to clear the ALT_RSTMGR_PERMODRST_QSPI register field value. */
1746	#define ALT_RSTMGR_PERMODRST_QSPI_CLR_MSK 0xffffffdf
1747	/* The reset value of the ALT_RSTMGR_PERMODRST_QSPI register field. */
1748	#define ALT_RSTMGR_PERMODRST_QSPI_RESET 0x1
1749	/* Extracts the ALT_RSTMGR_PERMODRST_QSPI field value from a register. */
1750	#define ALT_RSTMGR_PERMODRST_QSPI_GET(value) (((value) & 0x00000020) >> 5)
1751	/* Produces a ALT_RSTMGR_PERMODRST_QSPI register field value suitable for setting the register. */
1752	#define ALT_RSTMGR_PERMODRST_QSPI_SET(value) (((value) << 5) & 0x00000020)
1753
1754	/*
1755	* Field : L4 Watchdog 0 - l4wd0
1756	*
1757	* Resets watchdog 0 connected to L4
1758	*
1759	* Field Access Macros:
1760	*
1761	*/
1762	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
1763	#define ALT_RSTMGR_PERMODRST_L4WD0_LSB 6
1764	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
1765	#define ALT_RSTMGR_PERMODRST_L4WD0_MSB 6
1766	/* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
1767	#define ALT_RSTMGR_PERMODRST_L4WD0_WIDTH 1
1768	/* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */
1769	#define ALT_RSTMGR_PERMODRST_L4WD0_SET_MSK 0x00000040
1770	/* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */
1771	#define ALT_RSTMGR_PERMODRST_L4WD0_CLR_MSK 0xffffffbf
1772	/* The reset value of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
1773	#define ALT_RSTMGR_PERMODRST_L4WD0_RESET 0x1
1774	/* Extracts the ALT_RSTMGR_PERMODRST_L4WD0 field value from a register. */
1775	#define ALT_RSTMGR_PERMODRST_L4WD0_GET(value) (((value) & 0x00000040) >> 6)
1776	/* Produces a ALT_RSTMGR_PERMODRST_L4WD0 register field value suitable for setting the register. */
1777	#define ALT_RSTMGR_PERMODRST_L4WD0_SET(value) (((value) << 6) & 0x00000040)
1778
1779	/*
1780	* Field : L4 Watchdog 1 - l4wd1
1781	*
1782	* Resets watchdog 1 connected to L4
1783	*
1784	* Field Access Macros:
1785	*
1786	*/
1787	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
1788	#define ALT_RSTMGR_PERMODRST_L4WD1_LSB 7
1789	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
1790	#define ALT_RSTMGR_PERMODRST_L4WD1_MSB 7
1791	/* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
1792	#define ALT_RSTMGR_PERMODRST_L4WD1_WIDTH 1
1793	/* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */
1794	#define ALT_RSTMGR_PERMODRST_L4WD1_SET_MSK 0x00000080
1795	/* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */
1796	#define ALT_RSTMGR_PERMODRST_L4WD1_CLR_MSK 0xffffff7f
1797	/* The reset value of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
1798	#define ALT_RSTMGR_PERMODRST_L4WD1_RESET 0x1
1799	/* Extracts the ALT_RSTMGR_PERMODRST_L4WD1 field value from a register. */
1800	#define ALT_RSTMGR_PERMODRST_L4WD1_GET(value) (((value) & 0x00000080) >> 7)
1801	/* Produces a ALT_RSTMGR_PERMODRST_L4WD1 register field value suitable for setting the register. */
1802	#define ALT_RSTMGR_PERMODRST_L4WD1_SET(value) (((value) << 7) & 0x00000080)
1803
1804	/*
1805	* Field : OSC1 Timer 0 - osc1timer0
1806	*
1807	* Resets OSC1 timer 0 connected to L4
1808	*
1809	* Field Access Macros:
1810	*
1811	*/
1812	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
1813	#define ALT_RSTMGR_PERMODRST_OSC1TMR0_LSB 8
1814	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
1815	#define ALT_RSTMGR_PERMODRST_OSC1TMR0_MSB 8
1816	/* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
1817	#define ALT_RSTMGR_PERMODRST_OSC1TMR0_WIDTH 1
1818	/* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */
1819	#define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET_MSK 0x00000100
1820	/* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */
1821	#define ALT_RSTMGR_PERMODRST_OSC1TMR0_CLR_MSK 0xfffffeff
1822	/* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
1823	#define ALT_RSTMGR_PERMODRST_OSC1TMR0_RESET 0x1
1824	/* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR0 field value from a register. */
1825	#define ALT_RSTMGR_PERMODRST_OSC1TMR0_GET(value) (((value) & 0x00000100) >> 8)
1826	/* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value suitable for setting the register. */
1827	#define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET(value) (((value) << 8) & 0x00000100)
1828
1829	/*
1830	* Field : OSC1 Timer 1 - osc1timer1
1831	*
1832	* Resets OSC1 timer 1 connected to L4
1833	*
1834	* Field Access Macros:
1835	*
1836	*/
1837	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
1838	#define ALT_RSTMGR_PERMODRST_OSC1TMR1_LSB 9
1839	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
1840	#define ALT_RSTMGR_PERMODRST_OSC1TMR1_MSB 9
1841	/* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
1842	#define ALT_RSTMGR_PERMODRST_OSC1TMR1_WIDTH 1
1843	/* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */
1844	#define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET_MSK 0x00000200
1845	/* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */
1846	#define ALT_RSTMGR_PERMODRST_OSC1TMR1_CLR_MSK 0xfffffdff
1847	/* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
1848	#define ALT_RSTMGR_PERMODRST_OSC1TMR1_RESET 0x1
1849	/* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR1 field value from a register. */
1850	#define ALT_RSTMGR_PERMODRST_OSC1TMR1_GET(value) (((value) & 0x00000200) >> 9)
1851	/* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value suitable for setting the register. */
1852	#define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET(value) (((value) << 9) & 0x00000200)
1853
1854	/*
1855	* Field : SP Timer 0 - sptimer0
1856	*
1857	* Resets SP timer 0 connected to L4
1858	*
1859	* Field Access Macros:
1860	*
1861	*/
1862	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
1863	#define ALT_RSTMGR_PERMODRST_SPTMR0_LSB 10
1864	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
1865	#define ALT_RSTMGR_PERMODRST_SPTMR0_MSB 10
1866	/* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
1867	#define ALT_RSTMGR_PERMODRST_SPTMR0_WIDTH 1
1868	/* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */
1869	#define ALT_RSTMGR_PERMODRST_SPTMR0_SET_MSK 0x00000400
1870	/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */
1871	#define ALT_RSTMGR_PERMODRST_SPTMR0_CLR_MSK 0xfffffbff
1872	/* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
1873	#define ALT_RSTMGR_PERMODRST_SPTMR0_RESET 0x1
1874	/* Extracts the ALT_RSTMGR_PERMODRST_SPTMR0 field value from a register. */
1875	#define ALT_RSTMGR_PERMODRST_SPTMR0_GET(value) (((value) & 0x00000400) >> 10)
1876	/* Produces a ALT_RSTMGR_PERMODRST_SPTMR0 register field value suitable for setting the register. */
1877	#define ALT_RSTMGR_PERMODRST_SPTMR0_SET(value) (((value) << 10) & 0x00000400)
1878
1879	/*
1880	* Field : SP Timer 1 - sptimer1
1881	*
1882	* Resets SP timer 1 connected to L4
1883	*
1884	* Field Access Macros:
1885	*
1886	*/
1887	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
1888	#define ALT_RSTMGR_PERMODRST_SPTMR1_LSB 11
1889	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
1890	#define ALT_RSTMGR_PERMODRST_SPTMR1_MSB 11
1891	/* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
1892	#define ALT_RSTMGR_PERMODRST_SPTMR1_WIDTH 1
1893	/* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */
1894	#define ALT_RSTMGR_PERMODRST_SPTMR1_SET_MSK 0x00000800
1895	/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */
1896	#define ALT_RSTMGR_PERMODRST_SPTMR1_CLR_MSK 0xfffff7ff
1897	/* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
1898	#define ALT_RSTMGR_PERMODRST_SPTMR1_RESET 0x1
1899	/* Extracts the ALT_RSTMGR_PERMODRST_SPTMR1 field value from a register. */
1900	#define ALT_RSTMGR_PERMODRST_SPTMR1_GET(value) (((value) & 0x00000800) >> 11)
1901	/* Produces a ALT_RSTMGR_PERMODRST_SPTMR1 register field value suitable for setting the register. */
1902	#define ALT_RSTMGR_PERMODRST_SPTMR1_SET(value) (((value) << 11) & 0x00000800)
1903
1904	/*
1905	* Field : I2C0 - i2c0
1906	*
1907	* Resets I2C0 controller
1908	*
1909	* Field Access Macros:
1910	*
1911	*/
1912	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
1913	#define ALT_RSTMGR_PERMODRST_I2C0_LSB 12
1914	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
1915	#define ALT_RSTMGR_PERMODRST_I2C0_MSB 12
1916	/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
1917	#define ALT_RSTMGR_PERMODRST_I2C0_WIDTH 1
1918	/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C0 register field value. */
1919	#define ALT_RSTMGR_PERMODRST_I2C0_SET_MSK 0x00001000
1920	/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C0 register field value. */
1921	#define ALT_RSTMGR_PERMODRST_I2C0_CLR_MSK 0xffffefff
1922	/* The reset value of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
1923	#define ALT_RSTMGR_PERMODRST_I2C0_RESET 0x1
1924	/* Extracts the ALT_RSTMGR_PERMODRST_I2C0 field value from a register. */
1925	#define ALT_RSTMGR_PERMODRST_I2C0_GET(value) (((value) & 0x00001000) >> 12)
1926	/* Produces a ALT_RSTMGR_PERMODRST_I2C0 register field value suitable for setting the register. */
1927	#define ALT_RSTMGR_PERMODRST_I2C0_SET(value) (((value) << 12) & 0x00001000)
1928
1929	/*
1930	* Field : I2C1 - i2c1
1931	*
1932	* Resets I2C1 controller
1933	*
1934	* Field Access Macros:
1935	*
1936	*/
1937	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
1938	#define ALT_RSTMGR_PERMODRST_I2C1_LSB 13
1939	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
1940	#define ALT_RSTMGR_PERMODRST_I2C1_MSB 13
1941	/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
1942	#define ALT_RSTMGR_PERMODRST_I2C1_WIDTH 1
1943	/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C1 register field value. */
1944	#define ALT_RSTMGR_PERMODRST_I2C1_SET_MSK 0x00002000
1945	/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C1 register field value. */
1946	#define ALT_RSTMGR_PERMODRST_I2C1_CLR_MSK 0xffffdfff
1947	/* The reset value of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
1948	#define ALT_RSTMGR_PERMODRST_I2C1_RESET 0x1
1949	/* Extracts the ALT_RSTMGR_PERMODRST_I2C1 field value from a register. */
1950	#define ALT_RSTMGR_PERMODRST_I2C1_GET(value) (((value) & 0x00002000) >> 13)
1951	/* Produces a ALT_RSTMGR_PERMODRST_I2C1 register field value suitable for setting the register. */
1952	#define ALT_RSTMGR_PERMODRST_I2C1_SET(value) (((value) << 13) & 0x00002000)
1953
1954	/*
1955	* Field : I2C2 - i2c2
1956	*
1957	* Resets I2C2 controller
1958	*
1959	* Field Access Macros:
1960	*
1961	*/
1962	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
1963	#define ALT_RSTMGR_PERMODRST_I2C2_LSB 14
1964	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
1965	#define ALT_RSTMGR_PERMODRST_I2C2_MSB 14
1966	/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
1967	#define ALT_RSTMGR_PERMODRST_I2C2_WIDTH 1
1968	/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C2 register field value. */
1969	#define ALT_RSTMGR_PERMODRST_I2C2_SET_MSK 0x00004000
1970	/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C2 register field value. */
1971	#define ALT_RSTMGR_PERMODRST_I2C2_CLR_MSK 0xffffbfff
1972	/* The reset value of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
1973	#define ALT_RSTMGR_PERMODRST_I2C2_RESET 0x1
1974	/* Extracts the ALT_RSTMGR_PERMODRST_I2C2 field value from a register. */
1975	#define ALT_RSTMGR_PERMODRST_I2C2_GET(value) (((value) & 0x00004000) >> 14)
1976	/* Produces a ALT_RSTMGR_PERMODRST_I2C2 register field value suitable for setting the register. */
1977	#define ALT_RSTMGR_PERMODRST_I2C2_SET(value) (((value) << 14) & 0x00004000)
1978
1979	/*
1980	* Field : I2C3 - i2c3
1981	*
1982	* Resets I2C3 controller
1983	*
1984	* Field Access Macros:
1985	*
1986	*/
1987	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
1988	#define ALT_RSTMGR_PERMODRST_I2C3_LSB 15
1989	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
1990	#define ALT_RSTMGR_PERMODRST_I2C3_MSB 15
1991	/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
1992	#define ALT_RSTMGR_PERMODRST_I2C3_WIDTH 1
1993	/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C3 register field value. */
1994	#define ALT_RSTMGR_PERMODRST_I2C3_SET_MSK 0x00008000
1995	/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C3 register field value. */
1996	#define ALT_RSTMGR_PERMODRST_I2C3_CLR_MSK 0xffff7fff
1997	/* The reset value of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
1998	#define ALT_RSTMGR_PERMODRST_I2C3_RESET 0x1
1999	/* Extracts the ALT_RSTMGR_PERMODRST_I2C3 field value from a register. */
2000	#define ALT_RSTMGR_PERMODRST_I2C3_GET(value) (((value) & 0x00008000) >> 15)
2001	/* Produces a ALT_RSTMGR_PERMODRST_I2C3 register field value suitable for setting the register. */
2002	#define ALT_RSTMGR_PERMODRST_I2C3_SET(value) (((value) << 15) & 0x00008000)
2003
2004	/*
2005	* Field : UART0 - uart0
2006	*
2007	* Resets UART0
2008	*
2009	* Field Access Macros:
2010	*
2011	*/
2012	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */
2013	#define ALT_RSTMGR_PERMODRST_UART0_LSB 16
2014	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */
2015	#define ALT_RSTMGR_PERMODRST_UART0_MSB 16
2016	/* The width in bits of the ALT_RSTMGR_PERMODRST_UART0 register field. */
2017	#define ALT_RSTMGR_PERMODRST_UART0_WIDTH 1
2018	/* The mask used to set the ALT_RSTMGR_PERMODRST_UART0 register field value. */
2019	#define ALT_RSTMGR_PERMODRST_UART0_SET_MSK 0x00010000
2020	/* The mask used to clear the ALT_RSTMGR_PERMODRST_UART0 register field value. */
2021	#define ALT_RSTMGR_PERMODRST_UART0_CLR_MSK 0xfffeffff
2022	/* The reset value of the ALT_RSTMGR_PERMODRST_UART0 register field. */
2023	#define ALT_RSTMGR_PERMODRST_UART0_RESET 0x1
2024	/* Extracts the ALT_RSTMGR_PERMODRST_UART0 field value from a register. */
2025	#define ALT_RSTMGR_PERMODRST_UART0_GET(value) (((value) & 0x00010000) >> 16)
2026	/* Produces a ALT_RSTMGR_PERMODRST_UART0 register field value suitable for setting the register. */
2027	#define ALT_RSTMGR_PERMODRST_UART0_SET(value) (((value) << 16) & 0x00010000)
2028
2029	/*
2030	* Field : UART1 - uart1
2031	*
2032	* Resets UART1
2033	*
2034	* Field Access Macros:
2035	*
2036	*/
2037	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */
2038	#define ALT_RSTMGR_PERMODRST_UART1_LSB 17
2039	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */
2040	#define ALT_RSTMGR_PERMODRST_UART1_MSB 17
2041	/* The width in bits of the ALT_RSTMGR_PERMODRST_UART1 register field. */
2042	#define ALT_RSTMGR_PERMODRST_UART1_WIDTH 1
2043	/* The mask used to set the ALT_RSTMGR_PERMODRST_UART1 register field value. */
2044	#define ALT_RSTMGR_PERMODRST_UART1_SET_MSK 0x00020000
2045	/* The mask used to clear the ALT_RSTMGR_PERMODRST_UART1 register field value. */
2046	#define ALT_RSTMGR_PERMODRST_UART1_CLR_MSK 0xfffdffff
2047	/* The reset value of the ALT_RSTMGR_PERMODRST_UART1 register field. */
2048	#define ALT_RSTMGR_PERMODRST_UART1_RESET 0x1
2049	/* Extracts the ALT_RSTMGR_PERMODRST_UART1 field value from a register. */
2050	#define ALT_RSTMGR_PERMODRST_UART1_GET(value) (((value) & 0x00020000) >> 17)
2051	/* Produces a ALT_RSTMGR_PERMODRST_UART1 register field value suitable for setting the register. */
2052	#define ALT_RSTMGR_PERMODRST_UART1_SET(value) (((value) << 17) & 0x00020000)
2053
2054	/*
2055	* Field : SPIM0 - spim0
2056	*
2057	* Resets SPIM0 controller
2058	*
2059	* Field Access Macros:
2060	*
2061	*/
2062	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
2063	#define ALT_RSTMGR_PERMODRST_SPIM0_LSB 18
2064	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
2065	#define ALT_RSTMGR_PERMODRST_SPIM0_MSB 18
2066	/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
2067	#define ALT_RSTMGR_PERMODRST_SPIM0_WIDTH 1
2068	/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */
2069	#define ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK 0x00040000
2070	/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */
2071	#define ALT_RSTMGR_PERMODRST_SPIM0_CLR_MSK 0xfffbffff
2072	/* The reset value of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
2073	#define ALT_RSTMGR_PERMODRST_SPIM0_RESET 0x1
2074	/* Extracts the ALT_RSTMGR_PERMODRST_SPIM0 field value from a register. */
2075	#define ALT_RSTMGR_PERMODRST_SPIM0_GET(value) (((value) & 0x00040000) >> 18)
2076	/* Produces a ALT_RSTMGR_PERMODRST_SPIM0 register field value suitable for setting the register. */
2077	#define ALT_RSTMGR_PERMODRST_SPIM0_SET(value) (((value) << 18) & 0x00040000)
2078
2079	/*
2080	* Field : SPIM1 - spim1
2081	*
2082	* Resets SPIM1 controller
2083	*
2084	* Field Access Macros:
2085	*
2086	*/
2087	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
2088	#define ALT_RSTMGR_PERMODRST_SPIM1_LSB 19
2089	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
2090	#define ALT_RSTMGR_PERMODRST_SPIM1_MSB 19
2091	/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
2092	#define ALT_RSTMGR_PERMODRST_SPIM1_WIDTH 1
2093	/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */
2094	#define ALT_RSTMGR_PERMODRST_SPIM1_SET_MSK 0x00080000
2095	/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */
2096	#define ALT_RSTMGR_PERMODRST_SPIM1_CLR_MSK 0xfff7ffff
2097	/* The reset value of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
2098	#define ALT_RSTMGR_PERMODRST_SPIM1_RESET 0x1
2099	/* Extracts the ALT_RSTMGR_PERMODRST_SPIM1 field value from a register. */
2100	#define ALT_RSTMGR_PERMODRST_SPIM1_GET(value) (((value) & 0x00080000) >> 19)
2101	/* Produces a ALT_RSTMGR_PERMODRST_SPIM1 register field value suitable for setting the register. */
2102	#define ALT_RSTMGR_PERMODRST_SPIM1_SET(value) (((value) << 19) & 0x00080000)
2103
2104	/*
2105	* Field : SPIS0 - spis0
2106	*
2107	* Resets SPIS0 controller
2108	*
2109	* Field Access Macros:
2110	*
2111	*/
2112	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
2113	#define ALT_RSTMGR_PERMODRST_SPIS0_LSB 20
2114	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
2115	#define ALT_RSTMGR_PERMODRST_SPIS0_MSB 20
2116	/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
2117	#define ALT_RSTMGR_PERMODRST_SPIS0_WIDTH 1
2118	/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */
2119	#define ALT_RSTMGR_PERMODRST_SPIS0_SET_MSK 0x00100000
2120	/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */
2121	#define ALT_RSTMGR_PERMODRST_SPIS0_CLR_MSK 0xffefffff
2122	/* The reset value of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
2123	#define ALT_RSTMGR_PERMODRST_SPIS0_RESET 0x1
2124	/* Extracts the ALT_RSTMGR_PERMODRST_SPIS0 field value from a register. */
2125	#define ALT_RSTMGR_PERMODRST_SPIS0_GET(value) (((value) & 0x00100000) >> 20)
2126	/* Produces a ALT_RSTMGR_PERMODRST_SPIS0 register field value suitable for setting the register. */
2127	#define ALT_RSTMGR_PERMODRST_SPIS0_SET(value) (((value) << 20) & 0x00100000)
2128
2129	/*
2130	* Field : SPIS1 - spis1
2131	*
2132	* Resets SPIS1 controller
2133	*
2134	* Field Access Macros:
2135	*
2136	*/
2137	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
2138	#define ALT_RSTMGR_PERMODRST_SPIS1_LSB 21
2139	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
2140	#define ALT_RSTMGR_PERMODRST_SPIS1_MSB 21
2141	/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
2142	#define ALT_RSTMGR_PERMODRST_SPIS1_WIDTH 1
2143	/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */
2144	#define ALT_RSTMGR_PERMODRST_SPIS1_SET_MSK 0x00200000
2145	/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */
2146	#define ALT_RSTMGR_PERMODRST_SPIS1_CLR_MSK 0xffdfffff
2147	/* The reset value of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
2148	#define ALT_RSTMGR_PERMODRST_SPIS1_RESET 0x1
2149	/* Extracts the ALT_RSTMGR_PERMODRST_SPIS1 field value from a register. */
2150	#define ALT_RSTMGR_PERMODRST_SPIS1_GET(value) (((value) & 0x00200000) >> 21)
2151	/* Produces a ALT_RSTMGR_PERMODRST_SPIS1 register field value suitable for setting the register. */
2152	#define ALT_RSTMGR_PERMODRST_SPIS1_SET(value) (((value) << 21) & 0x00200000)
2153
2154	/*
2155	* Field : SD/MMC - sdmmc
2156	*
2157	* Resets SD/MMC controller
2158	*
2159	* Field Access Macros:
2160	*
2161	*/
2162	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
2163	#define ALT_RSTMGR_PERMODRST_SDMMC_LSB 22
2164	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
2165	#define ALT_RSTMGR_PERMODRST_SDMMC_MSB 22
2166	/* The width in bits of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
2167	#define ALT_RSTMGR_PERMODRST_SDMMC_WIDTH 1
2168	/* The mask used to set the ALT_RSTMGR_PERMODRST_SDMMC register field value. */
2169	#define ALT_RSTMGR_PERMODRST_SDMMC_SET_MSK 0x00400000
2170	/* The mask used to clear the ALT_RSTMGR_PERMODRST_SDMMC register field value. */
2171	#define ALT_RSTMGR_PERMODRST_SDMMC_CLR_MSK 0xffbfffff
2172	/* The reset value of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
2173	#define ALT_RSTMGR_PERMODRST_SDMMC_RESET 0x1
2174	/* Extracts the ALT_RSTMGR_PERMODRST_SDMMC field value from a register. */
2175	#define ALT_RSTMGR_PERMODRST_SDMMC_GET(value) (((value) & 0x00400000) >> 22)
2176	/* Produces a ALT_RSTMGR_PERMODRST_SDMMC register field value suitable for setting the register. */
2177	#define ALT_RSTMGR_PERMODRST_SDMMC_SET(value) (((value) << 22) & 0x00400000)
2178
2179	/*
2180	* Field : CAN0 - can0
2181	*
2182	* Resets CAN0 controller.
2183	*
2184	* Writes to this field on devices not containing CAN controllers will be ignored.
2185	*
2186	* Field Access Macros:
2187	*
2188	*/
2189	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
2190	#define ALT_RSTMGR_PERMODRST_CAN0_LSB 23
2191	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
2192	#define ALT_RSTMGR_PERMODRST_CAN0_MSB 23
2193	/* The width in bits of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
2194	#define ALT_RSTMGR_PERMODRST_CAN0_WIDTH 1
2195	/* The mask used to set the ALT_RSTMGR_PERMODRST_CAN0 register field value. */
2196	#define ALT_RSTMGR_PERMODRST_CAN0_SET_MSK 0x00800000
2197	/* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN0 register field value. */
2198	#define ALT_RSTMGR_PERMODRST_CAN0_CLR_MSK 0xff7fffff
2199	/* The reset value of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
2200	#define ALT_RSTMGR_PERMODRST_CAN0_RESET 0x1
2201	/* Extracts the ALT_RSTMGR_PERMODRST_CAN0 field value from a register. */
2202	#define ALT_RSTMGR_PERMODRST_CAN0_GET(value) (((value) & 0x00800000) >> 23)
2203	/* Produces a ALT_RSTMGR_PERMODRST_CAN0 register field value suitable for setting the register. */
2204	#define ALT_RSTMGR_PERMODRST_CAN0_SET(value) (((value) << 23) & 0x00800000)
2205
2206	/*
2207	* Field : CAN1 - can1
2208	*
2209	* Resets CAN1 controller.
2210	*
2211	* Writes to this field on devices not containing CAN controllers will be ignored.
2212	*
2213	* Field Access Macros:
2214	*
2215	*/
2216	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
2217	#define ALT_RSTMGR_PERMODRST_CAN1_LSB 24
2218	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
2219	#define ALT_RSTMGR_PERMODRST_CAN1_MSB 24
2220	/* The width in bits of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
2221	#define ALT_RSTMGR_PERMODRST_CAN1_WIDTH 1
2222	/* The mask used to set the ALT_RSTMGR_PERMODRST_CAN1 register field value. */
2223	#define ALT_RSTMGR_PERMODRST_CAN1_SET_MSK 0x01000000
2224	/* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN1 register field value. */
2225	#define ALT_RSTMGR_PERMODRST_CAN1_CLR_MSK 0xfeffffff
2226	/* The reset value of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
2227	#define ALT_RSTMGR_PERMODRST_CAN1_RESET 0x1
2228	/* Extracts the ALT_RSTMGR_PERMODRST_CAN1 field value from a register. */
2229	#define ALT_RSTMGR_PERMODRST_CAN1_GET(value) (((value) & 0x01000000) >> 24)
2230	/* Produces a ALT_RSTMGR_PERMODRST_CAN1 register field value suitable for setting the register. */
2231	#define ALT_RSTMGR_PERMODRST_CAN1_SET(value) (((value) << 24) & 0x01000000)
2232
2233	/*
2234	* Field : GPIO0 - gpio0
2235	*
2236	* Resets GPIO0
2237	*
2238	* Field Access Macros:
2239	*
2240	*/
2241	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
2242	#define ALT_RSTMGR_PERMODRST_GPIO0_LSB 25
2243	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
2244	#define ALT_RSTMGR_PERMODRST_GPIO0_MSB 25
2245	/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
2246	#define ALT_RSTMGR_PERMODRST_GPIO0_WIDTH 1
2247	/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */
2248	#define ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK 0x02000000
2249	/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */
2250	#define ALT_RSTMGR_PERMODRST_GPIO0_CLR_MSK 0xfdffffff
2251	/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
2252	#define ALT_RSTMGR_PERMODRST_GPIO0_RESET 0x1
2253	/* Extracts the ALT_RSTMGR_PERMODRST_GPIO0 field value from a register. */
2254	#define ALT_RSTMGR_PERMODRST_GPIO0_GET(value) (((value) & 0x02000000) >> 25)
2255	/* Produces a ALT_RSTMGR_PERMODRST_GPIO0 register field value suitable for setting the register. */
2256	#define ALT_RSTMGR_PERMODRST_GPIO0_SET(value) (((value) << 25) & 0x02000000)
2257
2258	/*
2259	* Field : GPIO1 - gpio1
2260	*
2261	* Resets GPIO1
2262	*
2263	* Field Access Macros:
2264	*
2265	*/
2266	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
2267	#define ALT_RSTMGR_PERMODRST_GPIO1_LSB 26
2268	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
2269	#define ALT_RSTMGR_PERMODRST_GPIO1_MSB 26
2270	/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
2271	#define ALT_RSTMGR_PERMODRST_GPIO1_WIDTH 1
2272	/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */
2273	#define ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK 0x04000000
2274	/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */
2275	#define ALT_RSTMGR_PERMODRST_GPIO1_CLR_MSK 0xfbffffff
2276	/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
2277	#define ALT_RSTMGR_PERMODRST_GPIO1_RESET 0x1
2278	/* Extracts the ALT_RSTMGR_PERMODRST_GPIO1 field value from a register. */
2279	#define ALT_RSTMGR_PERMODRST_GPIO1_GET(value) (((value) & 0x04000000) >> 26)
2280	/* Produces a ALT_RSTMGR_PERMODRST_GPIO1 register field value suitable for setting the register. */
2281	#define ALT_RSTMGR_PERMODRST_GPIO1_SET(value) (((value) << 26) & 0x04000000)
2282
2283	/*
2284	* Field : GPIO2 - gpio2
2285	*
2286	* Resets GPIO2
2287	*
2288	* Field Access Macros:
2289	*
2290	*/
2291	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
2292	#define ALT_RSTMGR_PERMODRST_GPIO2_LSB 27
2293	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
2294	#define ALT_RSTMGR_PERMODRST_GPIO2_MSB 27
2295	/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
2296	#define ALT_RSTMGR_PERMODRST_GPIO2_WIDTH 1
2297	/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */
2298	#define ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK 0x08000000
2299	/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */
2300	#define ALT_RSTMGR_PERMODRST_GPIO2_CLR_MSK 0xf7ffffff
2301	/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
2302	#define ALT_RSTMGR_PERMODRST_GPIO2_RESET 0x1
2303	/* Extracts the ALT_RSTMGR_PERMODRST_GPIO2 field value from a register. */
2304	#define ALT_RSTMGR_PERMODRST_GPIO2_GET(value) (((value) & 0x08000000) >> 27)
2305	/* Produces a ALT_RSTMGR_PERMODRST_GPIO2 register field value suitable for setting the register. */
2306	#define ALT_RSTMGR_PERMODRST_GPIO2_SET(value) (((value) << 27) & 0x08000000)
2307
2308	/*
2309	* Field : DMA Controller - dma
2310	*
2311	* Resets DMA controller
2312	*
2313	* Field Access Macros:
2314	*
2315	*/
2316	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */
2317	#define ALT_RSTMGR_PERMODRST_DMA_LSB 28
2318	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */
2319	#define ALT_RSTMGR_PERMODRST_DMA_MSB 28
2320	/* The width in bits of the ALT_RSTMGR_PERMODRST_DMA register field. */
2321	#define ALT_RSTMGR_PERMODRST_DMA_WIDTH 1
2322	/* The mask used to set the ALT_RSTMGR_PERMODRST_DMA register field value. */
2323	#define ALT_RSTMGR_PERMODRST_DMA_SET_MSK 0x10000000
2324	/* The mask used to clear the ALT_RSTMGR_PERMODRST_DMA register field value. */
2325	#define ALT_RSTMGR_PERMODRST_DMA_CLR_MSK 0xefffffff
2326	/* The reset value of the ALT_RSTMGR_PERMODRST_DMA register field. */
2327	#define ALT_RSTMGR_PERMODRST_DMA_RESET 0x1
2328	/* Extracts the ALT_RSTMGR_PERMODRST_DMA field value from a register. */
2329	#define ALT_RSTMGR_PERMODRST_DMA_GET(value) (((value) & 0x10000000) >> 28)
2330	/* Produces a ALT_RSTMGR_PERMODRST_DMA register field value suitable for setting the register. */
2331	#define ALT_RSTMGR_PERMODRST_DMA_SET(value) (((value) << 28) & 0x10000000)
2332
2333	/*
2334	* Field : SDRAM Controller Subsystem - sdr
2335	*
2336	* Resets SDRAM Controller Subsystem affected by a warm or cold reset.
2337	*
2338	* Field Access Macros:
2339	*
2340	*/
2341	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */
2342	#define ALT_RSTMGR_PERMODRST_SDR_LSB 29
2343	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */
2344	#define ALT_RSTMGR_PERMODRST_SDR_MSB 29
2345	/* The width in bits of the ALT_RSTMGR_PERMODRST_SDR register field. */
2346	#define ALT_RSTMGR_PERMODRST_SDR_WIDTH 1
2347	/* The mask used to set the ALT_RSTMGR_PERMODRST_SDR register field value. */
2348	#define ALT_RSTMGR_PERMODRST_SDR_SET_MSK 0x20000000
2349	/* The mask used to clear the ALT_RSTMGR_PERMODRST_SDR register field value. */
2350	#define ALT_RSTMGR_PERMODRST_SDR_CLR_MSK 0xdfffffff
2351	/* The reset value of the ALT_RSTMGR_PERMODRST_SDR register field. */
2352	#define ALT_RSTMGR_PERMODRST_SDR_RESET 0x1
2353	/* Extracts the ALT_RSTMGR_PERMODRST_SDR field value from a register. */
2354	#define ALT_RSTMGR_PERMODRST_SDR_GET(value) (((value) & 0x20000000) >> 29)
2355	/* Produces a ALT_RSTMGR_PERMODRST_SDR register field value suitable for setting the register. */
2356	#define ALT_RSTMGR_PERMODRST_SDR_SET(value) (((value) << 29) & 0x20000000)
2357
2358	#ifndef __ASSEMBLY__
2359	/*
2360	* WARNING: The C register and register group struct declarations are provided for
2361	* convenience and illustrative purposes. They should, however, be used with
2362	* caution as the C language standard provides no guarantees about the alignment or
2363	* atomicity of device memory accesses. The recommended practice for writing
2364	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
2365	* alt_write_word() functions.
2366	*
2367	* The struct declaration for register ALT_RSTMGR_PERMODRST.
2368	*/
2369	struct ALT_RSTMGR_PERMODRST_s
2370	{
2371	uint32_t emac0 : 1; /* EMAC0 */
2372	uint32_t emac1 : 1; /* EMAC1 */
2373	uint32_t usb0 : 1; /* USB0 */
2374	uint32_t usb1 : 1; /* USB1 */
2375	uint32_t nand : 1; /* NAND Flash */
2376	uint32_t qspi : 1; /* QSPI Flash */
2377	uint32_t l4wd0 : 1; /* L4 Watchdog 0 */
2378	uint32_t l4wd1 : 1; /* L4 Watchdog 1 */
2379	uint32_t osc1timer0 : 1; /* OSC1 Timer 0 */
2380	uint32_t osc1timer1 : 1; /* OSC1 Timer 1 */
2381	uint32_t sptimer0 : 1; /* SP Timer 0 */
2382	uint32_t sptimer1 : 1; /* SP Timer 1 */
2383	uint32_t i2c0 : 1; /* I2C0 */
2384	uint32_t i2c1 : 1; /* I2C1 */
2385	uint32_t i2c2 : 1; /* I2C2 */
2386	uint32_t i2c3 : 1; /* I2C3 */
2387	uint32_t uart0 : 1; /* UART0 */
2388	uint32_t uart1 : 1; /* UART1 */
2389	uint32_t spim0 : 1; /* SPIM0 */
2390	uint32_t spim1 : 1; /* SPIM1 */
2391	uint32_t spis0 : 1; /* SPIS0 */
2392	uint32_t spis1 : 1; /* SPIS1 */
2393	uint32_t sdmmc : 1; /* SD/MMC */
2394	uint32_t can0 : 1; /* CAN0 */
2395	uint32_t can1 : 1; /* CAN1 */
2396	uint32_t gpio0 : 1; /* GPIO0 */
2397	uint32_t gpio1 : 1; /* GPIO1 */
2398	uint32_t gpio2 : 1; /* GPIO2 */
2399	uint32_t dma : 1; /* DMA Controller */
2400	uint32_t sdr : 1; /* SDRAM Controller Subsystem */
2401	uint32_t : 2; /* UNDEFINED */
2402	};
2403
2404	/* The typedef declaration for register ALT_RSTMGR_PERMODRST. */
2405	typedef volatile struct ALT_RSTMGR_PERMODRST_s ALT_RSTMGR_PERMODRST_t;
2406	#endif /* __ASSEMBLY__ */
2407
2408	/* The byte offset of the ALT_RSTMGR_PERMODRST register from the beginning of the component. */
2409	#define ALT_RSTMGR_PERMODRST_OFST 0x14
2410
2411	/*
2412	* Register : Peripheral 2 Module Reset Register - per2modrst
2413	*
2414	* The PER2MODRST register is used by software to trigger module resets (individual
2415	* module reset signals). Software explicitly asserts and de-asserts module reset
2416	* signals by writing bits in the appropriate *MODRST register. It is up to
2417	* software to ensure module reset signals are asserted for the appropriate length
2418	* of time and are de-asserted in the correct order. It is also up to software to
2419	* not assert a module reset signal that would prevent software from de-asserting
2420	* the module reset signal. For example, software should not assert the module
2421	* reset to the CPU executing the software.
2422	*
2423	* Software writes a bit to 1 to assert the module reset signal and to 0 to de-
2424	* assert the module reset signal.
2425	*
2426	* All fields are reset by a cold reset.All fields are also reset by a warm reset
2427	* if not masked by the corresponding PERWARMMASK field.
2428	*
2429	* The reset value of all fields is 1. This holds the corresponding module in reset
2430	* until software is ready to release the module from reset by writing 0 to its
2431	* field.
2432	*
2433	* Register Layout
2434	*
2435	* Bits \| Access \| Reset \| Description
2436	* :-------\|:-------\|:------\|:------------
2437	* [0] \| RW \| 0x1 \| FPGA DMA0
2438	* [1] \| RW \| 0x1 \| FPGA DMA1
2439	* [2] \| RW \| 0x1 \| FPGA DMA2
2440	* [3] \| RW \| 0x1 \| FPGA DMA3
2441	* [4] \| RW \| 0x1 \| FPGA DMA4
2442	* [5] \| RW \| 0x1 \| FPGA DMA5
2443	* [6] \| RW \| 0x1 \| FPGA DMA6
2444	* [7] \| RW \| 0x1 \| FPGA DMA7
2445	* [31:8] \| ??? \| 0x0 \| UNDEFINED
2446	*
2447	*/
2448	/*
2449	* Field : FPGA DMA0 - dmaif0
2450	*
2451	* Resets DMA channel 0 interface adapter between FPGA Fabric and HPS DMA
2452	* Controller
2453	*
2454	* Field Access Macros:
2455	*
2456	*/
2457	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
2458	#define ALT_RSTMGR_PER2MODRST_DMAIF0_LSB 0
2459	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
2460	#define ALT_RSTMGR_PER2MODRST_DMAIF0_MSB 0
2461	/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
2462	#define ALT_RSTMGR_PER2MODRST_DMAIF0_WIDTH 1
2463	/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */
2464	#define ALT_RSTMGR_PER2MODRST_DMAIF0_SET_MSK 0x00000001
2465	/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */
2466	#define ALT_RSTMGR_PER2MODRST_DMAIF0_CLR_MSK 0xfffffffe
2467	/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
2468	#define ALT_RSTMGR_PER2MODRST_DMAIF0_RESET 0x1
2469	/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF0 field value from a register. */
2470	#define ALT_RSTMGR_PER2MODRST_DMAIF0_GET(value) (((value) & 0x00000001) >> 0)
2471	/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF0 register field value suitable for setting the register. */
2472	#define ALT_RSTMGR_PER2MODRST_DMAIF0_SET(value) (((value) << 0) & 0x00000001)
2473
2474	/*
2475	* Field : FPGA DMA1 - dmaif1
2476	*
2477	* Resets DMA channel 1 interface adapter between FPGA Fabric and HPS DMA
2478	* Controller
2479	*
2480	* Field Access Macros:
2481	*
2482	*/
2483	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
2484	#define ALT_RSTMGR_PER2MODRST_DMAIF1_LSB 1
2485	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
2486	#define ALT_RSTMGR_PER2MODRST_DMAIF1_MSB 1
2487	/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
2488	#define ALT_RSTMGR_PER2MODRST_DMAIF1_WIDTH 1
2489	/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */
2490	#define ALT_RSTMGR_PER2MODRST_DMAIF1_SET_MSK 0x00000002
2491	/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */
2492	#define ALT_RSTMGR_PER2MODRST_DMAIF1_CLR_MSK 0xfffffffd
2493	/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
2494	#define ALT_RSTMGR_PER2MODRST_DMAIF1_RESET 0x1
2495	/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF1 field value from a register. */
2496	#define ALT_RSTMGR_PER2MODRST_DMAIF1_GET(value) (((value) & 0x00000002) >> 1)
2497	/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF1 register field value suitable for setting the register. */
2498	#define ALT_RSTMGR_PER2MODRST_DMAIF1_SET(value) (((value) << 1) & 0x00000002)
2499
2500	/*
2501	* Field : FPGA DMA2 - dmaif2
2502	*
2503	* Resets DMA channel 2 interface adapter between FPGA Fabric and HPS DMA
2504	* Controller
2505	*
2506	* Field Access Macros:
2507	*
2508	*/
2509	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
2510	#define ALT_RSTMGR_PER2MODRST_DMAIF2_LSB 2
2511	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
2512	#define ALT_RSTMGR_PER2MODRST_DMAIF2_MSB 2
2513	/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
2514	#define ALT_RSTMGR_PER2MODRST_DMAIF2_WIDTH 1
2515	/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */
2516	#define ALT_RSTMGR_PER2MODRST_DMAIF2_SET_MSK 0x00000004
2517	/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */
2518	#define ALT_RSTMGR_PER2MODRST_DMAIF2_CLR_MSK 0xfffffffb
2519	/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
2520	#define ALT_RSTMGR_PER2MODRST_DMAIF2_RESET 0x1
2521	/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF2 field value from a register. */
2522	#define ALT_RSTMGR_PER2MODRST_DMAIF2_GET(value) (((value) & 0x00000004) >> 2)
2523	/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF2 register field value suitable for setting the register. */
2524	#define ALT_RSTMGR_PER2MODRST_DMAIF2_SET(value) (((value) << 2) & 0x00000004)
2525
2526	/*
2527	* Field : FPGA DMA3 - dmaif3
2528	*
2529	* Resets DMA channel 3 interface adapter between FPGA Fabric and HPS DMA
2530	* Controller
2531	*
2532	* Field Access Macros:
2533	*
2534	*/
2535	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
2536	#define ALT_RSTMGR_PER2MODRST_DMAIF3_LSB 3
2537	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
2538	#define ALT_RSTMGR_PER2MODRST_DMAIF3_MSB 3
2539	/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
2540	#define ALT_RSTMGR_PER2MODRST_DMAIF3_WIDTH 1
2541	/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */
2542	#define ALT_RSTMGR_PER2MODRST_DMAIF3_SET_MSK 0x00000008
2543	/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */
2544	#define ALT_RSTMGR_PER2MODRST_DMAIF3_CLR_MSK 0xfffffff7
2545	/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
2546	#define ALT_RSTMGR_PER2MODRST_DMAIF3_RESET 0x1
2547	/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF3 field value from a register. */
2548	#define ALT_RSTMGR_PER2MODRST_DMAIF3_GET(value) (((value) & 0x00000008) >> 3)
2549	/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF3 register field value suitable for setting the register. */
2550	#define ALT_RSTMGR_PER2MODRST_DMAIF3_SET(value) (((value) << 3) & 0x00000008)
2551
2552	/*
2553	* Field : FPGA DMA4 - dmaif4
2554	*
2555	* Resets DMA channel 4 interface adapter between FPGA Fabric and HPS DMA
2556	* Controller
2557	*
2558	* Field Access Macros:
2559	*
2560	*/
2561	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
2562	#define ALT_RSTMGR_PER2MODRST_DMAIF4_LSB 4
2563	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
2564	#define ALT_RSTMGR_PER2MODRST_DMAIF4_MSB 4
2565	/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
2566	#define ALT_RSTMGR_PER2MODRST_DMAIF4_WIDTH 1
2567	/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */
2568	#define ALT_RSTMGR_PER2MODRST_DMAIF4_SET_MSK 0x00000010
2569	/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */
2570	#define ALT_RSTMGR_PER2MODRST_DMAIF4_CLR_MSK 0xffffffef
2571	/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
2572	#define ALT_RSTMGR_PER2MODRST_DMAIF4_RESET 0x1
2573	/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF4 field value from a register. */
2574	#define ALT_RSTMGR_PER2MODRST_DMAIF4_GET(value) (((value) & 0x00000010) >> 4)
2575	/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF4 register field value suitable for setting the register. */
2576	#define ALT_RSTMGR_PER2MODRST_DMAIF4_SET(value) (((value) << 4) & 0x00000010)
2577
2578	/*
2579	* Field : FPGA DMA5 - dmaif5
2580	*
2581	* Resets DMA channel 5 interface adapter between FPGA Fabric and HPS DMA
2582	* Controller
2583	*
2584	* Field Access Macros:
2585	*
2586	*/
2587	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
2588	#define ALT_RSTMGR_PER2MODRST_DMAIF5_LSB 5
2589	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
2590	#define ALT_RSTMGR_PER2MODRST_DMAIF5_MSB 5
2591	/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
2592	#define ALT_RSTMGR_PER2MODRST_DMAIF5_WIDTH 1
2593	/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */
2594	#define ALT_RSTMGR_PER2MODRST_DMAIF5_SET_MSK 0x00000020
2595	/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */
2596	#define ALT_RSTMGR_PER2MODRST_DMAIF5_CLR_MSK 0xffffffdf
2597	/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
2598	#define ALT_RSTMGR_PER2MODRST_DMAIF5_RESET 0x1
2599	/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF5 field value from a register. */
2600	#define ALT_RSTMGR_PER2MODRST_DMAIF5_GET(value) (((value) & 0x00000020) >> 5)
2601	/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF5 register field value suitable for setting the register. */
2602	#define ALT_RSTMGR_PER2MODRST_DMAIF5_SET(value) (((value) << 5) & 0x00000020)
2603
2604	/*
2605	* Field : FPGA DMA6 - dmaif6
2606	*
2607	* Resets DMA channel 6 interface adapter between FPGA Fabric and HPS DMA
2608	* Controller
2609	*
2610	* Field Access Macros:
2611	*
2612	*/
2613	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
2614	#define ALT_RSTMGR_PER2MODRST_DMAIF6_LSB 6
2615	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
2616	#define ALT_RSTMGR_PER2MODRST_DMAIF6_MSB 6
2617	/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
2618	#define ALT_RSTMGR_PER2MODRST_DMAIF6_WIDTH 1
2619	/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */
2620	#define ALT_RSTMGR_PER2MODRST_DMAIF6_SET_MSK 0x00000040
2621	/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */
2622	#define ALT_RSTMGR_PER2MODRST_DMAIF6_CLR_MSK 0xffffffbf
2623	/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
2624	#define ALT_RSTMGR_PER2MODRST_DMAIF6_RESET 0x1
2625	/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF6 field value from a register. */
2626	#define ALT_RSTMGR_PER2MODRST_DMAIF6_GET(value) (((value) & 0x00000040) >> 6)
2627	/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF6 register field value suitable for setting the register. */
2628	#define ALT_RSTMGR_PER2MODRST_DMAIF6_SET(value) (((value) << 6) & 0x00000040)
2629
2630	/*
2631	* Field : FPGA DMA7 - dmaif7
2632	*
2633	* Resets DMA channel 7 interface adapter between FPGA Fabric and HPS DMA
2634	* Controller
2635	*
2636	* Field Access Macros:
2637	*
2638	*/
2639	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
2640	#define ALT_RSTMGR_PER2MODRST_DMAIF7_LSB 7
2641	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
2642	#define ALT_RSTMGR_PER2MODRST_DMAIF7_MSB 7
2643	/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
2644	#define ALT_RSTMGR_PER2MODRST_DMAIF7_WIDTH 1
2645	/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */
2646	#define ALT_RSTMGR_PER2MODRST_DMAIF7_SET_MSK 0x00000080
2647	/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */
2648	#define ALT_RSTMGR_PER2MODRST_DMAIF7_CLR_MSK 0xffffff7f
2649	/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
2650	#define ALT_RSTMGR_PER2MODRST_DMAIF7_RESET 0x1
2651	/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF7 field value from a register. */
2652	#define ALT_RSTMGR_PER2MODRST_DMAIF7_GET(value) (((value) & 0x00000080) >> 7)
2653	/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF7 register field value suitable for setting the register. */
2654	#define ALT_RSTMGR_PER2MODRST_DMAIF7_SET(value) (((value) << 7) & 0x00000080)
2655
2656	#ifndef __ASSEMBLY__
2657	/*
2658	* WARNING: The C register and register group struct declarations are provided for
2659	* convenience and illustrative purposes. They should, however, be used with
2660	* caution as the C language standard provides no guarantees about the alignment or
2661	* atomicity of device memory accesses. The recommended practice for writing
2662	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
2663	* alt_write_word() functions.
2664	*
2665	* The struct declaration for register ALT_RSTMGR_PER2MODRST.
2666	*/
2667	struct ALT_RSTMGR_PER2MODRST_s
2668	{
2669	uint32_t dmaif0 : 1; /* FPGA DMA0 */
2670	uint32_t dmaif1 : 1; /* FPGA DMA1 */
2671	uint32_t dmaif2 : 1; /* FPGA DMA2 */
2672	uint32_t dmaif3 : 1; /* FPGA DMA3 */
2673	uint32_t dmaif4 : 1; /* FPGA DMA4 */
2674	uint32_t dmaif5 : 1; /* FPGA DMA5 */
2675	uint32_t dmaif6 : 1; /* FPGA DMA6 */
2676	uint32_t dmaif7 : 1; /* FPGA DMA7 */
2677	uint32_t : 24; /* UNDEFINED */
2678	};
2679
2680	/* The typedef declaration for register ALT_RSTMGR_PER2MODRST. */
2681	typedef volatile struct ALT_RSTMGR_PER2MODRST_s ALT_RSTMGR_PER2MODRST_t;
2682	#endif /* __ASSEMBLY__ */
2683
2684	/* The byte offset of the ALT_RSTMGR_PER2MODRST register from the beginning of the component. */
2685	#define ALT_RSTMGR_PER2MODRST_OFST 0x18
2686
2687	/*
2688	* Register : Bridge Module Reset Register - brgmodrst
2689	*
2690	* The BRGMODRST register is used by software to trigger module resets (individual
2691	* module reset signals). Software explicitly asserts and de-asserts module reset
2692	* signals by writing bits in the appropriate *MODRST register. It is up to
2693	* software to ensure module reset signals are asserted for the appropriate length
2694	* of time and are de-asserted in the correct order. It is also up to software to
2695	* not assert a module reset signal that would prevent software from de-asserting
2696	* the module reset signal. For example, software should not assert the module
2697	* reset to the CPU executing the software.
2698	*
2699	* Software writes a bit to 1 to assert the module reset signal and to 0 to de-
2700	* assert the module reset signal.
2701	*
2702	* All fields are reset by a cold reset.All fields are also reset by a warm reset
2703	* if not masked by the corresponding BRGWARMMASK field.
2704	*
2705	* The reset value of all fields is 1. This holds the corresponding module in reset
2706	* until software is ready to release the module from reset by writing 0 to its
2707	* field.
2708	*
2709	* Register Layout
2710	*
2711	* Bits \| Access \| Reset \| Description
2712	* :-------\|:-------\|:------\|:------------------
2713	* [0] \| RW \| 0x1 \| HPS2FPGA Bridge
2714	* [1] \| RW \| 0x1 \| LWHPS2FPGA Bridge
2715	* [2] \| RW \| 0x1 \| FPGA2HPS Bridge
2716	* [31:3] \| ??? \| 0x0 \| UNDEFINED
2717	*
2718	*/
2719	/*
2720	* Field : HPS2FPGA Bridge - hps2fpga
2721	*
2722	* Resets HPS2FPGA Bridge
2723	*
2724	* Field Access Macros:
2725	*
2726	*/
2727	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */
2728	#define ALT_RSTMGR_BRGMODRST_H2F_LSB 0
2729	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */
2730	#define ALT_RSTMGR_BRGMODRST_H2F_MSB 0
2731	/* The width in bits of the ALT_RSTMGR_BRGMODRST_H2F register field. */
2732	#define ALT_RSTMGR_BRGMODRST_H2F_WIDTH 1
2733	/* The mask used to set the ALT_RSTMGR_BRGMODRST_H2F register field value. */
2734	#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001
2735	/* The mask used to clear the ALT_RSTMGR_BRGMODRST_H2F register field value. */
2736	#define ALT_RSTMGR_BRGMODRST_H2F_CLR_MSK 0xfffffffe
2737	/* The reset value of the ALT_RSTMGR_BRGMODRST_H2F register field. */
2738	#define ALT_RSTMGR_BRGMODRST_H2F_RESET 0x1
2739	/* Extracts the ALT_RSTMGR_BRGMODRST_H2F field value from a register. */
2740	#define ALT_RSTMGR_BRGMODRST_H2F_GET(value) (((value) & 0x00000001) >> 0)
2741	/* Produces a ALT_RSTMGR_BRGMODRST_H2F register field value suitable for setting the register. */
2742	#define ALT_RSTMGR_BRGMODRST_H2F_SET(value) (((value) << 0) & 0x00000001)
2743
2744	/*
2745	* Field : LWHPS2FPGA Bridge - lwhps2fpga
2746	*
2747	* Resets LWHPS2FPGA Bridge
2748	*
2749	* Field Access Macros:
2750	*
2751	*/
2752	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
2753	#define ALT_RSTMGR_BRGMODRST_LWH2F_LSB 1
2754	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
2755	#define ALT_RSTMGR_BRGMODRST_LWH2F_MSB 1
2756	/* The width in bits of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
2757	#define ALT_RSTMGR_BRGMODRST_LWH2F_WIDTH 1
2758	/* The mask used to set the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */
2759	#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002
2760	/* The mask used to clear the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */
2761	#define ALT_RSTMGR_BRGMODRST_LWH2F_CLR_MSK 0xfffffffd
2762	/* The reset value of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
2763	#define ALT_RSTMGR_BRGMODRST_LWH2F_RESET 0x1
2764	/* Extracts the ALT_RSTMGR_BRGMODRST_LWH2F field value from a register. */
2765	#define ALT_RSTMGR_BRGMODRST_LWH2F_GET(value) (((value) & 0x00000002) >> 1)
2766	/* Produces a ALT_RSTMGR_BRGMODRST_LWH2F register field value suitable for setting the register. */
2767	#define ALT_RSTMGR_BRGMODRST_LWH2F_SET(value) (((value) << 1) & 0x00000002)
2768
2769	/*
2770	* Field : FPGA2HPS Bridge - fpga2hps
2771	*
2772	* Resets FPGA2HPS Bridge
2773	*
2774	* Field Access Macros:
2775	*
2776	*/
2777	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */
2778	#define ALT_RSTMGR_BRGMODRST_F2H_LSB 2
2779	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */
2780	#define ALT_RSTMGR_BRGMODRST_F2H_MSB 2
2781	/* The width in bits of the ALT_RSTMGR_BRGMODRST_F2H register field. */
2782	#define ALT_RSTMGR_BRGMODRST_F2H_WIDTH 1
2783	/* The mask used to set the ALT_RSTMGR_BRGMODRST_F2H register field value. */
2784	#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004
2785	/* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2H register field value. */
2786	#define ALT_RSTMGR_BRGMODRST_F2H_CLR_MSK 0xfffffffb
2787	/* The reset value of the ALT_RSTMGR_BRGMODRST_F2H register field. */
2788	#define ALT_RSTMGR_BRGMODRST_F2H_RESET 0x1
2789	/* Extracts the ALT_RSTMGR_BRGMODRST_F2H field value from a register. */
2790	#define ALT_RSTMGR_BRGMODRST_F2H_GET(value) (((value) & 0x00000004) >> 2)
2791	/* Produces a ALT_RSTMGR_BRGMODRST_F2H register field value suitable for setting the register. */
2792	#define ALT_RSTMGR_BRGMODRST_F2H_SET(value) (((value) << 2) & 0x00000004)
2793
2794	#ifndef __ASSEMBLY__
2795	/*
2796	* WARNING: The C register and register group struct declarations are provided for
2797	* convenience and illustrative purposes. They should, however, be used with
2798	* caution as the C language standard provides no guarantees about the alignment or
2799	* atomicity of device memory accesses. The recommended practice for writing
2800	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
2801	* alt_write_word() functions.
2802	*
2803	* The struct declaration for register ALT_RSTMGR_BRGMODRST.
2804	*/
2805	struct ALT_RSTMGR_BRGMODRST_s
2806	{
2807	uint32_t hps2fpga : 1; /* HPS2FPGA Bridge */
2808	uint32_t lwhps2fpga : 1; /* LWHPS2FPGA Bridge */
2809	uint32_t fpga2hps : 1; /* FPGA2HPS Bridge */
2810	uint32_t : 29; /* UNDEFINED */
2811	};
2812
2813	/* The typedef declaration for register ALT_RSTMGR_BRGMODRST. */
2814	typedef volatile struct ALT_RSTMGR_BRGMODRST_s ALT_RSTMGR_BRGMODRST_t;
2815	#endif /* __ASSEMBLY__ */
2816
2817	/* The byte offset of the ALT_RSTMGR_BRGMODRST register from the beginning of the component. */
2818	#define ALT_RSTMGR_BRGMODRST_OFST 0x1c
2819
2820	/*
2821	* Register : Miscellaneous Module Reset Register - miscmodrst
2822	*
2823	* The MISCMODRST register is used by software to trigger module resets (individual
2824	* module reset signals). Software explicitly asserts and de-asserts module reset
2825	* signals by writing bits in the appropriate *MODRST register. It is up to
2826	* software to ensure module reset signals are asserted for the appropriate length
2827	* of time and are de-asserted in the correct order. It is also up to software to
2828	* not assert a module reset signal that would prevent software from de-asserting
2829	* the module reset signal. For example, software should not assert the module
2830	* reset to the CPU executing the software.
2831	*
2832	* Software writes a bit to 1 to assert the module reset signal and to 0 to de-
2833	* assert the module reset signal.
2834	*
2835	* All fields are only reset by a cold reset
2836	*
2837	* Register Layout
2838	*
2839	* Bits \| Access \| Reset \| Description
2840	* :--------\|:-------\|:------\|:--------------------------------------
2841	* [0] \| RW \| 0x0 \| Boot ROM
2842	* [1] \| RW \| 0x0 \| On-chip RAM
2843	* [2] \| RW \| 0x0 \| System Manager (Cold or Warm)
2844	* [3] \| RW \| 0x0 \| System Manager (Cold-only)
2845	* [4] \| RW \| 0x0 \| FPGA Manager
2846	* [5] \| RW \| 0x0 \| ACP ID Mapper
2847	* [6] \| RW \| 0x0 \| HPS to FPGA Core (Cold or Warm)
2848	* [7] \| RW \| 0x0 \| HPS to FPGA Core (Cold-only)
2849	* [8] \| RW \| 0x0 \| nRST Pin
2850	* [9] \| RW \| 0x0 \| Timestamp
2851	* [10] \| RW \| 0x0 \| Clock Manager
2852	* [11] \| RW \| 0x0 \| Scan Manager
2853	* [12] \| RW \| 0x0 \| Freeze Controller
2854	* [13] \| RW \| 0x0 \| System/Debug
2855	* [14] \| RW \| 0x0 \| Debug
2856	* [15] \| RW \| 0x0 \| TAP Controller
2857	* [16] \| RW \| 0x0 \| SDRAM Controller Subsystem Cold Reset
2858	* [31:17] \| ??? \| 0x0 \| UNDEFINED
2859	*
2860	*/
2861	/*
2862	* Field : Boot ROM - rom
2863	*
2864	* Resets Boot ROM
2865	*
2866	* Field Access Macros:
2867	*
2868	*/
2869	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */
2870	#define ALT_RSTMGR_MISCMODRST_ROM_LSB 0
2871	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */
2872	#define ALT_RSTMGR_MISCMODRST_ROM_MSB 0
2873	/* The width in bits of the ALT_RSTMGR_MISCMODRST_ROM register field. */
2874	#define ALT_RSTMGR_MISCMODRST_ROM_WIDTH 1
2875	/* The mask used to set the ALT_RSTMGR_MISCMODRST_ROM register field value. */
2876	#define ALT_RSTMGR_MISCMODRST_ROM_SET_MSK 0x00000001
2877	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_ROM register field value. */
2878	#define ALT_RSTMGR_MISCMODRST_ROM_CLR_MSK 0xfffffffe
2879	/* The reset value of the ALT_RSTMGR_MISCMODRST_ROM register field. */
2880	#define ALT_RSTMGR_MISCMODRST_ROM_RESET 0x0
2881	/* Extracts the ALT_RSTMGR_MISCMODRST_ROM field value from a register. */
2882	#define ALT_RSTMGR_MISCMODRST_ROM_GET(value) (((value) & 0x00000001) >> 0)
2883	/* Produces a ALT_RSTMGR_MISCMODRST_ROM register field value suitable for setting the register. */
2884	#define ALT_RSTMGR_MISCMODRST_ROM_SET(value) (((value) << 0) & 0x00000001)
2885
2886	/*
2887	* Field : On-chip RAM - ocram
2888	*
2889	* Resets On-chip RAM
2890	*
2891	* Field Access Macros:
2892	*
2893	*/
2894	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
2895	#define ALT_RSTMGR_MISCMODRST_OCRAM_LSB 1
2896	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
2897	#define ALT_RSTMGR_MISCMODRST_OCRAM_MSB 1
2898	/* The width in bits of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
2899	#define ALT_RSTMGR_MISCMODRST_OCRAM_WIDTH 1
2900	/* The mask used to set the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */
2901	#define ALT_RSTMGR_MISCMODRST_OCRAM_SET_MSK 0x00000002
2902	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */
2903	#define ALT_RSTMGR_MISCMODRST_OCRAM_CLR_MSK 0xfffffffd
2904	/* The reset value of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
2905	#define ALT_RSTMGR_MISCMODRST_OCRAM_RESET 0x0
2906	/* Extracts the ALT_RSTMGR_MISCMODRST_OCRAM field value from a register. */
2907	#define ALT_RSTMGR_MISCMODRST_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
2908	/* Produces a ALT_RSTMGR_MISCMODRST_OCRAM register field value suitable for setting the register. */
2909	#define ALT_RSTMGR_MISCMODRST_OCRAM_SET(value) (((value) << 1) & 0x00000002)
2910
2911	/*
2912	* Field : System Manager (Cold or Warm) - sysmgr
2913	*
2914	* Resets logic in System Manager that doesn't differentiate between cold and warm
2915	* resets
2916	*
2917	* Field Access Macros:
2918	*
2919	*/
2920	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
2921	#define ALT_RSTMGR_MISCMODRST_SYSMGR_LSB 2
2922	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
2923	#define ALT_RSTMGR_MISCMODRST_SYSMGR_MSB 2
2924	/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
2925	#define ALT_RSTMGR_MISCMODRST_SYSMGR_WIDTH 1
2926	/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */
2927	#define ALT_RSTMGR_MISCMODRST_SYSMGR_SET_MSK 0x00000004
2928	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */
2929	#define ALT_RSTMGR_MISCMODRST_SYSMGR_CLR_MSK 0xfffffffb
2930	/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
2931	#define ALT_RSTMGR_MISCMODRST_SYSMGR_RESET 0x0
2932	/* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGR field value from a register. */
2933	#define ALT_RSTMGR_MISCMODRST_SYSMGR_GET(value) (((value) & 0x00000004) >> 2)
2934	/* Produces a ALT_RSTMGR_MISCMODRST_SYSMGR register field value suitable for setting the register. */
2935	#define ALT_RSTMGR_MISCMODRST_SYSMGR_SET(value) (((value) << 2) & 0x00000004)
2936
2937	/*
2938	* Field : System Manager (Cold-only) - sysmgrcold
2939	*
2940	* Resets logic in System Manager that is only reset by a cold reset (ignores warm
2941	* reset)
2942	*
2943	* Field Access Macros:
2944	*
2945	*/
2946	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
2947	#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_LSB 3
2948	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
2949	#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_MSB 3
2950	/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
2951	#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_WIDTH 1
2952	/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */
2953	#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET_MSK 0x00000008
2954	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */
2955	#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_CLR_MSK 0xfffffff7
2956	/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
2957	#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_RESET 0x0
2958	/* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD field value from a register. */
2959	#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_GET(value) (((value) & 0x00000008) >> 3)
2960	/* Produces a ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value suitable for setting the register. */
2961	#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET(value) (((value) << 3) & 0x00000008)
2962
2963	/*
2964	* Field : FPGA Manager - fpgamgr
2965	*
2966	* Resets FPGA Manager
2967	*
2968	* Field Access Macros:
2969	*
2970	*/
2971	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
2972	#define ALT_RSTMGR_MISCMODRST_FPGAMGR_LSB 4
2973	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
2974	#define ALT_RSTMGR_MISCMODRST_FPGAMGR_MSB 4
2975	/* The width in bits of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
2976	#define ALT_RSTMGR_MISCMODRST_FPGAMGR_WIDTH 1
2977	/* The mask used to set the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */
2978	#define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET_MSK 0x00000010
2979	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */
2980	#define ALT_RSTMGR_MISCMODRST_FPGAMGR_CLR_MSK 0xffffffef
2981	/* The reset value of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
2982	#define ALT_RSTMGR_MISCMODRST_FPGAMGR_RESET 0x0
2983	/* Extracts the ALT_RSTMGR_MISCMODRST_FPGAMGR field value from a register. */
2984	#define ALT_RSTMGR_MISCMODRST_FPGAMGR_GET(value) (((value) & 0x00000010) >> 4)
2985	/* Produces a ALT_RSTMGR_MISCMODRST_FPGAMGR register field value suitable for setting the register. */
2986	#define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET(value) (((value) << 4) & 0x00000010)
2987
2988	/*
2989	* Field : ACP ID Mapper - acpidmap
2990	*
2991	* Resets ACP ID Mapper
2992	*
2993	* Field Access Macros:
2994	*
2995	*/
2996	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
2997	#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_LSB 5
2998	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
2999	#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_MSB 5
3000	/* The width in bits of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
3001	#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_WIDTH 1
3002	/* The mask used to set the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */
3003	#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET_MSK 0x00000020
3004	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */
3005	#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_CLR_MSK 0xffffffdf
3006	/* The reset value of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
3007	#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_RESET 0x0
3008	/* Extracts the ALT_RSTMGR_MISCMODRST_ACPIDMAP field value from a register. */
3009	#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_GET(value) (((value) & 0x00000020) >> 5)
3010	/* Produces a ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value suitable for setting the register. */
3011	#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET(value) (((value) << 5) & 0x00000020)
3012
3013	/*
3014	* Field : HPS to FPGA Core (Cold or Warm) - s2f
3015	*
3016	* Resets logic in FPGA core that doesn't differentiate between HPS cold and warm
3017	* resets (h2f_rst_n = 1)
3018	*
3019	* Field Access Macros:
3020	*
3021	*/
3022	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */
3023	#define ALT_RSTMGR_MISCMODRST_S2F_LSB 6
3024	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */
3025	#define ALT_RSTMGR_MISCMODRST_S2F_MSB 6
3026	/* The width in bits of the ALT_RSTMGR_MISCMODRST_S2F register field. */
3027	#define ALT_RSTMGR_MISCMODRST_S2F_WIDTH 1
3028	/* The mask used to set the ALT_RSTMGR_MISCMODRST_S2F register field value. */
3029	#define ALT_RSTMGR_MISCMODRST_S2F_SET_MSK 0x00000040
3030	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2F register field value. */
3031	#define ALT_RSTMGR_MISCMODRST_S2F_CLR_MSK 0xffffffbf
3032	/* The reset value of the ALT_RSTMGR_MISCMODRST_S2F register field. */
3033	#define ALT_RSTMGR_MISCMODRST_S2F_RESET 0x0
3034	/* Extracts the ALT_RSTMGR_MISCMODRST_S2F field value from a register. */
3035	#define ALT_RSTMGR_MISCMODRST_S2F_GET(value) (((value) & 0x00000040) >> 6)
3036	/* Produces a ALT_RSTMGR_MISCMODRST_S2F register field value suitable for setting the register. */
3037	#define ALT_RSTMGR_MISCMODRST_S2F_SET(value) (((value) << 6) & 0x00000040)
3038
3039	/*
3040	* Field : HPS to FPGA Core (Cold-only) - s2fcold
3041	*
3042	* Resets logic in FPGA core that is only reset by a cold reset (ignores warm
3043	* reset) (h2f_cold_rst_n = 1)
3044	*
3045	* Field Access Macros:
3046	*
3047	*/
3048	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
3049	#define ALT_RSTMGR_MISCMODRST_S2FCOLD_LSB 7
3050	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
3051	#define ALT_RSTMGR_MISCMODRST_S2FCOLD_MSB 7
3052	/* The width in bits of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
3053	#define ALT_RSTMGR_MISCMODRST_S2FCOLD_WIDTH 1
3054	/* The mask used to set the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */
3055	#define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET_MSK 0x00000080
3056	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */
3057	#define ALT_RSTMGR_MISCMODRST_S2FCOLD_CLR_MSK 0xffffff7f
3058	/* The reset value of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
3059	#define ALT_RSTMGR_MISCMODRST_S2FCOLD_RESET 0x0
3060	/* Extracts the ALT_RSTMGR_MISCMODRST_S2FCOLD field value from a register. */
3061	#define ALT_RSTMGR_MISCMODRST_S2FCOLD_GET(value) (((value) & 0x00000080) >> 7)
3062	/* Produces a ALT_RSTMGR_MISCMODRST_S2FCOLD register field value suitable for setting the register. */
3063	#define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET(value) (((value) << 7) & 0x00000080)
3064
3065	/*
3066	* Field : nRST Pin - nrstpin
3067	*
3068	* Pulls nRST pin low
3069	*
3070	* Field Access Macros:
3071	*
3072	*/
3073	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
3074	#define ALT_RSTMGR_MISCMODRST_NRSTPIN_LSB 8
3075	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
3076	#define ALT_RSTMGR_MISCMODRST_NRSTPIN_MSB 8
3077	/* The width in bits of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
3078	#define ALT_RSTMGR_MISCMODRST_NRSTPIN_WIDTH 1
3079	/* The mask used to set the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */
3080	#define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET_MSK 0x00000100
3081	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */
3082	#define ALT_RSTMGR_MISCMODRST_NRSTPIN_CLR_MSK 0xfffffeff
3083	/* The reset value of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
3084	#define ALT_RSTMGR_MISCMODRST_NRSTPIN_RESET 0x0
3085	/* Extracts the ALT_RSTMGR_MISCMODRST_NRSTPIN field value from a register. */
3086	#define ALT_RSTMGR_MISCMODRST_NRSTPIN_GET(value) (((value) & 0x00000100) >> 8)
3087	/* Produces a ALT_RSTMGR_MISCMODRST_NRSTPIN register field value suitable for setting the register. */
3088	#define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET(value) (((value) << 8) & 0x00000100)
3089
3090	/*
3091	* Field : Timestamp - timestampcold
3092	*
3093	* Resets debug timestamp to 0 (cold reset only)
3094	*
3095	* Field Access Macros:
3096	*
3097	*/
3098	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
3099	#define ALT_RSTMGR_MISCMODRST_TSCOLD_LSB 9
3100	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
3101	#define ALT_RSTMGR_MISCMODRST_TSCOLD_MSB 9
3102	/* The width in bits of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
3103	#define ALT_RSTMGR_MISCMODRST_TSCOLD_WIDTH 1
3104	/* The mask used to set the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */
3105	#define ALT_RSTMGR_MISCMODRST_TSCOLD_SET_MSK 0x00000200
3106	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */
3107	#define ALT_RSTMGR_MISCMODRST_TSCOLD_CLR_MSK 0xfffffdff
3108	/* The reset value of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
3109	#define ALT_RSTMGR_MISCMODRST_TSCOLD_RESET 0x0
3110	/* Extracts the ALT_RSTMGR_MISCMODRST_TSCOLD field value from a register. */
3111	#define ALT_RSTMGR_MISCMODRST_TSCOLD_GET(value) (((value) & 0x00000200) >> 9)
3112	/* Produces a ALT_RSTMGR_MISCMODRST_TSCOLD register field value suitable for setting the register. */
3113	#define ALT_RSTMGR_MISCMODRST_TSCOLD_SET(value) (((value) << 9) & 0x00000200)
3114
3115	/*
3116	* Field : Clock Manager - clkmgrcold
3117	*
3118	* Resets Clock Manager (cold reset only)
3119	*
3120	* Field Access Macros:
3121	*
3122	*/
3123	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
3124	#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_LSB 10
3125	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
3126	#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_MSB 10
3127	/* The width in bits of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
3128	#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_WIDTH 1
3129	/* The mask used to set the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */
3130	#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET_MSK 0x00000400
3131	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */
3132	#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_CLR_MSK 0xfffffbff
3133	/* The reset value of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
3134	#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_RESET 0x0
3135	/* Extracts the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD field value from a register. */
3136	#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_GET(value) (((value) & 0x00000400) >> 10)
3137	/* Produces a ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value suitable for setting the register. */
3138	#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET(value) (((value) << 10) & 0x00000400)
3139
3140	/*
3141	* Field : Scan Manager - scanmgr
3142	*
3143	* Resets Scan Manager
3144	*
3145	* Field Access Macros:
3146	*
3147	*/
3148	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
3149	#define ALT_RSTMGR_MISCMODRST_SCANMGR_LSB 11
3150	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
3151	#define ALT_RSTMGR_MISCMODRST_SCANMGR_MSB 11
3152	/* The width in bits of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
3153	#define ALT_RSTMGR_MISCMODRST_SCANMGR_WIDTH 1
3154	/* The mask used to set the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */
3155	#define ALT_RSTMGR_MISCMODRST_SCANMGR_SET_MSK 0x00000800
3156	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */
3157	#define ALT_RSTMGR_MISCMODRST_SCANMGR_CLR_MSK 0xfffff7ff
3158	/* The reset value of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
3159	#define ALT_RSTMGR_MISCMODRST_SCANMGR_RESET 0x0
3160	/* Extracts the ALT_RSTMGR_MISCMODRST_SCANMGR field value from a register. */
3161	#define ALT_RSTMGR_MISCMODRST_SCANMGR_GET(value) (((value) & 0x00000800) >> 11)
3162	/* Produces a ALT_RSTMGR_MISCMODRST_SCANMGR register field value suitable for setting the register. */
3163	#define ALT_RSTMGR_MISCMODRST_SCANMGR_SET(value) (((value) << 11) & 0x00000800)
3164
3165	/*
3166	* Field : Freeze Controller - frzctrlcold
3167	*
3168	* Resets Freeze Controller in System Manager (cold reset only)
3169	*
3170	* Field Access Macros:
3171	*
3172	*/
3173	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */
3174	#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_LSB 12
3175	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */
3176	#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_MSB 12
3177	/* The width in bits of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */
3178	#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_WIDTH 1
3179	/* The mask used to set the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value. */
3180	#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET_MSK 0x00001000
3181	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value. */
3182	#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_CLR_MSK 0xffffefff
3183	/* The reset value of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */
3184	#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_RESET 0x0
3185	/* Extracts the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD field value from a register. */
3186	#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_GET(value) (((value) & 0x00001000) >> 12)
3187	/* Produces a ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value suitable for setting the register. */
3188	#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET(value) (((value) << 12) & 0x00001000)
3189
3190	/*
3191	* Field : System/Debug - sysdbg
3192	*
3193	* Resets logic that spans the system and debug domains.
3194	*
3195	* Field Access Macros:
3196	*
3197	*/
3198	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */
3199	#define ALT_RSTMGR_MISCMODRST_SYSDBG_LSB 13
3200	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */
3201	#define ALT_RSTMGR_MISCMODRST_SYSDBG_MSB 13
3202	/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */
3203	#define ALT_RSTMGR_MISCMODRST_SYSDBG_WIDTH 1
3204	/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSDBG register field value. */
3205	#define ALT_RSTMGR_MISCMODRST_SYSDBG_SET_MSK 0x00002000
3206	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSDBG register field value. */
3207	#define ALT_RSTMGR_MISCMODRST_SYSDBG_CLR_MSK 0xffffdfff
3208	/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */
3209	#define ALT_RSTMGR_MISCMODRST_SYSDBG_RESET 0x0
3210	/* Extracts the ALT_RSTMGR_MISCMODRST_SYSDBG field value from a register. */
3211	#define ALT_RSTMGR_MISCMODRST_SYSDBG_GET(value) (((value) & 0x00002000) >> 13)
3212	/* Produces a ALT_RSTMGR_MISCMODRST_SYSDBG register field value suitable for setting the register. */
3213	#define ALT_RSTMGR_MISCMODRST_SYSDBG_SET(value) (((value) << 13) & 0x00002000)
3214
3215	/*
3216	* Field : Debug - dbg
3217	*
3218	* Resets logic located only in the debug domain.
3219	*
3220	* Field Access Macros:
3221	*
3222	*/
3223	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_DBG register field. */
3224	#define ALT_RSTMGR_MISCMODRST_DBG_LSB 14
3225	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_DBG register field. */
3226	#define ALT_RSTMGR_MISCMODRST_DBG_MSB 14
3227	/* The width in bits of the ALT_RSTMGR_MISCMODRST_DBG register field. */
3228	#define ALT_RSTMGR_MISCMODRST_DBG_WIDTH 1
3229	/* The mask used to set the ALT_RSTMGR_MISCMODRST_DBG register field value. */
3230	#define ALT_RSTMGR_MISCMODRST_DBG_SET_MSK 0x00004000
3231	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_DBG register field value. */
3232	#define ALT_RSTMGR_MISCMODRST_DBG_CLR_MSK 0xffffbfff
3233	/* The reset value of the ALT_RSTMGR_MISCMODRST_DBG register field. */
3234	#define ALT_RSTMGR_MISCMODRST_DBG_RESET 0x0
3235	/* Extracts the ALT_RSTMGR_MISCMODRST_DBG field value from a register. */
3236	#define ALT_RSTMGR_MISCMODRST_DBG_GET(value) (((value) & 0x00004000) >> 14)
3237	/* Produces a ALT_RSTMGR_MISCMODRST_DBG register field value suitable for setting the register. */
3238	#define ALT_RSTMGR_MISCMODRST_DBG_SET(value) (((value) << 14) & 0x00004000)
3239
3240	/*
3241	* Field : TAP Controller - tapcold
3242	*
3243	* Resets portion of DAP JTAG TAP controller no reset by a debug probe reset (i.e.
3244	* nTRST pin). Cold reset only.
3245	*
3246	* Field Access Macros:
3247	*
3248	*/
3249	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */
3250	#define ALT_RSTMGR_MISCMODRST_TAPCOLD_LSB 15
3251	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */
3252	#define ALT_RSTMGR_MISCMODRST_TAPCOLD_MSB 15
3253	/* The width in bits of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */
3254	#define ALT_RSTMGR_MISCMODRST_TAPCOLD_WIDTH 1
3255	/* The mask used to set the ALT_RSTMGR_MISCMODRST_TAPCOLD register field value. */
3256	#define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET_MSK 0x00008000
3257	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_TAPCOLD register field value. */
3258	#define ALT_RSTMGR_MISCMODRST_TAPCOLD_CLR_MSK 0xffff7fff
3259	/* The reset value of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */
3260	#define ALT_RSTMGR_MISCMODRST_TAPCOLD_RESET 0x0
3261	/* Extracts the ALT_RSTMGR_MISCMODRST_TAPCOLD field value from a register. */
3262	#define ALT_RSTMGR_MISCMODRST_TAPCOLD_GET(value) (((value) & 0x00008000) >> 15)
3263	/* Produces a ALT_RSTMGR_MISCMODRST_TAPCOLD register field value suitable for setting the register. */
3264	#define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET(value) (((value) << 15) & 0x00008000)
3265
3266	/*
3267	* Field : SDRAM Controller Subsystem Cold Reset - sdrcold
3268	*
3269	* Resets logic in SDRAM Controller Subsystem affected only by a cold reset.
3270	*
3271	* Field Access Macros:
3272	*
3273	*/
3274	/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */
3275	#define ALT_RSTMGR_MISCMODRST_SDRCOLD_LSB 16
3276	/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */
3277	#define ALT_RSTMGR_MISCMODRST_SDRCOLD_MSB 16
3278	/* The width in bits of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */
3279	#define ALT_RSTMGR_MISCMODRST_SDRCOLD_WIDTH 1
3280	/* The mask used to set the ALT_RSTMGR_MISCMODRST_SDRCOLD register field value. */
3281	#define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET_MSK 0x00010000
3282	/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SDRCOLD register field value. */
3283	#define ALT_RSTMGR_MISCMODRST_SDRCOLD_CLR_MSK 0xfffeffff
3284	/* The reset value of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */
3285	#define ALT_RSTMGR_MISCMODRST_SDRCOLD_RESET 0x0
3286	/* Extracts the ALT_RSTMGR_MISCMODRST_SDRCOLD field value from a register. */
3287	#define ALT_RSTMGR_MISCMODRST_SDRCOLD_GET(value) (((value) & 0x00010000) >> 16)
3288	/* Produces a ALT_RSTMGR_MISCMODRST_SDRCOLD register field value suitable for setting the register. */
3289	#define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET(value) (((value) << 16) & 0x00010000)
3290
3291	#ifndef __ASSEMBLY__
3292	/*
3293	* WARNING: The C register and register group struct declarations are provided for
3294	* convenience and illustrative purposes. They should, however, be used with
3295	* caution as the C language standard provides no guarantees about the alignment or
3296	* atomicity of device memory accesses. The recommended practice for writing
3297	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
3298	* alt_write_word() functions.
3299	*
3300	* The struct declaration for register ALT_RSTMGR_MISCMODRST.
3301	*/
3302	struct ALT_RSTMGR_MISCMODRST_s
3303	{
3304	uint32_t rom : 1; /* Boot ROM */
3305	uint32_t ocram : 1; /* On-chip RAM */
3306	uint32_t sysmgr : 1; /* System Manager (Cold or Warm) */
3307	uint32_t sysmgrcold : 1; /* System Manager (Cold-only) */
3308	uint32_t fpgamgr : 1; /* FPGA Manager */
3309	uint32_t acpidmap : 1; /* ACP ID Mapper */
3310	uint32_t s2f : 1; /* HPS to FPGA Core (Cold or Warm) */
3311	uint32_t s2fcold : 1; /* HPS to FPGA Core (Cold-only) */
3312	uint32_t nrstpin : 1; /* nRST Pin */
3313	uint32_t timestampcold : 1; /* Timestamp */
3314	uint32_t clkmgrcold : 1; /* Clock Manager */
3315	uint32_t scanmgr : 1; /* Scan Manager */
3316	uint32_t frzctrlcold : 1; /* Freeze Controller */
3317	uint32_t sysdbg : 1; /* System/Debug */
3318	uint32_t dbg : 1; /* Debug */
3319	uint32_t tapcold : 1; /* TAP Controller */
3320	uint32_t sdrcold : 1; /* SDRAM Controller Subsystem Cold Reset */
3321	uint32_t : 15; /* UNDEFINED */
3322	};
3323
3324	/* The typedef declaration for register ALT_RSTMGR_MISCMODRST. */
3325	typedef volatile struct ALT_RSTMGR_MISCMODRST_s ALT_RSTMGR_MISCMODRST_t;
3326	#endif /* __ASSEMBLY__ */
3327
3328	/* The byte offset of the ALT_RSTMGR_MISCMODRST register from the beginning of the component. */
3329	#define ALT_RSTMGR_MISCMODRST_OFST 0x20
3330
3331	#ifndef __ASSEMBLY__
3332	/*
3333	* WARNING: The C register and register group struct declarations are provided for
3334	* convenience and illustrative purposes. They should, however, be used with
3335	* caution as the C language standard provides no guarantees about the alignment or
3336	* atomicity of device memory accesses. The recommended practice for writing
3337	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
3338	* alt_write_word() functions.
3339	*
3340	* The struct declaration for register group ALT_RSTMGR.
3341	*/
3342	struct ALT_RSTMGR_s
3343	{
3344	volatile ALT_RSTMGR_STAT_t stat; /* ALT_RSTMGR_STAT */
3345	volatile ALT_RSTMGR_CTL_t ctrl; /* ALT_RSTMGR_CTL */
3346	volatile ALT_RSTMGR_COUNTS_t counts; /* ALT_RSTMGR_COUNTS */
3347	volatile uint32_t _pad_0xc_0xf; /* UNDEFINED */
3348	volatile ALT_RSTMGR_MPUMODRST_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */
3349	volatile ALT_RSTMGR_PERMODRST_t permodrst; /* ALT_RSTMGR_PERMODRST */
3350	volatile ALT_RSTMGR_PER2MODRST_t per2modrst; /* ALT_RSTMGR_PER2MODRST */
3351	volatile ALT_RSTMGR_BRGMODRST_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */
3352	volatile ALT_RSTMGR_MISCMODRST_t miscmodrst; /* ALT_RSTMGR_MISCMODRST */
3353	volatile uint32_t _pad_0x24_0x100[55]; /* UNDEFINED */
3354	};
3355
3356	/* The typedef declaration for register group ALT_RSTMGR. */
3357	typedef volatile struct ALT_RSTMGR_s ALT_RSTMGR_t;
3358	/* The struct declaration for the raw register contents of register group ALT_RSTMGR. */
3359	struct ALT_RSTMGR_raw_s
3360	{
3361	volatile uint32_t stat; /* ALT_RSTMGR_STAT */
3362	volatile uint32_t ctrl; /* ALT_RSTMGR_CTL */
3363	volatile uint32_t counts; /* ALT_RSTMGR_COUNTS */
3364	volatile uint32_t _pad_0xc_0xf; /* UNDEFINED */
3365	volatile uint32_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */
3366	volatile uint32_t permodrst; /* ALT_RSTMGR_PERMODRST */
3367	volatile uint32_t per2modrst; /* ALT_RSTMGR_PER2MODRST */
3368	volatile uint32_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */
3369	volatile uint32_t miscmodrst; /* ALT_RSTMGR_MISCMODRST */
3370	volatile uint32_t _pad_0x24_0x100[55]; /* UNDEFINED */
3371	};
3372
3373	/* The typedef declaration for the raw register contents of register group ALT_RSTMGR. */
3374	typedef volatile struct ALT_RSTMGR_raw_s ALT_RSTMGR_raw_t;
3375	#endif /* __ASSEMBLY__ */
3376
3377
3378	#ifdef __cplusplus
3379	}
3380	#endif /* __cplusplus */
3381	#endif /* __ALTERA_ALT_RSTMGR_H__ */
3382

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source: rtems/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h @ 2afb22b

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