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alt_gpio.h @ 2afb22b

Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

The make preinstall step itself needs time and disk space.

Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.

There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.

The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.

An introduction of a new build system is difficult.

Include paths specified by the -B option are system headers. This may suppress warnings.

The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

cpukit/include

cpukit/score/cpu/@RTEMS_CPU@/include

cpukit/libnetworking

The new BSP include directories are:

bsps/include

bsps/@RTEMS_CPU@/include

bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

Property mode set to 100644

File size: 89.1 KB

Line
1	/*******************************************************************************
2	* *
3	* Copyright 2013 Altera Corporation. All Rights Reserved. *
4	* *
5	* Redistribution and use in source and binary forms, with or without *
6	* modification, are permitted provided that the following conditions are met: *
7	* *
8	* 1. Redistributions of source code must retain the above copyright notice, *
9	* this list of conditions and the following disclaimer. *
10	* *
11	* 2. Redistributions in binary form must reproduce the above copyright notice, *
12	* this list of conditions and the following disclaimer in the documentation *
13	* and/or other materials provided with the distribution. *
14	* *
15	* 3. The name of the author may not be used to endorse or promote products *
16	* derived from this software without specific prior written permission. *
17	* *
18	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
20	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
21	* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
22	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
23	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
24	* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
25	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
26	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
27	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
28	* *
29	*******************************************************************************/
30
31	/* Altera - ALT_GPIO */
32
33	#ifndef __ALTERA_ALT_GPIO_H__
34	#define __ALTERA_ALT_GPIO_H__
35
36	#ifdef __cplusplus
37	extern "C"
38	{
39	#endif /* __cplusplus */
40
41	/*
42	* Component : GPIO Module - ALT_GPIO
43	* GPIO Module
44	*
45	* Registers in the GPIO module
46	*
47	*/
48	/*
49	* Register : Port A Data Register - gpio_swporta_dr
50	*
51	* This GPIO Data register is used to input or output data
52	*
53	* Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
54	*
55	* Register Layout
56	*
57	* Bits \| Access \| Reset \| Description
58	* :--------\|:-------\|:------\|:------------
59	* [28:0] \| RW \| 0x0 \| Port A Data
60	* [31:29] \| ??? \| 0x0 \| UNDEFINED
61	*
62	*/
63	/*
64	* Field : Port A Data - gpio_swporta_dr
65	*
66	* Values written to this register are output on the I/O signals of the GPIO Data
67	* Register, if the corresponding data direction bits for GPIO Data Direction Field
68	* are set to Output mode. The value read back is equal to the last value written
69	* to this register.
70	*
71	* Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
72	*
73	* Field Access Macros:
74	*
75	*/
76	/* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
77	#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_LSB 0
78	/* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
79	#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_MSB 28
80	/* The width in bits of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
81	#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_WIDTH 29
82	/* The mask used to set the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */
83	#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET_MSK 0x1fffffff
84	/* The mask used to clear the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */
85	#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_CLR_MSK 0xe0000000
86	/* The reset value of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
87	#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_RESET 0x0
88	/* Extracts the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR field value from a register. */
89	#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_GET(value) (((value) & 0x1fffffff) >> 0)
90	/* Produces a ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value suitable for setting the register. */
91	#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET(value) (((value) << 0) & 0x1fffffff)
92
93	#ifndef __ASSEMBLY__
94	/*
95	* WARNING: The C register and register group struct declarations are provided for
96	* convenience and illustrative purposes. They should, however, be used with
97	* caution as the C language standard provides no guarantees about the alignment or
98	* atomicity of device memory accesses. The recommended practice for writing
99	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
100	* alt_write_word() functions.
101	*
102	* The struct declaration for register ALT_GPIO_SWPORTA_DR.
103	*/
104	struct ALT_GPIO_SWPORTA_DR_s
105	{
106	uint32_t gpio_swporta_dr : 29; /* Port A Data */
107	uint32_t : 3; /* UNDEFINED */
108	};
109
110	/* The typedef declaration for register ALT_GPIO_SWPORTA_DR. */
111	typedef volatile struct ALT_GPIO_SWPORTA_DR_s ALT_GPIO_SWPORTA_DR_t;
112	#endif /* __ASSEMBLY__ */
113
114	/* The byte offset of the ALT_GPIO_SWPORTA_DR register from the beginning of the component. */
115	#define ALT_GPIO_SWPORTA_DR_OFST 0x0
116	/* The address of the ALT_GPIO_SWPORTA_DR register. */
117	#define ALT_GPIO_SWPORTA_DR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_SWPORTA_DR_OFST))
118
119	/*
120	* Register : Port A Data Direction Register - gpio_swporta_ddr
121	*
122	* This register establishes the direction of each corresponding GPIO Data Field
123	* Bit.
124	*
125	* Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
126	*
127	* Register Layout
128	*
129	* Bits \| Access \| Reset \| Description
130	* :--------\|:-------\|:------\|:----------------------------
131	* [28:0] \| RW \| 0x0 \| Port A Data Direction Field
132	* [31:29] \| ??? \| 0x0 \| UNDEFINED
133	*
134	*/
135	/*
136	* Field : Port A Data Direction Field - gpio_swporta_ddr
137	*
138	* Values written to this register independently control the direction of the
139	* corresponding data bit in the Port A Data Register.
140	*
141	* Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
142	*
143	* Field Enumeration Values:
144	*
145	* Enum \| Value \| Description
146	* :--------------------------------------------\|:------\|:-----------------
147	* ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN \| 0x0 \| Input Direction
148	* ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT \| 0x1 \| Output Direction
149	*
150	* Field Access Macros:
151	*
152	*/
153	/*
154	* Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR
155	*
156	* Input Direction
157	*/
158	#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN 0x0
159	/*
160	* Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR
161	*
162	* Output Direction
163	*/
164	#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT 0x1
165
166	/* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
167	#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_LSB 0
168	/* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
169	#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_MSB 28
170	/* The width in bits of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
171	#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_WIDTH 29
172	/* The mask used to set the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */
173	#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET_MSK 0x1fffffff
174	/* The mask used to clear the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */
175	#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_CLR_MSK 0xe0000000
176	/* The reset value of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
177	#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_RESET 0x0
178	/* Extracts the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR field value from a register. */
179	#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_GET(value) (((value) & 0x1fffffff) >> 0)
180	/* Produces a ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value suitable for setting the register. */
181	#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET(value) (((value) << 0) & 0x1fffffff)
182
183	#ifndef __ASSEMBLY__
184	/*
185	* WARNING: The C register and register group struct declarations are provided for
186	* convenience and illustrative purposes. They should, however, be used with
187	* caution as the C language standard provides no guarantees about the alignment or
188	* atomicity of device memory accesses. The recommended practice for writing
189	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
190	* alt_write_word() functions.
191	*
192	* The struct declaration for register ALT_GPIO_SWPORTA_DDR.
193	*/
194	struct ALT_GPIO_SWPORTA_DDR_s
195	{
196	uint32_t gpio_swporta_ddr : 29; /* Port A Data Direction Field */
197	uint32_t : 3; /* UNDEFINED */
198	};
199
200	/* The typedef declaration for register ALT_GPIO_SWPORTA_DDR. */
201	typedef volatile struct ALT_GPIO_SWPORTA_DDR_s ALT_GPIO_SWPORTA_DDR_t;
202	#endif /* __ASSEMBLY__ */
203
204	/* The byte offset of the ALT_GPIO_SWPORTA_DDR register from the beginning of the component. */
205	#define ALT_GPIO_SWPORTA_DDR_OFST 0x4
206	/* The address of the ALT_GPIO_SWPORTA_DDR register. */
207	#define ALT_GPIO_SWPORTA_DDR_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_SWPORTA_DDR_OFST))
208
209	/*
210	* Register : Interrupt Enable Register - gpio_inten
211	*
212	* The Interrupt enable register allows interrupts for each bit of the Port A data
213	* register.
214	*
215	* Register Layout
216	*
217	* Bits \| Access \| Reset \| Description
218	* :--------\|:-------\|:------\|:-----------------------
219	* [28:0] \| RW \| 0x0 \| Interrupt Enable Field
220	* [31:29] \| ??? \| 0x0 \| UNDEFINED
221	*
222	*/
223	/*
224	* Field : Interrupt Enable Field - gpio_inten
225	*
226	* Allows each bit of Port A Data Register to be configured for interrupt
227	* capability. Interrupts are disabled on the corresponding bits of Port A Data
228	* Register if the corresponding data direction register is set to Output.
229	*
230	* Field Enumeration Values:
231	*
232	* Enum \| Value \| Description
233	* :--------------------------------\|:------\|:----------------------------
234	* ALT_GPIO_INTEN_GPIO_INTEN_E_DIS \| 0x0 \| Disable Interrupt on Port A
235	* ALT_GPIO_INTEN_GPIO_INTEN_E_EN \| 0x1 \| Enable Interrupt on Port A
236	*
237	* Field Access Macros:
238	*
239	*/
240	/*
241	* Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN
242	*
243	* Disable Interrupt on Port A
244	*/
245	#define ALT_GPIO_INTEN_GPIO_INTEN_E_DIS 0x0
246	/*
247	* Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN
248	*
249	* Enable Interrupt on Port A
250	*/
251	#define ALT_GPIO_INTEN_GPIO_INTEN_E_EN 0x1
252
253	/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
254	#define ALT_GPIO_INTEN_GPIO_INTEN_LSB 0
255	/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
256	#define ALT_GPIO_INTEN_GPIO_INTEN_MSB 28
257	/* The width in bits of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
258	#define ALT_GPIO_INTEN_GPIO_INTEN_WIDTH 29
259	/* The mask used to set the ALT_GPIO_INTEN_GPIO_INTEN register field value. */
260	#define ALT_GPIO_INTEN_GPIO_INTEN_SET_MSK 0x1fffffff
261	/* The mask used to clear the ALT_GPIO_INTEN_GPIO_INTEN register field value. */
262	#define ALT_GPIO_INTEN_GPIO_INTEN_CLR_MSK 0xe0000000
263	/* The reset value of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
264	#define ALT_GPIO_INTEN_GPIO_INTEN_RESET 0x0
265	/* Extracts the ALT_GPIO_INTEN_GPIO_INTEN field value from a register. */
266	#define ALT_GPIO_INTEN_GPIO_INTEN_GET(value) (((value) & 0x1fffffff) >> 0)
267	/* Produces a ALT_GPIO_INTEN_GPIO_INTEN register field value suitable for setting the register. */
268	#define ALT_GPIO_INTEN_GPIO_INTEN_SET(value) (((value) << 0) & 0x1fffffff)
269
270	#ifndef __ASSEMBLY__
271	/*
272	* WARNING: The C register and register group struct declarations are provided for
273	* convenience and illustrative purposes. They should, however, be used with
274	* caution as the C language standard provides no guarantees about the alignment or
275	* atomicity of device memory accesses. The recommended practice for writing
276	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
277	* alt_write_word() functions.
278	*
279	* The struct declaration for register ALT_GPIO_INTEN.
280	*/
281	struct ALT_GPIO_INTEN_s
282	{
283	uint32_t gpio_inten : 29; /* Interrupt Enable Field */
284	uint32_t : 3; /* UNDEFINED */
285	};
286
287	/* The typedef declaration for register ALT_GPIO_INTEN. */
288	typedef volatile struct ALT_GPIO_INTEN_s ALT_GPIO_INTEN_t;
289	#endif /* __ASSEMBLY__ */
290
291	/* The byte offset of the ALT_GPIO_INTEN register from the beginning of the component. */
292	#define ALT_GPIO_INTEN_OFST 0x30
293	/* The address of the ALT_GPIO_INTEN register. */
294	#define ALT_GPIO_INTEN_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_INTEN_OFST))
295
296	/*
297	* Register : Interrupt Mask Register - gpio_intmask
298	*
299	* Controls which pins cause interrupts on Port A Data Register inputs.
300	*
301	* Register Layout
302	*
303	* Bits \| Access \| Reset \| Description
304	* :--------\|:-------\|:------\|:---------------------
305	* [28:0] \| RW \| 0x0 \| Interrupt Mask Field
306	* [31:29] \| ??? \| 0x0 \| UNDEFINED
307	*
308	*/
309	/*
310	* Field : Interrupt Mask Field - gpio_intmask
311	*
312	* Controls whether an interrupt on Port A Data Register can generate an interrupt
313	* to the interrupt controller by not masking it. The unmasked status can be read
314	* as well as the resultant status after masking.
315	*
316	* Field Enumeration Values:
317	*
318	* Enum \| Value \| Description
319	* :----------------------------------\|:------\|:----------------------------
320	* ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS \| 0x0 \| Interrupt bits are unmasked
321	* ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN \| 0x1 \| Mask Interrupt
322	*
323	* Field Access Macros:
324	*
325	*/
326	/*
327	* Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK
328	*
329	* Interrupt bits are unmasked
330	*/
331	#define ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS 0x0
332	/*
333	* Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK
334	*
335	* Mask Interrupt
336	*/
337	#define ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN 0x1
338
339	/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
340	#define ALT_GPIO_INTMSK_GPIO_INTMSK_LSB 0
341	/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
342	#define ALT_GPIO_INTMSK_GPIO_INTMSK_MSB 28
343	/* The width in bits of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
344	#define ALT_GPIO_INTMSK_GPIO_INTMSK_WIDTH 29
345	/* The mask used to set the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */
346	#define ALT_GPIO_INTMSK_GPIO_INTMSK_SET_MSK 0x1fffffff
347	/* The mask used to clear the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */
348	#define ALT_GPIO_INTMSK_GPIO_INTMSK_CLR_MSK 0xe0000000
349	/* The reset value of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
350	#define ALT_GPIO_INTMSK_GPIO_INTMSK_RESET 0x0
351	/* Extracts the ALT_GPIO_INTMSK_GPIO_INTMSK field value from a register. */
352	#define ALT_GPIO_INTMSK_GPIO_INTMSK_GET(value) (((value) & 0x1fffffff) >> 0)
353	/* Produces a ALT_GPIO_INTMSK_GPIO_INTMSK register field value suitable for setting the register. */
354	#define ALT_GPIO_INTMSK_GPIO_INTMSK_SET(value) (((value) << 0) & 0x1fffffff)
355
356	#ifndef __ASSEMBLY__
357	/*
358	* WARNING: The C register and register group struct declarations are provided for
359	* convenience and illustrative purposes. They should, however, be used with
360	* caution as the C language standard provides no guarantees about the alignment or
361	* atomicity of device memory accesses. The recommended practice for writing
362	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
363	* alt_write_word() functions.
364	*
365	* The struct declaration for register ALT_GPIO_INTMSK.
366	*/
367	struct ALT_GPIO_INTMSK_s
368	{
369	uint32_t gpio_intmask : 29; /* Interrupt Mask Field */
370	uint32_t : 3; /* UNDEFINED */
371	};
372
373	/* The typedef declaration for register ALT_GPIO_INTMSK. */
374	typedef volatile struct ALT_GPIO_INTMSK_s ALT_GPIO_INTMSK_t;
375	#endif /* __ASSEMBLY__ */
376
377	/* The byte offset of the ALT_GPIO_INTMSK register from the beginning of the component. */
378	#define ALT_GPIO_INTMSK_OFST 0x34
379	/* The address of the ALT_GPIO_INTMSK register. */
380	#define ALT_GPIO_INTMSK_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_INTMSK_OFST))
381
382	/*
383	* Register : Interrupt Level Register - gpio_inttype_level
384	*
385	* The interrupt level register defines the type of interrupt (edge or level).
386	*
387	* Register Layout
388	*
389	* Bits \| Access \| Reset \| Description
390	* :--------\|:-------\|:------\|:----------------------
391	* [28:0] \| RW \| 0x0 \| Interrupt Level Field
392	* [31:29] \| ??? \| 0x0 \| UNDEFINED
393	*
394	*/
395	/*
396	* Field : Interrupt Level Field - gpio_inttype_level
397	*
398	* This field controls the type of interrupt that can occur on the Port A Data
399	* Register.
400	*
401	* Field Enumeration Values:
402	*
403	* Enum \| Value \| Description
404	* :--------------------------------------------------\|:------\|:----------------
405	* ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL \| 0x0 \| Level-sensitive
406	* ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE \| 0x1 \| Edge-sensitive
407	*
408	* Field Access Macros:
409	*
410	*/
411	/*
412	* Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL
413	*
414	* Level-sensitive
415	*/
416	#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL 0x0
417	/*
418	* Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL
419	*
420	* Edge-sensitive
421	*/
422	#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE 0x1
423
424	/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
425	#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_LSB 0
426	/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
427	#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_MSB 28
428	/* The width in bits of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
429	#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_WIDTH 29
430	/* The mask used to set the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */
431	#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET_MSK 0x1fffffff
432	/* The mask used to clear the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */
433	#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_CLR_MSK 0xe0000000
434	/* The reset value of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
435	#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_RESET 0x0
436	/* Extracts the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL field value from a register. */
437	#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_GET(value) (((value) & 0x1fffffff) >> 0)
438	/* Produces a ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value suitable for setting the register. */
439	#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET(value) (((value) << 0) & 0x1fffffff)
440
441	#ifndef __ASSEMBLY__
442	/*
443	* WARNING: The C register and register group struct declarations are provided for
444	* convenience and illustrative purposes. They should, however, be used with
445	* caution as the C language standard provides no guarantees about the alignment or
446	* atomicity of device memory accesses. The recommended practice for writing
447	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
448	* alt_write_word() functions.
449	*
450	* The struct declaration for register ALT_GPIO_INTTYPE_LEVEL.
451	*/
452	struct ALT_GPIO_INTTYPE_LEVEL_s
453	{
454	uint32_t gpio_inttype_level : 29; /* Interrupt Level Field */
455	uint32_t : 3; /* UNDEFINED */
456	};
457
458	/* The typedef declaration for register ALT_GPIO_INTTYPE_LEVEL. */
459	typedef volatile struct ALT_GPIO_INTTYPE_LEVEL_s ALT_GPIO_INTTYPE_LEVEL_t;
460	#endif /* __ASSEMBLY__ */
461
462	/* The byte offset of the ALT_GPIO_INTTYPE_LEVEL register from the beginning of the component. */
463	#define ALT_GPIO_INTTYPE_LEVEL_OFST 0x38
464	/* The address of the ALT_GPIO_INTTYPE_LEVEL register. */
465	#define ALT_GPIO_INTTYPE_LEVEL_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_INTTYPE_LEVEL_OFST))
466
467	/*
468	* Register : Interrupt Polarity Register - gpio_int_polarity
469	*
470	* Controls the Polarity of Interrupts that can occur on inputs of Port A Data
471	* Register
472	*
473	* Register Layout
474	*
475	* Bits \| Access \| Reset \| Description
476	* :--------\|:-------\|:------\|:-----------------------
477	* [28:0] \| RW \| 0x0 \| Polarity Control Field
478	* [31:29] \| ??? \| 0x0 \| UNDEFINED
479	*
480	*/
481	/*
482	* Field : Polarity Control Field - gpio_int_polarity
483	*
484	* Controls the polarity of edge or level sensitivity that can occur on input of
485	* Port A Data Register.
486	*
487	* Field Enumeration Values:
488	*
489	* Enum \| Value \| Description
490	* :----------------------------------------\|:------\|:------------
491	* ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW \| 0x0 \| Active low
492	* ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH \| 0x1 \| Active high
493	*
494	* Field Access Macros:
495	*
496	*/
497	/*
498	* Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL
499	*
500	* Active low
501	*/
502	#define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW 0x0
503	/*
504	* Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL
505	*
506	* Active high
507	*/
508	#define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH 0x1
509
510	/* The Least Significant Bit (LSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
511	#define ALT_GPIO_INT_POL_GPIO_INT_POL_LSB 0
512	/* The Most Significant Bit (MSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
513	#define ALT_GPIO_INT_POL_GPIO_INT_POL_MSB 28
514	/* The width in bits of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
515	#define ALT_GPIO_INT_POL_GPIO_INT_POL_WIDTH 29
516	/* The mask used to set the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */
517	#define ALT_GPIO_INT_POL_GPIO_INT_POL_SET_MSK 0x1fffffff
518	/* The mask used to clear the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */
519	#define ALT_GPIO_INT_POL_GPIO_INT_POL_CLR_MSK 0xe0000000
520	/* The reset value of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
521	#define ALT_GPIO_INT_POL_GPIO_INT_POL_RESET 0x0
522	/* Extracts the ALT_GPIO_INT_POL_GPIO_INT_POL field value from a register. */
523	#define ALT_GPIO_INT_POL_GPIO_INT_POL_GET(value) (((value) & 0x1fffffff) >> 0)
524	/* Produces a ALT_GPIO_INT_POL_GPIO_INT_POL register field value suitable for setting the register. */
525	#define ALT_GPIO_INT_POL_GPIO_INT_POL_SET(value) (((value) << 0) & 0x1fffffff)
526
527	#ifndef __ASSEMBLY__
528	/*
529	* WARNING: The C register and register group struct declarations are provided for
530	* convenience and illustrative purposes. They should, however, be used with
531	* caution as the C language standard provides no guarantees about the alignment or
532	* atomicity of device memory accesses. The recommended practice for writing
533	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
534	* alt_write_word() functions.
535	*
536	* The struct declaration for register ALT_GPIO_INT_POL.
537	*/
538	struct ALT_GPIO_INT_POL_s
539	{
540	uint32_t gpio_int_polarity : 29; /* Polarity Control Field */
541	uint32_t : 3; /* UNDEFINED */
542	};
543
544	/* The typedef declaration for register ALT_GPIO_INT_POL. */
545	typedef volatile struct ALT_GPIO_INT_POL_s ALT_GPIO_INT_POL_t;
546	#endif /* __ASSEMBLY__ */
547
548	/* The byte offset of the ALT_GPIO_INT_POL register from the beginning of the component. */
549	#define ALT_GPIO_INT_POL_OFST 0x3c
550	/* The address of the ALT_GPIO_INT_POL register. */
551	#define ALT_GPIO_INT_POL_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_INT_POL_OFST))
552
553	/*
554	* Register : Interrupt Status Register - gpio_intstatus
555	*
556	* The Interrupt status is reported for all Port A Data Register Bits.
557	*
558	* Register Layout
559	*
560	* Bits \| Access \| Reset \| Description
561	* :--------\|:-------\|:------\|:-----------------------
562	* [28:0] \| RW \| 0x0 \| Interrupt Status Field
563	* [31:29] \| ??? \| 0x0 \| UNDEFINED
564	*
565	*/
566	/*
567	* Field : Interrupt Status Field - gpio_intstatus
568	*
569	* Interrupt status of Port A Data Register.
570	*
571	* Field Enumeration Values:
572	*
573	* Enum \| Value \| Description
574	* :--------------------------------------\|:------\|:------------
575	* ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT \| 0x0 \| Inactive
576	* ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT \| 0x1 \| Active
577	*
578	* Field Access Macros:
579	*
580	*/
581	/*
582	* Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT
583	*
584	* Inactive
585	*/
586	#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT 0x0
587	/*
588	* Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT
589	*
590	* Active
591	*/
592	#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT 0x1
593
594	/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
595	#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_LSB 0
596	/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
597	#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_MSB 28
598	/* The width in bits of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
599	#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_WIDTH 29
600	/* The mask used to set the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */
601	#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET_MSK 0x1fffffff
602	/* The mask used to clear the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */
603	#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_CLR_MSK 0xe0000000
604	/* The reset value of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
605	#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_RESET 0x0
606	/* Extracts the ALT_GPIO_INTSTAT_GPIO_INTSTAT field value from a register. */
607	#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0)
608	/* Produces a ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value suitable for setting the register. */
609	#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff)
610
611	#ifndef __ASSEMBLY__
612	/*
613	* WARNING: The C register and register group struct declarations are provided for
614	* convenience and illustrative purposes. They should, however, be used with
615	* caution as the C language standard provides no guarantees about the alignment or
616	* atomicity of device memory accesses. The recommended practice for writing
617	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
618	* alt_write_word() functions.
619	*
620	* The struct declaration for register ALT_GPIO_INTSTAT.
621	*/
622	struct ALT_GPIO_INTSTAT_s
623	{
624	uint32_t gpio_intstatus : 29; /* Interrupt Status Field */
625	uint32_t : 3; /* UNDEFINED */
626	};
627
628	/* The typedef declaration for register ALT_GPIO_INTSTAT. */
629	typedef volatile struct ALT_GPIO_INTSTAT_s ALT_GPIO_INTSTAT_t;
630	#endif /* __ASSEMBLY__ */
631
632	/* The byte offset of the ALT_GPIO_INTSTAT register from the beginning of the component. */
633	#define ALT_GPIO_INTSTAT_OFST 0x40
634	/* The address of the ALT_GPIO_INTSTAT register. */
635	#define ALT_GPIO_INTSTAT_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_INTSTAT_OFST))
636
637	/*
638	* Register : Raw Interrupt Status Register - gpio_raw_intstatus
639	*
640	* This is the Raw Interrupt Status Register for Port A Data Register. It is used
641	* with the Interrupt Mask Register to allow interrupts from the Port A Data
642	* Register.
643	*
644	* Register Layout
645	*
646	* Bits \| Access \| Reset \| Description
647	* :--------\|:-------\|:------\|:---------------------------
648	* [28:0] \| RW \| 0x0 \| Raw Interrupt Status Field
649	* [31:29] \| ??? \| 0x0 \| UNDEFINED
650	*
651	*/
652	/*
653	* Field : Raw Interrupt Status Field - gpio_raw_intstatus
654	*
655	* Raw interrupt of status of Port A Data Register (premasking bits)
656	*
657	* Field Enumeration Values:
658	*
659	* Enum \| Value \| Description
660	* :----------------------------------------------\|:------\|:------------
661	* ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT \| 0x0 \| Inactive
662	* ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT \| 0x1 \| Active
663	*
664	* Field Access Macros:
665	*
666	*/
667	/*
668	* Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT
669	*
670	* Inactive
671	*/
672	#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT 0x0
673	/*
674	* Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT
675	*
676	* Active
677	*/
678	#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT 0x1
679
680	/* The Least Significant Bit (LSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
681	#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_LSB 0
682	/* The Most Significant Bit (MSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
683	#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_MSB 28
684	/* The width in bits of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
685	#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_WIDTH 29
686	/* The mask used to set the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */
687	#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET_MSK 0x1fffffff
688	/* The mask used to clear the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */
689	#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_CLR_MSK 0xe0000000
690	/* The reset value of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
691	#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_RESET 0x0
692	/* Extracts the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT field value from a register. */
693	#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0)
694	/* Produces a ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value suitable for setting the register. */
695	#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff)
696
697	#ifndef __ASSEMBLY__
698	/*
699	* WARNING: The C register and register group struct declarations are provided for
700	* convenience and illustrative purposes. They should, however, be used with
701	* caution as the C language standard provides no guarantees about the alignment or
702	* atomicity of device memory accesses. The recommended practice for writing
703	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
704	* alt_write_word() functions.
705	*
706	* The struct declaration for register ALT_GPIO_RAW_INTSTAT.
707	*/
708	struct ALT_GPIO_RAW_INTSTAT_s
709	{
710	uint32_t gpio_raw_intstatus : 29; /* Raw Interrupt Status Field */
711	uint32_t : 3; /* UNDEFINED */
712	};
713
714	/* The typedef declaration for register ALT_GPIO_RAW_INTSTAT. */
715	typedef volatile struct ALT_GPIO_RAW_INTSTAT_s ALT_GPIO_RAW_INTSTAT_t;
716	#endif /* __ASSEMBLY__ */
717
718	/* The byte offset of the ALT_GPIO_RAW_INTSTAT register from the beginning of the component. */
719	#define ALT_GPIO_RAW_INTSTAT_OFST 0x44
720	/* The address of the ALT_GPIO_RAW_INTSTAT register. */
721	#define ALT_GPIO_RAW_INTSTAT_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_RAW_INTSTAT_OFST))
722
723	/*
724	* Register : Debounce Enable Register - gpio_debounce
725	*
726	* Debounces each IO Pin
727	*
728	* Register Layout
729	*
730	* Bits \| Access \| Reset \| Description
731	* :--------\|:-------\|:------\|:--------------------------------
732	* [28:0] \| RW \| 0x0 \| ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
733	* [31:29] \| ??? \| 0x0 \| UNDEFINED
734	*
735	*/
736	/*
737	* Field : gpio_debounce
738	*
739	* Controls whether an external signal that is the source of an interrupt needs to
740	* be debounced to remove any spurious glitches. A signal must be valid for two
741	* periods of an external clock (gpio_db_clk) before it is internally processed.
742	*
743	* Field Enumeration Values:
744	*
745	* Enum \| Value \| Description
746	* :--------------------------------------\|:------\|:----------------
747	* ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS \| 0x0 \| No debounce
748	* ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN \| 0x1 \| Enable debounce
749	*
750	* Field Access Macros:
751	*
752	*/
753	/*
754	* Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
755	*
756	* No debounce
757	*/
758	#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS 0x0
759	/*
760	* Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
761	*
762	* Enable debounce
763	*/
764	#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN 0x1
765
766	/* The Least Significant Bit (LSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
767	#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_LSB 0
768	/* The Most Significant Bit (MSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
769	#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_MSB 28
770	/* The width in bits of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
771	#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_WIDTH 29
772	/* The mask used to set the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */
773	#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET_MSK 0x1fffffff
774	/* The mask used to clear the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */
775	#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_CLR_MSK 0xe0000000
776	/* The reset value of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
777	#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_RESET 0x0
778	/* Extracts the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE field value from a register. */
779	#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_GET(value) (((value) & 0x1fffffff) >> 0)
780	/* Produces a ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value suitable for setting the register. */
781	#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET(value) (((value) << 0) & 0x1fffffff)
782
783	#ifndef __ASSEMBLY__
784	/*
785	* WARNING: The C register and register group struct declarations are provided for
786	* convenience and illustrative purposes. They should, however, be used with
787	* caution as the C language standard provides no guarantees about the alignment or
788	* atomicity of device memory accesses. The recommended practice for writing
789	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
790	* alt_write_word() functions.
791	*
792	* The struct declaration for register ALT_GPIO_DEBOUNCE.
793	*/
794	struct ALT_GPIO_DEBOUNCE_s
795	{
796	uint32_t gpio_debounce : 29; /* ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE */
797	uint32_t : 3; /* UNDEFINED */
798	};
799
800	/* The typedef declaration for register ALT_GPIO_DEBOUNCE. */
801	typedef volatile struct ALT_GPIO_DEBOUNCE_s ALT_GPIO_DEBOUNCE_t;
802	#endif /* __ASSEMBLY__ */
803
804	/* The byte offset of the ALT_GPIO_DEBOUNCE register from the beginning of the component. */
805	#define ALT_GPIO_DEBOUNCE_OFST 0x48
806	/* The address of the ALT_GPIO_DEBOUNCE register. */
807	#define ALT_GPIO_DEBOUNCE_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_DEBOUNCE_OFST))
808
809	/*
810	* Register : Clear Interrupt Register - gpio_porta_eoi
811	*
812	* Port A Data Register interrupt handling.
813	*
814	* Register Layout
815	*
816	* Bits \| Access \| Reset \| Description
817	* :--------\|:-------\|:------\|:-----------------------------
818	* [28:0] \| W \| 0x0 \| Clears Edge Interrupts Field
819	* [31:29] \| ??? \| 0x0 \| UNDEFINED
820	*
821	*/
822	/*
823	* Field : Clears Edge Interrupts Field - gpio_porta_eoi
824	*
825	* Controls the clearing of edge type interrupts from the Port A Data Register.
826	*
827	* Field Enumeration Values:
828	*
829	* Enum \| Value \| Description
830	* :------------------------------------------\|:------\|:-------------------
831	* ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR \| 0x0 \| No interrupt clear
832	* ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR \| 0x1 \| Clear interrupt
833	*
834	* Field Access Macros:
835	*
836	*/
837	/*
838	* Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI
839	*
840	* No interrupt clear
841	*/
842	#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR 0x0
843	/*
844	* Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI
845	*
846	* Clear interrupt
847	*/
848	#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR 0x1
849
850	/* The Least Significant Bit (LSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
851	#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_LSB 0
852	/* The Most Significant Bit (MSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
853	#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_MSB 28
854	/* The width in bits of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
855	#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_WIDTH 29
856	/* The mask used to set the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */
857	#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET_MSK 0x1fffffff
858	/* The mask used to clear the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */
859	#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_CLR_MSK 0xe0000000
860	/* The reset value of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
861	#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_RESET 0x0
862	/* Extracts the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI field value from a register. */
863	#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_GET(value) (((value) & 0x1fffffff) >> 0)
864	/* Produces a ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value suitable for setting the register. */
865	#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET(value) (((value) << 0) & 0x1fffffff)
866
867	#ifndef __ASSEMBLY__
868	/*
869	* WARNING: The C register and register group struct declarations are provided for
870	* convenience and illustrative purposes. They should, however, be used with
871	* caution as the C language standard provides no guarantees about the alignment or
872	* atomicity of device memory accesses. The recommended practice for writing
873	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
874	* alt_write_word() functions.
875	*
876	* The struct declaration for register ALT_GPIO_PORTA_EOI.
877	*/
878	struct ALT_GPIO_PORTA_EOI_s
879	{
880	uint32_t gpio_porta_eoi : 29; /* Clears Edge Interrupts Field */
881	uint32_t : 3; /* UNDEFINED */
882	};
883
884	/* The typedef declaration for register ALT_GPIO_PORTA_EOI. */
885	typedef volatile struct ALT_GPIO_PORTA_EOI_s ALT_GPIO_PORTA_EOI_t;
886	#endif /* __ASSEMBLY__ */
887
888	/* The byte offset of the ALT_GPIO_PORTA_EOI register from the beginning of the component. */
889	#define ALT_GPIO_PORTA_EOI_OFST 0x4c
890	/* The address of the ALT_GPIO_PORTA_EOI register. */
891	#define ALT_GPIO_PORTA_EOI_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_PORTA_EOI_OFST))
892
893	/*
894	* Register : External Port A Register - gpio_ext_porta
895	*
896	* The external port register is used to input data to the metastability flops.
897	*
898	* Register Layout
899	*
900	* Bits \| Access \| Reset \| Description
901	* :--------\|:-------\|:------\|:--------------------
902	* [28:0] \| R \| 0x0 \| External Port Field
903	* [31:29] \| ??? \| 0x0 \| UNDEFINED
904	*
905	*/
906	/*
907	* Field : External Port Field - gpio_ext_porta
908	*
909	* When Port A Data Register is configured as Input, then reading this location
910	* reads the values on the signals. When the data direction of Port A Data Register
911	* is set as Output, reading this location reads Port A Data Register
912	*
913	* Field Access Macros:
914	*
915	*/
916	/* The Least Significant Bit (LSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
917	#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_LSB 0
918	/* The Most Significant Bit (MSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
919	#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_MSB 28
920	/* The width in bits of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
921	#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_WIDTH 29
922	/* The mask used to set the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */
923	#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET_MSK 0x1fffffff
924	/* The mask used to clear the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */
925	#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_CLR_MSK 0xe0000000
926	/* The reset value of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
927	#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_RESET 0x0
928	/* Extracts the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA field value from a register. */
929	#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_GET(value) (((value) & 0x1fffffff) >> 0)
930	/* Produces a ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value suitable for setting the register. */
931	#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET(value) (((value) << 0) & 0x1fffffff)
932
933	#ifndef __ASSEMBLY__
934	/*
935	* WARNING: The C register and register group struct declarations are provided for
936	* convenience and illustrative purposes. They should, however, be used with
937	* caution as the C language standard provides no guarantees about the alignment or
938	* atomicity of device memory accesses. The recommended practice for writing
939	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
940	* alt_write_word() functions.
941	*
942	* The struct declaration for register ALT_GPIO_EXT_PORTA.
943	*/
944	struct ALT_GPIO_EXT_PORTA_s
945	{
946	const uint32_t gpio_ext_porta : 29; /* External Port Field */
947	uint32_t : 3; /* UNDEFINED */
948	};
949
950	/* The typedef declaration for register ALT_GPIO_EXT_PORTA. */
951	typedef volatile struct ALT_GPIO_EXT_PORTA_s ALT_GPIO_EXT_PORTA_t;
952	#endif /* __ASSEMBLY__ */
953
954	/* The byte offset of the ALT_GPIO_EXT_PORTA register from the beginning of the component. */
955	#define ALT_GPIO_EXT_PORTA_OFST 0x50
956	/* The address of the ALT_GPIO_EXT_PORTA register. */
957	#define ALT_GPIO_EXT_PORTA_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_EXT_PORTA_OFST))
958
959	/*
960	* Register : Synchronization Level Register - gpio_ls_sync
961	*
962	* The Synchronization level register is used to synchronize input with l4_mp_clk
963	*
964	* Register Layout
965	*
966	* Bits \| Access \| Reset \| Description
967	* :-------\|:-------\|:------\|:----------------------------
968	* [0] \| RW \| 0x0 \| Synchronization Level Field
969	* [31:1] \| ??? \| 0x0 \| UNDEFINED
970	*
971	*/
972	/*
973	* Field : Synchronization Level Field - gpio_ls_sync
974	*
975	* The level-sensitive interrupts is synchronized to l4_mp_clk.
976	*
977	* Field Enumeration Values:
978	*
979	* Enum \| Value \| Description
980	* :---------------------------------------\|:------\|:--------------------------------
981	* ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC \| 0x0 \| No synchronization to l4_mp_clk
982	* ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC \| 0x1 \| Synchronize to l4_mp_clk
983	*
984	* Field Access Macros:
985	*
986	*/
987	/*
988	* Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC
989	*
990	* No synchronization to l4_mp_clk
991	*/
992	#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC 0x0
993	/*
994	* Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC
995	*
996	* Synchronize to l4_mp_clk
997	*/
998	#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC 0x1
999
1000	/* The Least Significant Bit (LSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1001	#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_LSB 0
1002	/* The Most Significant Bit (MSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1003	#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_MSB 0
1004	/* The width in bits of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1005	#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_WIDTH 1
1006	/* The mask used to set the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */
1007	#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET_MSK 0x00000001
1008	/* The mask used to clear the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */
1009	#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_CLR_MSK 0xfffffffe
1010	/* The reset value of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1011	#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_RESET 0x0
1012	/* Extracts the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC field value from a register. */
1013	#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_GET(value) (((value) & 0x00000001) >> 0)
1014	/* Produces a ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value suitable for setting the register. */
1015	#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET(value) (((value) << 0) & 0x00000001)
1016
1017	#ifndef __ASSEMBLY__
1018	/*
1019	* WARNING: The C register and register group struct declarations are provided for
1020	* convenience and illustrative purposes. They should, however, be used with
1021	* caution as the C language standard provides no guarantees about the alignment or
1022	* atomicity of device memory accesses. The recommended practice for writing
1023	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1024	* alt_write_word() functions.
1025	*
1026	* The struct declaration for register ALT_GPIO_LS_SYNC.
1027	*/
1028	struct ALT_GPIO_LS_SYNC_s
1029	{
1030	uint32_t gpio_ls_sync : 1; /* Synchronization Level Field */
1031	uint32_t : 31; /* UNDEFINED */
1032	};
1033
1034	/* The typedef declaration for register ALT_GPIO_LS_SYNC. */
1035	typedef volatile struct ALT_GPIO_LS_SYNC_s ALT_GPIO_LS_SYNC_t;
1036	#endif /* __ASSEMBLY__ */
1037
1038	/* The byte offset of the ALT_GPIO_LS_SYNC register from the beginning of the component. */
1039	#define ALT_GPIO_LS_SYNC_OFST 0x60
1040	/* The address of the ALT_GPIO_LS_SYNC register. */
1041	#define ALT_GPIO_LS_SYNC_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_LS_SYNC_OFST))
1042
1043	/*
1044	* Register : ID Code Register - gpio_id_code
1045	*
1046	* GPIO ID code.
1047	*
1048	* Register Layout
1049	*
1050	* Bits \| Access \| Reset \| Description
1051	* :-------\|:-------\|:------\|:--------------
1052	* [31:0] \| R \| 0x0 \| ID Code Field
1053	*
1054	*/
1055	/*
1056	* Field : ID Code Field - gpio_id_code
1057	*
1058	* Chip identification
1059	*
1060	* Field Access Macros:
1061	*
1062	*/
1063	/* The Least Significant Bit (LSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1064	#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_LSB 0
1065	/* The Most Significant Bit (MSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1066	#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_MSB 31
1067	/* The width in bits of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1068	#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_WIDTH 32
1069	/* The mask used to set the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */
1070	#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET_MSK 0xffffffff
1071	/* The mask used to clear the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */
1072	#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_CLR_MSK 0x00000000
1073	/* The reset value of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1074	#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_RESET 0x0
1075	/* Extracts the ALT_GPIO_ID_CODE_GPIO_ID_CODE field value from a register. */
1076	#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0)
1077	/* Produces a ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value suitable for setting the register. */
1078	#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET(value) (((value) << 0) & 0xffffffff)
1079
1080	#ifndef __ASSEMBLY__
1081	/*
1082	* WARNING: The C register and register group struct declarations are provided for
1083	* convenience and illustrative purposes. They should, however, be used with
1084	* caution as the C language standard provides no guarantees about the alignment or
1085	* atomicity of device memory accesses. The recommended practice for writing
1086	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1087	* alt_write_word() functions.
1088	*
1089	* The struct declaration for register ALT_GPIO_ID_CODE.
1090	*/
1091	struct ALT_GPIO_ID_CODE_s
1092	{
1093	const uint32_t gpio_id_code : 32; /* ID Code Field */
1094	};
1095
1096	/* The typedef declaration for register ALT_GPIO_ID_CODE. */
1097	typedef volatile struct ALT_GPIO_ID_CODE_s ALT_GPIO_ID_CODE_t;
1098	#endif /* __ASSEMBLY__ */
1099
1100	/* The byte offset of the ALT_GPIO_ID_CODE register from the beginning of the component. */
1101	#define ALT_GPIO_ID_CODE_OFST 0x64
1102	/* The address of the ALT_GPIO_ID_CODE register. */
1103	#define ALT_GPIO_ID_CODE_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_ID_CODE_OFST))
1104
1105	/*
1106	* Register : GPIO Version Register - gpio_ver_id_code
1107	*
1108	* GPIO Component Version
1109	*
1110	* Register Layout
1111	*
1112	* Bits \| Access \| Reset \| Description
1113	* :-------\|:-------\|:-----------\|:------------------------------
1114	* [31:0] \| R \| 0x3230382a \| ASCII Component Version Field
1115	*
1116	*/
1117	/*
1118	* Field : ASCII Component Version Field - gpio_ver_id_code
1119	*
1120	* ASCII value for each number in the version, followed by *. For example.
1121	* 32_30_31_2A represents the version 2.01
1122	*
1123	* Field Access Macros:
1124	*
1125	*/
1126	/* The Least Significant Bit (LSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1127	#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_LSB 0
1128	/* The Most Significant Bit (MSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1129	#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_MSB 31
1130	/* The width in bits of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1131	#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_WIDTH 32
1132	/* The mask used to set the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */
1133	#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET_MSK 0xffffffff
1134	/* The mask used to clear the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */
1135	#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_CLR_MSK 0x00000000
1136	/* The reset value of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1137	#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_RESET 0x3230382a
1138	/* Extracts the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE field value from a register. */
1139	#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0)
1140	/* Produces a ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value suitable for setting the register. */
1141	#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET(value) (((value) << 0) & 0xffffffff)
1142
1143	#ifndef __ASSEMBLY__
1144	/*
1145	* WARNING: The C register and register group struct declarations are provided for
1146	* convenience and illustrative purposes. They should, however, be used with
1147	* caution as the C language standard provides no guarantees about the alignment or
1148	* atomicity of device memory accesses. The recommended practice for writing
1149	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1150	* alt_write_word() functions.
1151	*
1152	* The struct declaration for register ALT_GPIO_VER_ID_CODE.
1153	*/
1154	struct ALT_GPIO_VER_ID_CODE_s
1155	{
1156	const uint32_t gpio_ver_id_code : 32; /* ASCII Component Version Field */
1157	};
1158
1159	/* The typedef declaration for register ALT_GPIO_VER_ID_CODE. */
1160	typedef volatile struct ALT_GPIO_VER_ID_CODE_s ALT_GPIO_VER_ID_CODE_t;
1161	#endif /* __ASSEMBLY__ */
1162
1163	/* The byte offset of the ALT_GPIO_VER_ID_CODE register from the beginning of the component. */
1164	#define ALT_GPIO_VER_ID_CODE_OFST 0x6c
1165	/* The address of the ALT_GPIO_VER_ID_CODE register. */
1166	#define ALT_GPIO_VER_ID_CODE_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_VER_ID_CODE_OFST))
1167
1168	/*
1169	* Register : Configuration Register 2 - gpio_config_reg2
1170	*
1171	* Specifies the bit width of port A.
1172	*
1173	* Register Layout
1174	*
1175	* Bits \| Access \| Reset \| Description
1176	* :--------\|:-------\|:------\|:----------------------
1177	* [4:0] \| R \| 0x1c \| Port A Width (less 1)
1178	* [9:5] \| R \| 0x7 \| Port B Width (less 1)
1179	* [14:10] \| R \| 0x7 \| Port C Width (less 1)
1180	* [19:15] \| R \| 0x7 \| Port D Width (less 1)
1181	* [31:20] \| ??? \| 0x0 \| UNDEFINED
1182	*
1183	*/
1184	/*
1185	* Field : Port A Width (less 1) - encoded_id_pwidth_a
1186	*
1187	* Specifies the width of GPIO Port A. The value 28 represents the 29-bit width
1188	* less one.
1189	*
1190	* Field Enumeration Values:
1191	*
1192	* Enum \| Value \| Description
1193	* :-------------------------------------------------------\|:------\|:--------------------------
1194	* ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS \| 0x7 \| Width (less 1) of 8 bits
1195	* ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS \| 0x1c \| Width (less 1) of 29 bits
1196	*
1197	* Field Access Macros:
1198	*
1199	*/
1200	/*
1201	* Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
1202	*
1203	* Width (less 1) of 8 bits
1204	*/
1205	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS 0x7
1206	/*
1207	* Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
1208	*
1209	* Width (less 1) of 29 bits
1210	*/
1211	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS 0x1c
1212
1213	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1214	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_LSB 0
1215	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1216	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_MSB 4
1217	/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1218	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_WIDTH 5
1219	/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */
1220	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET_MSK 0x0000001f
1221	/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */
1222	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_CLR_MSK 0xffffffe0
1223	/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1224	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_RESET 0x1c
1225	/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A field value from a register. */
1226	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_GET(value) (((value) & 0x0000001f) >> 0)
1227	/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value suitable for setting the register. */
1228	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET(value) (((value) << 0) & 0x0000001f)
1229
1230	/*
1231	* Field : Port B Width (less 1) - encoded_id_pwidth_b
1232	*
1233	* Specifies the width of GPIO Port B. Ignored because there is no Port B in the
1234	* GPIO.
1235	*
1236	* Field Enumeration Values:
1237	*
1238	* Enum \| Value \| Description
1239	* :-------------------------------------------------------\|:------\|:--------------------------
1240	* ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS \| 0x7 \| Width (less 1) of 8 bits
1241	* ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS \| 0x1c \| Width (less 1) of 29 bits
1242	*
1243	* Field Access Macros:
1244	*
1245	*/
1246	/*
1247	* Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
1248	*
1249	* Width (less 1) of 8 bits
1250	*/
1251	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS 0x7
1252	/*
1253	* Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
1254	*
1255	* Width (less 1) of 29 bits
1256	*/
1257	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS 0x1c
1258
1259	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1260	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_LSB 5
1261	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1262	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_MSB 9
1263	/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1264	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_WIDTH 5
1265	/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */
1266	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET_MSK 0x000003e0
1267	/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */
1268	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_CLR_MSK 0xfffffc1f
1269	/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1270	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_RESET 0x7
1271	/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B field value from a register. */
1272	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_GET(value) (((value) & 0x000003e0) >> 5)
1273	/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value suitable for setting the register. */
1274	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET(value) (((value) << 5) & 0x000003e0)
1275
1276	/*
1277	* Field : Port C Width (less 1) - encoded_id_pwidth_c
1278	*
1279	* Specifies the width of GPIO Port C. Ignored because there is no Port C in the
1280	* GPIO.
1281	*
1282	* Field Enumeration Values:
1283	*
1284	* Enum \| Value \| Description
1285	* :-------------------------------------------------------\|:------\|:--------------------------
1286	* ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS \| 0x7 \| Width (less 1) of 8 bits
1287	* ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS \| 0x1c \| Width (less 1) of 29 bits
1288	*
1289	* Field Access Macros:
1290	*
1291	*/
1292	/*
1293	* Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
1294	*
1295	* Width (less 1) of 8 bits
1296	*/
1297	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS 0x7
1298	/*
1299	* Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
1300	*
1301	* Width (less 1) of 29 bits
1302	*/
1303	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS 0x1c
1304
1305	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1306	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_LSB 10
1307	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1308	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_MSB 14
1309	/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1310	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_WIDTH 5
1311	/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */
1312	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET_MSK 0x00007c00
1313	/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */
1314	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_CLR_MSK 0xffff83ff
1315	/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1316	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_RESET 0x7
1317	/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C field value from a register. */
1318	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_GET(value) (((value) & 0x00007c00) >> 10)
1319	/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value suitable for setting the register. */
1320	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET(value) (((value) << 10) & 0x00007c00)
1321
1322	/*
1323	* Field : Port D Width (less 1) - encoded_id_pwidth_d
1324	*
1325	* Specifies the width of GPIO Port D. Ignored because there is no Port D in the
1326	* GPIO.
1327	*
1328	* Field Enumeration Values:
1329	*
1330	* Enum \| Value \| Description
1331	* :-------------------------------------------------------\|:------\|:--------------------------
1332	* ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS \| 0x7 \| Width (less 1) of 8 bits
1333	* ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS \| 0x1c \| Width (less 1) of 29 bits
1334	*
1335	* Field Access Macros:
1336	*
1337	*/
1338	/*
1339	* Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
1340	*
1341	* Width (less 1) of 8 bits
1342	*/
1343	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS 0x7
1344	/*
1345	* Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
1346	*
1347	* Width (less 1) of 29 bits
1348	*/
1349	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS 0x1c
1350
1351	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1352	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_LSB 15
1353	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1354	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_MSB 19
1355	/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1356	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_WIDTH 5
1357	/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */
1358	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET_MSK 0x000f8000
1359	/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */
1360	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_CLR_MSK 0xfff07fff
1361	/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1362	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_RESET 0x7
1363	/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D field value from a register. */
1364	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_GET(value) (((value) & 0x000f8000) >> 15)
1365	/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value suitable for setting the register. */
1366	#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET(value) (((value) << 15) & 0x000f8000)
1367
1368	#ifndef __ASSEMBLY__
1369	/*
1370	* WARNING: The C register and register group struct declarations are provided for
1371	* convenience and illustrative purposes. They should, however, be used with
1372	* caution as the C language standard provides no guarantees about the alignment or
1373	* atomicity of device memory accesses. The recommended practice for writing
1374	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1375	* alt_write_word() functions.
1376	*
1377	* The struct declaration for register ALT_GPIO_CFG_REG2.
1378	*/
1379	struct ALT_GPIO_CFG_REG2_s
1380	{
1381	const uint32_t encoded_id_pwidth_a : 5; /* Port A Width (less 1) */
1382	const uint32_t encoded_id_pwidth_b : 5; /* Port B Width (less 1) */
1383	const uint32_t encoded_id_pwidth_c : 5; /* Port C Width (less 1) */
1384	const uint32_t encoded_id_pwidth_d : 5; /* Port D Width (less 1) */
1385	uint32_t : 12; /* UNDEFINED */
1386	};
1387
1388	/* The typedef declaration for register ALT_GPIO_CFG_REG2. */
1389	typedef volatile struct ALT_GPIO_CFG_REG2_s ALT_GPIO_CFG_REG2_t;
1390	#endif /* __ASSEMBLY__ */
1391
1392	/* The byte offset of the ALT_GPIO_CFG_REG2 register from the beginning of the component. */
1393	#define ALT_GPIO_CFG_REG2_OFST 0x70
1394	/* The address of the ALT_GPIO_CFG_REG2 register. */
1395	#define ALT_GPIO_CFG_REG2_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_CFG_REG2_OFST))
1396
1397	/*
1398	* Register : Configuration Register 1 - gpio_config_reg1
1399	*
1400	* Reports settings of various GPIO configuration parameters
1401	*
1402	* Register Layout
1403	*
1404	* Bits \| Access \| Reset \| Description
1405	* :--------\|:-------\|:------\|:----------------------------------
1406	* [1:0] \| R \| 0x2 \| APB DATA WIDTH
1407	* [3:2] \| R \| 0x0 \| NUM PORTS
1408	* [4] \| R \| 0x1 \| PORT A SINGLE CTL
1409	* [5] \| R \| 0x1 \| PORT B SINGLE CTL
1410	* [6] \| R \| 0x1 \| PORT C SINGLE CTL
1411	* [7] \| R \| 0x1 \| PORT D SINGLE CTL
1412	* [8] \| R \| 0x0 \| HW PORTA
1413	* [11:9] \| ??? \| 0x0 \| UNDEFINED
1414	* [12] \| R \| 0x1 \| Port A Interrupt Field
1415	* [13] \| R \| 0x1 \| Debounce Field
1416	* [14] \| R \| 0x1 \| Encoded GPIO Parameters Available
1417	* [15] \| R \| 0x1 \| ID Field
1418	* [20:16] \| R \| 0x1f \| Encoded ID Width Field
1419	* [31:21] \| ??? \| 0x0 \| UNDEFINED
1420	*
1421	*/
1422	/*
1423	* Field : APB DATA WIDTH - apb_data_width
1424	*
1425	* Fixed to support an ABP data bus width of 32-bits.
1426	*
1427	* Field Enumeration Values:
1428	*
1429	* Enum \| Value \| Description
1430	* :-----------------------------------------------\|:------\|:-------------------------
1431	* ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS \| 0x2 \| APB Data Width = 32-bits
1432	*
1433	* Field Access Macros:
1434	*
1435	*/
1436	/*
1437	* Enumerated value for register field ALT_GPIO_CFG_REG1_APB_DATA_WIDTH
1438	*
1439	* APB Data Width = 32-bits
1440	*/
1441	#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2
1442
1443	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1444	#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_LSB 0
1445	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1446	#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_MSB 1
1447	/* The width in bits of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1448	#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_WIDTH 2
1449	/* The mask used to set the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */
1450	#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET_MSK 0x00000003
1451	/* The mask used to clear the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */
1452	#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
1453	/* The reset value of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1454	#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_RESET 0x2
1455	/* Extracts the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH field value from a register. */
1456	#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
1457	/* Produces a ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value suitable for setting the register. */
1458	#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
1459
1460	/*
1461	* Field : NUM PORTS - num_ports
1462	*
1463	* The value of this register is fixed at one port (Port A).
1464	*
1465	* Field Enumeration Values:
1466	*
1467	* Enum \| Value \| Description
1468	* :---------------------------------------\|:------\|:-------------------------
1469	* ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA \| 0x0 \| Number of GPIO Ports = 1
1470	*
1471	* Field Access Macros:
1472	*
1473	*/
1474	/*
1475	* Enumerated value for register field ALT_GPIO_CFG_REG1_NUM_PORTS
1476	*
1477	* Number of GPIO Ports = 1
1478	*/
1479	#define ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA 0x0
1480
1481	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1482	#define ALT_GPIO_CFG_REG1_NUM_PORTS_LSB 2
1483	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1484	#define ALT_GPIO_CFG_REG1_NUM_PORTS_MSB 3
1485	/* The width in bits of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1486	#define ALT_GPIO_CFG_REG1_NUM_PORTS_WIDTH 2
1487	/* The mask used to set the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */
1488	#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET_MSK 0x0000000c
1489	/* The mask used to clear the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */
1490	#define ALT_GPIO_CFG_REG1_NUM_PORTS_CLR_MSK 0xfffffff3
1491	/* The reset value of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1492	#define ALT_GPIO_CFG_REG1_NUM_PORTS_RESET 0x0
1493	/* Extracts the ALT_GPIO_CFG_REG1_NUM_PORTS field value from a register. */
1494	#define ALT_GPIO_CFG_REG1_NUM_PORTS_GET(value) (((value) & 0x0000000c) >> 2)
1495	/* Produces a ALT_GPIO_CFG_REG1_NUM_PORTS register field value suitable for setting the register. */
1496	#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET(value) (((value) << 2) & 0x0000000c)
1497
1498	/*
1499	* Field : PORT A SINGLE CTL - porta_single_ctl
1500	*
1501	* Indicates the mode of operation of Port A to be software controlled only.
1502	*
1503	* Field Enumeration Values:
1504	*
1505	* Enum \| Value \| Description
1506	* :-------------------------------------------------\|:------\|:-----------------------------------------
1507	* ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY \| 0x1 \| Software Enabled Individual Port Control
1508	*
1509	* Field Access Macros:
1510	*
1511	*/
1512	/*
1513	* Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL
1514	*
1515	* Software Enabled Individual Port Control
1516	*/
1517	#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY 0x1
1518
1519	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1520	#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_LSB 4
1521	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1522	#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_MSB 4
1523	/* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1524	#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_WIDTH 1
1525	/* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */
1526	#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET_MSK 0x00000010
1527	/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */
1528	#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_CLR_MSK 0xffffffef
1529	/* The reset value of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1530	#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_RESET 0x1
1531	/* Extracts the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL field value from a register. */
1532	#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_GET(value) (((value) & 0x00000010) >> 4)
1533	/* Produces a ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value suitable for setting the register. */
1534	#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET(value) (((value) << 4) & 0x00000010)
1535
1536	/*
1537	* Field : PORT B SINGLE CTL - portb_single_ctl
1538	*
1539	* Indicates the mode of operation of Port B to be software controlled only.
1540	* Ignored because there is no Port B in the GPIO.
1541	*
1542	* Field Enumeration Values:
1543	*
1544	* Enum \| Value \| Description
1545	* :-------------------------------------------------\|:------\|:-----------------------------------------
1546	* ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY \| 0x1 \| Software Enabled Individual Port Control
1547	*
1548	* Field Access Macros:
1549	*
1550	*/
1551	/*
1552	* Enumerated value for register field ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL
1553	*
1554	* Software Enabled Individual Port Control
1555	*/
1556	#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY 0x1
1557
1558	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1559	#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_LSB 5
1560	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1561	#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_MSB 5
1562	/* The width in bits of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1563	#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_WIDTH 1
1564	/* The mask used to set the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */
1565	#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET_MSK 0x00000020
1566	/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */
1567	#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_CLR_MSK 0xffffffdf
1568	/* The reset value of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1569	#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_RESET 0x1
1570	/* Extracts the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL field value from a register. */
1571	#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_GET(value) (((value) & 0x00000020) >> 5)
1572	/* Produces a ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value suitable for setting the register. */
1573	#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET(value) (((value) << 5) & 0x00000020)
1574
1575	/*
1576	* Field : PORT C SINGLE CTL - portc_single_ctl
1577	*
1578	* Indicates the mode of operation of Port C to be software controlled only.
1579	* Ignored because there is no Port C in the GPIO.
1580	*
1581	* Field Enumeration Values:
1582	*
1583	* Enum \| Value \| Description
1584	* :-------------------------------------------------\|:------\|:-----------------------------------------
1585	* ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY \| 0x1 \| Software Enabled Individual Port Control
1586	*
1587	* Field Access Macros:
1588	*
1589	*/
1590	/*
1591	* Enumerated value for register field ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL
1592	*
1593	* Software Enabled Individual Port Control
1594	*/
1595	#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY 0x1
1596
1597	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1598	#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_LSB 6
1599	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1600	#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_MSB 6
1601	/* The width in bits of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1602	#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_WIDTH 1
1603	/* The mask used to set the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */
1604	#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET_MSK 0x00000040
1605	/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */
1606	#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_CLR_MSK 0xffffffbf
1607	/* The reset value of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1608	#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_RESET 0x1
1609	/* Extracts the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL field value from a register. */
1610	#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_GET(value) (((value) & 0x00000040) >> 6)
1611	/* Produces a ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value suitable for setting the register. */
1612	#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET(value) (((value) << 6) & 0x00000040)
1613
1614	/*
1615	* Field : PORT D SINGLE CTL - portd_single_ctl
1616	*
1617	* Indicates the mode of operation of Port D to be software controlled only.
1618	* Ignored because there is no Port D in the GPIO.
1619	*
1620	* Field Enumeration Values:
1621	*
1622	* Enum \| Value \| Description
1623	* :-------------------------------------------------\|:------\|:-----------------------------------------
1624	* ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY \| 0x1 \| Software Enabled Individual Port Control
1625	*
1626	* Field Access Macros:
1627	*
1628	*/
1629	/*
1630	* Enumerated value for register field ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL
1631	*
1632	* Software Enabled Individual Port Control
1633	*/
1634	#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY 0x1
1635
1636	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1637	#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_LSB 7
1638	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1639	#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_MSB 7
1640	/* The width in bits of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1641	#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_WIDTH 1
1642	/* The mask used to set the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */
1643	#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET_MSK 0x00000080
1644	/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */
1645	#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_CLR_MSK 0xffffff7f
1646	/* The reset value of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1647	#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_RESET 0x1
1648	/* Extracts the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL field value from a register. */
1649	#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_GET(value) (((value) & 0x00000080) >> 7)
1650	/* Produces a ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value suitable for setting the register. */
1651	#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET(value) (((value) << 7) & 0x00000080)
1652
1653	/*
1654	* Field : HW PORTA - hw_porta
1655	*
1656	* The value is fixed to enable Port A configuration to be controlled by software
1657	* only.
1658	*
1659	* Field Enumeration Values:
1660	*
1661	* Enum \| Value \| Description
1662	* :-----------------------------------------\|:------\|:---------------------------------------
1663	* ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD \| 0x0 \| Software Configuration Control Enabled
1664	*
1665	* Field Access Macros:
1666	*
1667	*/
1668	/*
1669	* Enumerated value for register field ALT_GPIO_CFG_REG1_HW_PORTA
1670	*
1671	* Software Configuration Control Enabled
1672	*/
1673	#define ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD 0x0
1674
1675	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1676	#define ALT_GPIO_CFG_REG1_HW_PORTA_LSB 8
1677	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1678	#define ALT_GPIO_CFG_REG1_HW_PORTA_MSB 8
1679	/* The width in bits of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1680	#define ALT_GPIO_CFG_REG1_HW_PORTA_WIDTH 1
1681	/* The mask used to set the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */
1682	#define ALT_GPIO_CFG_REG1_HW_PORTA_SET_MSK 0x00000100
1683	/* The mask used to clear the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */
1684	#define ALT_GPIO_CFG_REG1_HW_PORTA_CLR_MSK 0xfffffeff
1685	/* The reset value of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1686	#define ALT_GPIO_CFG_REG1_HW_PORTA_RESET 0x0
1687	/* Extracts the ALT_GPIO_CFG_REG1_HW_PORTA field value from a register. */
1688	#define ALT_GPIO_CFG_REG1_HW_PORTA_GET(value) (((value) & 0x00000100) >> 8)
1689	/* Produces a ALT_GPIO_CFG_REG1_HW_PORTA register field value suitable for setting the register. */
1690	#define ALT_GPIO_CFG_REG1_HW_PORTA_SET(value) (((value) << 8) & 0x00000100)
1691
1692	/*
1693	* Field : Port A Interrupt Field - porta_intr
1694	*
1695	* The value of this field is fixed to allow interrupts on Port A.
1696	*
1697	* Field Enumeration Values:
1698	*
1699	* Enum \| Value \| Description
1700	* :-------------------------------------------\|:------\|:--------------------------
1701	* ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR \| 0x1 \| Port A Interrupts Enabled
1702	*
1703	* Field Access Macros:
1704	*
1705	*/
1706	/*
1707	* Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_INTR
1708	*
1709	* Port A Interrupts Enabled
1710	*/
1711	#define ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR 0x1
1712
1713	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
1714	#define ALT_GPIO_CFG_REG1_PORTA_INTR_LSB 12
1715	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
1716	#define ALT_GPIO_CFG_REG1_PORTA_INTR_MSB 12
1717	/* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
1718	#define ALT_GPIO_CFG_REG1_PORTA_INTR_WIDTH 1
1719	/* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */
1720	#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET_MSK 0x00001000
1721	/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */
1722	#define ALT_GPIO_CFG_REG1_PORTA_INTR_CLR_MSK 0xffffefff
1723	/* The reset value of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
1724	#define ALT_GPIO_CFG_REG1_PORTA_INTR_RESET 0x1
1725	/* Extracts the ALT_GPIO_CFG_REG1_PORTA_INTR field value from a register. */
1726	#define ALT_GPIO_CFG_REG1_PORTA_INTR_GET(value) (((value) & 0x00001000) >> 12)
1727	/* Produces a ALT_GPIO_CFG_REG1_PORTA_INTR register field value suitable for setting the register. */
1728	#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET(value) (((value) << 12) & 0x00001000)
1729
1730	/*
1731	* Field : Debounce Field - debounce
1732	*
1733	* The value of this field is fixed to allow debouncing of the Port A signals.
1734	*
1735	* Field Enumeration Values:
1736	*
1737	* Enum \| Value \| Description
1738	* :---------------------------------------\|:------\|:--------------------
1739	* ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA \| 0x1 \| Debounce is Enabled
1740	*
1741	* Field Access Macros:
1742	*
1743	*/
1744	/*
1745	* Enumerated value for register field ALT_GPIO_CFG_REG1_DEBOUNCE
1746	*
1747	* Debounce is Enabled
1748	*/
1749	#define ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA 0x1
1750
1751	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
1752	#define ALT_GPIO_CFG_REG1_DEBOUNCE_LSB 13
1753	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
1754	#define ALT_GPIO_CFG_REG1_DEBOUNCE_MSB 13
1755	/* The width in bits of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
1756	#define ALT_GPIO_CFG_REG1_DEBOUNCE_WIDTH 1
1757	/* The mask used to set the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */
1758	#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET_MSK 0x00002000
1759	/* The mask used to clear the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */
1760	#define ALT_GPIO_CFG_REG1_DEBOUNCE_CLR_MSK 0xffffdfff
1761	/* The reset value of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
1762	#define ALT_GPIO_CFG_REG1_DEBOUNCE_RESET 0x1
1763	/* Extracts the ALT_GPIO_CFG_REG1_DEBOUNCE field value from a register. */
1764	#define ALT_GPIO_CFG_REG1_DEBOUNCE_GET(value) (((value) & 0x00002000) >> 13)
1765	/* Produces a ALT_GPIO_CFG_REG1_DEBOUNCE register field value suitable for setting the register. */
1766	#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET(value) (((value) << 13) & 0x00002000)
1767
1768	/*
1769	* Field : Encoded GPIO Parameters Available - add_encoded_params
1770	*
1771	* Fixed to allow the indentification of the Designware IP component.
1772	*
1773	* Field Enumeration Values:
1774	*
1775	* Enum \| Value \| Description
1776	* :------------------------------------------------\|:------\|:--------------------------
1777	* ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS \| 0x1 \| Enable IP indentification
1778	*
1779	* Field Access Macros:
1780	*
1781	*/
1782	/*
1783	* Enumerated value for register field ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS
1784	*
1785	* Enable IP indentification
1786	*/
1787	#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1
1788
1789	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
1790	#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_LSB 14
1791	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
1792	#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_MSB 14
1793	/* The width in bits of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
1794	#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_WIDTH 1
1795	/* The mask used to set the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */
1796	#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET_MSK 0x00004000
1797	/* The mask used to clear the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */
1798	#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_CLR_MSK 0xffffbfff
1799	/* The reset value of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
1800	#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_RESET 0x1
1801	/* Extracts the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS field value from a register. */
1802	#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00004000) >> 14)
1803	/* Produces a ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value suitable for setting the register. */
1804	#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET(value) (((value) << 14) & 0x00004000)
1805
1806	/*
1807	* Field : ID Field - gpio_id
1808	*
1809	* Provides an ID code value
1810	*
1811	* Field Enumeration Values:
1812	*
1813	* Enum \| Value \| Description
1814	* :-----------------------------------\|:------\|:-------------
1815	* ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE \| 0x1 \| GPIO ID Code
1816	*
1817	* Field Access Macros:
1818	*
1819	*/
1820	/*
1821	* Enumerated value for register field ALT_GPIO_CFG_REG1_GPIO_ID
1822	*
1823	* GPIO ID Code
1824	*/
1825	#define ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE 0x1
1826
1827	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
1828	#define ALT_GPIO_CFG_REG1_GPIO_ID_LSB 15
1829	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
1830	#define ALT_GPIO_CFG_REG1_GPIO_ID_MSB 15
1831	/* The width in bits of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
1832	#define ALT_GPIO_CFG_REG1_GPIO_ID_WIDTH 1
1833	/* The mask used to set the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */
1834	#define ALT_GPIO_CFG_REG1_GPIO_ID_SET_MSK 0x00008000
1835	/* The mask used to clear the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */
1836	#define ALT_GPIO_CFG_REG1_GPIO_ID_CLR_MSK 0xffff7fff
1837	/* The reset value of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
1838	#define ALT_GPIO_CFG_REG1_GPIO_ID_RESET 0x1
1839	/* Extracts the ALT_GPIO_CFG_REG1_GPIO_ID field value from a register. */
1840	#define ALT_GPIO_CFG_REG1_GPIO_ID_GET(value) (((value) & 0x00008000) >> 15)
1841	/* Produces a ALT_GPIO_CFG_REG1_GPIO_ID register field value suitable for setting the register. */
1842	#define ALT_GPIO_CFG_REG1_GPIO_ID_SET(value) (((value) << 15) & 0x00008000)
1843
1844	/*
1845	* Field : Encoded ID Width Field - encoded_id_width
1846	*
1847	* This value is fixed at 32 bits.
1848	*
1849	* Field Enumeration Values:
1850	*
1851	* Enum \| Value \| Description
1852	* :--------------------------------------------\|:------\|:------------------
1853	* ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH \| 0x1f \| Width of ID Field
1854	*
1855	* Field Access Macros:
1856	*
1857	*/
1858	/*
1859	* Enumerated value for register field ALT_GPIO_CFG_REG1_ENC_ID_WIDTH
1860	*
1861	* Width of ID Field
1862	*/
1863	#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH 0x1f
1864
1865	/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
1866	#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_LSB 16
1867	/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
1868	#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_MSB 20
1869	/* The width in bits of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
1870	#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_WIDTH 5
1871	/* The mask used to set the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */
1872	#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET_MSK 0x001f0000
1873	/* The mask used to clear the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */
1874	#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_CLR_MSK 0xffe0ffff
1875	/* The reset value of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
1876	#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_RESET 0x1f
1877	/* Extracts the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH field value from a register. */
1878	#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_GET(value) (((value) & 0x001f0000) >> 16)
1879	/* Produces a ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value suitable for setting the register. */
1880	#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET(value) (((value) << 16) & 0x001f0000)
1881
1882	#ifndef __ASSEMBLY__
1883	/*
1884	* WARNING: The C register and register group struct declarations are provided for
1885	* convenience and illustrative purposes. They should, however, be used with
1886	* caution as the C language standard provides no guarantees about the alignment or
1887	* atomicity of device memory accesses. The recommended practice for writing
1888	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1889	* alt_write_word() functions.
1890	*
1891	* The struct declaration for register ALT_GPIO_CFG_REG1.
1892	*/
1893	struct ALT_GPIO_CFG_REG1_s
1894	{
1895	const uint32_t apb_data_width : 2; /* APB DATA WIDTH */
1896	const uint32_t num_ports : 2; /* NUM PORTS */
1897	const uint32_t porta_single_ctl : 1; /* PORT A SINGLE CTL */
1898	const uint32_t portb_single_ctl : 1; /* PORT B SINGLE CTL */
1899	const uint32_t portc_single_ctl : 1; /* PORT C SINGLE CTL */
1900	const uint32_t portd_single_ctl : 1; /* PORT D SINGLE CTL */
1901	const uint32_t hw_porta : 1; /* HW PORTA */
1902	uint32_t : 3; /* UNDEFINED */
1903	const uint32_t porta_intr : 1; /* Port A Interrupt Field */
1904	const uint32_t debounce : 1; /* Debounce Field */
1905	const uint32_t add_encoded_params : 1; /* Encoded GPIO Parameters Available */
1906	const uint32_t gpio_id : 1; /* ID Field */
1907	const uint32_t encoded_id_width : 5; /* Encoded ID Width Field */
1908	uint32_t : 11; /* UNDEFINED */
1909	};
1910
1911	/* The typedef declaration for register ALT_GPIO_CFG_REG1. */
1912	typedef volatile struct ALT_GPIO_CFG_REG1_s ALT_GPIO_CFG_REG1_t;
1913	#endif /* __ASSEMBLY__ */
1914
1915	/* The byte offset of the ALT_GPIO_CFG_REG1 register from the beginning of the component. */
1916	#define ALT_GPIO_CFG_REG1_OFST 0x74
1917	/* The address of the ALT_GPIO_CFG_REG1 register. */
1918	#define ALT_GPIO_CFG_REG1_ADDR(base) ALT_CAST(void , (ALT_CAST(char , (base)) + ALT_GPIO_CFG_REG1_OFST))
1919
1920	#ifndef __ASSEMBLY__
1921	/*
1922	* WARNING: The C register and register group struct declarations are provided for
1923	* convenience and illustrative purposes. They should, however, be used with
1924	* caution as the C language standard provides no guarantees about the alignment or
1925	* atomicity of device memory accesses. The recommended practice for writing
1926	* hardware drivers is to use the SoCAL access macros and alt_read_word() and
1927	* alt_write_word() functions.
1928	*
1929	* The struct declaration for register group ALT_GPIO.
1930	*/
1931	struct ALT_GPIO_s
1932	{
1933	volatile ALT_GPIO_SWPORTA_DR_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */
1934	volatile ALT_GPIO_SWPORTA_DDR_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */
1935	volatile uint32_t _pad_0x8_0x2f[10]; /* UNDEFINED */
1936	volatile ALT_GPIO_INTEN_t gpio_inten; /* ALT_GPIO_INTEN */
1937	volatile ALT_GPIO_INTMSK_t gpio_intmask; /* ALT_GPIO_INTMSK */
1938	volatile ALT_GPIO_INTTYPE_LEVEL_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */
1939	volatile ALT_GPIO_INT_POL_t gpio_int_polarity; /* ALT_GPIO_INT_POL */
1940	volatile ALT_GPIO_INTSTAT_t gpio_intstatus; /* ALT_GPIO_INTSTAT */
1941	volatile ALT_GPIO_RAW_INTSTAT_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */
1942	volatile ALT_GPIO_DEBOUNCE_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */
1943	volatile ALT_GPIO_PORTA_EOI_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */
1944	volatile ALT_GPIO_EXT_PORTA_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */
1945	volatile uint32_t _pad_0x54_0x5f[3]; /* UNDEFINED */
1946	volatile ALT_GPIO_LS_SYNC_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */
1947	volatile ALT_GPIO_ID_CODE_t gpio_id_code; /* ALT_GPIO_ID_CODE */
1948	volatile uint32_t _pad_0x68_0x6b; /* UNDEFINED */
1949	volatile ALT_GPIO_VER_ID_CODE_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */
1950	volatile ALT_GPIO_CFG_REG2_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */
1951	volatile ALT_GPIO_CFG_REG1_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */
1952	volatile uint32_t _pad_0x78_0x80[2]; /* UNDEFINED */
1953	};
1954
1955	/* The typedef declaration for register group ALT_GPIO. */
1956	typedef volatile struct ALT_GPIO_s ALT_GPIO_t;
1957	/* The struct declaration for the raw register contents of register group ALT_GPIO. */
1958	struct ALT_GPIO_raw_s
1959	{
1960	volatile uint32_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */
1961	volatile uint32_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */
1962	volatile uint32_t _pad_0x8_0x2f[10]; /* UNDEFINED */
1963	volatile uint32_t gpio_inten; /* ALT_GPIO_INTEN */
1964	volatile uint32_t gpio_intmask; /* ALT_GPIO_INTMSK */
1965	volatile uint32_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */
1966	volatile uint32_t gpio_int_polarity; /* ALT_GPIO_INT_POL */
1967	volatile uint32_t gpio_intstatus; /* ALT_GPIO_INTSTAT */
1968	volatile uint32_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */
1969	volatile uint32_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */
1970	volatile uint32_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */
1971	volatile uint32_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */
1972	volatile uint32_t _pad_0x54_0x5f[3]; /* UNDEFINED */
1973	volatile uint32_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */
1974	volatile uint32_t gpio_id_code; /* ALT_GPIO_ID_CODE */
1975	volatile uint32_t _pad_0x68_0x6b; /* UNDEFINED */
1976	volatile uint32_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */
1977	volatile uint32_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */
1978	volatile uint32_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */
1979	volatile uint32_t _pad_0x78_0x80[2]; /* UNDEFINED */
1980	};
1981
1982	/* The typedef declaration for the raw register contents of register group ALT_GPIO. */
1983	typedef volatile struct ALT_GPIO_raw_s ALT_GPIO_raw_t;
1984	#endif /* __ASSEMBLY__ */
1985
1986
1987	#ifdef __cplusplus
1988	}
1989	#endif /* __cplusplus */
1990	#endif /* __ALTERA_ALT_GPIO_H__ */
1991

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source: rtems/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h @ 2afb22b

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