source: rtems/bsps/arm/altera-cyclone-v/include/bsp/irq.h @ cd5573c

Last change on this file since cd5573c was cd5573c, checked in by Sebastian Huber <sebastian.huber@…>, on 06/19/21 at 10:40:57

bsps/irq: Add BSP_INTERRUPT_VECTOR_COUNT

Assert BSP_INTERRUPT_VECTOR_MAX + 1 == BSP_INTERRUPT_VECTOR_COUNT.

After building all BSPs with this patch, BSP_INTERRUPT_VECTOR_MAX can be
removed and replaced by BSP_INTERRUPT_VECTOR_COUNT. The
BSP_INTERRUPT_VECTOR_COUNT allows a default implementation which supports no
interrupt vector at all. Using COUNT instead of MAX may avoid some
interpretation issues, for example is the maximum value a valid vector number
or not.

Update #3269.
  • Property mode set to 100644
File size: 1.2 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup RTEMSBSPsARMCycVIRQ
5 */
6
7/*
8 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
9 *
10 *  embedded brains GmbH
11 *  Dornierstr. 4
12 *  82178 Puchheim
13 *  Germany
14 *  <info@embedded-brains.de>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 */
20
21#ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H
22#define LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H
23
24#ifndef ASM
25
26#include <rtems/irq.h>
27#include <rtems/irq-extension.h>
28
29#include <bsp/arm-a9mpcore-irq.h>
30#include <dev/irq/arm-gic-irq.h>
31#include <bsp/alt_interrupt_common.h>
32
33#ifdef __cplusplus
34extern "C" {
35#endif /* __cplusplus */
36
37/**
38 * @defgroup RTEMSBSPsARMCycVIRQ Interrupt Support
39 *
40 * @ingroup RTEMSBSPsARMCycV
41 *
42 * @ingroup bsp_interrupt
43 *
44 * @brief Intel Cyclone V Interrupt Support.
45 *
46 * @{
47 */
48
49/* Use interrupt IDs as defined in alt_interrupt_common.h */
50#define BSP_INTERRUPT_VECTOR_MAX ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ
51#define BSP_INTERRUPT_VECTOR_COUNT \
52  (ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ + 1)
53
54/** @} */
55
56#ifdef __cplusplus
57}
58#endif /* __cplusplus */
59
60#endif /* ASM */
61
62#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H */
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