1 | /*! \file |
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2 | * Altera - SoC Reset Manager |
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3 | */ |
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4 | |
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5 | /****************************************************************************** |
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6 | * |
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7 | * Copyright 2013 Altera Corporation. All Rights Reserved. |
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8 | * |
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9 | * Redistribution and use in source and binary forms, with or without |
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10 | * modification, are permitted provided that the following conditions are met: |
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11 | * |
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12 | * 1. Redistributions of source code must retain the above copyright notice, |
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13 | * this list of conditions and the following disclaimer. |
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14 | * |
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15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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16 | * this list of conditions and the following disclaimer in the documentation |
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17 | * and/or other materials provided with the distribution. |
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18 | * |
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19 | * 3. The name of the author may not be used to endorse or promote products |
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20 | * derived from this software without specific prior written permission. |
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21 | * |
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22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR |
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23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO |
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25 | * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
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26 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
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27 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
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30 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
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31 | * OF SUCH DAMAGE. |
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32 | * |
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33 | ******************************************************************************/ |
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34 | |
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35 | #ifndef __ALT_RESET_MGR_H__ |
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36 | #define __ALT_RESET_MGR_H__ |
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37 | |
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38 | #include "hwlib.h" |
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39 | #include <stdbool.h> |
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40 | |
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41 | #ifdef __cplusplus |
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42 | extern "C" |
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43 | { |
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44 | #endif /* __cplusplus */ |
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45 | |
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46 | /*! \addtogroup RST_MGR The Reset Manager |
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47 | * |
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48 | * The Reset Manager API defines functions for accessing, configuring, and |
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49 | * controlling the HPS reset behavior. |
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50 | * @{ |
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51 | */ |
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52 | |
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53 | /******************************************************************************/ |
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54 | /*! \addtogroup RST_MGR_STATUS Reset Status |
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55 | * |
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56 | * This functional group provides information on various aspects of SoC reset |
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57 | * status and timeout events. |
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58 | * |
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59 | * @{ |
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60 | */ |
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61 | |
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62 | /******************************************************************************/ |
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63 | /*! |
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64 | * This type definition enumerates the set of reset causes and timeout events as |
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65 | * register mask values. |
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66 | */ |
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67 | typedef enum ALT_RESET_EVENT_e |
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68 | { |
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69 | /*! Power-On Voltage Detector Cold Reset */ |
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70 | ALT_RESET_EVENT_PORVOLTRST = 0x00000001, |
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71 | |
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72 | /*! nPOR Pin Cold Reset */ |
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73 | ALT_RESET_EVENT_NPORPINRST = 0x00000002, |
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74 | |
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75 | /*! FPGA Core Cold Reset */ |
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76 | ALT_RESET_EVENT_FPGACOLDRST = 0x00000004, |
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77 | |
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78 | /*! CONFIG_IO Cold Reset */ |
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79 | ALT_RESET_EVENT_CONFIGIOCOLDRST = 0x00000008, |
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80 | |
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81 | /*! Software Cold Reset */ |
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82 | ALT_RESET_EVENT_SWCOLDRST = 0x00000010, |
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83 | |
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84 | /*! nRST Pin Warm Reset */ |
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85 | ALT_RESET_EVENT_NRSTPINRST = 0x00000100, |
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86 | |
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87 | /*! FPGA Core Warm Reset */ |
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88 | ALT_RESET_EVENT_FPGAWARMRST = 0x00000200, |
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89 | |
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90 | /*! Software Warm Reset */ |
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91 | ALT_RESET_EVENT_SWWARMRST = 0x00000400, |
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92 | |
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93 | /*! MPU Watchdog 0 Warm Reset */ |
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94 | ALT_RESET_EVENT_MPUWD0RST = 0x00001000, |
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95 | |
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96 | /*! MPU Watchdog 1 Warm Reset */ |
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97 | ALT_RESET_EVENT_MPUWD1RST = 0x00002000, |
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98 | |
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99 | /*! L4 Watchdog 0 Warm Reset */ |
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100 | ALT_RESET_EVENT_L4WD0RST = 0x00004000, |
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101 | |
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102 | /*! L4 Watchdog 1 Warm Reset */ |
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103 | ALT_RESET_EVENT_L4WD1RST = 0x00008000, |
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104 | |
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105 | /*! FPGA Core Debug Reset */ |
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106 | ALT_RESET_EVENT_FPGADBGRST = 0x00040000, |
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107 | |
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108 | /*! DAP Debug Reset */ |
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109 | ALT_RESET_EVENT_CDBGREQRST = 0x00080000, |
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110 | |
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111 | /*! SDRAM Self-Refresh Timeout */ |
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112 | ALT_RESET_EVENT_SDRSELFREFTIMEOUT = 0x01000000, |
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113 | |
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114 | /*! FPGA manager handshake Timeout */ |
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115 | ALT_RESET_EVENT_FPGAMGRHSTIMEOUT = 0x02000000, |
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116 | |
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117 | /*! SCAN manager handshake Timeout */ |
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118 | ALT_RESET_EVENT_SCANHSTIMEOUT = 0x04000000, |
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119 | |
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120 | /*! FPGA handshake Timeout */ |
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121 | ALT_RESET_EVENT_FPGAHSTIMEOUT = 0x08000000, |
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122 | |
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123 | /*! ETR Stall Timeout */ |
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124 | ALT_RESET_EVENT_ETRSTALLTIMEOUT = 0x10000000 |
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125 | } ALT_RESET_EVENT_t; |
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126 | |
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127 | /******************************************************************************/ |
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128 | /*! |
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129 | * Gets the reset and timeout events that caused the last reset. |
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130 | * |
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131 | * The ALT_RESET_EVENT_t enumeration values should be used to selectively |
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132 | * examine the returned reset cause(s). |
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133 | * |
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134 | * \returns A mask of the reset and/or timeout events that caused the last |
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135 | * reset. |
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136 | */ |
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137 | uint32_t alt_reset_event_get(void); |
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138 | |
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139 | /******************************************************************************/ |
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140 | /*! |
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141 | * Clears the reset and timeout events that caused the last reset. |
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142 | * |
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143 | * \param event_mask |
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144 | * A mask of the selected reset and timeout events to clear in the |
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145 | * Reset Manager \e stat register. The mask selection can be formed |
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146 | * using the ALT_RESET_EVENT_t enumeration values. |
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147 | * |
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148 | * \retval ALT_E_SUCCESS The operation was succesful. |
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149 | * \retval ALT_E_ERROR The operation failed. |
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150 | */ |
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151 | ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask); |
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152 | |
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153 | /*! @} */ |
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154 | |
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155 | /******************************************************************************/ |
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156 | /*! \addtogroup RST_MGR_CTRL Reset Control |
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157 | * |
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158 | * This functional group provides global and selective reset control for the SoC |
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159 | * and its constituent modules. |
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160 | * |
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161 | * @{ |
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162 | */ |
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163 | |
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164 | /******************************************************************************/ |
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165 | /*! |
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166 | * Initiate a cold reset of the SoC. |
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167 | * |
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168 | * If this function is successful, then it should never return. |
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169 | * |
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170 | * \retval ALT_E_SUCCESS The operation was succesful. |
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171 | * \retval ALT_E_ERROR The operation failed. |
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172 | */ |
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173 | ALT_STATUS_CODE alt_reset_cold_reset(void); |
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174 | |
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175 | /******************************************************************************/ |
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176 | /*! |
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177 | * Initiate a warm reset of the SoC. |
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178 | * |
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179 | * Perform a hardware sequenced warm reset of the SoC. A hardware sequenced |
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180 | * reset handshake with certain modules can optionally be requested in an |
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181 | * attempt to ensure an orderly reset transition. |
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182 | * |
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183 | * \param warm_reset_delay |
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184 | * Specifies the number of cycles after the Reset Manager releases |
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185 | * the Clock Manager reset before releasing any other hardware |
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186 | * controlled resets. Value must be greater than 16 and less than |
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187 | * 256. |
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188 | * |
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189 | * \param nRST_pin_clk_assertion |
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190 | * Specifies that number of clock cycles (osc1_clk?) to externally |
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191 | * assert the warm reset pin (nRST). 0 <= \e nRST_pin_clk_assertion <= |
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192 | * (2**20 - 1). A value of 0 prevents any assertion of nRST. |
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193 | * |
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194 | * \param sdram_refresh |
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195 | * Controls whether the contents of SDRAM survive a hardware |
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196 | * sequenced warm reset. The reset manager requests the SDRAM |
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197 | * controller to put SDRAM devices into self-refresh mode before |
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198 | * asserting warm reset signals. An argument value of \b true |
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199 | * enables the option, \b false disables the option. |
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200 | * |
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201 | * \param fpga_mgr_handshake |
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202 | * Controls whether a handshake between the reset manager and FPGA |
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203 | * manager occurs before a warm reset. The handshake is used to |
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204 | * warn the FPGA manager that a warm reset is imminent so it can |
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205 | * prepare for it by driving its output clock to a quiescent state |
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206 | * to avoid glitches. An argument value of \b true enables the |
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207 | * option, \b false disables the option. |
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208 | * |
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209 | * \param scan_mgr_handshake |
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210 | * Controls whether a handshake between the reset manager and scan |
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211 | * manager occurs before a warm reset. The handshake is used to |
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212 | * warn the scan manager that a warm reset is imminent so it can |
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213 | * prepare for it by driving its output clock to a quiescent state |
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214 | * to avoid glitches. An argument value of \b true enables the |
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215 | * option, \b false disables the option. |
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216 | * |
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217 | * \param fpga_handshake |
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218 | * Controls whether a handshake between the reset manager and the |
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219 | * FPGA occurs before a warm reset. The handshake is used to warn |
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220 | * the FPGA that a warm reset is imminent so that the FPGA prepare |
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221 | * for the reset event in soft IP. An argument value of \b true |
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222 | * enables the option, \b false disables the option. |
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223 | * |
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224 | * \param etr_stall |
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225 | * Controls whether the ETR is requested to idle its AXI master |
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226 | * interface (i.e. finish outstanding transactions and not initiate |
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227 | * any more) to the L3 Interconnect before a warm reset. An |
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228 | * argument value of \b true enables the option, \b false disables |
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229 | * the option. |
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230 | * |
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231 | * \retval ALT_E_SUCCESS The operation was succesful. |
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232 | * \retval ALT_E_ERROR The operation failed. |
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233 | */ |
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234 | ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay, |
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235 | uint32_t nRST_pin_clk_assertion, |
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236 | bool sdram_refresh, |
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237 | bool fpga_mgr_handshake, |
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238 | bool scan_mgr_handshake, |
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239 | bool fpga_handshake, |
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240 | bool etr_stall); |
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241 | |
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242 | #if 0 |
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243 | /*! \addtogroup RST_MGR_MPU |
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244 | * |
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245 | * This functional group provides reset control for the Cortex-A9 MPU module. |
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246 | * |
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247 | * @{ |
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248 | */ |
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249 | |
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250 | /*! @} */ |
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251 | |
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252 | /*! \addtogroup RST_MGR_PERIPH |
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253 | * |
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254 | * This functional group provides inidividual reset control for the HPS |
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255 | * peripheral modules. |
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256 | * |
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257 | * @{ |
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258 | */ |
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259 | |
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260 | /*! @} */ |
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261 | |
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262 | /*! \addtogroup RST_MGR_BRG |
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263 | * |
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264 | * This functional group provides inidividual reset control for the bridge |
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265 | * interfaces between the HPS and FPGA. |
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266 | * |
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267 | * @{ |
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268 | */ |
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269 | |
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270 | /*! @} */ |
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271 | |
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272 | /*! \addtogroup RST_MGR_MISC |
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273 | * |
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274 | * This functional group provides inidividual reset control for miscellaneous |
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275 | * HPS modules. |
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276 | * |
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277 | * @{ |
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278 | */ |
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279 | |
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280 | /*! @} */ |
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281 | |
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282 | #endif |
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283 | |
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284 | /*! @} */ |
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285 | |
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286 | /*! @} */ |
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287 | |
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288 | #ifdef __cplusplus |
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289 | } |
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290 | #endif /* __cplusplus */ |
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291 | #endif /* __ALT_RESET_MGR_H__ */ |
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