source: rtems/bsps/arm/altera-cyclone-v/include/bsp/alt_dma_common.h @ 9d41fca

5
Last change on this file since 9d41fca was 9d41fca, checked in by Sebastian Huber <sebastian.huber@…>, on 02/27/19 at 10:39:29

bsp/altera-cyclone-v: Adjust Doxygen file groups

Update #3707.
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1/**
2 * @file
3 *
4 * @ingroup RTEMSBSPsARMCycVContrib
5 */
6
7/******************************************************************************
8 *
9 * Copyright 2013 Altera Corporation. All Rights Reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 *
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 *
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 *
21 * 3. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
27 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
33 * OF SUCH DAMAGE.
34 *
35 ******************************************************************************/
36
37#ifndef __ALT_DMA_COMMON_H__
38#define __ALT_DMA_COMMON_H__
39
40#ifdef __cplusplus
41extern "C"
42{
43#endif  /* __cplusplus */
44
45/*!
46 * \addtogroup ALT_DMA_COMMON DMA Controller Common API Definitions
47 *
48 * This module contains the common definitions for the DMA controller related
49 * APIs.
50 *
51 * @{
52 */
53
54/*!
55 * This type definition enumerates the DMA controller channel threads.
56 */
57typedef enum ALT_DMA_CHANNEL_e
58{
59    ALT_DMA_CHANNEL_0 = 0, /*!< DMA Channel Thread 0 */
60    ALT_DMA_CHANNEL_1 = 1, /*!< DMA Channel Thread 1 */
61    ALT_DMA_CHANNEL_2 = 2, /*!< DMA Channel Thread 2 */
62    ALT_DMA_CHANNEL_3 = 3, /*!< DMA Channel Thread 3 */
63    ALT_DMA_CHANNEL_4 = 4, /*!< DMA Channel Thread 4 */
64    ALT_DMA_CHANNEL_5 = 5, /*!< DMA Channel Thread 5 */
65    ALT_DMA_CHANNEL_6 = 6, /*!< DMA Channel Thread 6 */
66    ALT_DMA_CHANNEL_7 = 7  /*!< DMA Channel Thread 7 */
67}
68ALT_DMA_CHANNEL_t;
69
70/*!
71 * This type definition enumerates the SoC system peripherals implementing the
72 * required request interface that enables direct DMA transfers to/from the
73 * device.
74 *
75 * FPGA soft IP interface to the DMA are required to comply with the Synopsys
76 * protocol.
77 *
78 * Request interface numbers 4 through 7 are multiplexed between the CAN
79 * controllers and soft logic implemented in the FPGA fabric. The selection
80 * between the CAN controller and FPGA interfaces is determined at DMA
81 * initialization.
82 */
83typedef enum ALT_DMA_PERIPH_e
84{
85    ALT_DMA_PERIPH_FPGA_0             = 0,  /*!< FPGA soft IP interface 0 */
86    ALT_DMA_PERIPH_FPGA_1             = 1,  /*!< FPGA soft IP interface 1 */
87    ALT_DMA_PERIPH_FPGA_2             = 2,  /*!< FPGA soft IP interface 2 */
88    ALT_DMA_PERIPH_FPGA_3             = 3,  /*!< FPGA soft IP interface 3 */
89
90    ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4,  /*!< Selectively MUXed FPGA 4 or CAN 0 interface 1 */
91    ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5,  /*!< Selectively MUXed FPGA 5 or CAN 0 interface 2 */
92    ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6,  /*!< Selectively MUXed FPGA 6 or CAN 1 interface 1 */
93    ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7,  /*!< Selectively MUXed FPGA 7 or CAN 1 interface 2 */
94
95    ALT_DMA_PERIPH_FPGA_4             = 4,  /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */
96    ALT_DMA_PERIPH_FPGA_5             = 5,  /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */
97    ALT_DMA_PERIPH_FPGA_6             = 6,  /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */
98    ALT_DMA_PERIPH_FPGA_7             = 7,  /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */
99
100    ALT_DMA_PERIPH_CAN0_IF1           = 4,  /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */
101    ALT_DMA_PERIPH_CAN0_IF2           = 5,  /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */
102    ALT_DMA_PERIPH_CAN1_IF1           = 6,  /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */
103    ALT_DMA_PERIPH_CAN1_IF2           = 7,  /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */
104
105    ALT_DMA_PERIPH_I2C0_TX            = 8,  /*!< I<sup>2</sup>C 0 TX */
106    ALT_DMA_PERIPH_I2C0_RX            = 9,  /*!< I<sup>2</sup>C 0 RX */
107    ALT_DMA_PERIPH_I2C1_TX            = 10, /*!< I<sup>2</sup>C 1 TX */
108    ALT_DMA_PERIPH_I2C1_RX            = 11, /*!< I<sup>2</sup>C 1 RX */
109    ALT_DMA_PERIPH_I2C2_TX            = 12, /*!< I<sup>2</sup>C 2 TX */
110    ALT_DMA_PERIPH_I2C2_RX            = 13, /*!< I<sup>2</sup>C 2 RX */
111    ALT_DMA_PERIPH_I2C3_TX            = 14, /*!< I<sup>2</sup>C 3 TX */
112    ALT_DMA_PERIPH_I2C3_RX            = 15, /*!< I<sup>2</sup>C 3 RX */
113    ALT_DMA_PERIPH_SPI0_MASTER_TX     = 16, /*!< SPI 0 Master TX */
114    ALT_DMA_PERIPH_SPI0_MASTER_RX     = 17, /*!< SPI 0 Master RX */
115    ALT_DMA_PERIPH_SPI0_SLAVE_TX      = 18, /*!< SPI 0 Slave TX */
116    ALT_DMA_PERIPH_SPI0_SLAVE_RX      = 19, /*!< SPI 0 Slave RX */
117    ALT_DMA_PERIPH_SPI1_MASTER_TX     = 20, /*!< SPI 1 Master TX */
118    ALT_DMA_PERIPH_SPI1_MASTER_RX     = 21, /*!< SPI 1 Master RX */
119    ALT_DMA_PERIPH_SPI1_SLAVE_TX      = 22, /*!< SPI 1 Slave TX */
120    ALT_DMA_PERIPH_SPI1_SLAVE_RX      = 23, /*!< SPI 1 Slave RX */
121    ALT_DMA_PERIPH_QSPI_FLASH_TX      = 24, /*!< QSPI Flash TX */
122    ALT_DMA_PERIPH_QSPI_FLASH_RX      = 25, /*!< QSPI Flash RX */
123    ALT_DMA_PERIPH_STM                = 26, /*!< System Trace Macrocell */
124    ALT_DMA_PERIPH_RESERVED           = 27, /*!< Reserved */
125    ALT_DMA_PERIPH_UART0_TX           = 28, /*!< UART 0 TX */
126    ALT_DMA_PERIPH_UART0_RX           = 29, /*!< UART 0 RX */
127    ALT_DMA_PERIPH_UART1_TX           = 30, /*!< UART 1 TX */
128    ALT_DMA_PERIPH_UART1_RX           = 31  /*!< UART 1 RX */
129}
130ALT_DMA_PERIPH_t;
131
132/*!
133 * This type enumerates the DMA security state options available.
134 */
135typedef enum ALT_DMA_SECURITY_e
136{
137    ALT_DMA_SECURITY_DEFAULT   = 0, /*!< Use the default security value (e.g. reset default) */
138    ALT_DMA_SECURITY_SECURE    = 1, /*!< Secure */
139    ALT_DMA_SECURITY_NONSECURE = 2  /*!< Non-secure */
140}
141ALT_DMA_SECURITY_t;
142
143/*!
144 * This type definition enumerates the DMA event-interrupt resources.
145 */
146typedef enum ALT_DMA_EVENT_e
147{
148    ALT_DMA_EVENT_0     = 0, /*!< DMA Event 0 */
149    ALT_DMA_EVENT_1     = 1, /*!< DMA Event 1 */
150    ALT_DMA_EVENT_2     = 2, /*!< DMA Event 2 */
151    ALT_DMA_EVENT_3     = 3, /*!< DMA Event 3 */
152    ALT_DMA_EVENT_4     = 4, /*!< DMA Event 4 */
153    ALT_DMA_EVENT_5     = 5, /*!< DMA Event 5 */
154    ALT_DMA_EVENT_6     = 6, /*!< DMA Event 6 */
155    ALT_DMA_EVENT_7     = 7, /*!< DMA Event 7 */
156    ALT_DMA_EVENT_ABORT = 8  /*!< DMA Abort Event */
157}
158ALT_DMA_EVENT_t;
159
160/*!
161 * @}
162 */
163
164#ifdef __cplusplus
165}
166#endif /* __cplusplus */
167
168#endif /* __ALT_DMA_COMMON_H__ */
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