1 | /****************************************************************************** |
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2 | * |
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3 | * Copyright 2013 Altera Corporation. All Rights Reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions are met: |
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7 | * |
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8 | * 1. Redistributions of source code must retain the above copyright notice, |
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9 | * this list of conditions and the following disclaimer. |
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10 | * |
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11 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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12 | * this list of conditions and the following disclaimer in the documentation |
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13 | * and/or other materials provided with the distribution. |
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14 | * |
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15 | * 3. The name of the author may not be used to endorse or promote products |
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16 | * derived from this software without specific prior written permission. |
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17 | * |
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18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR |
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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20 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO |
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21 | * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
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22 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
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23 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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24 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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25 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
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26 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
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27 | * OF SUCH DAMAGE. |
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28 | * |
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29 | ******************************************************************************/ |
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30 | |
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31 | #ifndef __ALT_CACHE_H__ |
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32 | #define __ALT_CACHE_H__ |
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33 | |
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34 | #include "hwlib.h" |
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35 | |
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36 | #ifdef __cplusplus |
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37 | extern "C" |
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38 | { |
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39 | #endif |
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40 | |
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41 | /*! |
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42 | * \addtogroup CACHE_MGR Cache Management API |
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43 | * |
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44 | * This module defines the cache management API for enabling and disabling L1 |
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45 | * data cache, L1 instruction cache, L1 dynamic branch prediction caches, L1 |
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46 | * TLB cache, and L2 cache in the SoC. As well, many it allows users to perform |
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47 | * cache maintenance operations on these caches. This includes the following |
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48 | * operations: |
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49 | * * Invalidate: Marks the cache line as being invalid, freeing up the space |
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50 | * to cache other data. All APIs which enable caches invalidates the memory |
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51 | * before being enabling the cache. |
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52 | * * Clean: If the cache line is dirty, it synchronizes the cache line data |
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53 | * with the upper level memory system and marks that line as clean. All APIs |
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54 | * which disable caches cleans the memory before disabling the cache. |
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55 | * * Purge: A term used in this API as a short form for clean and invalidate. |
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56 | * This operation cleans and invalidates a cache line in that order, as a |
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57 | * single command to the cache controller. |
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58 | * |
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59 | * The following reference materials were used in the design of this API: |
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60 | * * ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition |
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61 | * * Cortex™-A9 Technical Reference Manual |
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62 | * * Cortex™-A9 MPCore Technical Reference Manual |
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63 | * * CoreLink™ Level 2 Cache Controller L2C-310 Technical Reference |
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64 | * Manual |
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65 | * |
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66 | * @{ |
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67 | */ |
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68 | |
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69 | /*! |
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70 | * \addtogroup CACHE_SYS System Level Cache Management API |
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71 | * |
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72 | * This API group provides cache maintenance operations which affects multiple |
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73 | * cache levels. |
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74 | * |
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75 | * The enable and disable functions enables and disables all caches in the |
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76 | * system respectively. For caches shared by the CPU core(s), particularly the |
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77 | * L2 cache, once that cache is enabled or disabled it will not be invalidated |
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78 | * or cleaned again respectively. This allows the safe system-wide enable and |
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79 | * disable to be used in single-core and multi-core scenarios. |
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80 | * |
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81 | * For cache maintenance operations, this API implements the procedures |
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82 | * outlined in the L2C-310 Technical Reference Manual, section 3.3.10, |
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83 | * subsection "System cache maintenance considerations". This allows for a |
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84 | * convenient way to invalidate, clean, or clean and invalidate cache data from |
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85 | * the L1 to L2 to L3 while avoiding any potential race conditions in |
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86 | * mutli-core or multi-master scenarios. It assumes that the L1 and L2 cache is |
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87 | * set in "non-exclusive" mode. This means a segment of data can reside in both |
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88 | * the L1 and L2 simultaneously. This is the default mode for caches in the |
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89 | * system. |
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90 | * |
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91 | * The current implementation of the system cache APIs assumes that the MMU is |
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92 | * configured with a flat memory mapping or that every virtual address matches |
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93 | * perfectly with the physical address. This restriction may be lifted in a |
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94 | * future release of the cache API implementation. |
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95 | * |
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96 | * @{ |
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97 | */ |
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98 | |
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99 | /*! |
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100 | * Enables support for a non-flat virtual memory. A flat virtual memory is |
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101 | * where every virtual address matches exactly to the physical address, making |
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102 | * the virtual to physical translation trivial. Adding support for non-flat |
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103 | * adds some overhead for the VA to PA translation and error detection. |
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104 | * |
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105 | * To enable non-flat virtual memory support, defined |
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106 | * ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY=1 in your Makefile when compiling |
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107 | * HWLibs. |
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108 | */ |
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109 | #ifndef ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY |
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110 | #define ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY (0) |
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111 | #endif |
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112 | |
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113 | /*! |
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114 | * This is the system wide cache line size, given in bytes. |
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115 | */ |
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116 | #define ALT_CACHE_LINE_SIZE 32 |
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117 | |
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118 | /*! |
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119 | * Enables all caches and features which improve reliability and speed on all |
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120 | * cache controllers visible to the current CPU core. This includes parity |
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121 | * error detection. Cache controllers visible to multiple CPU cores, for |
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122 | * example the L2, will first be checked to be disabled before being enabled. |
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123 | * All necessary cache maintenance operations will be done automatically. |
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124 | * |
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125 | * \retval ALT_E_SUCCESS The operation was successful. |
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126 | * \retval ALT_E_ERROR The operation failed. |
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127 | */ |
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128 | ALT_STATUS_CODE alt_cache_system_enable(void); |
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129 | |
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130 | /*! |
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131 | * Disables all cache controllers visible to the current CPU core. Cache |
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132 | * controllers visible to multiple CPU cores, for example the L2, will first |
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133 | * be checked to be enabled before being disabled. All necessary cache |
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134 | * maintenance operations will be done automatically. |
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135 | * |
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136 | * \retval ALT_E_SUCCESS The operation was successful. |
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137 | * \retval ALT_E_ERROR The operation failed. |
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138 | */ |
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139 | ALT_STATUS_CODE alt_cache_system_disable(void); |
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140 | |
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141 | /*! |
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142 | * Invalidates the specified contents of all cache levels visible to the |
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143 | * current CPU core for the given memory segment. |
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144 | * |
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145 | * The memory segment address and length specified must align to the |
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146 | * characteristics of the cache line. This means the address and length must be |
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147 | * multiples of the cache line size. To determine the cache line size, use the |
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148 | * \b ALT_CACHE_LINE_SIZE macro. |
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149 | * |
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150 | * The following pseudocode outlines the operations carried out by this |
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151 | * function: |
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152 | * -# L2 invalidate address(es) |
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153 | * -# L2 cache sync |
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154 | * -# L1 invalidate address(es) |
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155 | * -# DSB instruction |
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156 | * |
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157 | * The current implementation of the system cache APIs assumes that the MMU is |
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158 | * configured with a flat memory mapping or that every virtual address matches |
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159 | * perfectly with the physical address. This restriction may be lifted in a |
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160 | * future release of the cache API implementation. |
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161 | * |
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162 | * \param vaddress |
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163 | * The virtual address of the memory segment to be invalidated. |
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164 | * |
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165 | * \param length |
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166 | * The length of the memory segment to be invalidated. |
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167 | * |
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168 | * \retval ALT_E_SUCCESS The operation was successful. |
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169 | * \retval ALT_E_ERROR The operation failed. |
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170 | * \retval ALT_E_BAD_ARG The memory segment is invalid. |
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171 | * \retval ALT_E_TMO The memory operation timed out. |
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172 | */ |
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173 | ALT_STATUS_CODE alt_cache_system_invalidate(void * vaddress, size_t length); |
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174 | |
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175 | /*! |
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176 | * Cleans the specified contents of all cache levels visible to the current |
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177 | * CPU core for the given memory segment. |
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178 | * |
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179 | * The memory segment address and length specified must align to the |
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180 | * characteristics of the cache line. This means the address and length must be |
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181 | * multiples of the cache line size. To determine the cache line size, use the |
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182 | * \b ALT_CACHE_LINE_SIZE macro. |
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183 | * |
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184 | * The following pseudocode outlines the operations carried out by this |
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185 | * function: |
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186 | * -# L1 clean address(es) |
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187 | * -# DSB instruction |
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188 | * -# L2 clean address(es) |
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189 | * -# L2 cache sync |
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190 | * |
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191 | * The current implementation of the system cache APIs assumes that the MMU is |
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192 | * configured with a flat memory mapping or that every virtual address matches |
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193 | * perfectly with the physical address. This restriction may be lifted in a |
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194 | * future release of the cache API implementation. |
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195 | * |
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196 | * \param vaddress |
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197 | * The virtual address of the memory segment to be cleaned. |
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198 | * |
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199 | * \param length |
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200 | * The length of the memory segment to be cleaned. |
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201 | * |
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202 | * \retval ALT_E_SUCCESS The operation was successful. |
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203 | * \retval ALT_E_ERROR The operation failed. |
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204 | * \retval ALT_E_BAD_ARG The memory segment is invalid. |
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205 | * \retval ALT_E_TMO The memory operation timed out. |
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206 | */ |
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207 | ALT_STATUS_CODE alt_cache_system_clean(void * vaddress, size_t length); |
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208 | |
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209 | /*! |
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210 | * Cleans and invalidates the specified contents of all cache levels visible |
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211 | * to the current CPU core for the given memory segment. |
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212 | * |
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213 | * The memory segment address and length specified must align to the |
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214 | * characteristics of the cache line. This means the address and length must be |
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215 | * multiples of the cache line size. To determine the cache line size, use the |
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216 | * \b ALT_CACHE_LINE_SIZE macro. |
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217 | * |
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218 | * The following pseudocode outlines the operations carried out by this |
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219 | * function: |
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220 | * -# L1 clean address(es) |
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221 | * -# DSB instruction |
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222 | * -# L2 clean and invalidate address(es) |
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223 | * -# L2 cache sync |
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224 | * -# L1 invalidate address(es) |
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225 | * -# DSB instruction |
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226 | * |
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227 | * The current implementation of the system cache APIs assumes that the MMU is |
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228 | * configured with a flat memory mapping or that every virtual address matches |
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229 | * perfectly with the physical address. This restriction may be lifted in a |
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230 | * future release of the cache API implementation. |
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231 | * |
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232 | * \param vaddress |
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233 | * The virtual address of the memory segment to be purged. |
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234 | * |
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235 | * \param length |
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236 | * The length of the memory segment to be purged. |
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237 | * |
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238 | * \retval ALT_E_SUCCESS The operation was successful. |
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239 | * \retval ALT_E_ERROR The operation failed. |
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240 | * \retval ALT_E_BAD_ARG The memory segment is invalid. |
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241 | * \retval ALT_E_TMO The memory operation timed out. |
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242 | */ |
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243 | ALT_STATUS_CODE alt_cache_system_purge(void * vaddress, size_t length); |
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244 | |
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245 | /*! |
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246 | * @} |
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247 | */ |
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248 | |
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249 | /*! |
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250 | * \addtogroup CACHE_L1 L1 Cache Management API |
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251 | * |
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252 | * This API group provides functions to interact with various components of the |
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253 | * L1 cache on the SoCFPGA. This includes the following cache components: |
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254 | * * Instruction Cache |
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255 | * * Data Cache |
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256 | * * Parity error detection |
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257 | * * Dynamic branch prediction |
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258 | * * Data prefetching |
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259 | * |
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260 | * The API within this group only affects the L1 cache on the current CPU. To |
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261 | * interact the L1 cache on another CPU, the API must be called from that other |
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262 | * CPU. |
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263 | * |
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264 | * With respect to bring-up, the L1 and L2 cache controller setups are fully |
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265 | * independent. The L2 can be setup at any time, before or after the L1 is setup. |
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266 | * \internal |
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267 | * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up". |
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268 | * \endinternal |
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269 | * |
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270 | * @{ |
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271 | */ |
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272 | |
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273 | /*! |
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274 | * Enables all L1 caches and features on the current CPU core. This includes |
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275 | * the instruction cache, data cache, parity error detection, branch target |
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276 | * address cache, global history buffer, and data prefetching. All necessary |
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277 | * maintenance tasks will be taken care of. |
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278 | * |
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279 | * This function should not be mixed with other L1 cache related functions |
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280 | * which enable or disable caches individually. |
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281 | * |
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282 | * \retval ALT_E_SUCCESS The operation was successful. |
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283 | * \retval ALT_E_ERROR The operation failed. |
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284 | */ |
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285 | ALT_STATUS_CODE alt_cache_l1_enable_all(void); |
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286 | |
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287 | /*! |
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288 | * Disables all L1 caches and features on the current CPU core. This includes |
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289 | * the instruction cache, data cache, parity error detection, branch target |
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290 | * address cache, global history buffer, and data prefetching. All necessary |
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291 | * maintenance tasks will be taken care of. |
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292 | * |
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293 | * This function should not be mixed with other L1 cache related functions |
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294 | * which enable or disable caches individually. |
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295 | * |
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296 | * \retval ALT_E_SUCCESS The operation was successful. |
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297 | * \retval ALT_E_ERROR The operation failed. |
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298 | */ |
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299 | ALT_STATUS_CODE alt_cache_l1_disable_all(void); |
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300 | |
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301 | /*! |
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302 | * Enables the L1 instruction cache on the current CPU core. If the cache is |
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303 | * already enabled, nothing is done. Otherwise the instruction cache is first |
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304 | * invalidated before being enabled. |
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305 | * |
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306 | * \retval ALT_E_SUCCESS The operation was successful. |
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307 | * \retval ALT_E_ERROR The operation failed. |
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308 | */ |
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309 | ALT_STATUS_CODE alt_cache_l1_instruction_enable(void); |
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310 | |
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311 | /*! |
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312 | * Disables the L1 instruction cache on the current CPU core. |
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313 | * |
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314 | * \retval ALT_E_SUCCESS The operation was successful. |
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315 | * \retval ALT_E_ERROR The operation failed. |
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316 | */ |
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317 | ALT_STATUS_CODE alt_cache_l1_instruction_disable(void); |
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318 | |
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319 | /*! |
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320 | * Returns \b true when the L1 instruction cache is enabled and \b false when |
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321 | * it is disabled on the current CPU core. |
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322 | * |
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323 | * \retval true The L1 instruction cache is enabled. |
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324 | * \retval false The L1 instruction cache is disabled. |
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325 | */ |
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326 | bool alt_cache_l1_instruction_is_enabled(void); |
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327 | |
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328 | /*! |
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329 | * Invalidates the contents of the L1 instruction cache on the current CPU |
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330 | * core. |
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331 | * |
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332 | * Normally this is done automatically as part of |
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333 | * alt_cache_l1_instruction_enable(), but in certain circumstances it may be |
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334 | * necessary to invalidate it manually. An example of this situation is when |
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335 | * the address space is remapped and the processor executes instructions from |
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336 | * the new memory area. |
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337 | * |
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338 | * \retval ALT_E_SUCCESS The operation was successful. |
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339 | * \retval ALT_E_ERROR The operation failed. |
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340 | */ |
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341 | ALT_STATUS_CODE alt_cache_l1_instruction_invalidate(void); |
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342 | |
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343 | /*! |
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344 | * Enables the L1 data cache on the current CPU core. |
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345 | * |
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346 | * If the cache is already enabled nothing is done. Otherwise the data cache is |
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347 | * first invalidated before being enabled. |
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348 | * |
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349 | * \retval ALT_E_SUCCESS The operation was successful. |
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350 | * \retval ALT_E_ERROR The operation failed. |
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351 | */ |
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352 | ALT_STATUS_CODE alt_cache_l1_data_enable(void); |
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353 | |
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354 | /*! |
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355 | * Disables the L1 data cache on the current CPU core. |
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356 | * |
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357 | * If the cache is already disabled nothing is done. Otherwise the data cache |
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358 | * is first cleaned before being disabled. |
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359 | * |
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360 | * \retval ALT_E_SUCCESS The operation was successful. |
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361 | * \retval ALT_E_ERROR The operation failed. |
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362 | */ |
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363 | ALT_STATUS_CODE alt_cache_l1_data_disable(void); |
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364 | |
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365 | /*! |
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366 | * Returns \b true when the L1 data cache is enabled and \b false when it is |
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367 | * disabled on the current CPU core. |
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368 | * |
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369 | * \retval true The L1 data cache is enabled. |
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370 | * \retval false The L1 data cache is disabled. |
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371 | */ |
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372 | bool alt_cache_l1_data_is_enabled(void); |
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373 | |
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374 | /*! |
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375 | * Invalidates the specified contents of the L1 data cache on the current CPU |
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376 | * core for the given memory segment. |
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377 | * |
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378 | * The memory segment address and length specified must align to the |
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379 | * characteristics of the cache line. This means the address and length must be |
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380 | * multiples of the cache line size. To determine the cache line size, use the |
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381 | * \b ALT_CACHE_LINE_SIZE macro. |
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382 | * |
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383 | * \param vaddress |
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384 | * The virtual address of the memory segment to be invalidated. |
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385 | * |
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386 | * \param length |
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387 | * The length of the memory segment to be invalidated. |
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388 | * |
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389 | * \retval ALT_E_SUCCESS The operation was successful. |
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390 | * \retval ALT_E_ERROR The operation failed. |
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391 | * \retval ALT_E_BAD_ARG The memory segment is invalid. |
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392 | */ |
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393 | ALT_STATUS_CODE alt_cache_l1_data_invalidate(void * vaddress, size_t length); |
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394 | |
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395 | /*! |
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396 | * Invalidates the entire contents of the L1 data cache on the current CPU |
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397 | * core. |
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398 | * |
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399 | * Normally this is done automatically as part of alt_cache_l1_data_enable(), |
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400 | * but in certain circumstances it may be necessary to invalidate it manually. |
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401 | * An example of this situation is when the address space is remapped and the |
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402 | * processor accesses memory from the new memory area. |
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403 | * |
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404 | * \retval ALT_E_SUCCESS The operation was successful. |
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405 | * \retval ALT_E_ERROR The operation failed. |
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406 | */ |
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407 | ALT_STATUS_CODE alt_cache_l1_data_invalidate_all(void); |
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408 | |
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409 | /*! |
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410 | * Cleans the specified contents of the L1 data cache on the current CPU core |
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411 | * for the given memory segment. |
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412 | * |
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413 | * The memory segment address and length specified must align to the |
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414 | * characteristics of the cache line. This means the address and length must be |
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415 | * multiples of the cache line size. To determine the cache line size, use the |
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416 | * \b ALT_CACHE_LINE_SIZE macro. |
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417 | * |
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418 | * \param vaddress |
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419 | * The virtual address of the memory segment to be cleaned. |
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420 | * |
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421 | * \param length |
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422 | * The length of the memory segment to be cleaned. |
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423 | * |
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424 | * \retval ALT_E_SUCCESS The operation was successful. |
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425 | * \retval ALT_E_ERROR The operation failed. |
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426 | * \retval ALT_E_BAD_ARG The memory segment is invalid. |
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427 | */ |
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428 | ALT_STATUS_CODE alt_cache_l1_data_clean(void * vaddress, size_t length); |
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429 | |
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430 | /*! |
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431 | * Cleans the entire L1 data cache for the current CPU core. |
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432 | * |
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433 | * \retval ALT_E_SUCCESS The operation was successful. |
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434 | * \retval ALT_E_ERROR The operation failed. |
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435 | */ |
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436 | ALT_STATUS_CODE alt_cache_l1_data_clean_all(void); |
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437 | |
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438 | /*! |
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439 | * Cleans and invalidates the specified contents of the L1 data cache on the |
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440 | * current CPU core for the given memory segment. |
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441 | * |
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442 | * The memory segment address and length specified must align to the |
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443 | * characteristics of the cache line. This means the address and length must be |
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444 | * multiples of the cache line size. To determine the cache line size, use the |
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445 | * \b ALT_CACHE_LINE_SIZE macro. |
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446 | * |
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447 | * Normally this is done automatically as part of alt_cache_l1_data_disable(), |
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448 | * but in certain circumstances it may be necessary to purged it manually. |
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449 | * An example of this situation is when the address space is remapped and the |
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450 | * processor accesses memory from the new memory area. |
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451 | * |
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452 | * \param vaddress |
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453 | * The virtual address of the memory segment to be purged. |
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454 | * |
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455 | * \param length |
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456 | * The length of the memory segment to be purged. |
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457 | * |
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458 | * \retval ALT_E_SUCCESS The operation was successful. |
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459 | * \retval ALT_E_ERROR The operation failed. |
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460 | * \retval ALT_E_BAD_ARG The memory segment is invalid. |
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461 | */ |
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462 | ALT_STATUS_CODE alt_cache_l1_data_purge(void * vaddress, size_t length); |
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463 | |
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464 | /*! |
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465 | * Cleans and invalidates the entire L1 data cache for the current CPU core. |
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466 | * |
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467 | * \retval ALT_E_SUCCESS The operation was successful. |
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468 | * \retval ALT_E_ERROR The operation failed. |
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469 | */ |
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470 | ALT_STATUS_CODE alt_cache_l1_data_purge_all(void); |
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471 | |
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472 | /*! |
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473 | * Enables the parity error detection feature in the L1 caches on the current |
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474 | * CPU core. |
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475 | * |
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476 | * Ideally parity should be enabled before any L1 caches are enabled. If the |
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477 | * instruction, data, and / or dynamic branch predictor caches are already |
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478 | * enabled, they will first be cleaned (if needed) and disabled before parity |
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479 | * is enabled in hardware. Afterwards, the affected caches will be invalidated |
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480 | * and enabled. |
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481 | * |
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482 | * Parity and TLB interaction deserves special attention. The TLB is considered |
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483 | * to be a L1 cache but is enabled when the MMU, which is grouped in another |
---|
484 | * API, is enabled. Due to the system-wide influence of the MMU, it cannot be |
---|
485 | * disabled and enabled with impunity as the other L1 caches, which are |
---|
486 | * designed to operate as transparently as possible. Thus parity error |
---|
487 | * detection must be enabled before the L1 TLB cache, and by extension the MMU, |
---|
488 | * is enabled. |
---|
489 | * |
---|
490 | * For a parity error to be reported, the appropriate CPU PARITYFAIL interrupt |
---|
491 | * for the current CPU core must be enabled using the interrupt controller API. |
---|
492 | * For CPU0, ALT_INT_INTERRUPT_CPU0_PARITYFAIL is asserted if any parity error |
---|
493 | * is detected while the other PARITYFAIL interrupts are for parity errors in a |
---|
494 | * specific memory. Refer to the interrupt controller API for more details |
---|
495 | * about programming the interrupt controller. |
---|
496 | * |
---|
497 | * In the event of a parity error is detected, the appropriate CPU parity |
---|
498 | * interrupt will be raised. CPU parity interrupts are all edge triggered and |
---|
499 | * are cleared by acknowledging them in the interrupt controller API. |
---|
500 | * |
---|
501 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
502 | * \retval ALT_E_ERROR The operation failed. |
---|
503 | */ |
---|
504 | ALT_STATUS_CODE alt_cache_l1_parity_enable(void); |
---|
505 | |
---|
506 | /*! |
---|
507 | * Disables parity error detection in the L1 caches. |
---|
508 | * |
---|
509 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
510 | * \retval ALT_E_ERROR The operation failed. |
---|
511 | */ |
---|
512 | ALT_STATUS_CODE alt_cache_l1_parity_disable(void); |
---|
513 | |
---|
514 | /*! |
---|
515 | * Returns \b true when parity error detection is enabled and \b false when it |
---|
516 | * is disabled on the current CPU core. |
---|
517 | * |
---|
518 | * \retval true Parity error detection for L1 caches is |
---|
519 | * enabled. |
---|
520 | * \retval false Parity error detection for L1 caches is |
---|
521 | * disabled. |
---|
522 | */ |
---|
523 | bool alt_cache_l1_parity_is_enabled(void); |
---|
524 | |
---|
525 | /*! |
---|
526 | * Enables the dynamic branch predictor features on the current CPU core. |
---|
527 | * |
---|
528 | * This operation enables both the Branch Target Address Cache (BTAC) and |
---|
529 | * the Global History Buffer (GHB). Affected caches are automatically |
---|
530 | * invalidated before use. |
---|
531 | * |
---|
532 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
533 | * \retval ALT_E_ERROR The operation failed. |
---|
534 | */ |
---|
535 | ALT_STATUS_CODE alt_cache_l1_branch_enable(void); |
---|
536 | |
---|
537 | /*! |
---|
538 | * Disables the dynamic branch predictor features on the current CPU core. |
---|
539 | * |
---|
540 | * This operation disables both the Branch Target Address Cache (BTAC) and |
---|
541 | * the Global History Buffer (GHB). |
---|
542 | * |
---|
543 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
544 | * \retval ALT_E_ERROR The operation failed. |
---|
545 | */ |
---|
546 | ALT_STATUS_CODE alt_cache_l1_branch_disable(void); |
---|
547 | |
---|
548 | /*! |
---|
549 | * Returns \b true when both the dynamic predictor features are enabled and |
---|
550 | * \b false when they are disabled on the current CPU core. |
---|
551 | * |
---|
552 | * \retval true The L1 branch predictor caches are all enabled. |
---|
553 | * \retval false Some or all L1 branch predictor caches are |
---|
554 | * disabled. |
---|
555 | */ |
---|
556 | bool alt_cache_l1_branch_is_enabled(void); |
---|
557 | |
---|
558 | /*! |
---|
559 | * Invalidates the dynamic branch predictor feature caches on the current CPU |
---|
560 | * core. |
---|
561 | * |
---|
562 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
563 | * \retval ALT_E_ERROR The operation failed. |
---|
564 | */ |
---|
565 | ALT_STATUS_CODE alt_cache_l1_branch_invalidate(void); |
---|
566 | |
---|
567 | /*! |
---|
568 | * Enables the L1 cache data prefetch feature on the current CPU core. |
---|
569 | * |
---|
570 | * This allows data to be prefetched into the data cache before it is to be |
---|
571 | * used. For example in a loop the current iteration may want to preload the |
---|
572 | * data which will be used in the next teration. This is done by using the PLD |
---|
573 | * instructions. |
---|
574 | * |
---|
575 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
576 | * \retval ALT_E_ERROR The operation failed. |
---|
577 | */ |
---|
578 | ALT_STATUS_CODE alt_cache_l1_prefetch_enable(void); |
---|
579 | |
---|
580 | /*! |
---|
581 | * Disables the L1 cache data prefetch feature on the current CPU core. |
---|
582 | * |
---|
583 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
584 | * \retval ALT_E_ERROR The operation failed. |
---|
585 | */ |
---|
586 | ALT_STATUS_CODE alt_cache_l1_prefetch_disable(void); |
---|
587 | |
---|
588 | /*! |
---|
589 | * Returns \b true if the L1 cache data prefetch feature is enabled and |
---|
590 | * \b false if it is disabled on the current CPU core. |
---|
591 | * |
---|
592 | * \retval true The L1 data cache prefetch feature is enabled. |
---|
593 | * \retval false The L1 data cache prefetch feature is disabled. |
---|
594 | */ |
---|
595 | bool alt_cache_l1_prefetch_is_enabled(void); |
---|
596 | |
---|
597 | /*! |
---|
598 | * @} |
---|
599 | */ |
---|
600 | |
---|
601 | /*! |
---|
602 | * \addtogroup CACHE_L2 L2 Cache Management API |
---|
603 | * |
---|
604 | * This API group provides functions to interact with various features of the |
---|
605 | * L2 cache on the SoCFPGA. This includes the following features: |
---|
606 | * * L2 cache |
---|
607 | * * Parity error detection |
---|
608 | * * Data prefetching |
---|
609 | * * Interrupt Management |
---|
610 | * |
---|
611 | * \internal |
---|
612 | * Additional features that may be implemented in the future: |
---|
613 | * * Lockdown |
---|
614 | * * Event counter |
---|
615 | * \endinternal |
---|
616 | * |
---|
617 | * The API within this group affects the L2 cache which is visible to all CPUs |
---|
618 | * on the system. |
---|
619 | * |
---|
620 | * With respect to bring-up, the L1 and L2 cache controller setups are fully |
---|
621 | * independent. The L2 can be setup at any time, before or after the L1 is setup. |
---|
622 | * \internal |
---|
623 | * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up". |
---|
624 | * \endinternal |
---|
625 | * |
---|
626 | * @{ |
---|
627 | */ |
---|
628 | |
---|
629 | /*! |
---|
630 | * Initializes the L2 cache controller. |
---|
631 | * |
---|
632 | * \retval ALT_E_SUCCESS Successful status. |
---|
633 | * \retval ALT_E_ERROR Details about error status code |
---|
634 | */ |
---|
635 | ALT_STATUS_CODE alt_cache_l2_init(void); |
---|
636 | |
---|
637 | /*! |
---|
638 | * Uninitializes the L2 cache controller. |
---|
639 | * |
---|
640 | * \retval ALT_E_SUCCESS Successful status. |
---|
641 | * \retval ALT_E_ERROR Details about error status code |
---|
642 | */ |
---|
643 | ALT_STATUS_CODE alt_cache_l2_uninit(void); |
---|
644 | |
---|
645 | /*! |
---|
646 | * Enables the L2 cache features for data and instruction prefetching. |
---|
647 | * |
---|
648 | * Prefetching can be enabled or disabled while the L2 cache is enabled. |
---|
649 | * \internal |
---|
650 | * Source: Use the Prefetch Control Register. |
---|
651 | * \endinternal |
---|
652 | * |
---|
653 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
654 | * \retval ALT_E_ERROR The operation failed. |
---|
655 | */ |
---|
656 | ALT_STATUS_CODE alt_cache_l2_prefetch_enable(void); |
---|
657 | |
---|
658 | /*! |
---|
659 | * Disables the L2 cache features for data and instruction prefetching. |
---|
660 | * |
---|
661 | * Prefetching can be enabled or disabled while the L2 cache is enabled. |
---|
662 | * \internal |
---|
663 | * Source: Use the Prefetch Control Register. |
---|
664 | * \endinternal |
---|
665 | * |
---|
666 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
667 | * \retval ALT_E_ERROR The operation failed. |
---|
668 | */ |
---|
669 | ALT_STATUS_CODE alt_cache_l2_prefetch_disable(void); |
---|
670 | |
---|
671 | /*! |
---|
672 | * Returns \b true if either L2 cache data or instruction prefetch features are |
---|
673 | * enabled and \b false if no prefetching features are enabled. |
---|
674 | * |
---|
675 | * \retval true The L2 data and instruction prefetch features |
---|
676 | * are enabled. |
---|
677 | * \retval false Some L2 data and instruction prefetch features |
---|
678 | * are disabled. |
---|
679 | */ |
---|
680 | bool alt_cache_l2_prefetch_is_enabled(void); |
---|
681 | |
---|
682 | /*! |
---|
683 | * Enables parity error detection in the L2 cache. |
---|
684 | * |
---|
685 | * Ideally parity should be enabled before the L2 cache is enabled. If the |
---|
686 | * cache is already enabled, it will first be cleaned and disabled before |
---|
687 | * parity is enabled in hardware. Afterwards, the cache will be invalidated and |
---|
688 | * enabled. |
---|
689 | * |
---|
690 | * For a parity error to be reported, the ALT_CACHE_L2_INTERRUPT_PARRD and / or |
---|
691 | * ALT_CACHE_L2_INTERRUPT_PARRT interrupt condition(s) must be enabled. This is |
---|
692 | * done by calling alt_cache_l2_int_enable(). As well, the L2 cache interrupt |
---|
693 | * must be enabled using the interrupt controller API. Refer to the interrupt |
---|
694 | * controller API for more details about programming the interrupt controller. |
---|
695 | * |
---|
696 | * In the event of a parity error is detected, the appropriate L2 cache parity |
---|
697 | * interrupt will be raised. To clear the parity interrupt(s), the appropriate |
---|
698 | * L2 cache parity interrupt must be cleared by calling |
---|
699 | * alt_cache_l2_int_status_clear(). |
---|
700 | * |
---|
701 | * For ECC support, refer to the ECC related API documentation for more |
---|
702 | * information. |
---|
703 | * |
---|
704 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
705 | * \retval ALT_E_ERROR The operation failed. |
---|
706 | */ |
---|
707 | ALT_STATUS_CODE alt_cache_l2_parity_enable(void); |
---|
708 | |
---|
709 | /*! |
---|
710 | * Disables parity error detection in the L2 cache. |
---|
711 | * |
---|
712 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
713 | * \retval ALT_E_ERROR The operation failed. |
---|
714 | */ |
---|
715 | ALT_STATUS_CODE alt_cache_l2_parity_disable(void); |
---|
716 | |
---|
717 | /*! |
---|
718 | * Returns \b true when parity error detection is enabled and \b false when it |
---|
719 | * is disabled. |
---|
720 | * |
---|
721 | * \retval true The L2 cache parity error detection feature is |
---|
722 | * enabled. |
---|
723 | * \retval false The L2 cache parity error detection feature is |
---|
724 | * disabled. |
---|
725 | */ |
---|
726 | bool alt_cache_l2_parity_is_enabled(void); |
---|
727 | |
---|
728 | /*! |
---|
729 | * Enables the L2 cache. |
---|
730 | * |
---|
731 | * If the L2 cache is already enabled, nothing is done. Otherwise the entire |
---|
732 | * contents of the cache is first invalidated before being enabled. |
---|
733 | * |
---|
734 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
735 | * \retval ALT_E_ERROR The operation failed. |
---|
736 | */ |
---|
737 | ALT_STATUS_CODE alt_cache_l2_enable(void); |
---|
738 | |
---|
739 | /*! |
---|
740 | * Disables the L2 cache. |
---|
741 | * |
---|
742 | * If the L2 cache is already disabled, nothing is done. Otherwise the entire |
---|
743 | * contents of the cache is first cleaned before being disabled. |
---|
744 | * |
---|
745 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
746 | * \retval ALT_E_ERROR The operation failed. |
---|
747 | */ |
---|
748 | ALT_STATUS_CODE alt_cache_l2_disable(void); |
---|
749 | |
---|
750 | /*! |
---|
751 | * Returns \b true when the L2 cache is enabled and \b false when it is |
---|
752 | * disabled. |
---|
753 | * |
---|
754 | * \retval true The L2 cache is enabled. |
---|
755 | * \retval false The L2 cache is disabled. |
---|
756 | */ |
---|
757 | bool alt_cache_l2_is_enabled(void); |
---|
758 | |
---|
759 | /*! |
---|
760 | * Flushes the L2 cache controller hardware buffers. |
---|
761 | * |
---|
762 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
763 | * \retval ALT_E_ERROR The operation failed. |
---|
764 | * \retval ALT_E_TMO The memory operation timed out. |
---|
765 | */ |
---|
766 | ALT_STATUS_CODE alt_cache_l2_sync(void); |
---|
767 | |
---|
768 | /*! |
---|
769 | * Invalidates the specified contents of the L2 cache for the given memory |
---|
770 | * segment. |
---|
771 | * |
---|
772 | * The memory segment address and length specified must align to the |
---|
773 | * characteristics of the cache line. This means the address and length must be |
---|
774 | * multiples of the cache line size. To determine the cache line size, use the |
---|
775 | * \b ALT_CACHE_LINE_SIZE macro. |
---|
776 | * |
---|
777 | * \param paddress |
---|
778 | * The physical address of the memory segment to be invalidated. |
---|
779 | * |
---|
780 | * \param length |
---|
781 | * The length of the memory segment to be invalidated. |
---|
782 | * |
---|
783 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
784 | * \retval ALT_E_ERROR The operation failed. |
---|
785 | * \retval ALT_E_BAD_ARG The memory segment is invalid. |
---|
786 | * \retval ALT_E_TMO The memory operation timed out. |
---|
787 | */ |
---|
788 | ALT_STATUS_CODE alt_cache_l2_invalidate(void * paddress, size_t length); |
---|
789 | |
---|
790 | /*! |
---|
791 | * Invalidates th entire contents of the L2 cache. |
---|
792 | * |
---|
793 | * Normally this is done automatically as part of alt_cache_l2_enable(), but |
---|
794 | * in certain circumstances it may be necessary to invalidate it manually. An |
---|
795 | * example of this situation is when the address space is remapped and the |
---|
796 | * processor accesses memory from the new memory area. |
---|
797 | |
---|
798 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
799 | * \retval ALT_E_ERROR The operation failed. |
---|
800 | * \retval ALT_E_TMO The memory operation timed out. |
---|
801 | */ |
---|
802 | ALT_STATUS_CODE alt_cache_l2_invalidate_all(void); |
---|
803 | |
---|
804 | /*! |
---|
805 | * Cleans the specified contents of the L2 cache for the given memory segment. |
---|
806 | * |
---|
807 | * The memory segment address and length specified must align to the |
---|
808 | * characteristics of the cache line. This means the address and length must be |
---|
809 | * multiples of the cache line size. To determine the cache line size, use the |
---|
810 | * \b ALT_CACHE_LINE_SIZE macro. |
---|
811 | * |
---|
812 | * \param paddress |
---|
813 | * The physical address of the memory segment to be cleaned. |
---|
814 | * |
---|
815 | * \param length |
---|
816 | * The length of the memory segment to be cleaned. |
---|
817 | * |
---|
818 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
819 | * \retval ALT_E_ERROR The operation failed. |
---|
820 | * \retval ALT_E_BAD_ARG The memory segment is invalid. |
---|
821 | * \retval ALT_E_TMO The memory operation timed out. |
---|
822 | */ |
---|
823 | ALT_STATUS_CODE alt_cache_l2_clean(void * paddress, size_t length); |
---|
824 | |
---|
825 | /*! |
---|
826 | * Cleans the entire L2 cache. All L2 cache controller interrupts will be |
---|
827 | * temporarily disabled while the clean operation is in progress and restored |
---|
828 | * once the it is finished. |
---|
829 | * |
---|
830 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
831 | * \retval ALT_E_ERROR The operation failed. |
---|
832 | * \retval ALT_E_TMO The memory operation timed out. |
---|
833 | */ |
---|
834 | ALT_STATUS_CODE alt_cache_l2_clean_all(void); |
---|
835 | |
---|
836 | /*! |
---|
837 | * Cleans and invalidates the specified contents of the L2 cache for the |
---|
838 | * given memory segment. |
---|
839 | * |
---|
840 | * The memory segment address and length specified must align to the |
---|
841 | * characteristics of the cache line. This means the address and length must be |
---|
842 | * multiples of the cache line size. To determine the cache line size, use the |
---|
843 | * \b ALT_CACHE_LINE_SIZE macro. |
---|
844 | * |
---|
845 | * \param paddress |
---|
846 | * The physical address of the memory segment to be purged. |
---|
847 | * |
---|
848 | * \param length |
---|
849 | * The length of the memory segment to be purged. |
---|
850 | * |
---|
851 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
852 | * \retval ALT_E_ERROR The operation failed. |
---|
853 | * \retval ALT_E_BAD_ARG The memory segment is invalid. |
---|
854 | */ |
---|
855 | ALT_STATUS_CODE alt_cache_l2_purge(void * paddress, size_t length); |
---|
856 | |
---|
857 | /*! |
---|
858 | * Cleans and invalidates the entire L2 cache. All L2 cache controller |
---|
859 | * interrupts will be temporarily disabled while the clean and invalidate |
---|
860 | * operation is in progress and restored once the it is finished. |
---|
861 | * |
---|
862 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
863 | * \retval ALT_E_ERROR The operation failed. |
---|
864 | * \retval ALT_E_TMO The memory operation timed out. |
---|
865 | */ |
---|
866 | ALT_STATUS_CODE alt_cache_l2_purge_all(void); |
---|
867 | |
---|
868 | /*! |
---|
869 | * This type definition enumerates all the interrupt conditions that can be |
---|
870 | * generated by the L2 cache controller as register mask values. |
---|
871 | */ |
---|
872 | enum ALT_CACHE_L2_INTERRUPT_e |
---|
873 | { |
---|
874 | /*! Decode error received on the master ports from L3. */ |
---|
875 | ALT_CACHE_L2_INTERRUPT_DECERR = 1 << 8, |
---|
876 | |
---|
877 | /*! Slave error received on the master ports from L3. */ |
---|
878 | ALT_CACHE_L2_INTERRUPT_SLVERR = 1 << 7, |
---|
879 | |
---|
880 | /*! Error on the L2 data RAM read. */ |
---|
881 | ALT_CACHE_L2_INTERRUPT_ERRRD = 1 << 6, |
---|
882 | |
---|
883 | /*! Error on the L2 tag RAM read. */ |
---|
884 | ALT_CACHE_L2_INTERRUPT_ERRRT = 1 << 5, |
---|
885 | |
---|
886 | /*! Error on the L2 data RAM write. */ |
---|
887 | ALT_CACHE_L2_INTERRUPT_ERRWD = 1 << 4, |
---|
888 | |
---|
889 | /*! Error on the L2 tag RAM write. */ |
---|
890 | ALT_CACHE_L2_INTERRUPT_ERRWT = 1 << 3, |
---|
891 | |
---|
892 | /*! Parity error on the L2 data RAM read. */ |
---|
893 | ALT_CACHE_L2_INTERRUPT_PARRD = 1 << 2, |
---|
894 | |
---|
895 | /*! Parity error on the L2 tag RAM read. */ |
---|
896 | ALT_CACHE_L2_INTERRUPT_PARRT = 1 << 1, |
---|
897 | |
---|
898 | /*! Event counter overflow or increment. */ |
---|
899 | ALT_CACHE_L2_INTERRUPT_ECNTR = 1 << 0 |
---|
900 | }; |
---|
901 | typedef enum ALT_CACHE_L2_INTERRUPT_e ALT_CACHE_L2_INTERRUPT_t; |
---|
902 | |
---|
903 | /*! |
---|
904 | * Enables the L2 cache controller interrupts for the specified set of |
---|
905 | * condition(s). |
---|
906 | * |
---|
907 | * \param interrupt |
---|
908 | * A register mask of the selected L2 cache controller |
---|
909 | * interrupting conditions. |
---|
910 | * |
---|
911 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
912 | * \retval ALT_E_ERROR The operation failed. |
---|
913 | */ |
---|
914 | ALT_STATUS_CODE alt_cache_l2_int_enable(uint32_t interrupt); |
---|
915 | |
---|
916 | /*! |
---|
917 | * Disables the L2 cache controller interrupts for the specified set of |
---|
918 | * condition(s). |
---|
919 | * |
---|
920 | * \param interrupt |
---|
921 | * A register mask of the selected L2 cache controller |
---|
922 | * interrupting conditions. |
---|
923 | * |
---|
924 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
925 | * \retval ALT_E_ERROR The operation failed. |
---|
926 | */ |
---|
927 | ALT_STATUS_CODE alt_cache_l2_int_disable(uint32_t interrupt); |
---|
928 | |
---|
929 | /*! |
---|
930 | * Gets the condition(s) causing the L2 cache controller to interrupt as a |
---|
931 | * register mask. |
---|
932 | * |
---|
933 | * \returns A register mask of the currently asserted and enabled |
---|
934 | * conditions resulting in an interrupt being generated. |
---|
935 | */ |
---|
936 | uint32_t alt_cache_l2_int_status_get(void); |
---|
937 | |
---|
938 | /*! |
---|
939 | * Clears the specified conditon(s) causing the L2 cache controller to |
---|
940 | * interrupt as a mask. Condition(s) specified which are not causing an |
---|
941 | * interrupt or condition(s) specified which are not enabled are ignored. |
---|
942 | * |
---|
943 | * \param interrupt |
---|
944 | * A register mask of the selected L2 cache controller |
---|
945 | * interrupting conditions. |
---|
946 | * |
---|
947 | * \retval ALT_E_SUCCESS The operation was successful. |
---|
948 | * \retval ALT_E_ERROR The operation failed. |
---|
949 | */ |
---|
950 | ALT_STATUS_CODE alt_cache_l2_int_status_clear(uint32_t interrupt); |
---|
951 | |
---|
952 | /*! |
---|
953 | * @} |
---|
954 | */ |
---|
955 | |
---|
956 | /*! |
---|
957 | * @} |
---|
958 | */ |
---|
959 | |
---|
960 | #ifdef __cplusplus |
---|
961 | } |
---|
962 | #endif |
---|
963 | |
---|
964 | #endif /* __ALT_CACHE_H__ */ |
---|