source: rtems/bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_address_space.c @ 9d41fca

5
Last change on this file since 9d41fca was 9d41fca, checked in by Sebastian Huber <sebastian.huber@…>, on 02/27/19 at 10:39:29

bsp/altera-cyclone-v: Adjust Doxygen file groups

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1/**
2 * @file
3 *
4 * @ingroup RTEMSBSPsARMCycVContrib
5 */
6
7/******************************************************************************
8 *
9 * alt_address_space.c - API for the Altera SoC FPGA address space.
10 *
11 ******************************************************************************/
12
13/******************************************************************************
14 *
15 * Copyright 2013 Altera Corporation. All Rights Reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are met:
19 *
20 * 1. Redistributions of source code must retain the above copyright notice,
21 * this list of conditions and the following disclaimer.
22 *
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 *
27 * 3. The name of the author may not be used to endorse or promote products
28 * derived from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
31 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
33 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
34 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
35 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
39 * OF SUCH DAMAGE.
40 *
41 ******************************************************************************/
42
43#include <stddef.h>
44#include <bsp/alt_address_space.h>
45#include <bsp/socal/alt_l3.h>
46#include <bsp/socal/socal.h>
47#include <bsp/socal/alt_acpidmap.h>
48#include <bsp/hwlib.h>
49
50
51#define ALT_ACP_ID_MAX_INPUT_ID     7
52#define ALT_ACP_ID_MAX_OUTPUT_ID    4096
53
54/******************************************************************************/
55ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr,
56                                     ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr,
57                                     ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_bridge_attr,
58                                     ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_bridge_attr)
59{
60    uint32_t remap_reg_val = 0;
61
62    // Parameter checking and validation...
63    if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM)
64    {
65        remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_BOOTROM);
66    }
67    else if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM)
68    {
69        remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_OCRAM);
70    }
71    else
72    {
73        return ALT_E_INV_OPTION;
74    }
75
76    if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM)
77    {
78        remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_SDRAM);
79    }
80    else if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM)
81    {
82        remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_OCRAM);
83    }
84    else
85    {
86        return ALT_E_INV_OPTION;
87    }
88
89    if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_INACCESSIBLE)
90    {
91        remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_INVISIBLE);
92    }
93    else if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_ACCESSIBLE)
94    {
95        remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_VISIBLE);
96    }
97    else
98    {
99        return ALT_E_INV_OPTION;
100    }
101
102    if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_INACCESSIBLE)
103    {
104        remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_INVISIBLE);
105    }
106    else if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_ACCESSIBLE)
107    {
108        remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_VISIBLE);
109    }
110    else
111    {
112        return ALT_E_INV_OPTION;
113    }
114
115    // Perform the remap.
116    alt_write_word(ALT_L3_REMAP_ADDR, remap_reg_val);
117
118    return ALT_E_SUCCESS;
119}
120
121/******************************************************************************/
122// Remap the MPU address space view of address 0 to access the SDRAM controller.
123// This is done by setting the L2 cache address filtering register start address
124// to 0 and leaving the address filtering address end address value
125// unmodified. This causes all physical addresses in the range
126// address_filter_start <= physical_address < address_filter_end to be directed
127// to the to the AXI Master Port M1 which is connected to the SDRAM
128// controller. All other addresses are directed to AXI Master Port M0 which
129// connect the MPU subsystem to the L3 interconnect.
130//
131// It is unnecessary to modify the MPU remap options in the L3 remap register
132// because those options only affect addresses in the MPU subsystem address
133// ranges that are now redirected to the SDRAM controller and never reach the L3
134// interconnect anyway.
135ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void)
136{
137    uint32_t addr_filt_end = (alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR) &
138                              L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);
139    return alt_l2_addr_filter_cfg_set(0x0, addr_filt_end);
140}
141
142/******************************************************************************/
143// Return the L2 cache address filtering registers configuration settings in the
144// user provided start and end address range out parameters.
145ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start,
146                                           uint32_t* addr_filt_end)
147{
148    if (addr_filt_start == NULL || addr_filt_end == NULL)
149    {
150        return ALT_E_BAD_ARG;
151    }
152
153    uint32_t addr_filt_start_reg = alt_read_word(L2_CACHE_ADDR_FILTERING_START_ADDR);
154    uint32_t addr_filt_end_reg   = alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR);
155
156    *addr_filt_start = (addr_filt_start_reg & L2_CACHE_ADDR_FILTERING_START_ADDR_MASK);
157    *addr_filt_end = (addr_filt_end_reg & L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);
158    return ALT_E_SUCCESS;
159}
160
161/******************************************************************************/
162ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start,
163                                           uint32_t addr_filt_end)
164{
165    // Address filtering start and end values must be 1 MB aligned.
166    if (  (addr_filt_start & ~L2_CACHE_ADDR_FILTERING_START_ADDR_MASK)
167       || (addr_filt_end   & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK)  )
168    {
169        return ALT_E_ARG_RANGE;
170    }
171
172    // While it is possible to set the address filtering end value above its
173    // reset value and thereby access a larger SDRAM address range, it is not
174    // recommended. Doing so would potentially obscure any mapped HPS to FPGA
175    // bridge address spaces and peripherals on the L3 interconnect.
176    if (addr_filt_end > L2_CACHE_ADDR_FILTERING_END_RESET)
177    {
178        return ALT_E_ARG_RANGE;
179    }
180
181    // NOTE: ARM (ARM DDI 0246F CoreLink Level 2 Cache Controller L2C-310 TRM)
182    // recommends programming the Address Filtering End Register before the
183    // Address Filtering Start Register to avoid unpredictable behavior between
184    // the two writes.
185    alt_write_word(L2_CACHE_ADDR_FILTERING_END_ADDR, addr_filt_end);
186    // It is recommended that address filtering always remain enabled.
187    addr_filt_start |= L2_CACHE_ADDR_FILTERING_ENABLE_MASK;
188    alt_write_word(L2_CACHE_ADDR_FILTERING_START_ADDR, addr_filt_start);
189
190    return ALT_E_SUCCESS;
191}
192
193/******************************************************************************/
194ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id,
195                                              const uint32_t output_id,
196                                              const ALT_ACP_ID_MAP_PAGE_t page,
197                                              const uint32_t aruser)
198{
199    if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
200    {
201        return ALT_E_BAD_ARG;
202    }
203
204    switch (output_id)
205    {
206    case ALT_ACP_ID_OUT_FIXED_ID_2:
207        alt_write_word(ALT_ACPIDMAP_VID2RD_ADDR,
208                         ALT_ACPIDMAP_VID2RD_MID_SET(input_id)
209                       | ALT_ACPIDMAP_VID2RD_PAGE_SET(page)
210                       | ALT_ACPIDMAP_VID2RD_USER_SET(aruser)
211                       | ALT_ACPIDMAP_VID2RD_FORCE_SET(1UL));
212        break;
213    case ALT_ACP_ID_OUT_DYNAM_ID_3:
214        alt_write_word(ALT_ACPIDMAP_VID3RD_ADDR,
215                         ALT_ACPIDMAP_VID3RD_MID_SET(input_id)
216                       | ALT_ACPIDMAP_VID3RD_PAGE_SET(page)
217                       | ALT_ACPIDMAP_VID3RD_USER_SET(aruser)
218                       | ALT_ACPIDMAP_VID3RD_FORCE_SET(1UL));
219        break;
220    case ALT_ACP_ID_OUT_DYNAM_ID_4:
221        alt_write_word(ALT_ACPIDMAP_VID4RD_ADDR,
222                         ALT_ACPIDMAP_VID4RD_MID_SET(input_id)
223                       | ALT_ACPIDMAP_VID4RD_PAGE_SET(page)
224                       | ALT_ACPIDMAP_VID4RD_USER_SET(aruser)
225                       | ALT_ACPIDMAP_VID4RD_FORCE_SET(1UL));
226        break;
227    case ALT_ACP_ID_OUT_DYNAM_ID_5:
228        alt_write_word(ALT_ACPIDMAP_VID5RD_ADDR,
229                         ALT_ACPIDMAP_VID5RD_MID_SET(input_id)
230                       | ALT_ACPIDMAP_VID5RD_PAGE_SET(page)
231                       | ALT_ACPIDMAP_VID5RD_USER_SET(aruser)
232                       | ALT_ACPIDMAP_VID5RD_FORCE_SET(1UL));
233        break;
234    case ALT_ACP_ID_OUT_DYNAM_ID_6:
235        alt_write_word(ALT_ACPIDMAP_VID6RD_ADDR,
236                         ALT_ACPIDMAP_VID6RD_MID_SET(input_id)
237                       | ALT_ACPIDMAP_VID6RD_PAGE_SET(page)
238                       | ALT_ACPIDMAP_VID6RD_USER_SET(aruser)
239                       | ALT_ACPIDMAP_VID6RD_FORCE_SET(1UL));
240        break;
241    default:
242        return ALT_E_BAD_ARG;
243    }
244
245    return ALT_E_SUCCESS;
246}
247
248/******************************************************************************/
249ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id,
250                                               const uint32_t output_id,
251                                               const ALT_ACP_ID_MAP_PAGE_t page,
252                                               const uint32_t awuser)
253{
254    if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
255    {
256        return ALT_E_BAD_ARG;
257    }
258
259    switch (output_id)
260    {
261    case ALT_ACP_ID_OUT_FIXED_ID_2:
262        alt_write_word(ALT_ACPIDMAP_VID2WR_ADDR,
263                         ALT_ACPIDMAP_VID2WR_MID_SET(input_id)
264                       | ALT_ACPIDMAP_VID2WR_PAGE_SET(page)
265                       | ALT_ACPIDMAP_VID2WR_USER_SET(awuser)
266                       | ALT_ACPIDMAP_VID2WR_FORCE_SET(1UL));
267        break;
268    case ALT_ACP_ID_OUT_DYNAM_ID_3:
269        alt_write_word(ALT_ACPIDMAP_VID3WR_ADDR,
270                         ALT_ACPIDMAP_VID3WR_MID_SET(input_id)
271                       | ALT_ACPIDMAP_VID3WR_PAGE_SET(page)
272                       | ALT_ACPIDMAP_VID3WR_USER_SET(awuser)
273                       | ALT_ACPIDMAP_VID3WR_FORCE_SET(1UL));
274        break;
275    case ALT_ACP_ID_OUT_DYNAM_ID_4:
276        alt_write_word(ALT_ACPIDMAP_VID4WR_ADDR,
277                         ALT_ACPIDMAP_VID4WR_MID_SET(input_id)
278                       | ALT_ACPIDMAP_VID4WR_PAGE_SET(page)
279                       | ALT_ACPIDMAP_VID4WR_USER_SET(awuser)
280                       | ALT_ACPIDMAP_VID4WR_FORCE_SET(1UL));
281        break;
282    case ALT_ACP_ID_OUT_DYNAM_ID_5:
283        alt_write_word(ALT_ACPIDMAP_VID5WR_ADDR,
284                         ALT_ACPIDMAP_VID5WR_MID_SET(input_id)
285                       | ALT_ACPIDMAP_VID5WR_PAGE_SET(page)
286                       | ALT_ACPIDMAP_VID5WR_USER_SET(awuser)
287                       | ALT_ACPIDMAP_VID5WR_FORCE_SET(1UL));
288        break;
289    case ALT_ACP_ID_OUT_DYNAM_ID_6:
290        alt_write_word(ALT_ACPIDMAP_VID6WR_ADDR,
291                         ALT_ACPIDMAP_VID6WR_MID_SET(input_id)
292                       | ALT_ACPIDMAP_VID6WR_PAGE_SET(page)
293                       | ALT_ACPIDMAP_VID6WR_USER_SET(awuser)
294                       | ALT_ACPIDMAP_VID6WR_FORCE_SET(1UL)
295            );
296        break;
297    default:
298        return ALT_E_BAD_ARG;
299    }
300
301    return ALT_E_SUCCESS;
302}
303
304/******************************************************************************/
305ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id)
306{
307    if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
308    {
309        return ALT_E_BAD_ARG;
310    }
311
312    uint32_t aruser, page;
313
314    switch (output_id)
315    {
316    case ALT_ACP_ID_OUT_FIXED_ID_2:
317        aruser = ALT_ACPIDMAP_VID2RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR));
318        page = ALT_ACPIDMAP_VID2RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR));
319        break;
320    case ALT_ACP_ID_OUT_DYNAM_ID_3:
321        aruser = ALT_ACPIDMAP_VID3RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR));
322        page = ALT_ACPIDMAP_VID3RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR));
323        break;
324    case ALT_ACP_ID_OUT_DYNAM_ID_4:
325        aruser = ALT_ACPIDMAP_VID4RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR));
326        page = ALT_ACPIDMAP_VID4RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR));
327        break;
328    case ALT_ACP_ID_OUT_DYNAM_ID_5:
329        aruser = ALT_ACPIDMAP_VID5RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR));
330        page = ALT_ACPIDMAP_VID5RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR));
331        break;
332    case ALT_ACP_ID_OUT_DYNAM_ID_6:
333        aruser = ALT_ACPIDMAP_VID6RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR));
334        page = ALT_ACPIDMAP_VID6RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR));
335        break;
336    default:
337        return ALT_E_BAD_ARG;
338    }
339
340    alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR,
341                     ALT_ACPIDMAP_DYNRD_PAGE_SET(page)
342                   | ALT_ACPIDMAP_DYNRD_USER_SET(aruser));
343    return ALT_E_SUCCESS;
344}
345
346/******************************************************************************/
347ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id)
348{
349    if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
350    {
351        return ALT_E_BAD_ARG;
352    }
353
354    uint32_t awuser, page;
355
356    switch (output_id)
357    {
358    case ALT_ACP_ID_OUT_FIXED_ID_2:
359        awuser = ALT_ACPIDMAP_VID2WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));
360        page   = ALT_ACPIDMAP_VID2WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));
361        break;
362    case ALT_ACP_ID_OUT_DYNAM_ID_3:
363        awuser = ALT_ACPIDMAP_VID3WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));
364        page   = ALT_ACPIDMAP_VID3WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));
365        break;
366    case ALT_ACP_ID_OUT_DYNAM_ID_4:
367        awuser = ALT_ACPIDMAP_VID4WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));
368        page   = ALT_ACPIDMAP_VID4WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));
369        break;
370    case ALT_ACP_ID_OUT_DYNAM_ID_5:
371        awuser = ALT_ACPIDMAP_VID5WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));
372        page   = ALT_ACPIDMAP_VID5WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));
373        break;
374    case ALT_ACP_ID_OUT_DYNAM_ID_6:
375        awuser = ALT_ACPIDMAP_VID6WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));
376        page   = ALT_ACPIDMAP_VID6WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));
377        break;
378    default:
379        return ALT_E_BAD_ARG;
380    }
381
382    alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,
383                     ALT_ACPIDMAP_DYNWR_PAGE_SET(page)
384                   | ALT_ACPIDMAP_DYNWR_USER_SET(awuser));
385    return ALT_E_SUCCESS;
386}
387
388/******************************************************************************/
389ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
390                                                        const uint32_t aruser)
391{
392    alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR,
393                     ALT_ACPIDMAP_DYNRD_PAGE_SET(page)
394                   | ALT_ACPIDMAP_DYNRD_USER_SET(aruser));
395    return ALT_E_SUCCESS;
396}
397
398/******************************************************************************/
399ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
400                                                         const uint32_t awuser)
401{
402    alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,
403                     ALT_ACPIDMAP_DYNWR_PAGE_SET(page)
404                   | ALT_ACPIDMAP_DYNWR_USER_SET(awuser));
405    return ALT_E_SUCCESS;
406}
407
408/******************************************************************************/
409ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id,
410                                                bool * fixed,
411                                                uint32_t * input_id,
412                                                ALT_ACP_ID_MAP_PAGE_t * page,
413                                                uint32_t * aruser)
414{
415    if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
416    {
417        return ALT_E_BAD_ARG;
418    }
419
420    switch (output_id)
421    {
422    case ALT_ACP_ID_OUT_FIXED_ID_2:
423        *aruser   = ALT_ACPIDMAP_VID2RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
424        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
425        *input_id = ALT_ACPIDMAP_VID2RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
426        *fixed    = ALT_ACPIDMAP_VID2RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
427        break;
428    case ALT_ACP_ID_OUT_DYNAM_ID_3:
429        *aruser   = ALT_ACPIDMAP_VID3RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
430        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
431        *input_id = ALT_ACPIDMAP_VID3RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
432        *fixed    = ALT_ACPIDMAP_VID3RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
433        break;
434    case ALT_ACP_ID_OUT_DYNAM_ID_4:
435        *aruser   = ALT_ACPIDMAP_VID4RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
436        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
437        *input_id = ALT_ACPIDMAP_VID4RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
438        *fixed    = ALT_ACPIDMAP_VID4RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
439        break;
440    case ALT_ACP_ID_OUT_DYNAM_ID_5:
441        *aruser   = ALT_ACPIDMAP_VID5RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
442        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
443        *input_id = ALT_ACPIDMAP_VID5RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
444        *fixed    = ALT_ACPIDMAP_VID5RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
445        break;
446    case ALT_ACP_ID_OUT_DYNAM_ID_6:
447        *aruser   = ALT_ACPIDMAP_VID6RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
448        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
449        *input_id = ALT_ACPIDMAP_VID6RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
450        *fixed    = ALT_ACPIDMAP_VID6RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
451        break;
452    case ALT_ACP_ID_OUT_DYNAM_ID_7:
453        *aruser   = ALT_ACPIDMAP_DYNRD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR));
454        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNRD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR));
455        break;
456    default:
457        return ALT_E_BAD_ARG;
458    }
459
460    return ALT_E_SUCCESS;
461}
462
463ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id,
464                                                 bool * fixed,
465                                                 uint32_t * input_id,
466                                                 ALT_ACP_ID_MAP_PAGE_t * page,
467                                                 uint32_t * awuser)
468{
469    if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
470    {
471        return ALT_E_BAD_ARG;
472    }
473
474    switch (output_id)
475    {
476    case ALT_ACP_ID_OUT_FIXED_ID_2:
477        *awuser   = ALT_ACPIDMAP_VID2WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
478        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
479        *input_id = ALT_ACPIDMAP_VID2WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
480        *fixed    = ALT_ACPIDMAP_VID2WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
481        break;
482    case ALT_ACP_ID_OUT_DYNAM_ID_3:
483        *awuser   = ALT_ACPIDMAP_VID3WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
484        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
485        *input_id = ALT_ACPIDMAP_VID3WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
486        *fixed    = ALT_ACPIDMAP_VID3WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
487        break;
488    case ALT_ACP_ID_OUT_DYNAM_ID_4:
489        *awuser   = ALT_ACPIDMAP_VID4WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
490        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
491        *input_id = ALT_ACPIDMAP_VID4WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
492        *fixed    = ALT_ACPIDMAP_VID4WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
493        break;
494    case ALT_ACP_ID_OUT_DYNAM_ID_5:
495        *awuser   = ALT_ACPIDMAP_VID5WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
496        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
497        *input_id = ALT_ACPIDMAP_VID5WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
498        *fixed    = ALT_ACPIDMAP_VID5WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
499        break;
500    case ALT_ACP_ID_OUT_DYNAM_ID_6:
501        *awuser   = ALT_ACPIDMAP_VID6WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
502        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
503        *input_id = ALT_ACPIDMAP_VID6WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
504        *fixed    = ALT_ACPIDMAP_VID6WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
505        break;
506    case ALT_ACP_ID_OUT_DYNAM_ID_7:
507        *awuser   = ALT_ACPIDMAP_DYNWR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));
508        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNWR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));
509        break;
510    default:
511        return ALT_E_BAD_ARG;
512    }
513
514    return ALT_E_SUCCESS;
515}
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