source: rtems/bsps/aarch64/shared/start/start.S @ ed9c88c

Last change on this file since ed9c88c was ed9c88c, checked in by Kinsey Moore <kinsey.moore@…>, on Oct 2, 2020 at 2:27:54 PM

bsps: Add Cortex-A53 ILP32 BSP variant

This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53
emulation with interrupt support using GICv3 and clock support using
the ARM GPT.

  • Property mode set to 100644
File size: 5.2 KB
Line 
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/**
4 * @file
5 *
6 * @ingroup RTEMSBSPsAArch64Shared
7 *
8 * @brief Boot and system start code.
9 */
10
11/*
12 * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
13 * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 *    notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 *    notice, this list of conditions and the following disclaimer in the
22 *    documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <rtems/asm.h>
38#include <rtems/score/percpu.h>
39
40#include <bspopts.h>
41
42        /* Global symbols */
43        .globl  _start
44        .section        ".bsp_start_text", "ax"
45
46/* Start entry */
47
48_start:
49
50        /*
51         * We do not save the context since we do not return to the boot
52         * loader but preserve x1 and x2 to allow access to bootloader parameters
53         */
54#ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION
55        mov     x5, x1          /* machine type number or ~0 for DT boot */
56        mov     x6, x2          /* physical address of ATAGs or DTB */
57#else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
58        mov     x0, XZR
59        mov     x1, XZR
60        mov     x2, XZR
61        mov     x3, XZR
62        mov     x4, XZR
63        mov     x5, XZR
64        mov     x6, XZR
65        mov     x7, XZR
66        mov     x8, XZR
67        mov     x9, XZR
68        mov     x10, XZR
69        mov     x11, XZR
70        mov     x12, XZR
71        mov     x13, XZR
72        mov     x14, XZR
73        mov     x15, XZR
74        mov     x16, XZR
75        mov     x17, XZR
76        mov     x18, XZR
77        mov     x19, XZR
78        mov     x20, XZR
79        mov     x21, XZR
80        mov     x22, XZR
81        mov     x23, XZR
82        mov     x24, XZR
83        mov     x25, XZR
84        mov     x26, XZR
85        mov     x27, XZR
86        mov     x28, XZR
87        mov     x29, XZR
88        mov     x30, XZR
89#ifdef AARCH64_MULTILIB_VFP
90#endif
91#endif
92
93#ifdef RTEMS_SMP
94        /* Read MPIDR and get current processor index */
95        mrs     x7, mpidr_el1
96        and     x7, #0xff
97#endif
98
99#ifdef RTEMS_SMP
100        /*
101         * Get current per-CPU control and store it in PL1 only Thread ID
102         * Register (TPIDRPRW).
103         */
104#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
105        ldr     w1, =_Per_CPU_Information
106#else
107        ldr     x1, =_Per_CPU_Information
108#endif
109        add     x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2
110        mcr     p15, 0, x1, c13, c0, 4
111
112#endif
113
114        /* Calculate interrupt stack area end for current processor */
115#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
116        ldr     w1, =_ISR_Stack_size
117#else
118        ldr     x1, =_ISR_Stack_size
119#endif
120#ifdef RTEMS_SMP
121        add     x3, x7, #1
122        mul     x1, x1, x3
123#endif
124#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
125        ldr     w2, =_ISR_Stack_area_begin
126#else
127        ldr     x2, =_ISR_Stack_area_begin
128#endif
129        add     x3, x1, x2
130
131        /* Save original DAIF value */
132        mrs     x4, DAIF
133
134#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
135        mov     x8, XZR
136        mov     x9, XZR
137        mov     x10, XZR
138        mov     x11, XZR
139        mov     x12, XZR
140        mov     x13, XZR
141        mov     x14, XZR
142        mov     x15, XZR
143#endif
144
145        /*
146         * SPx: the stack pointer corresponding to the current exception level
147         * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1
148         * Exception operation (synchronous errors, IRQ, FIQ, System Errors) uses SP0
149        */
150#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
151        ldr     w1, =bsp_stack_exception_size
152#else
153        ldr     x1, =bsp_stack_exception_size
154#endif
155        /* Switch to SP0 and set exception stack */
156        msr     spsel, #0
157        mov     sp, x3
158        /* Switch back to SPx for normal operation */
159        msr     spsel, #1
160        sub     x3, x3, x1
161
162        /* Set SP1 stack used for normal operation */
163        mov     sp, x3
164
165        /* Stay in EL1 mode */
166
167#ifdef AARCH64_MULTILIB_VFP
168#ifdef AARCH64_MULTILIB_HAS_CPACR
169        /* Read CPACR */
170        mrs x0, CPACR_EL1
171
172        /* Enable EL1 access permissions for CP10 */
173        orr x0, x0, #(1 << 20)
174
175        /* Write CPACR */
176        msr CPACR_EL1, x0
177        isb
178#endif
179
180        /* FPU does not need to be enabled on AArch64 */
181
182#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
183        mov     x0, #0
184        mov     CPTR_EL3, XZR
185        mov     CPTR_EL2, XZR
186        mov     d0, XZR
187        mov     d1, XZR
188        mov     d2, XZR
189        mov     d3, XZR
190        mov     d4, XZR
191        mov     d5, XZR
192        mov     d6, XZR
193        mov     d7, XZR
194        mov     d8, XZR
195        mov     d9, XZR
196        mov     d10, XZR
197        mov     d11, XZR
198        mov     d12, XZR
199        mov     d13, XZR
200        mov     d14, XZR
201        mov     d15, XZR
202        mov     d16, XZR
203        mov     d17, XZR
204        mov     d18, XZR
205        mov     d19, XZR
206        mov     d20, XZR
207        mov     d21, XZR
208        mov     d22, XZR
209        mov     d23, XZR
210        mov     d24, XZR
211        mov     d25, XZR
212        mov     d26, XZR
213        mov     d27, XZR
214        mov     d28, XZR
215        mov     d29, XZR
216        mov     d30, XZR
217        mov     d31, XZR
218#endif /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
219
220#endif /* AARCH64_MULTILIB_VFP */
221
222        /*
223         * Invoke the start hook 0.
224         *
225         */
226
227        mov     x1, x5          /* machine type number or ~0 for DT boot */
228        bl      bsp_start_hook_0
229
230        /* Branch to start hook 1 */
231        bl      bsp_start_hook_1
232
233        /* Branch to boot card */
234        mov     x0, #0
235        bl      boot_card
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