source: rtems/bsps/aarch64/shared/start/start.S @ a27ba3f

Last change on this file since a27ba3f was a27ba3f, checked in by Kinsey Moore <kinsey.moore@…>, on Jan 8, 2021 at 4:13:42 PM

bsps/aarch64: Add support for EL2 start

Add the stub necessary to boot on AArch64 under EL2 and drop to EL1 for
normal operation.

  • Property mode set to 100644
File size: 5.8 KB
Line 
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/**
4 * @file
5 *
6 * @ingroup RTEMSBSPsAArch64Shared
7 *
8 * @brief Boot and system start code.
9 */
10
11/*
12 * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
13 * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 *    notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 *    notice, this list of conditions and the following disclaimer in the
22 *    documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <rtems/asm.h>
38#include <rtems/score/percpu.h>
39
40#include <bspopts.h>
41
42        /* Global symbols */
43        .globl  _start
44        .section        ".bsp_start_text", "ax"
45
46/* Start entry */
47
48_start:
49
50        /*
51         * We do not save the context since we do not return to the boot
52         * loader but preserve x1 and x2 to allow access to bootloader parameters
53         */
54#ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION
55        mov     x5, x1          /* machine type number or ~0 for DT boot */
56        mov     x6, x2          /* physical address of ATAGs or DTB */
57#else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
58        mov     x0, XZR
59        mov     x1, XZR
60        mov     x2, XZR
61        mov     x3, XZR
62        mov     x4, XZR
63        mov     x5, XZR
64        mov     x6, XZR
65        mov     x7, XZR
66        mov     x8, XZR
67        mov     x9, XZR
68        mov     x10, XZR
69        mov     x11, XZR
70        mov     x12, XZR
71        mov     x13, XZR
72        mov     x14, XZR
73        mov     x15, XZR
74        mov     x16, XZR
75        mov     x17, XZR
76        mov     x18, XZR
77        mov     x19, XZR
78        mov     x20, XZR
79        mov     x21, XZR
80        mov     x22, XZR
81        mov     x23, XZR
82        mov     x24, XZR
83        mov     x25, XZR
84        mov     x26, XZR
85        mov     x27, XZR
86        mov     x28, XZR
87        mov     x29, XZR
88        mov     x30, XZR
89#ifdef AARCH64_MULTILIB_VFP
90#endif
91#endif
92
93        /* Initialize SCTLR_EL1 */
94        mov x0, XZR
95#if defined(RTEMS_DEBUG)
96        /* Enable Stack alignment checking */
97        orr x0, x0, #(1<<3)
98#endif
99        msr SCTLR_EL1, x0
100
101#ifdef BSP_START_IN_HYP_SUPPORT
102        /* Drop from EL2 to EL1 */
103
104        /* Configure HCR_EL2 */
105        mrs x0, HCR_EL2
106        /* Set EL1 Execution state to AArch64 */
107        orr x0, x0, #(1<<31)
108        /* Disable ID traps */
109        bic x0, x0, #(1<<15)
110        bic x0, x0, #(1<<16)
111        bic x0, x0, #(1<<17)
112        bic x0, x0, #(1<<18)
113        msr HCR_EL2, x0
114
115        /* Set to EL1h mode for eret */
116        mov x0, #0b00101
117        msr SPSR_EL2, x0
118
119        /* Set EL1 entry point */
120        adr x0, _el1_start
121        msr ELR_EL2, x0
122        eret
123_el1_start:
124#endif
125
126#ifdef RTEMS_SMP
127        /* Read MPIDR and get current processor index */
128        mrs     x7, mpidr_el1
129        and     x7, #0xff
130#endif
131
132#ifdef RTEMS_SMP
133        /*
134         * Get current per-CPU control and store it in PL1 only Thread ID
135         * Register (TPIDRPRW).
136         */
137#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
138        ldr     w1, =_Per_CPU_Information
139#else
140        ldr     x1, =_Per_CPU_Information
141#endif
142        add     x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2
143        mcr     p15, 0, x1, c13, c0, 4
144
145#endif
146
147        /* Calculate interrupt stack area end for current processor */
148#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
149        ldr     w1, =_ISR_Stack_size
150#else
151        ldr     x1, =_ISR_Stack_size
152#endif
153#ifdef RTEMS_SMP
154        add     x3, x7, #1
155        mul     x1, x1, x3
156#endif
157#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
158        ldr     w2, =_ISR_Stack_area_begin
159#else
160        ldr     x2, =_ISR_Stack_area_begin
161#endif
162        add     x3, x1, x2
163
164        /* Save original DAIF value */
165        mrs     x4, DAIF
166
167#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
168        mov     x8, XZR
169        mov     x9, XZR
170        mov     x10, XZR
171        mov     x11, XZR
172        mov     x12, XZR
173        mov     x13, XZR
174        mov     x14, XZR
175        mov     x15, XZR
176#endif
177
178        /*
179         * SPx: the stack pointer corresponding to the current exception level
180         * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1
181         * Exception operation (synchronous errors, IRQ, FIQ, System Errors) uses SP0
182        */
183#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
184        ldr     w1, =bsp_stack_exception_size
185#else
186        ldr     x1, =bsp_stack_exception_size
187#endif
188        /* Switch to SP0 and set exception stack */
189        msr     spsel, #0
190        mov     sp, x3
191        /* Switch back to SPx for normal operation */
192        msr     spsel, #1
193        sub     x3, x3, x1
194
195        /* Set SP1 stack used for normal operation */
196        mov     sp, x3
197
198        /* Stay in EL1 mode */
199
200#ifdef AARCH64_MULTILIB_VFP
201#ifdef AARCH64_MULTILIB_HAS_CPACR
202        /* Read CPACR */
203        mrs x0, CPACR_EL1
204
205        /* Enable EL1 access permissions for CP10 */
206        orr x0, x0, #(1 << 20)
207
208        /* Write CPACR */
209        msr CPACR_EL1, x0
210        isb
211#endif
212
213        /* FPU does not need to be enabled on AArch64 */
214
215#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
216        mov     x0, #0
217        mov     CPTR_EL3, XZR
218        mov     CPTR_EL2, XZR
219        mov     d0, XZR
220        mov     d1, XZR
221        mov     d2, XZR
222        mov     d3, XZR
223        mov     d4, XZR
224        mov     d5, XZR
225        mov     d6, XZR
226        mov     d7, XZR
227        mov     d8, XZR
228        mov     d9, XZR
229        mov     d10, XZR
230        mov     d11, XZR
231        mov     d12, XZR
232        mov     d13, XZR
233        mov     d14, XZR
234        mov     d15, XZR
235        mov     d16, XZR
236        mov     d17, XZR
237        mov     d18, XZR
238        mov     d19, XZR
239        mov     d20, XZR
240        mov     d21, XZR
241        mov     d22, XZR
242        mov     d23, XZR
243        mov     d24, XZR
244        mov     d25, XZR
245        mov     d26, XZR
246        mov     d27, XZR
247        mov     d28, XZR
248        mov     d29, XZR
249        mov     d30, XZR
250        mov     d31, XZR
251#endif /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
252
253#endif /* AARCH64_MULTILIB_VFP */
254
255        /*
256         * Invoke the start hook 0.
257         *
258         */
259
260        mov     x1, x5          /* machine type number or ~0 for DT boot */
261        bl      bsp_start_hook_0
262
263        /* Branch to start hook 1 */
264        bl      bsp_start_hook_1
265
266        /* Branch to boot card */
267        mov     x0, #0
268        bl      boot_card
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