source: rtems/bsps/aarch64/shared/start/start.S @ 9951cee

Last change on this file since 9951cee was 9951cee, checked in by Kinsey Moore <kinsey.moore@…>, on Feb 15, 2021 at 3:05:10 PM

bsps/aarch64: RTEMS_DEBUG stack alignment faults

Run with stack alignment faults enabled under RTEMS_DEBUG to catch any
stack misalignments early. This makes it easier to track them down
should they ever occur.

  • Property mode set to 100644
File size: 5.3 KB
Line 
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/**
4 * @file
5 *
6 * @ingroup RTEMSBSPsAArch64Shared
7 *
8 * @brief Boot and system start code.
9 */
10
11/*
12 * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
13 * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 *    notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 *    notice, this list of conditions and the following disclaimer in the
22 *    documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <rtems/asm.h>
38#include <rtems/score/percpu.h>
39
40#include <bspopts.h>
41
42        /* Global symbols */
43        .globl  _start
44        .section        ".bsp_start_text", "ax"
45
46/* Start entry */
47
48_start:
49
50        /*
51         * We do not save the context since we do not return to the boot
52         * loader but preserve x1 and x2 to allow access to bootloader parameters
53         */
54#ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION
55        mov     x5, x1          /* machine type number or ~0 for DT boot */
56        mov     x6, x2          /* physical address of ATAGs or DTB */
57#else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
58        mov     x0, XZR
59        mov     x1, XZR
60        mov     x2, XZR
61        mov     x3, XZR
62        mov     x4, XZR
63        mov     x5, XZR
64        mov     x6, XZR
65        mov     x7, XZR
66        mov     x8, XZR
67        mov     x9, XZR
68        mov     x10, XZR
69        mov     x11, XZR
70        mov     x12, XZR
71        mov     x13, XZR
72        mov     x14, XZR
73        mov     x15, XZR
74        mov     x16, XZR
75        mov     x17, XZR
76        mov     x18, XZR
77        mov     x19, XZR
78        mov     x20, XZR
79        mov     x21, XZR
80        mov     x22, XZR
81        mov     x23, XZR
82        mov     x24, XZR
83        mov     x25, XZR
84        mov     x26, XZR
85        mov     x27, XZR
86        mov     x28, XZR
87        mov     x29, XZR
88        mov     x30, XZR
89#ifdef AARCH64_MULTILIB_VFP
90#endif
91#endif
92
93        /* Initialize SCTLR_EL1 */
94        mov x0, XZR
95#if defined(RTEMS_DEBUG)
96        /* Enable Stack alignment checking */
97        orr x0, x0, #(1<<3)
98#endif
99        msr SCTLR_EL1, x0
100
101#ifdef RTEMS_SMP
102        /* Read MPIDR and get current processor index */
103        mrs     x7, mpidr_el1
104        and     x7, #0xff
105#endif
106
107#ifdef RTEMS_SMP
108        /*
109         * Get current per-CPU control and store it in PL1 only Thread ID
110         * Register (TPIDRPRW).
111         */
112#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
113        ldr     w1, =_Per_CPU_Information
114#else
115        ldr     x1, =_Per_CPU_Information
116#endif
117        add     x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2
118        mcr     p15, 0, x1, c13, c0, 4
119
120#endif
121
122        /* Calculate interrupt stack area end for current processor */
123#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
124        ldr     w1, =_ISR_Stack_size
125#else
126        ldr     x1, =_ISR_Stack_size
127#endif
128#ifdef RTEMS_SMP
129        add     x3, x7, #1
130        mul     x1, x1, x3
131#endif
132#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
133        ldr     w2, =_ISR_Stack_area_begin
134#else
135        ldr     x2, =_ISR_Stack_area_begin
136#endif
137        add     x3, x1, x2
138
139        /* Save original DAIF value */
140        mrs     x4, DAIF
141
142#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
143        mov     x8, XZR
144        mov     x9, XZR
145        mov     x10, XZR
146        mov     x11, XZR
147        mov     x12, XZR
148        mov     x13, XZR
149        mov     x14, XZR
150        mov     x15, XZR
151#endif
152
153        /*
154         * SPx: the stack pointer corresponding to the current exception level
155         * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1
156         * Exception operation (synchronous errors, IRQ, FIQ, System Errors) uses SP0
157        */
158#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
159        ldr     w1, =bsp_stack_exception_size
160#else
161        ldr     x1, =bsp_stack_exception_size
162#endif
163        /* Switch to SP0 and set exception stack */
164        msr     spsel, #0
165        mov     sp, x3
166        /* Switch back to SPx for normal operation */
167        msr     spsel, #1
168        sub     x3, x3, x1
169
170        /* Set SP1 stack used for normal operation */
171        mov     sp, x3
172
173        /* Stay in EL1 mode */
174
175#ifdef AARCH64_MULTILIB_VFP
176#ifdef AARCH64_MULTILIB_HAS_CPACR
177        /* Read CPACR */
178        mrs x0, CPACR_EL1
179
180        /* Enable EL1 access permissions for CP10 */
181        orr x0, x0, #(1 << 20)
182
183        /* Write CPACR */
184        msr CPACR_EL1, x0
185        isb
186#endif
187
188        /* FPU does not need to be enabled on AArch64 */
189
190#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
191        mov     x0, #0
192        mov     CPTR_EL3, XZR
193        mov     CPTR_EL2, XZR
194        mov     d0, XZR
195        mov     d1, XZR
196        mov     d2, XZR
197        mov     d3, XZR
198        mov     d4, XZR
199        mov     d5, XZR
200        mov     d6, XZR
201        mov     d7, XZR
202        mov     d8, XZR
203        mov     d9, XZR
204        mov     d10, XZR
205        mov     d11, XZR
206        mov     d12, XZR
207        mov     d13, XZR
208        mov     d14, XZR
209        mov     d15, XZR
210        mov     d16, XZR
211        mov     d17, XZR
212        mov     d18, XZR
213        mov     d19, XZR
214        mov     d20, XZR
215        mov     d21, XZR
216        mov     d22, XZR
217        mov     d23, XZR
218        mov     d24, XZR
219        mov     d25, XZR
220        mov     d26, XZR
221        mov     d27, XZR
222        mov     d28, XZR
223        mov     d29, XZR
224        mov     d30, XZR
225        mov     d31, XZR
226#endif /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
227
228#endif /* AARCH64_MULTILIB_VFP */
229
230        /*
231         * Invoke the start hook 0.
232         *
233         */
234
235        mov     x1, x5          /* machine type number or ~0 for DT boot */
236        bl      bsp_start_hook_0
237
238        /* Branch to start hook 1 */
239        bl      bsp_start_hook_1
240
241        /* Branch to boot card */
242        mov     x0, #0
243        bl      boot_card
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