source: rtems/bsps/aarch64/shared/start/start.S @ 93088fb8

Last change on this file since 93088fb8 was 93088fb8, checked in by Gedare Bloom <gedare@…>, on Jun 24, 2021 at 3:33:22 PM

bsps/aarch64: replace boot options with asm switch code

  • Property mode set to 100644
File size: 6.4 KB
Line 
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/**
4 * @file
5 *
6 * @ingroup RTEMSBSPsAArch64Shared
7 *
8 * @brief Boot and system start code.
9 */
10
11/*
12 * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
13 * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 *    notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 *    notice, this list of conditions and the following disclaimer in the
22 *    documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <rtems/asm.h>
38#include <rtems/score/percpu.h>
39
40#include <bspopts.h>
41
42        /* Global symbols */
43        .globl  _start
44        .section        ".bsp_start_text", "ax"
45
46/* Start entry */
47
48_start:
49
50        /*
51         * We do not save the context since we do not return to the boot
52         * loader but preserve x1 and x2 to allow access to bootloader parameters
53         */
54#ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION
55        mov     x5, x1          /* machine type number or ~0 for DT boot */
56        mov     x6, x2          /* physical address of ATAGs or DTB */
57#else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
58        mov     x0, XZR
59        mov     x1, XZR
60        mov     x2, XZR
61        mov     x3, XZR
62        mov     x4, XZR
63        mov     x5, XZR
64        mov     x6, XZR
65        mov     x7, XZR
66        mov     x8, XZR
67        mov     x9, XZR
68        mov     x10, XZR
69        mov     x11, XZR
70        mov     x12, XZR
71        mov     x13, XZR
72        mov     x14, XZR
73        mov     x15, XZR
74        mov     x16, XZR
75        mov     x17, XZR
76        mov     x18, XZR
77        mov     x19, XZR
78        mov     x20, XZR
79        mov     x21, XZR
80        mov     x22, XZR
81        mov     x23, XZR
82        mov     x24, XZR
83        mov     x25, XZR
84        mov     x26, XZR
85        mov     x27, XZR
86        mov     x28, XZR
87        mov     x29, XZR
88        mov     x30, XZR
89#ifdef AARCH64_MULTILIB_VFP
90#endif
91#endif
92
93        /* Initialize SCTLR_EL1 */
94        mov x0, XZR
95#if defined(RTEMS_DEBUG)
96        /* Enable Stack alignment checking */
97        orr x0, x0, #(1<<3)
98#endif
99        msr SCTLR_EL1, x0
100
101  mrs x0, CurrentEL
102  cmp x0, #(1<<2)
103  b.eq _el1_start
104  cmp x0, #(2<<2)
105  b.eq _el2_start
106
107_el3_start:
108        /* Drop from EL3 to EL2 */
109
110  /* Initialize HCR_EL2 and SCTLR_EL2 */
111  msr HCR_EL2, XZR
112  msr SCTLR_EL2, XZR
113  /* Set EL2 Execution state via SCR_EL3 */
114  mrs x0, SCR_EL3
115  /* Set EL2 to AArch64 */
116  orr x0, x0, #(1<<10)
117#ifdef AARCH64_IS_NONSECURE
118  /* Set EL1 to NS */
119  orr x0, x0, #1
120#endif
121  msr SCR_EL3, x0
122
123  /* set EL2h mode for eret */
124#ifdef AARCH64_IS_NONSECURE
125  mov x0, #0b01001
126#else
127  mov x0, #0b00101
128#endif
129
130  msr SPSR_EL3, x0
131
132  /* Set EL2 entry point */
133#ifdef AARCH64_IS_NONSECURE
134  adr x0, _el2_start
135#else
136  adr x0, _el1_start
137#endif
138  msr ELR_EL3, x0
139  eret
140
141_el2_start:
142        /* Drop from EL2 to EL1 */
143
144        /* Configure HCR_EL2 */
145        mrs x0, HCR_EL2
146        /* Set EL1 Execution state to AArch64 */
147        orr x0, x0, #(1<<31)
148        /* Disable ID traps */
149        bic x0, x0, #(1<<15)
150        bic x0, x0, #(1<<16)
151        bic x0, x0, #(1<<17)
152        bic x0, x0, #(1<<18)
153        msr HCR_EL2, x0
154
155        /* Set to EL1h mode for eret */
156        mov x0, #0b00101
157        msr SPSR_EL2, x0
158
159        /* Set EL1 entry point */
160        adr x0, _el1_start
161        msr ELR_EL2, x0
162        eret
163
164_el1_start:
165
166#ifdef RTEMS_SMP
167        /* Read MPIDR and get current processor index */
168        mrs     x7, mpidr_el1
169        and     x7, #0xff
170#endif
171
172#ifdef RTEMS_SMP
173        /*
174         * Get current per-CPU control and store it in PL1 only Thread ID
175         * Register (TPIDRPRW).
176         */
177#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
178        ldr     w1, =_Per_CPU_Information
179#else
180        ldr     x1, =_Per_CPU_Information
181#endif
182        add     x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2
183        mcr     p15, 0, x1, c13, c0, 4
184
185#endif
186
187        /* Calculate interrupt stack area end for current processor */
188#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
189        ldr     w1, =_ISR_Stack_size
190#else
191        ldr     x1, =_ISR_Stack_size
192#endif
193#ifdef RTEMS_SMP
194        add     x3, x7, #1
195        mul     x1, x1, x3
196#endif
197#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
198        ldr     w2, =_ISR_Stack_area_begin
199#else
200        ldr     x2, =_ISR_Stack_area_begin
201#endif
202        add     x3, x1, x2
203
204        /* Save original DAIF value */
205        mrs     x4, DAIF
206
207#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
208        mov     x8, XZR
209        mov     x9, XZR
210        mov     x10, XZR
211        mov     x11, XZR
212        mov     x12, XZR
213        mov     x13, XZR
214        mov     x14, XZR
215        mov     x15, XZR
216#endif
217
218        /*
219         * SPx: the stack pointer corresponding to the current exception level
220         * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1
221         * Exception operation (synchronous errors, IRQ, FIQ, System Errors) uses SP0
222        */
223#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
224        ldr     w1, =bsp_stack_exception_size
225#else
226        ldr     x1, =bsp_stack_exception_size
227#endif
228        /* Switch to SP0 and set exception stack */
229        msr     spsel, #0
230        mov     sp, x3
231        /* Switch back to SPx for normal operation */
232        msr     spsel, #1
233        sub     x3, x3, x1
234
235        /* Set SP1 stack used for normal operation */
236        mov     sp, x3
237
238        /* Stay in EL1 mode */
239
240#ifdef AARCH64_MULTILIB_VFP
241#ifdef AARCH64_MULTILIB_HAS_CPACR
242        /* Read CPACR */
243        mrs x0, CPACR_EL1
244
245        /* Enable EL1 access permissions for CP10 */
246        orr x0, x0, #(1 << 20)
247
248        /* Write CPACR */
249        msr CPACR_EL1, x0
250        isb
251#endif
252
253        /* FPU does not need to be enabled on AArch64 */
254
255#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
256        mov     x0, #0
257        mov     CPTR_EL3, XZR
258        mov     CPTR_EL2, XZR
259        mov     d0, XZR
260        mov     d1, XZR
261        mov     d2, XZR
262        mov     d3, XZR
263        mov     d4, XZR
264        mov     d5, XZR
265        mov     d6, XZR
266        mov     d7, XZR
267        mov     d8, XZR
268        mov     d9, XZR
269        mov     d10, XZR
270        mov     d11, XZR
271        mov     d12, XZR
272        mov     d13, XZR
273        mov     d14, XZR
274        mov     d15, XZR
275        mov     d16, XZR
276        mov     d17, XZR
277        mov     d18, XZR
278        mov     d19, XZR
279        mov     d20, XZR
280        mov     d21, XZR
281        mov     d22, XZR
282        mov     d23, XZR
283        mov     d24, XZR
284        mov     d25, XZR
285        mov     d26, XZR
286        mov     d27, XZR
287        mov     d28, XZR
288        mov     d29, XZR
289        mov     d30, XZR
290        mov     d31, XZR
291#endif /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
292
293#endif /* AARCH64_MULTILIB_VFP */
294
295        /*
296         * Invoke the start hook 0.
297         *
298         */
299
300        mov     x1, x5          /* machine type number or ~0 for DT boot */
301        bl      bsp_start_hook_0
302
303        /* Branch to start hook 1 */
304        bl      bsp_start_hook_1
305
306        /* Branch to boot card */
307        mov     x0, #0
308        bl      boot_card
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