1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @ingroup RTEMSBSPsAArch64Shared |
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7 | * |
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8 | * @brief Boot and system start code. |
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9 | */ |
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10 | |
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11 | /* |
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12 | * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) |
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13 | * Written by Kinsey Moore <kinsey.moore@oarcorp.com> |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions |
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17 | * are met: |
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18 | * 1. Redistributions of source code must retain the above copyright |
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19 | * notice, this list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright |
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21 | * notice, this list of conditions and the following disclaimer in the |
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22 | * documentation and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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34 | * POSSIBILITY OF SUCH DAMAGE. |
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35 | */ |
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36 | |
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37 | #include <rtems/asm.h> |
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38 | #include <rtems/score/percpu.h> |
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39 | |
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40 | #include <bspopts.h> |
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41 | |
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42 | /* Global symbols */ |
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43 | .globl _start |
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44 | .section ".bsp_start_text", "ax" |
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45 | |
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46 | /* Start entry */ |
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47 | |
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48 | _start: |
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49 | |
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50 | /* |
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51 | * We do not save the context since we do not return to the boot |
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52 | * loader but preserve x1 and x2 to allow access to bootloader parameters |
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53 | */ |
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54 | #ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION |
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55 | mov x5, x1 /* machine type number or ~0 for DT boot */ |
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56 | mov x6, x2 /* physical address of ATAGs or DTB */ |
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57 | #else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */ |
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58 | mov x0, XZR |
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59 | mov x1, XZR |
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60 | mov x2, XZR |
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61 | mov x3, XZR |
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62 | mov x4, XZR |
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63 | mov x5, XZR |
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64 | mov x6, XZR |
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65 | mov x7, XZR |
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66 | mov x8, XZR |
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67 | mov x9, XZR |
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68 | mov x10, XZR |
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69 | mov x11, XZR |
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70 | mov x12, XZR |
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71 | mov x13, XZR |
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72 | mov x14, XZR |
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73 | mov x15, XZR |
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74 | mov x16, XZR |
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75 | mov x17, XZR |
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76 | mov x18, XZR |
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77 | mov x19, XZR |
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78 | mov x20, XZR |
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79 | mov x21, XZR |
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80 | mov x22, XZR |
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81 | mov x23, XZR |
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82 | mov x24, XZR |
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83 | mov x25, XZR |
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84 | mov x26, XZR |
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85 | mov x27, XZR |
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86 | mov x28, XZR |
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87 | mov x29, XZR |
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88 | mov x30, XZR |
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89 | #ifdef AARCH64_MULTILIB_VFP |
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90 | #endif |
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91 | #endif |
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92 | |
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93 | #ifdef RTEMS_SMP |
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94 | /* Read MPIDR and get current processor index */ |
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95 | mrs x7, mpidr_el1 |
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96 | and x7, #0xff |
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97 | #endif |
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98 | |
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99 | #ifdef RTEMS_SMP |
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100 | /* |
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101 | * Get current per-CPU control and store it in PL1 only Thread ID |
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102 | * Register (TPIDRPRW). |
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103 | */ |
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104 | #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 |
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105 | ldr w1, =_Per_CPU_Information |
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106 | #else |
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107 | ldr x1, =_Per_CPU_Information |
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108 | #endif |
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109 | add x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2 |
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110 | mcr p15, 0, x1, c13, c0, 4 |
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111 | |
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112 | #endif |
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113 | |
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114 | /* Calculate interrupt stack area end for current processor */ |
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115 | #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 |
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116 | ldr w1, =_ISR_Stack_size |
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117 | #else |
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118 | ldr x1, =_ISR_Stack_size |
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119 | #endif |
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120 | #ifdef RTEMS_SMP |
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121 | add x3, x7, #1 |
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122 | mul x1, x1, x3 |
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123 | #endif |
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124 | #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 |
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125 | ldr w2, =_ISR_Stack_area_begin |
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126 | #else |
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127 | ldr x2, =_ISR_Stack_area_begin |
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128 | #endif |
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129 | add x3, x1, x2 |
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130 | |
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131 | /* Save original DAIF value */ |
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132 | mrs x4, DAIF |
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133 | |
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134 | #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION |
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135 | mov x8, XZR |
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136 | mov x9, XZR |
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137 | mov x10, XZR |
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138 | mov x11, XZR |
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139 | mov x12, XZR |
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140 | mov x13, XZR |
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141 | mov x14, XZR |
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142 | mov x15, XZR |
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143 | #endif |
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144 | |
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145 | /* |
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146 | * SPx: the stack pointer corresponding to the current exception level |
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147 | * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1 |
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148 | * Exception operation (synchronous errors, IRQ, FIQ, System Errors) uses SP0 |
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149 | */ |
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150 | #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 |
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151 | ldr w1, =bsp_stack_exception_size |
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152 | #else |
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153 | ldr x1, =bsp_stack_exception_size |
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154 | #endif |
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155 | /* Switch to SP0 and set exception stack */ |
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156 | msr spsel, #0 |
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157 | mov sp, x3 |
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158 | /* Switch back to SPx for normal operation */ |
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159 | msr spsel, #1 |
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160 | sub x3, x3, x1 |
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161 | |
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162 | /* Set SP1 stack used for normal operation */ |
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163 | mov sp, x3 |
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164 | |
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165 | /* Stay in EL1 mode */ |
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166 | |
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167 | #ifdef AARCH64_MULTILIB_VFP |
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168 | #ifdef AARCH64_MULTILIB_HAS_CPACR |
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169 | /* Read CPACR */ |
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170 | mrs x0, CPACR_EL1 |
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171 | |
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172 | /* Enable EL1 access permissions for CP10 */ |
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173 | orr x0, x0, #(1 << 20) |
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174 | |
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175 | /* Write CPACR */ |
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176 | msr CPACR_EL1, x0 |
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177 | isb |
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178 | #endif |
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179 | |
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180 | /* FPU does not need to be enabled on AArch64 */ |
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181 | |
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182 | #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION |
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183 | mov x0, #0 |
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184 | mov CPTR_EL3, XZR |
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185 | mov CPTR_EL2, XZR |
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186 | mov d0, XZR |
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187 | mov d1, XZR |
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188 | mov d2, XZR |
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189 | mov d3, XZR |
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190 | mov d4, XZR |
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191 | mov d5, XZR |
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192 | mov d6, XZR |
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193 | mov d7, XZR |
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194 | mov d8, XZR |
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195 | mov d9, XZR |
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196 | mov d10, XZR |
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197 | mov d11, XZR |
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198 | mov d12, XZR |
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199 | mov d13, XZR |
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200 | mov d14, XZR |
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201 | mov d15, XZR |
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202 | mov d16, XZR |
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203 | mov d17, XZR |
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204 | mov d18, XZR |
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205 | mov d19, XZR |
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206 | mov d20, XZR |
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207 | mov d21, XZR |
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208 | mov d22, XZR |
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209 | mov d23, XZR |
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210 | mov d24, XZR |
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211 | mov d25, XZR |
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212 | mov d26, XZR |
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213 | mov d27, XZR |
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214 | mov d28, XZR |
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215 | mov d29, XZR |
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216 | mov d30, XZR |
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217 | mov d31, XZR |
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218 | #endif /* BSP_START_NEEDS_REGISTER_INITIALIZATION */ |
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219 | |
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220 | #endif /* AARCH64_MULTILIB_VFP */ |
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221 | |
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222 | /* |
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223 | * Invoke the start hook 0. |
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224 | * |
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225 | */ |
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226 | |
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227 | mov x1, x5 /* machine type number or ~0 for DT boot */ |
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228 | bl bsp_start_hook_0 |
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229 | |
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230 | /* Branch to start hook 1 */ |
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231 | bl bsp_start_hook_1 |
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232 | |
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233 | /* Branch to boot card */ |
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234 | mov x0, #0 |
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235 | bl boot_card |
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