[db68ea1] | 1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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| 2 | |
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| 3 | /** |
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| 4 | * @file |
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| 5 | * |
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| 6 | * @ingroup RTEMSBSPsAArch64Shared |
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| 7 | * |
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| 8 | * @brief Boot and system start code. |
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| 9 | */ |
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| 10 | |
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| 11 | /* |
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| 12 | * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) |
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| 13 | * Written by Kinsey Moore <kinsey.moore@oarcorp.com> |
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| 14 | * |
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| 15 | * Redistribution and use in source and binary forms, with or without |
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| 16 | * modification, are permitted provided that the following conditions |
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| 17 | * are met: |
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| 18 | * 1. Redistributions of source code must retain the above copyright |
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| 19 | * notice, this list of conditions and the following disclaimer. |
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| 20 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 21 | * notice, this list of conditions and the following disclaimer in the |
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| 22 | * documentation and/or other materials provided with the distribution. |
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| 23 | * |
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| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 34 | * POSSIBILITY OF SUCH DAMAGE. |
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| 35 | */ |
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| 36 | |
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| 37 | #include <rtems/asm.h> |
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| 38 | #include <rtems/score/percpu.h> |
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| 39 | |
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| 40 | #include <bspopts.h> |
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| 41 | |
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[17a9103] | 42 | /* Global symbols */ |
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| 43 | .globl _start |
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| 44 | .section ".bsp_start_text", "ax" |
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[db68ea1] | 45 | |
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| 46 | /* Start entry */ |
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| 47 | |
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| 48 | _start: |
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| 49 | |
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[17a9103] | 50 | /* |
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| 51 | * We do not save the context since we do not return to the boot |
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| 52 | * loader but preserve x1 and x2 to allow access to bootloader parameters |
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| 53 | */ |
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[db68ea1] | 54 | #ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION |
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[17a9103] | 55 | mov x5, x1 /* machine type number or ~0 for DT boot */ |
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| 56 | mov x6, x2 /* physical address of ATAGs or DTB */ |
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[db68ea1] | 57 | #else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */ |
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[17a9103] | 58 | mov x0, XZR |
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| 59 | mov x1, XZR |
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| 60 | mov x2, XZR |
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| 61 | mov x3, XZR |
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| 62 | mov x4, XZR |
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| 63 | mov x5, XZR |
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| 64 | mov x6, XZR |
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| 65 | mov x7, XZR |
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| 66 | mov x8, XZR |
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| 67 | mov x9, XZR |
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| 68 | mov x10, XZR |
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| 69 | mov x11, XZR |
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| 70 | mov x12, XZR |
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| 71 | mov x13, XZR |
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| 72 | mov x14, XZR |
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| 73 | mov x15, XZR |
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| 74 | mov x16, XZR |
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| 75 | mov x17, XZR |
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| 76 | mov x18, XZR |
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| 77 | mov x19, XZR |
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| 78 | mov x20, XZR |
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| 79 | mov x21, XZR |
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| 80 | mov x22, XZR |
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| 81 | mov x23, XZR |
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| 82 | mov x24, XZR |
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| 83 | mov x25, XZR |
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| 84 | mov x26, XZR |
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| 85 | mov x27, XZR |
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| 86 | mov x28, XZR |
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| 87 | mov x29, XZR |
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| 88 | mov x30, XZR |
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[db68ea1] | 89 | #ifdef AARCH64_MULTILIB_VFP |
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| 90 | #endif |
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| 91 | #endif |
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| 92 | |
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[17a9103] | 93 | /* Initialize SCTLR_EL1 */ |
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| 94 | mov x0, XZR |
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[9951cee] | 95 | #if defined(RTEMS_DEBUG) |
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[17a9103] | 96 | /* Enable Stack alignment checking */ |
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| 97 | orr x0, x0, #(1<<3) |
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[9951cee] | 98 | #endif |
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[17a9103] | 99 | msr SCTLR_EL1, x0 |
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[9951cee] | 100 | |
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[93088fb8] | 101 | mrs x0, CurrentEL |
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| 102 | cmp x0, #(1<<2) |
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| 103 | b.eq _el1_start |
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| 104 | cmp x0, #(2<<2) |
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| 105 | b.eq _el2_start |
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| 106 | |
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| 107 | _el3_start: |
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[17a9103] | 108 | /* Drop from EL3 to EL2 */ |
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[e613068e] | 109 | |
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| 110 | /* Initialize HCR_EL2 and SCTLR_EL2 */ |
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| 111 | msr HCR_EL2, XZR |
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| 112 | msr SCTLR_EL2, XZR |
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| 113 | /* Set EL2 Execution state via SCR_EL3 */ |
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| 114 | mrs x0, SCR_EL3 |
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| 115 | /* Set EL2 to AArch64 */ |
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| 116 | orr x0, x0, #(1<<10) |
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[76c6caad] | 117 | #ifdef AARCH64_IS_NONSECURE |
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[e613068e] | 118 | /* Set EL1 to NS */ |
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| 119 | orr x0, x0, #1 |
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[76c6caad] | 120 | #endif |
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[e613068e] | 121 | msr SCR_EL3, x0 |
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| 122 | |
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| 123 | /* set EL2h mode for eret */ |
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[76c6caad] | 124 | #ifdef AARCH64_IS_NONSECURE |
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[e613068e] | 125 | mov x0, #0b01001 |
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[76c6caad] | 126 | #else |
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| 127 | mov x0, #0b00101 |
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| 128 | #endif |
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| 129 | |
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[e613068e] | 130 | msr SPSR_EL3, x0 |
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| 131 | |
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| 132 | /* Set EL2 entry point */ |
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[76c6caad] | 133 | #ifdef AARCH64_IS_NONSECURE |
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[e613068e] | 134 | adr x0, _el2_start |
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[76c6caad] | 135 | #else |
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| 136 | adr x0, _el1_start |
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| 137 | #endif |
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[e613068e] | 138 | msr ELR_EL3, x0 |
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| 139 | eret |
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| 140 | |
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| 141 | _el2_start: |
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[17a9103] | 142 | /* Drop from EL2 to EL1 */ |
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| 143 | |
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| 144 | /* Configure HCR_EL2 */ |
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| 145 | mrs x0, HCR_EL2 |
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| 146 | /* Set EL1 Execution state to AArch64 */ |
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| 147 | orr x0, x0, #(1<<31) |
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| 148 | /* Disable ID traps */ |
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| 149 | bic x0, x0, #(1<<15) |
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| 150 | bic x0, x0, #(1<<16) |
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| 151 | bic x0, x0, #(1<<17) |
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| 152 | bic x0, x0, #(1<<18) |
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| 153 | msr HCR_EL2, x0 |
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| 154 | |
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| 155 | /* Set to EL1h mode for eret */ |
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| 156 | mov x0, #0b00101 |
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| 157 | msr SPSR_EL2, x0 |
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| 158 | |
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| 159 | /* Set EL1 entry point */ |
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| 160 | adr x0, _el1_start |
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| 161 | msr ELR_EL2, x0 |
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| 162 | eret |
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[93088fb8] | 163 | |
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[a27ba3f] | 164 | _el1_start: |
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| 165 | |
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[db68ea1] | 166 | #ifdef RTEMS_SMP |
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[17a9103] | 167 | /* Read MPIDR and get current processor index */ |
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| 168 | mrs x7, mpidr_el1 |
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| 169 | and x7, #0xff |
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[db68ea1] | 170 | #endif |
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| 171 | |
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| 172 | #ifdef RTEMS_SMP |
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[17a9103] | 173 | /* |
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| 174 | * Get current per-CPU control and store it in PL1 only Thread ID |
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| 175 | * Register (TPIDRPRW). |
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| 176 | */ |
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[ed9c88c] | 177 | #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 |
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[17a9103] | 178 | ldr w1, =_Per_CPU_Information |
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[ed9c88c] | 179 | #else |
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[17a9103] | 180 | ldr x1, =_Per_CPU_Information |
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[ed9c88c] | 181 | #endif |
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[17a9103] | 182 | add x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2 |
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| 183 | mcr p15, 0, x1, c13, c0, 4 |
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[db68ea1] | 184 | |
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| 185 | #endif |
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| 186 | |
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[17a9103] | 187 | /* Calculate interrupt stack area end for current processor */ |
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[ed9c88c] | 188 | #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 |
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[17a9103] | 189 | ldr w1, =_ISR_Stack_size |
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[ed9c88c] | 190 | #else |
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[17a9103] | 191 | ldr x1, =_ISR_Stack_size |
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[ed9c88c] | 192 | #endif |
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[db68ea1] | 193 | #ifdef RTEMS_SMP |
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[17a9103] | 194 | add x3, x7, #1 |
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| 195 | mul x1, x1, x3 |
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[db68ea1] | 196 | #endif |
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[ed9c88c] | 197 | #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 |
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[17a9103] | 198 | ldr w2, =_ISR_Stack_area_begin |
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[ed9c88c] | 199 | #else |
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[17a9103] | 200 | ldr x2, =_ISR_Stack_area_begin |
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[ed9c88c] | 201 | #endif |
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[17a9103] | 202 | add x3, x1, x2 |
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[db68ea1] | 203 | |
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[17a9103] | 204 | /* Save original DAIF value */ |
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| 205 | mrs x4, DAIF |
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[db68ea1] | 206 | |
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| 207 | #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION |
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[17a9103] | 208 | mov x8, XZR |
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| 209 | mov x9, XZR |
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| 210 | mov x10, XZR |
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| 211 | mov x11, XZR |
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| 212 | mov x12, XZR |
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| 213 | mov x13, XZR |
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| 214 | mov x14, XZR |
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| 215 | mov x15, XZR |
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[db68ea1] | 216 | #endif |
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| 217 | |
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[17a9103] | 218 | /* |
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| 219 | * SPx: the stack pointer corresponding to the current exception level |
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| 220 | * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1 |
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| 221 | * Exception operation (synchronous errors, IRQ, FIQ, System Errors) uses SP0 |
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| 222 | */ |
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[ed9c88c] | 223 | #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 |
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[17a9103] | 224 | ldr w1, =bsp_stack_exception_size |
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[ed9c88c] | 225 | #else |
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[17a9103] | 226 | ldr x1, =bsp_stack_exception_size |
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[ed9c88c] | 227 | #endif |
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[17a9103] | 228 | /* Switch to SP0 and set exception stack */ |
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| 229 | msr spsel, #0 |
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| 230 | mov sp, x3 |
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| 231 | /* Switch back to SPx for normal operation */ |
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| 232 | msr spsel, #1 |
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| 233 | sub x3, x3, x1 |
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[db68ea1] | 234 | |
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[17a9103] | 235 | /* Set SP1 stack used for normal operation */ |
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| 236 | mov sp, x3 |
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[db68ea1] | 237 | |
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[17a9103] | 238 | /* Stay in EL1 mode */ |
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[db68ea1] | 239 | |
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| 240 | #ifdef AARCH64_MULTILIB_VFP |
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| 241 | #ifdef AARCH64_MULTILIB_HAS_CPACR |
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[17a9103] | 242 | /* Read CPACR */ |
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| 243 | mrs x0, CPACR_EL1 |
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[db68ea1] | 244 | |
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[17a9103] | 245 | /* Enable EL1 access permissions for CP10 */ |
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| 246 | orr x0, x0, #(1 << 20) |
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[db68ea1] | 247 | |
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[17a9103] | 248 | /* Write CPACR */ |
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| 249 | msr CPACR_EL1, x0 |
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| 250 | isb |
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[db68ea1] | 251 | #endif |
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| 252 | |
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[17a9103] | 253 | /* FPU does not need to be enabled on AArch64 */ |
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[db68ea1] | 254 | |
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| 255 | #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION |
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[17a9103] | 256 | mov x0, #0 |
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| 257 | mov CPTR_EL3, XZR |
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| 258 | mov CPTR_EL2, XZR |
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| 259 | mov d0, XZR |
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| 260 | mov d1, XZR |
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| 261 | mov d2, XZR |
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| 262 | mov d3, XZR |
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| 263 | mov d4, XZR |
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| 264 | mov d5, XZR |
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| 265 | mov d6, XZR |
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| 266 | mov d7, XZR |
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| 267 | mov d8, XZR |
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| 268 | mov d9, XZR |
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| 269 | mov d10, XZR |
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| 270 | mov d11, XZR |
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| 271 | mov d12, XZR |
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| 272 | mov d13, XZR |
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| 273 | mov d14, XZR |
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| 274 | mov d15, XZR |
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| 275 | mov d16, XZR |
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| 276 | mov d17, XZR |
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| 277 | mov d18, XZR |
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| 278 | mov d19, XZR |
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| 279 | mov d20, XZR |
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| 280 | mov d21, XZR |
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| 281 | mov d22, XZR |
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| 282 | mov d23, XZR |
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| 283 | mov d24, XZR |
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| 284 | mov d25, XZR |
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| 285 | mov d26, XZR |
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| 286 | mov d27, XZR |
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| 287 | mov d28, XZR |
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| 288 | mov d29, XZR |
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| 289 | mov d30, XZR |
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| 290 | mov d31, XZR |
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[db68ea1] | 291 | #endif /* BSP_START_NEEDS_REGISTER_INITIALIZATION */ |
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| 292 | |
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| 293 | #endif /* AARCH64_MULTILIB_VFP */ |
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| 294 | |
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[17a9103] | 295 | /* |
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| 296 | * Invoke the start hook 0. |
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| 297 | * |
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| 298 | */ |
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[db68ea1] | 299 | |
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[17a9103] | 300 | mov x1, x5 /* machine type number or ~0 for DT boot */ |
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| 301 | bl bsp_start_hook_0 |
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[db68ea1] | 302 | |
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[17a9103] | 303 | /* Branch to start hook 1 */ |
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| 304 | bl bsp_start_hook_1 |
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[db68ea1] | 305 | |
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[17a9103] | 306 | /* Branch to boot card */ |
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| 307 | mov x0, #0 |
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| 308 | bl boot_card |
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