1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @ingroup RTEMSBSPsAArch64Shared |
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7 | * |
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8 | * @brief SMP startup and interop code. |
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9 | */ |
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10 | |
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11 | /* |
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12 | * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) |
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13 | * Written by Kinsey Moore <kinsey.moore@oarcorp.com> |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions |
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17 | * are met: |
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18 | * 1. Redistributions of source code must retain the above copyright |
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19 | * notice, this list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright |
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21 | * notice, this list of conditions and the following disclaimer in the |
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22 | * documentation and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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34 | * POSSIBILITY OF SUCH DAMAGE. |
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35 | */ |
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36 | |
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37 | #include <rtems/score/smpimpl.h> |
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38 | |
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39 | #include <bsp/irq.h> |
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40 | |
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41 | static void bsp_inter_processor_interrupt( void *arg ) |
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42 | { |
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43 | _SMP_Inter_processor_interrupt_handler( _Per_CPU_Get() ); |
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44 | } |
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45 | |
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46 | uint32_t _CPU_SMP_Initialize( void ) |
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47 | { |
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48 | return arm_gic_irq_processor_count(); |
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49 | } |
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50 | |
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51 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ) |
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52 | { |
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53 | if ( cpu_count > 0 ) { |
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54 | rtems_status_code sc; |
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55 | |
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56 | sc = rtems_interrupt_handler_install( |
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57 | ARM_GIC_IRQ_SGI_0, |
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58 | "IPI", |
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59 | RTEMS_INTERRUPT_UNIQUE, |
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60 | bsp_inter_processor_interrupt, |
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61 | NULL |
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62 | ); |
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63 | _Assert( sc == RTEMS_SUCCESSFUL ); |
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64 | (void) sc; |
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65 | |
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66 | #if defined( BSP_DATA_CACHE_ENABLED ) || \ |
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67 | defined( BSP_INSTRUCTION_CACHE_ENABLED ) |
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68 | /* Enable unified L2 cache */ |
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69 | rtems_cache_enable_data(); |
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70 | #endif |
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71 | } |
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72 | } |
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73 | |
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74 | void _CPU_SMP_Prepare_start_multitasking( void ) |
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75 | { |
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76 | /* Do nothing */ |
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77 | } |
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78 | |
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79 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ) |
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80 | { |
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81 | arm_gic_irq_generate_software_irq( |
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82 | ARM_GIC_IRQ_SGI_0, |
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83 | 1U << target_processor_index |
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84 | ); |
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85 | } |
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