source: rtems/bsps/aarch64/raspberrypi/include/bsp/irq.h @ b57c6541

Last change on this file since b57c6541 was b57c6541, checked in by Mohd Noor Aman <nooraman5718@…>, on 10/04/22 at 21:38:48

bsp/aarch64: Add new Raspberry Pi 4B BSP

This patch adds new Raspberry pi 4B AArch64 BSP to the RTEMS Family. Currently
only LP64 ABI is supported. ILP32 is not supported. RAM starts from 0x80000 in
64Bit kernel mode and MMU from 0x0. All Raspberrypi Pi 4B models and Raspberry
Pi 400 are supported. All the IRQs are similiar to the older Raspberry pi 2 ARM
BSP.

Raspberry Pi 4B has 2 types of UARTs. Only PL011 serial is supported currently.
Mini-UART is not supported. Mini-UART is default UART on the board so it needs
to be disabled by adding "dtoverlay=disable-bt" to the config.txt. No support
for additional 4 PL011-UARTs on the board.

The raspberrypi.h includes many of the address required for the future
development of the RPi 4B BSP. This includes peripherals, ARM Timer, VideoCore?
Timer, Watchdog, Mailbox, AUX, FIQs and IRQs.

  • Property mode set to 100644
File size: 2.7 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup raspberrypi_interrupt
5 *
6 * @brief Interrupt definitions.
7 */
8
9/**
10 * Copyright (c) 2013 Alan Cudmore
11 * Copyright (c) 2022 Mohd Noor Aman
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *
16 *  http://www.rtems.org/license/LICENSE
17 *
18 */
19
20#ifndef LIBBSP_ARM_RASPBERRYPI_IRQ_H
21#define LIBBSP_ARM_RASPBERRYPI_IRQ_H
22
23#ifndef ASM
24
25#include <rtems.h>
26#include <rtems/irq.h>
27#include <rtems/irq-extension.h>
28#include <dev/irq/arm-gic-irq.h>
29
30#if defined(RTEMS_SMP)
31#include <rtems/score/processormask.h>
32#endif
33
34/**
35 * @defgroup raspberrypi_interrupt Interrrupt Support
36 *
37 * @ingroup RTEMSBSPsARMRaspberryPi
38 *
39 * @brief Interrupt support.
40 */
41
42#define BCM2835_INTC_TOTAL_IRQ       (64 + 8)
43
44#define BCM2835_IRQ_SET1_MIN         0
45#define BCM2835_IRQ_SET2_MIN         32
46
47#define BCM2835_IRQ_ID_GPU_TIMER_M0  0
48#define BCM2835_IRQ_ID_GPU_TIMER_M1  1
49#define BCM2835_IRQ_ID_GPU_TIMER_M2  2
50#define BCM2835_IRQ_ID_GPU_TIMER_M3  3
51
52#define BCM2835_IRQ_ID_USB           9
53#define BCM2835_IRQ_ID_AUX           29
54#define BCM2835_IRQ_ID_SPI_SLAVE     43
55#define BCM2835_IRQ_ID_PWA0          45
56#define BCM2835_IRQ_ID_PWA1          46
57#define BCM2835_IRQ_ID_SMI           48
58#define BCM2835_IRQ_ID_GPIO_0        49
59#define BCM2835_IRQ_ID_GPIO_1        50
60#define BCM2835_IRQ_ID_GPIO_2        51
61#define BCM2835_IRQ_ID_GPIO_3        52
62#define BCM2835_IRQ_ID_I2C           53
63#define BCM2835_IRQ_ID_SPI           54
64#define BCM2835_IRQ_ID_PCM           55
65#define BCM2835_IRQ_ID_UART          57
66#define BCM2835_IRQ_ID_SD            62
67
68#define BCM2835_IRQ_ID_BASIC_BASE_ID 64
69#define BCM2835_IRQ_ID_TIMER_0       64
70#define BCM2835_IRQ_ID_MAILBOX_0     65
71#define BCM2835_IRQ_ID_DOORBELL_0    66
72#define BCM2835_IRQ_ID_DOORBELL_1    67
73#define BCM2835_IRQ_ID_GPU0_HALTED   68
74#define BCM2835_IRQ_ID_GPU1_HALTED   69
75#define BCM2835_IRQ_ID_ILL_ACCESS_1  70
76#define BCM2835_IRQ_ID_ILL_ACCESS_0  71
77#define BSP_TIMER_VIRT_PPI 27
78#define BSP_TIMER_PHYS_NS_PPI 30
79#define BSP_VPL011_SPI 32
80
81#define BSP_INTERRUPT_VECTOR_COUNT    BCM2835_INTC_TOTAL_IRQ
82#define BSP_INTERRUPT_VECTOR_INVALID (UINT32_MAX)
83
84#define BSP_IRQ_COUNT               (BCM2835_INTC_TOTAL_IRQ)
85
86#if defined(RTEMS_SMP)
87static inline rtems_status_code bsp_interrupt_set_affinity(
88  rtems_vector_number   vector,
89  const Processor_mask *affinity
90)
91{
92  (void) vector;
93  (void) affinity;
94  return RTEMS_UNSATISFIED;
95}
96
97static inline rtems_status_code bsp_interrupt_get_affinity(
98  rtems_vector_number  vector,
99  Processor_mask      *affinity
100)
101{
102  (void) vector;
103  _Processor_mask_From_index( affinity, 0 );
104  return RTEMS_UNSATISFIED;
105}
106#endif
107
108#endif /* ASM */
109#endif /* LIBBSP_ARM_RASPBERRYPI_IRQ_H */
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