source:
rtems-tools/tools/4.11/gdb/sparc/7.9/0021-sim-erc32-Add-data-watchpoint-support.patch
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bfd2b7d
Last change on this file since bfd2b7d was bfd2b7d, checked in by Joel Sherrill <joel.sherrill@…>, on 03/26/15 at 18:20:45 | |
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File size: 10.1 KB |
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sim/erc32/exec.c
From 933b0b5f256713f50959cd1f1c6ad565f40b12ab Mon Sep 17 00:00:00 2001 From: Jiri Gaisler <jiri@gaisler.se> Date: Thu, 19 Feb 2015 23:21:02 +0100 Subject: [PATCH 21/23] sim/erc32: Add data watchpoint support Add watchpoint to all processor targets (erc32, leon2, leon3). --- sim/erc32/exec.c | 54 +++++++++++++++++++++++++++------- sim/erc32/func.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- sim/erc32/sis.c | 32 +++++++++++++++----- sim/erc32/sis.h | 23 ++++++++++++++- 4 files changed, 179 insertions(+), 20 deletions(-) diff --git a/sim/erc32/exec.c b/sim/erc32/exec.c index f4a0124..134e789 100644
a b extract_byte_signed(uint32 data, uint32 address) 395 395 return(tmp); 396 396 } 397 397 398 /* Decode watchpoint address mask from opcode. Not correct for LDST, 399 SWAP and STFSR but watchpoints will work anyway. */ 400 401 static unsigned char 402 wpmask(uint32 op3) 403 { 404 switch (op3 & 3) { 405 case 0: return(3); /* word */ 406 case 1: return(0); /* byte */ 407 case 2: return(1); /* half-word */ 408 case 3: return(7); /* double word */ 409 } 410 } 411 398 412 int 399 413 dispatch_instruction(sregs) 400 414 struct pstate *sregs; … … dispatch_instruction(sregs) 698 712 } 699 713 if (eicc & 1) { 700 714 sregs->trap = (0x80 | ((rs1 + operand2) & 0x7f)); 715 if ((sregs->trap == 129) && (sis_gdb_break) && 716 (sregs->inst == 0x91d02001)) 717 { 718 sregs->trap = WPT_TRAP; 719 sregs->bphit = 1; 720 } 701 721 } 702 722 break; 703 723 … … dispatch_instruction(sregs) 1211 1231 1212 1232 address = rs1 + operand2; 1213 1233 1214 if (sregs->psr & PSR_S)1215 asi = 11;1216 else1217 asi = 10;1218 1219 1234 if (op3 & 4) { 1220 1235 sregs->icnt = T_ST; /* Set store instruction count */ 1236 if (sregs->wpwnum) { 1237 if (sregs->wphit = check_wpw(sregs, address, wpmask(op3))) { 1238 sregs->trap = WPT_TRAP; 1239 break; 1240 } 1241 } 1221 1242 #ifdef STAT 1222 1243 sregs->nstore++; 1223 1244 #endif 1224 1245 } else { 1225 1246 sregs->icnt = T_LD; /* Set load instruction count */ 1247 if (sregs->wprnum) { 1248 if (sregs->wphit = check_wpr(sregs, address, wpmask(op3))) { 1249 sregs->trap = WPT_TRAP; 1250 break; 1251 } 1252 } 1226 1253 #ifdef STAT 1227 1254 sregs->nload++; 1228 1255 #endif … … execute_trap(sregs) 2133 2160 { 2134 2161 int32 cwp; 2135 2162 2136 if (sregs->trap == 256) { 2137 sregs->pc = 0; 2138 sregs->npc = 4; 2139 sregs->trap = 0; 2140 } else if (sregs->trap == 257) { 2163 if (sregs->trap >= 256) { 2164 switch (sregs->trap) { 2165 case 256: 2166 sregs->pc = 0; 2167 sregs->npc = 4; 2168 sregs->trap = 0; 2169 break; 2170 case ERROR_TRAP: 2141 2171 return (ERROR); 2172 case WPT_TRAP: 2173 return (WPT_HIT); 2174 } 2142 2175 } else { 2143 2176 2144 2177 if ((sregs->psr & PSR_ET) == 0) … … init_regs(sregs) 2231 2264 sregs->fpu_pres = !nfp; 2232 2265 set_fsr(sregs->fsr); 2233 2266 sregs->bphit = 0; 2267 sregs->wphit = 0; 2234 2268 sregs->ildreg = 0; 2235 2269 sregs->ildtime = 0; 2236 2270 -
sim/erc32/func.c
diff --git a/sim/erc32/func.c b/sim/erc32/func.c index a22e800..7a8a4e4 100644
a b uint32 last_load_addr = 0; 61 61 int nouartrx = 0; 62 62 host_callback *sim_callback; 63 63 struct memsys *ms = &erc32sys; 64 int cputype = 0; /* 0 = erc32, 3 = leon3 */ 64 int cputype = 0; /* 0 = erc32, 2 = leon2,3 = leon3 */ 65 int sis_gdb_break; 65 66 66 67 #ifdef ERRINJ 67 68 uint32 errcnt = 0; … … exec_cmd(sregs, cmd) 624 625 stat = run_sim(sregs, UINT64_MAX, 0); 625 626 daddr = sregs->pc; 626 627 ms->sim_halt(); 628 } else if (strncmp(cmd1, "wp", clen) == 0) { 629 for (i = 0; i < sregs->wprnum; i++) { 630 printf(" %d : 0x%08x (read)\n", i + 1, sregs->wprs[i]); 631 } 632 for (i = 0; i < sregs->wpwnum; i++) { 633 printf(" %d : 0x%08x (write)\n", i + 1, sregs->wpws[i]); 634 } 635 } else if (strncmp(cmd1, "+wpr", clen) == 0) { 636 if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) { 637 sregs->wprs[sregs->wprnum] = VAL(cmd1) & ~0x3; 638 sregs->wprm[sregs->wprnum] = 3; 639 printf("added read watchpoint %d at 0x%08x\n", 640 sregs->wprnum + 1, sregs->wprs[sregs->wprnum]); 641 sregs->wprnum += 1; 642 } 643 } else if (strncmp(cmd1, "-wpr", clen) == 0) { 644 if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) { 645 i = VAL(cmd1) - 1; 646 if ((i >= 0) && (i < sregs->wprnum)) { 647 printf("deleted read watchpoint %d at 0x%08x\n", i + 1, 648 sregs->wprs[i]); 649 for (; i < sregs->wprnum - 1; i++) { 650 sregs->wprs[i] = sregs->wprs[i + 1]; 651 } 652 sregs->wprnum -= 1; 653 } 654 } 655 } else if (strncmp(cmd1, "+wpw", clen) == 0) { 656 if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) { 657 sregs->wpws[sregs->wpwnum] = VAL(cmd1) & ~0x3; 658 sregs->wpwm[sregs->wpwnum] = 3; 659 printf("added write watchpoint %d at 0x%08x\n", 660 sregs->wpwnum + 1, sregs->wpws[sregs->wpwnum]); 661 sregs->wpwnum += 1; 662 } 663 } else if (strncmp(cmd1, "-wpw", clen) == 0) { 664 if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) { 665 i = VAL(cmd1) - 1; 666 if ((i >= 0) && (i < sregs->wpwnum)) { 667 printf("deleted write watchpoint %d at 0x%08x\n", i + 1, 668 sregs->wpws[i]); 669 for (; i < sregs->wpwnum - 1; i++) { 670 sregs->wpws[i] = sregs->wpws[i + 1]; 671 } 672 sregs->wpwnum -= 1; 673 } 674 } 627 675 } else 628 676 printf("syntax error\n"); 629 677 } … … init_bpt(sregs) 714 762 struct pstate *sregs; 715 763 { 716 764 sregs->bptnum = 0; 765 sregs->wprnum = 0; 766 sregs->wpwnum = 0; 717 767 sregs->histlen = 0; 718 768 sregs->histind = 0; 719 769 sregs->histbuf = NULL; … … check_bpt(sregs) 1023 1073 return (0); 1024 1074 } 1025 1075 1076 int 1077 check_wpr(sregs, address, mask) 1078 struct pstate *sregs; 1079 int32 address; 1080 unsigned char mask; 1081 { 1082 int32 i, msk; 1083 1084 for (i = 0; i < sregs->wprnum; i++) { 1085 msk = ~(mask | sregs->wprm[i]); 1086 if (((address ^ sregs->wprs[i]) & msk) == 0) { 1087 sregs->wpaddress = address; 1088 if (sregs->wphit) return (0); 1089 return (WPT_HIT); 1090 } 1091 } 1092 return (0); 1093 } 1094 1095 int 1096 check_wpw(sregs, address, mask) 1097 struct pstate *sregs; 1098 int32 address; 1099 unsigned char mask; 1100 { 1101 int32 i, msk; 1102 1103 for (i = 0; i < sregs->wpwnum; i++) { 1104 msk = ~(mask | sregs->wpwm[i]); 1105 if (((address ^ sregs->wpws[i]) & msk) == 0) { 1106 sregs->wpaddress = address; 1107 if (sregs->wphit) return (0); 1108 return (WPT_HIT); 1109 } 1110 } 1111 return (0); 1112 } 1113 1026 1114 void 1027 1115 reset_all() 1028 1116 { -
sim/erc32/sis.c
diff --git a/sim/erc32/sis.c b/sim/erc32/sis.c index 99d5286..7c984bc 100644
a b run_sim(sregs, icount, dis) 75 75 sregs->trap = I_ACC_EXC; 76 76 } else { 77 77 if (deb) { 78 if ((sregs->bphit = check_bpt(sregs)) != 0) { 79 ms->restore_stdio(); 80 return (BPT_HIT); 81 } 82 if (sregs->histlen) { 78 if (sregs->histlen) { 83 79 sregs->histbuf[sregs->histind].addr = sregs->pc; 84 80 sregs->histbuf[sregs->histind].time = ebase.simtime; 85 81 sregs->histind++; … … run_sim(sregs, icount, dis) 90 86 printf(" %8" PRIu64 " ", ebase.simtime); 91 87 dis_mem(sregs->pc, 1, &dinfo); 92 88 } 89 if ((sregs->bptnum) && (sregs->bphit = check_bpt(sregs))) 90 icount = 0; 91 else { 92 dispatch_instruction(sregs); 93 icount--; 94 } 95 } else { 96 dispatch_instruction(sregs); 97 icount--; 93 98 } 94 dispatch_instruction(sregs);95 icount--;96 99 } 97 100 } 98 101 if (sregs->trap) { 99 102 irq = 0; 100 sregs->err_mode = execute_trap(sregs); 103 if ((sregs->err_mode = execute_trap(sregs)) == WPT_HIT) { 104 sregs->err_mode = 0; 105 sregs->trap = 0; 106 icount = 0; 107 } 101 108 if (sregs->err_mode) { 102 109 ms->error_mode(sregs->pc); 103 110 icount = 0; … … run_sim(sregs, icount, dis) 118 125 ctrl_c = 0; 119 126 return (CTRL_C); 120 127 } 128 if (sregs->bphit) 129 return (BPT_HIT); 130 if (sregs->wphit) 131 return (WPT_HIT); 121 132 return (TIME_OUT); 122 133 } 123 134 … … main(argc, argv) 283 294 printf(" %8" PRIu64 " ", ebase.simtime); 284 295 dis_mem(sregs.pc, 1, &dinfo); 285 296 break; 297 case WPT_HIT: 298 printf("watchpoint at 0x%08x reached, pc = 0x%08x\n", 299 sregs.wpaddress, sregs.pc); 300 sregs.wphit = 1; 301 break; 286 302 default: 287 303 break; 288 304 } -
sim/erc32/sis.h
diff --git a/sim/erc32/sis.h b/sim/erc32/sis.h index c043504..fda5f01 100644
a b 39 39 /* Maximum # of floating point queue */ 40 40 #define FPUQN 1 41 41 42 /* Maximum # of breakpoints */42 /* Maximum # of breakpoints and watchpoints */ 43 43 #define BPT_MAX 256 44 #define WPR_MAX 256 45 #define WPW_MAX 256 44 46 45 47 struct histype { 46 48 unsigned addr; … … struct pstate { 108 110 uint32 bptnum; 109 111 uint32 bphit; 110 112 uint32 bpts[BPT_MAX]; /* Breakpoints */ 113 uint32 wprnum; 114 uint32 wphit; 115 uint32 wprs[WPR_MAX]; /* Read Watchpoints */ 116 unsigned char wprm[WPR_MAX]; /* Read Watchpoint masks*/ 117 uint32 wpwnum; 118 uint32 wpws[WPW_MAX]; /* Write Watchpoints */ 119 unsigned char wpwm[WPW_MAX]; /* Write Watchpoint masks */ 120 uint32 wpaddress; 111 121 112 122 uint32 ltime; /* Load interlock time */ 113 123 uint32 hold; /* IU hold cycles in current inst */ … … struct memsys { 184 194 }; 185 195 186 196 197 /* return values for run_sim */ 187 198 #define OK 0 188 199 #define TIME_OUT 1 189 200 #define BPT_HIT 2 190 201 #define ERROR 3 191 202 #define CTRL_C 4 203 #define WPT_HIT 5 192 204 205 /* special simulator trap types */ 206 #define ERROR_TRAP 257 207 #define WPT_TRAP 258 208 209 /* cpu type defines */ 193 210 #define CPU_LEON2 2 194 211 #define CPU_LEON3 3 195 212 … … extern void advance_time (struct pstate *sregs); 240 257 extern uint32 now (void); 241 258 extern int wait_for_irq (void); 242 259 extern int check_bpt (struct pstate *sregs); 260 extern int check_wpr(struct pstate *sregs, int32 address, unsigned char mask); 261 extern int check_wpw(struct pstate *sregs, int32 address, unsigned char mask); 262 243 263 extern void reset_all (void); 244 264 extern void sys_reset (void); 245 265 extern void sys_halt (void); … … extern host_callback *sim_callback; 249 269 extern int current_target_byte_order; 250 270 extern int dumbio; 251 271 extern int cputype; 272 extern int sis_gdb_break; 252 273 253 274 /* exec.c */ 254 275 extern int dispatch_instruction (struct pstate *sregs);
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