source: rtems-schedsim/schedsim/rtems/sched_cpu/rtems/score/cpu.h @ c172779

Last change on this file since c172779 was c172779, checked in by Joel Sherrill <joel.sherrill@…>, on May 22, 2014 at 10:55:04 PM

cpu.h: Include sys/cpuset.h so RTEMS tasks.h doesn't have to be modified

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1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  BASED UPON SOURCE IN RTEMS, MODIFIED FOR SIMULATOR
7 *
8 *  This include file contains information pertaining to the XXX
9 *  processor.
10 *
11 *  @note This file is part of a porting template that is intended
12 *  to be used as the starting point when porting RTEMS to a new
13 *  CPU family.  The following needs to be done when using this as
14 *  the starting point for a new port:
15 *
16 *  + Anywhere there is an XXX, it should be replaced
17 *    with information about the CPU family being ported to.
18 *
19 *  + At the end of each comment section, there is a heading which
20 *    says "Port Specific Information:".  When porting to RTEMS,
21 *    add CPU family specific information in this section
22 */
23
24/*
25 *  COPYRIGHT (c) 1989-2013.
26 *  On-Line Applications Research Corporation (OAR).
27 *
28 *  The license and distribution terms for this file may be
29 *  found in the file LICENSE in this distribution or at
30 *  http://www.rtems.com/license/LICENSE.
31 */
32
33#ifndef _RTEMS_SCORE_CPU_H
34#define _RTEMS_SCORE_CPU_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40#include <rtems/score/no_cpu.h>            /* pick up machine definitions */
41#ifndef ASM
42/* only on simulator - included in different ways on real RTEMS */
43#include <sys/cpuset.h>
44#include <rtems/score/types.h>
45#endif
46
47/* conditional compilation parameters */
48
49/**
50 *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
51 *
52 *  If TRUE, then they are inlined.
53 *  If FALSE, then a subroutine call is made.
54 *
55 *  This conditional is an example of the classic trade-off of size
56 *  versus speed.  Inlining the call (TRUE) typically increases the
57 *  size of RTEMS while speeding up the enabling of dispatching.
58 *
59 *  @note In general, the @ref _Thread_Dispatch_disable_level will
60 *  only be 0 or 1 unless you are in an interrupt handler and that
61 *  interrupt handler invokes the executive.]  When not inlined
62 *  something calls @ref _Thread_Enable_dispatch which in turns calls
63 *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
64 *  one subroutine call is avoided entirely.
65 *
66 *  Port Specific Information:
67 *
68 *  XXX document implementation including references if appropriate
69 */
70#define CPU_INLINE_ENABLE_DISPATCH       TRUE
71
72/**
73 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
74 *  be unrolled one time?  In unrolled each iteration of the loop examines
75 *  two "nodes" on the chain being searched.  Otherwise, only one node
76 *  is examined per iteration.
77 *
78 *  If TRUE, then the loops are unrolled.
79 *  If FALSE, then the loops are not unrolled.
80 *
81 *  The primary factor in making this decision is the cost of disabling
82 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
83 *  body of the loop.  On some CPUs, the flash is more expensive than
84 *  one iteration of the loop body.  In this case, it might be desirable
85 *  to unroll the loop.  It is important to note that on some CPUs, this
86 *  code is the longest interrupt disable period in RTEMS.  So it is
87 *  necessary to strike a balance when setting this parameter.
88 *
89 *  Port Specific Information:
90 *
91 *  XXX document implementation including references if appropriate
92 */
93#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
94
95/**
96 *  Does RTEMS manage a dedicated interrupt stack in software?
97 *
98 *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
99 *  If FALSE, nothing is done.
100 *
101 *  If the CPU supports a dedicated interrupt stack in hardware,
102 *  then it is generally the responsibility of the BSP to allocate it
103 *  and set it up.
104 *
105 *  If the CPU does not support a dedicated interrupt stack, then
106 *  the porter has two options: (1) execute interrupts on the
107 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
108 *  interrupt stack.
109 *
110 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
111 *
112 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
113 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
114 *  possible that both are FALSE for a particular CPU.  Although it
115 *  is unclear what that would imply about the interrupt processing
116 *  procedure on that CPU.
117 *
118 *  Port Specific Information:
119 *
120 *  XXX document implementation including references if appropriate
121 */
122#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
123
124/**
125 *  Does the CPU follow the simple vectored interrupt model?
126 *
127 *  If TRUE, then RTEMS allocates the vector table it internally manages.
128 *  If FALSE, then the BSP is assumed to allocate and manage the vector
129 *  table
130 *
131 *  Port Specific Information:
132 *
133 *  XXX document implementation including references if appropriate
134 */
135#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
136
137/**
138 *  Does this CPU have hardware support for a dedicated interrupt stack?
139 *
140 *  If TRUE, then it must be installed during initialization.
141 *  If FALSE, then no installation is performed.
142 *
143 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
144 *
145 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
146 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
147 *  possible that both are FALSE for a particular CPU.  Although it
148 *  is unclear what that would imply about the interrupt processing
149 *  procedure on that CPU.
150 *
151 *  Port Specific Information:
152 *
153 *  XXX document implementation including references if appropriate
154 */
155#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
156
157/**
158 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
159 *
160 *  If TRUE, then the memory is allocated during initialization.
161 *  If FALSE, then the memory is allocated during initialization.
162 *
163 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
164 *
165 *  Port Specific Information:
166 *
167 *  XXX document implementation including references if appropriate
168 */
169#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
170
171/**
172 *  Does the RTEMS invoke the user's ISR with the vector number and
173 *  a pointer to the saved interrupt frame (1) or just the vector
174 *  number (0)?
175 *
176 *  Port Specific Information:
177 *
178 *  XXX document implementation including references if appropriate
179 */
180#define CPU_ISR_PASSES_FRAME_POINTER 0
181
182/**
183 *  @def CPU_HARDWARE_FP
184 *
185 *  Does the CPU have hardware floating point?
186 *
187 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
188 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
189 *
190 *  If there is a FP coprocessor such as the i387 or mc68881, then
191 *  the answer is TRUE.
192 *
193 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
194 *  It indicates whether or not this CPU model has FP support.  For
195 *  example, it would be possible to have an i386_nofp CPU model
196 *  which set this to false to indicate that you have an i386 without
197 *  an i387 and wish to leave floating point support out of RTEMS.
198 */
199
200/**
201 *  @def CPU_SOFTWARE_FP
202 *
203 *  Does the CPU have no hardware floating point and GCC provides a
204 *  software floating point implementation which must be context
205 *  switched?
206 *
207 *  This feature conditional is used to indicate whether or not there
208 *  is software implemented floating point that must be context
209 *  switched.  The determination of whether or not this applies
210 *  is very tool specific and the state saved/restored is also
211 *  compiler specific.
212 *
213 *  Port Specific Information:
214 *
215 *  XXX document implementation including references if appropriate
216 */
217#if ( NO_CPU_HAS_FPU == 1 )
218#define CPU_HARDWARE_FP     TRUE
219#else
220#define CPU_HARDWARE_FP     FALSE
221#endif
222#define CPU_SOFTWARE_FP     FALSE
223
224/**
225 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
226 *
227 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
228 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
229 *
230 *  So far, the only CPUs in which this option has been used are the
231 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
232 *  gcc both implicitly used the floating point registers to perform
233 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
234 *  seen to allocate floating point local variables and touch the FPU
235 *  even when the flow through a subroutine (like vfprintf()) might
236 *  not use floating point formats.
237 *
238 *  If a function which you would not think utilize the FP unit DOES,
239 *  then one can not easily predict which tasks will use the FP hardware.
240 *  In this case, this option should be TRUE.
241 *
242 *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
243 *
244 *  Port Specific Information:
245 *
246 *  XXX document implementation including references if appropriate
247 */
248#define CPU_ALL_TASKS_ARE_FP     TRUE
249
250/**
251 *  Should the IDLE task have a floating point context?
252 *
253 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
254 *  and it has a floating point context which is switched in and out.
255 *  If FALSE, then the IDLE task does not have a floating point context.
256 *
257 *  Setting this to TRUE negatively impacts the time required to preempt
258 *  the IDLE task from an interrupt because the floating point context
259 *  must be saved as part of the preemption.
260 *
261 *  Port Specific Information:
262 *
263 *  XXX document implementation including references if appropriate
264 */
265#define CPU_IDLE_TASK_IS_FP      FALSE
266
267/**
268 *  Should the saving of the floating point registers be deferred
269 *  until a context switch is made to another different floating point
270 *  task?
271 *
272 *  If TRUE, then the floating point context will not be stored until
273 *  necessary.  It will remain in the floating point registers and not
274 *  disturned until another floating point task is switched to.
275 *
276 *  If FALSE, then the floating point context is saved when a floating
277 *  point task is switched out and restored when the next floating point
278 *  task is restored.  The state of the floating point registers between
279 *  those two operations is not specified.
280 *
281 *  If the floating point context does NOT have to be saved as part of
282 *  interrupt dispatching, then it should be safe to set this to TRUE.
283 *
284 *  Setting this flag to TRUE results in using a different algorithm
285 *  for deciding when to save and restore the floating point context.
286 *  The deferred FP switch algorithm minimizes the number of times
287 *  the FP context is saved and restored.  The FP context is not saved
288 *  until a context switch is made to another, different FP task.
289 *  Thus in a system with only one FP task, the FP context will never
290 *  be saved or restored.
291 *
292 *  Port Specific Information:
293 *
294 *  XXX document implementation including references if appropriate
295 */
296#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
297
298/**
299 *  Does this port provide a CPU dependent IDLE task implementation?
300 *
301 *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
302 *  must be provided and is the default IDLE thread body instead of
303 *  @ref _CPU_Thread_Idle_body.
304 *
305 *  If FALSE, then use the generic IDLE thread body if the BSP does
306 *  not provide one.
307 *
308 *  This is intended to allow for supporting processors which have
309 *  a low power or idle mode.  When the IDLE thread is executed, then
310 *  the CPU can be powered down.
311 *
312 *  The order of precedence for selecting the IDLE thread body is:
313 *
314 *    -#  BSP provided
315 *    -#  CPU dependent (if provided)
316 *    -#  generic (if no BSP and no CPU dependent)
317 *
318 *  Port Specific Information:
319 *
320 *  XXX document implementation including references if appropriate
321 */
322#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
323
324/**
325 *  Does the stack grow up (toward higher addresses) or down
326 *  (toward lower addresses)?
327 *
328 *  If TRUE, then the grows upward.
329 *  If FALSE, then the grows toward smaller addresses.
330 *
331 *  Port Specific Information:
332 *
333 *  XXX document implementation including references if appropriate
334 */
335#define CPU_STACK_GROWS_UP               TRUE
336
337/**
338 *  The following is the variable attribute used to force alignment
339 *  of critical RTEMS structures.  On some processors it may make
340 *  sense to have these aligned on tighter boundaries than
341 *  the minimum requirements of the compiler in order to have as
342 *  much of the critical data area as possible in a cache line.
343 *
344 *  The placement of this macro in the declaration of the variables
345 *  is based on the syntactically requirements of the GNU C
346 *  "__attribute__" extension.  For example with GNU C, use
347 *  the following to force a structures to a 32 byte boundary.
348 *
349 *      __attribute__ ((aligned (32)))
350 *
351 *  @note Currently only the Priority Bit Map table uses this feature.
352 *        To benefit from using this, the data must be heavily
353 *        used so it will stay in the cache and used frequently enough
354 *        in the executive to justify turning this on.
355 *
356 *  Port Specific Information:
357 *
358 *  XXX document implementation including references if appropriate
359 */
360#define CPU_STRUCTURE_ALIGNMENT
361
362#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
363
364/**
365 *  @defgroup CPUEndian Processor Dependent Endianness Support
366 *
367 *  This group assists in issues related to processor endianness.
368 */
369
370/**
371 *  @ingroup CPUEndian
372 *  Define what is required to specify how the network to host conversion
373 *  routines are handled.
374 *
375 *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
376 *  same values.
377 *
378 *  @see CPU_LITTLE_ENDIAN
379 *
380 *  Port Specific Information:
381 *
382 *  XXX document implementation including references if appropriate
383 */
384#define CPU_BIG_ENDIAN                           TRUE
385
386/**
387 *  @ingroup CPUEndian
388 *  Define what is required to specify how the network to host conversion
389 *  routines are handled.
390 *
391 *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
392 *  same values.
393 *
394 *  @see CPU_BIG_ENDIAN
395 *
396 *  Port Specific Information:
397 *
398 *  XXX document implementation including references if appropriate
399 */
400#define CPU_LITTLE_ENDIAN                        FALSE
401
402/**
403 *  @ingroup CPUInterrupt
404 *  The following defines the number of bits actually used in the
405 *  interrupt field of the task mode.  How those bits map to the
406 *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
407 *
408 *  Port Specific Information:
409 *
410 *  XXX document implementation including references if appropriate
411 */
412#define CPU_MODES_INTERRUPT_MASK   0x00000001
413
414/*
415 *  Processor defined structures required for cpukit/score.
416 *
417 *  Port Specific Information:
418 *
419 *  XXX document implementation including references if appropriate
420 */
421
422/* may need to put some structures here.  */
423
424/**
425 * @defgroup CPUContext Processor Dependent Context Management
426 *
427 *  From the highest level viewpoint, there are 2 types of context to save.
428 *
429 *     -# Interrupt registers to save
430 *     -# Task level registers to save
431 *
432 *  Since RTEMS handles integer and floating point contexts separately, this
433 *  means we have the following 3 context items:
434 *
435 *     -# task level context stuff::  Context_Control
436 *     -# floating point task stuff:: Context_Control_fp
437 *     -# special interrupt level context :: CPU_Interrupt_frame
438 *
439 *  On some processors, it is cost-effective to save only the callee
440 *  preserved registers during a task context switch.  This means
441 *  that the ISR code needs to save those registers which do not
442 *  persist across function calls.  It is not mandatory to make this
443 *  distinctions between the caller/callee saves registers for the
444 *  purpose of minimizing context saved during task switch and on interrupts.
445 *  If the cost of saving extra registers is minimal, simplicity is the
446 *  choice.  Save the same context on interrupt entry as for tasks in
447 *  this case.
448 *
449 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
450 *  care should be used in designing the context area.
451 *
452 *  On some CPUs with hardware floating point support, the Context_Control_fp
453 *  structure will not be used or it simply consist of an array of a
454 *  fixed number of bytes.   This is done when the floating point context
455 *  is dumped by a "FP save context" type instruction and the format
456 *  is not really defined by the CPU.  In this case, there is no need
457 *  to figure out the exact format -- only the size.  Of course, although
458 *  this is enough information for RTEMS, it is probably not enough for
459 *  a debugger such as gdb.  But that is another problem.
460 *
461 *  Port Specific Information:
462 *
463 *  XXX document implementation including references if appropriate
464 */
465
466typedef struct {
467  /* There is no CPU specific per-CPU state */
468} CPU_Per_CPU_control;
469
470/**
471 *  @ingroup CPUContext Management
472 *  This defines the minimal set of integer and processor state registers
473 *  that must be saved during a voluntary context switch from one thread
474 *  to another.
475 */
476typedef struct {
477    /**
478     * This field is a hint that a port will have a number of integer
479     * registers that need to be saved at a context switch.
480     */
481    uint32_t   some_integer_register;
482    /**
483     * This field is a hint that a port will have a number of system
484     * registers that need to be saved at a context switch.
485     */
486    uint32_t   some_system_register;
487
488    /**
489     * This field is a hint that a port will have a register that
490     * is the stack pointer.
491     */
492    uint32_t   stack_pointer;
493
494#ifdef RTEMS_SMP
495    /**
496     * @brief On SMP configurations the thread context must contain a boolean
497     * indicator if this context is executing on a processor.
498     *
499     * This field must be updated during a context switch.  The context switch
500     * to the heir must wait until the heir context indicates that it is no
501     * longer executing on a processor.
502     */
503    volatile bool is_executing;
504#endif
505} Context_Control;
506
507/**
508 *  @ingroup CPUContext Management
509 *
510 *  This macro returns the stack pointer associated with @a _context.
511 *
512 *  @param[in] _context is the thread context area to access
513 *
514 *  @return This method returns the stack pointer.
515 */
516#define _CPU_Context_Get_SP( _context ) \
517  (_context)->stack_pointer
518
519#ifdef RTEMS_SMP
520  static inline bool _CPU_Context_Get_is_executing(
521    const Context_Control *context
522  )
523  {
524    return context->is_executing;
525  }
526
527  static inline void _CPU_Context_Set_is_executing(
528    Context_Control *context,
529    bool is_executing
530  )
531  {
532    context->is_executing = is_executing;
533  }
534#endif
535
536/**
537 *  @ingroup CPUContext Management
538 *  This defines the complete set of floating point registers that must
539 *  be saved during any context switch from one thread to another.
540 */
541typedef struct {
542    /** FPU registers are listed here */
543    double      some_float_register;
544} Context_Control_fp;
545
546/**
547 *  @ingroup CPUContext Management
548 *  This defines the set of integer and processor state registers that must
549 *  be saved during an interrupt.  This set does not include any which are
550 *  in @ref Context_Control.
551 */
552typedef struct {
553    /** This field is a hint that a port will have a number of integer
554     *  registers that need to be saved when an interrupt occurs or
555     *  when a context switch occurs at the end of an ISR.
556     */
557    uint32_t   special_interrupt_register;
558} CPU_Interrupt_frame;
559
560/**
561 *  This variable is optional.  It is used on CPUs on which it is difficult
562 *  to generate an "uninitialized" FP context.  It is filled in by
563 *  @ref _CPU_Initialize and copied into the task's FP context area during
564 *  @ref _CPU_Context_Initialize.
565 *
566 *  Port Specific Information:
567 *
568 *  XXX document implementation including references if appropriate
569 */
570SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
571
572/**
573 *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
574 *
575 *  On some CPUs, RTEMS supports a software managed interrupt stack.
576 *  This stack is allocated by the Interrupt Manager and the switch
577 *  is performed in @ref _ISR_Handler.  These variables contain pointers
578 *  to the lowest and highest addresses in the chunk of memory allocated
579 *  for the interrupt stack.  Since it is unknown whether the stack
580 *  grows up or down (in general), this give the CPU dependent
581 *  code the option of picking the version it wants to use.
582 *
583 *  @note These two variables are required if the macro
584 *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
585 *
586 *  Port Specific Information:
587 *
588 *  XXX document implementation including references if appropriate
589 */
590
591/**
592 *  @ingroup CPUInterrupt
593 *  This variable points to the lowest physical address of the interrupt
594 *  stack.
595 */
596SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
597
598/**
599 *  @ingroup CPUInterrupt
600 *  This variable points to the lowest physical address of the interrupt
601 *  stack.
602 */
603SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
604
605/*
606 *  Nothing prevents the porter from declaring more CPU specific variables.
607 *
608 *  Port Specific Information:
609 *
610 *  XXX document implementation including references if appropriate
611 */
612
613/* XXX: if needed, put more variables here */
614
615/**
616 *  @ingroup CPUContext
617 *  The size of the floating point context area.  On some CPUs this
618 *  will not be a "sizeof" because the format of the floating point
619 *  area is not defined -- only the size is.  This is usually on
620 *  CPUs with a "floating point save context" instruction.
621 *
622 *  Port Specific Information:
623 *
624 *  XXX document implementation including references if appropriate
625 */
626#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
627
628/**
629 *  Amount of extra stack (above minimum stack size) required by
630 *  MPCI receive server thread.  Remember that in a multiprocessor
631 *  system this thread must exist and be able to process all directives.
632 *
633 *  Port Specific Information:
634 *
635 *  XXX document implementation including references if appropriate
636 */
637#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
638
639/**
640 *  @ingroup CPUInterrupt
641 *  This defines the number of entries in the @ref _ISR_Vector_table managed
642 *  by RTEMS.
643 *
644 *  Port Specific Information:
645 *
646 *  XXX document implementation including references if appropriate
647 */
648#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
649
650/**
651 *  @ingroup CPUInterrupt
652 *  This defines the highest interrupt vector number for this port.
653 */
654#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
655
656/**
657 *  @ingroup CPUInterrupt
658 *  This is defined if the port has a special way to report the ISR nesting
659 *  level.  Most ports maintain the variable @a _ISR_Nest_level.
660 */
661#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
662
663/**
664 *  @ingroup CPUContext
665 *  Should be large enough to run all RTEMS tests.  This ensures
666 *  that a "reasonable" small application should not have any problems.
667 *
668 *  Port Specific Information:
669 *
670 *  XXX document implementation including references if appropriate
671 */
672#define CPU_STACK_MINIMUM_SIZE          (1024*4)
673
674/**
675 *  CPU's worst alignment requirement for data types on a byte boundary.  This
676 *  alignment does not take into account the requirements for the stack.
677 *
678 *  Port Specific Information:
679 *
680 *  XXX document implementation including references if appropriate
681 */
682#define CPU_ALIGNMENT              8
683
684/**
685 *  This number corresponds to the byte alignment requirement for the
686 *  heap handler.  This alignment requirement may be stricter than that
687 *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
688 *  common for the heap to follow the same alignment requirement as
689 *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
690 *  the heap, then this should be set to @ref CPU_ALIGNMENT.
691 *
692 *  @note  This does not have to be a power of 2 although it should be
693 *         a multiple of 2 greater than or equal to 2.  The requirement
694 *         to be a multiple of 2 is because the heap uses the least
695 *         significant field of the front and back flags to indicate
696 *         that a block is in use or free.  So you do not want any odd
697 *         length blocks really putting length data in that bit.
698 *
699 *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
700 *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
701 *         elements allocated from the heap meet all restrictions.
702 *
703 *  Port Specific Information:
704 *
705 *  XXX document implementation including references if appropriate
706 */
707#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
708
709/**
710 *  This number corresponds to the byte alignment requirement for memory
711 *  buffers allocated by the partition manager.  This alignment requirement
712 *  may be stricter than that for the data types alignment specified by
713 *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
714 *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
715 *  strict enough for the partition, then this should be set to
716 *  @ref CPU_ALIGNMENT.
717 *
718 *  @note  This does not have to be a power of 2.  It does have to
719 *         be greater or equal to than @ref CPU_ALIGNMENT.
720 *
721 *  Port Specific Information:
722 *
723 *  XXX document implementation including references if appropriate
724 */
725#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
726
727/**
728 *  This number corresponds to the byte alignment requirement for the
729 *  stack.  This alignment requirement may be stricter than that for the
730 *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
731 *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
732 *  set to 0.
733 *
734 *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
735 *
736 *  Port Specific Information:
737 *
738 *  XXX document implementation including references if appropriate
739 */
740#define CPU_STACK_ALIGNMENT        0
741
742/*
743 *  ISR handler macros
744 */
745
746/**
747 *  @ingroup CPUInterrupt
748 *  Support routine to initialize the RTEMS vector table after it is allocated.
749 *
750 *  Port Specific Information:
751 *
752 *  XXX document implementation including references if appropriate
753 */
754#define _CPU_Initialize_vectors()
755
756/**
757 *  XXX fake cpu isr level variable
758 */
759extern int _CPU_ISR_level_on_sched_cpu;
760
761/**
762 *  @ingroup CPUInterrupt
763 *  Disable all interrupts for an RTEMS critical section.  The previous
764 *  level is returned in @a _isr_cookie.
765 *
766 *  @param[out] _isr_cookie will contain the previous level cookie
767 *
768 *  Port Specific Information:
769 *
770 *  XXX document implementation including references if appropriate
771 */
772#define _CPU_ISR_Disable( _isr_cookie ) \
773  { \
774    (_isr_cookie) = _CPU_ISR_level_on_sched_cpu; \
775    _CPU_ISR_level_on_sched_cpu = 1; \
776  }
777
778/**
779 *  @ingroup CPUInterrupt
780 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
781 *  This indicates the end of an RTEMS critical section.  The parameter
782 *  @a _isr_cookie is not modified.
783 *
784 *  @param[in] _isr_cookie contain the previous level cookie
785 *
786 *  Port Specific Information:
787 *
788 *  XXX document implementation including references if appropriate
789 */
790#define _CPU_ISR_Enable( _isr_cookie )  \
791  { \
792    _CPU_ISR_level_on_sched_cpu = (_isr_cookie); \
793  }
794
795/**
796 *  @ingroup CPUInterrupt
797 *  This temporarily restores the interrupt to @a _isr_cookie before immediately
798 *  disabling them again.  This is used to divide long RTEMS critical
799 *  sections into two or more parts.  The parameter @a _isr_cookie is not
800 *  modified.
801 *
802 *  @param[in] _isr_cookie contain the previous level cookie
803 *
804 *  Port Specific Information:
805 *
806 *  XXX document implementation including references if appropriate
807 */
808#define _CPU_ISR_Flash( _isr_cookie ) \
809  { \
810  }
811
812/**
813 *  @ingroup CPUInterrupt
814 *
815 *  This routine and @ref _CPU_ISR_Get_level
816 *  Map the interrupt level in task mode onto the hardware that the CPU
817 *  actually provides.  Currently, interrupt levels which do not
818 *  map onto the CPU in a generic fashion are undefined.  Someday,
819 *  it would be nice if these were "mapped" by the application
820 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
821 *  8 - 255 would be available for bsp/application specific meaning.
822 *  This could be used to manage a programmable interrupt controller
823 *  via the rtems_task_mode directive.
824 *
825 *  Port Specific Information:
826 *
827 *  XXX document implementation including references if appropriate
828 */
829#define _CPU_ISR_Set_level( new_level ) \
830  { \
831    _CPU_ISR_level_on_sched_cpu = (new_level); \
832  }
833
834/**
835 *  @ingroup CPUInterrupt
836 *  Return the current interrupt disable level for this task in
837 *  the format used by the interrupt level portion of the task mode.
838 *
839 *  @note This routine usually must be implemented as a subroutine.
840 *
841 *  Port Specific Information:
842 *
843 *  XXX document implementation including references if appropriate
844 */
845#define _CPU_ISR_Get_level() (uint32_t) _CPU_ISR_level_on_sched_cpu
846
847/* end of ISR handler macros */
848
849/* Context handler macros */
850
851/**
852 *  @ingroup CPUContext
853 *  Initialize the context to a state suitable for starting a
854 *  task after a context restore operation.  Generally, this
855 *  involves:
856 *
857 *     - setting a starting address
858 *     - preparing the stack
859 *     - preparing the stack and frame pointers
860 *     - setting the proper interrupt level in the context
861 *     - initializing the floating point context
862 *
863 *  This routine generally does not set any unnecessary register
864 *  in the context.  The state of the "general data" registers is
865 *  undefined at task start time.
866 *
867 *  @param[in] _the_context is the context structure to be initialized
868 *  @param[in] _stack_base is the lowest physical address of this task's stack
869 *  @param[in] _size is the size of this task's stack
870 *  @param[in] _isr is the interrupt disable level
871 *  @param[in] _entry_point is the thread's entry point.  This is
872 *         always @a _Thread_Handler
873 *  @param[in] _is_fp is TRUE if the thread is to be a floating
874 *        point thread.  This is typically only used on CPUs where the
875 *        FPU may be easily disabled by software such as on the SPARC
876 *        where the PSR contains an enable FPU bit.
877 *
878 *  Port Specific Information:
879 *
880 *  XXX document implementation including references if appropriate
881 */
882#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
883                                 _isr, _entry_point, _is_fp, tls_area ) \
884  { \
885  }
886
887/**
888 *  This routine is responsible for somehow restarting the currently
889 *  executing task.  If you are lucky, then all that is necessary
890 *  is restoring the context.  Otherwise, there will need to be
891 *  a special assembly routine which does something special in this
892 *  case.  For many ports, simply adding a label to the restore path
893 *  of @ref _CPU_Context_switch will work.  On other ports, it may be
894 *  possibly to load a few arguments and jump to the restore path. It will
895 *  not work if restarting self conflicts with the stack frame
896 *  assumptions of restoring a context.
897 *
898 *  Port Specific Information:
899 *
900 *  XXX document implementation including references if appropriate
901 */
902#define _CPU_Context_Restart_self( _the_context ) \
903   _CPU_Context_restore( (_the_context) );
904
905/**
906 *  @ingroup CPUContext
907 *  The purpose of this macro is to allow the initial pointer into
908 *  a floating point context area (used to save the floating point
909 *  context) to be at an arbitrary place in the floating point
910 *  context area.
911 *
912 *  This is necessary because some FP units are designed to have
913 *  their context saved as a stack which grows into lower addresses.
914 *  Other FP units can be saved by simply moving registers into offsets
915 *  from the base of the context area.  Finally some FP units provide
916 *  a "dump context" instruction which could fill in from high to low
917 *  or low to high based on the whim of the CPU designers.
918 *
919 *  @param[in] _base is the lowest physical address of the floating point
920 *         context area
921 *  @param[in] _offset is the offset into the floating point area
922 *
923 *  Port Specific Information:
924 *
925 *  XXX document implementation including references if appropriate
926 */
927#define _CPU_Context_Fp_start( _base, _offset ) \
928   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
929
930/**
931 *  This routine initializes the FP context area passed to it to.
932 *  There are a few standard ways in which to initialize the
933 *  floating point context.  The code included for this macro assumes
934 *  that this is a CPU in which a "initial" FP context was saved into
935 *  @a _CPU_Null_fp_context and it simply copies it to the destination
936 *  context passed to it.
937 *
938 *  Other floating point context save/restore models include:
939 *    -# not doing anything, and
940 *    -# putting a "null FP status word" in the correct place in the FP context.
941 *
942 *  @param[in] _destination is the floating point context area
943 *
944 *  Port Specific Information:
945 *
946 *  XXX document implementation including references if appropriate
947 */
948#define _CPU_Context_Initialize_fp( _destination ) \
949  { \
950   *(*(_destination)) = _CPU_Null_fp_context; \
951  }
952
953/* end of Context handler macros */
954
955/* Fatal Error manager macros */
956
957/**
958 *  This routine copies _error into a known place -- typically a stack
959 *  location or a register, optionally disables interrupts, and
960 *  halts/stops the CPU.
961 *
962 *  Port Specific Information:
963 *
964 *  XXX document implementation including references if appropriate
965 */
966#define _CPU_Fatal_halt( _error ) \
967  { \
968  }
969
970/* end of Fatal Error manager macros */
971
972/* Bitfield handler macros */
973
974/**
975 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
976 *
977 *  This set of routines are used to implement fast searches for
978 *  the most important ready task.
979 */
980
981/**
982 *  @ingroup CPUBitfield
983 *  This definition is set to TRUE if the port uses the generic bitfield
984 *  manipulation implementation.
985 */
986#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
987
988/**
989 *  @ingroup CPUBitfield
990 *  This definition is set to TRUE if the port uses the data tables provided
991 *  by the generic bitfield manipulation implementation.
992 *  This can occur when actually using the generic bitfield manipulation
993 *  implementation or when implementing the same algorithm in assembly
994 *  language for improved performance.  It is unlikely that a port will use
995 *  the data if it has a bitfield scan instruction.
996 */
997#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
998
999/**
1000 *  @ingroup CPUBitfield
1001 *  This routine sets @a _output to the bit number of the first bit
1002 *  set in @a _value.  @a _value is of CPU dependent type
1003 *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
1004 *  wide although only the 16 least significant bits will be used.
1005 *
1006 *  There are a number of variables in using a "find first bit" type
1007 *  instruction.
1008 *
1009 *    -# What happens when run on a value of zero?
1010 *    -# Bits may be numbered from MSB to LSB or vice-versa.
1011 *    -# The numbering may be zero or one based.
1012 *    -# The "find first bit" instruction may search from MSB or LSB.
1013 *
1014 *  RTEMS guarantees that (1) will never happen so it is not a concern.
1015 *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
1016 *  @ref _CPU_Priority_bits_index.  These three form a set of routines
1017 *  which must logically operate together.  Bits in the _value are
1018 *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
1019 *  The basic major and minor values calculated by @ref _Priority_Major
1020 *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
1021 *  to properly range between the values returned by the "find first bit"
1022 *  instruction.  This makes it possible for @ref _Priority_Get_highest to
1023 *  calculate the major and directly index into the minor table.
1024 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
1025 *  is the first bit found.
1026 *
1027 *  This entire "find first bit" and mapping process depends heavily
1028 *  on the manner in which a priority is broken into a major and minor
1029 *  components with the major being the 4 MSB of a priority and minor
1030 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
1031 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
1032 *  to the lowest priority.
1033 *
1034 *  If your CPU does not have a "find first bit" instruction, then
1035 *  there are ways to make do without it.  Here are a handful of ways
1036 *  to implement this in software:
1037 *
1038@verbatim
1039      - a series of 16 bit test instructions
1040      - a "binary search using if's"
1041      - _number = 0
1042        if _value > 0x00ff
1043          _value >>=8
1044          _number = 8;
1045
1046        if _value > 0x0000f
1047          _value >=8
1048          _number += 4
1049
1050        _number += bit_set_table[ _value ]
1051@endverbatim
1052
1053 *    where bit_set_table[ 16 ] has values which indicate the first
1054 *      bit set
1055 *
1056 *  @param[in] _value is the value to be scanned
1057 *  @param[in] _output is the first bit set
1058 *
1059 *  Port Specific Information:
1060 *
1061 *  XXX document implementation including references if appropriate
1062 */
1063
1064#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1065#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1066  { \
1067    (_output) = 0;   /* do something to prevent warnings */ \
1068  }
1069#endif
1070
1071/* end of Bitfield handler macros */
1072
1073/**
1074 *  This routine builds the mask which corresponds to the bit fields
1075 *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1076 *  for that routine.
1077 *
1078 *  Port Specific Information:
1079 *
1080 *  XXX document implementation including references if appropriate
1081 */
1082#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1083
1084#define _CPU_Priority_Mask( _bit_number ) \
1085  ( 1 << (_bit_number) )
1086
1087#endif
1088
1089/**
1090 *  @ingroup CPUBitfield
1091 *  This routine translates the bit numbers returned by
1092 *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1093 *  a major or minor component of a priority.  See the discussion
1094 *  for that routine.
1095 *
1096 *  @param[in] _priority is the major or minor number to translate
1097 *
1098 *  Port Specific Information:
1099 *
1100 *  XXX document implementation including references if appropriate
1101 */
1102#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1103
1104#define _CPU_Priority_bits_index( _priority ) \
1105  (_priority)
1106
1107#endif
1108
1109/* end of Priority handler macros */
1110
1111/* functions */
1112
1113/**
1114 *  This routine performs CPU dependent initialization.
1115 *
1116 *  Port Specific Information:
1117 *
1118 *  XXX document implementation including references if appropriate
1119 */
1120void _CPU_Initialize(void);
1121
1122/**
1123 *  @ingroup CPUInterrupt
1124 *  This routine installs a "raw" interrupt handler directly into the
1125 *  processor's vector table.
1126 *
1127 *  @param[in] vector is the vector number
1128 *  @param[in] new_handler is the raw ISR handler to install
1129 *  @param[in] old_handler is the previously installed ISR Handler
1130 *
1131 *  Port Specific Information:
1132 *
1133 *  XXX document implementation including references if appropriate
1134 */
1135void _CPU_ISR_install_raw_handler(
1136  uint32_t    vector,
1137  proc_ptr    new_handler,
1138  proc_ptr   *old_handler
1139);
1140
1141/**
1142 *  @ingroup CPUInterrupt
1143 *  This routine installs an interrupt vector.
1144 *
1145 *  @param[in] vector is the vector number
1146 *  @param[in] new_handler is the RTEMS ISR handler to install
1147 *  @param[in] old_handler is the previously installed ISR Handler
1148 *
1149 *  Port Specific Information:
1150 *
1151 *  XXX document implementation including references if appropriate
1152 */
1153void _CPU_ISR_install_vector(
1154  uint32_t    vector,
1155  proc_ptr    new_handler,
1156  proc_ptr   *old_handler
1157);
1158
1159/**
1160 *  @ingroup CPUInterrupt
1161 *  This routine installs the hardware interrupt stack pointer.
1162 *
1163 *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1164 *         is TRUE.
1165 *
1166 *  Port Specific Information:
1167 *
1168 *  XXX document implementation including references if appropriate
1169 */
1170void _CPU_Install_interrupt_stack( void );
1171
1172typedef uint32_t CPU_Counter_ticks;
1173
1174CPU_Counter_ticks _CPU_Counter_read( void );
1175
1176CPU_Counter_ticks _CPU_Counter_difference(
1177  CPU_Counter_ticks second,
1178  CPU_Counter_ticks first
1179);
1180
1181/**
1182 *  This routine is the CPU dependent IDLE thread body.
1183 *
1184 *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1185 *         is TRUE.
1186 *
1187 *  Port Specific Information:
1188 *
1189 *  XXX document implementation including references if appropriate
1190 */
1191void *_CPU_Thread_Idle_body( uintptr_t ignored );
1192
1193/**
1194 *  @ingroup CPUContext
1195 *  This routine switches from the run context to the heir context.
1196 *
1197 *  @param[in] run points to the context of the currently executing task
1198 *  @param[in] heir points to the context of the heir task
1199 *
1200 *  Port Specific Information:
1201 *
1202 *  XXX document implementation including references if appropriate
1203 */
1204void _CPU_Context_switch(
1205  Context_Control  *run,
1206  Context_Control  *heir
1207);
1208
1209/**
1210 *  @ingroup CPUContext
1211 *  This routine is generally used only to restart self in an
1212 *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1213 *
1214 *  @param[in] new_context points to the context to be restored.
1215 *
1216 *  @note May be unnecessary to reload some registers.
1217 *
1218 *  Port Specific Information:
1219 *
1220 *  XXX document implementation including references if appropriate
1221 */
1222void _CPU_Context_restore(
1223  Context_Control *new_context
1224);
1225
1226/**
1227 *  @ingroup CPUContext
1228 *  This routine saves the floating point context passed to it.
1229 *
1230 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1231 *  point context area
1232 *
1233 *  @return on output @a *fp_context_ptr will contain the address that
1234 *  should be used with @ref _CPU_Context_restore_fp to restore this context.
1235 *
1236 *  Port Specific Information:
1237 *
1238 *  XXX document implementation including references if appropriate
1239 */
1240void _CPU_Context_save_fp(
1241  Context_Control_fp **fp_context_ptr
1242);
1243
1244/**
1245 *  @ingroup CPUContext
1246 *  This routine restores the floating point context passed to it.
1247 *
1248 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1249 *  point context area to restore
1250 *
1251 *  @return on output @a *fp_context_ptr will contain the address that
1252 *  should be used with @ref _CPU_Context_save_fp to save this context.
1253 *
1254 *  Port Specific Information:
1255 *
1256 *  XXX document implementation including references if appropriate
1257 */
1258void _CPU_Context_restore_fp(
1259  Context_Control_fp **fp_context_ptr
1260);
1261
1262#ifdef RTEMS_SMP
1263  #define _CPU_Context_switch_to_first_task_smp(_context )
1264
1265  uint32_t _CPU_SMP_Get_current_processor( void );
1266  uint32_t _CPU_SMP_Initialize( void );
1267  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1268  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1269  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1270  void _CPU_SMP_Processor_event_broadcast( void );
1271  void _CPU_SMP_Processor_event_receive( void );
1272#endif
1273typedef struct {
1274  uint32_t trap;
1275  CPU_Interrupt_frame *isf;
1276} CPU_Exception_frame;
1277
1278static inline void _CPU_Exception_frame_print(
1279  const CPU_Exception_frame *frame
1280)
1281{
1282  /* printk( "Printing exception frame\n" ); */
1283}
1284/**
1285 *  @ingroup CPUEndian
1286 *  The following routine swaps the endian format of an unsigned int.
1287 *  It must be static because it is referenced indirectly.
1288 *
1289 *  This version will work on any processor, but if there is a better
1290 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1291 *
1292 *     swap least significant two bytes with 16-bit rotate
1293 *     swap upper and lower 16-bits
1294 *     swap most significant two bytes with 16-bit rotate
1295 *
1296 *  Some CPUs have special instructions which swap a 32-bit quantity in
1297 *  a single instruction (e.g. i486).  It is probably best to avoid
1298 *  an "endian swapping control bit" in the CPU.  One good reason is
1299 *  that interrupts would probably have to be disabled to ensure that
1300 *  an interrupt does not try to access the same "chunk" with the wrong
1301 *  endian.  Another good reason is that on some CPUs, the endian bit
1302 *  endianness for ALL fetches -- both code and data -- so the code
1303 *  will be fetched incorrectly.
1304 *
1305 *  @param[in] value is the value to be swapped
1306 *  @return the value after being endian swapped
1307 *
1308 *  Port Specific Information:
1309 *
1310 *  XXX document implementation including references if appropriate
1311 */
1312static inline uint32_t CPU_swap_u32(
1313  uint32_t value
1314)
1315{
1316  uint32_t byte1, byte2, byte3, byte4, swapped;
1317
1318  byte4 = (value >> 24) & 0xff;
1319  byte3 = (value >> 16) & 0xff;
1320  byte2 = (value >> 8)  & 0xff;
1321  byte1 =  value        & 0xff;
1322
1323  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1324  return swapped;
1325}
1326
1327/**
1328 *  @ingroup CPUEndian
1329 *  This routine swaps a 16 bir quantity.
1330 *
1331 *  @param[in] value is the value to be swapped
1332 *  @return the value after being endian swapped
1333 */
1334#define CPU_swap_u16( value ) \
1335  (((value&0xff) << 8) | ((value >> 8)&0xff))
1336
1337/*
1338 *  SMP Support
1339 */
1340void __SMP_cpu_swap(
1341  uint32_t *a,
1342  uint32_t *value,
1343  uint32_t *prev
1344);
1345#define SMP_CPU_SWAP( _address, _value, _previous ) \
1346  do { \
1347    volatile unsigned int *_a = (volatile unsigned int *)_address; \
1348    _previous = *(_a); \
1349    *(_a) = _value; \
1350  } while (0)
1351
1352#ifdef __cplusplus
1353}
1354#endif
1355
1356#endif
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