source: rtems-schedsim/schedsim/rtems/sched_cpu/rtems/score/cpu.h @ 2d51251

Last change on this file since 2d51251 was 2d51251, checked in by Jennifer Averett <jennifer.averett@…>, on May 9, 2014 at 1:35:58 PM

schedsim: Add smp support.

  • Property mode set to 100644
File size: 42.7 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  BASED UPON SOURCE IN RTEMS, MODIFIED FOR SIMULATOR
7 *
8 *  This include file contains information pertaining to the XXX
9 *  processor.
10 *
11 *  @note This file is part of a porting template that is intended
12 *  to be used as the starting point when porting RTEMS to a new
13 *  CPU family.  The following needs to be done when using this as
14 *  the starting point for a new port:
15 *
16 *  + Anywhere there is an XXX, it should be replaced
17 *    with information about the CPU family being ported to.
18 *
19 *  + At the end of each comment section, there is a heading which
20 *    says "Port Specific Information:".  When porting to RTEMS,
21 *    add CPU family specific information in this section
22 */
23
24/*
25 *  COPYRIGHT (c) 1989-2013.
26 *  On-Line Applications Research Corporation (OAR).
27 *
28 *  The license and distribution terms for this file may be
29 *  found in the file LICENSE in this distribution or at
30 *  http://www.rtems.com/license/LICENSE.
31 */
32
33#ifndef _RTEMS_SCORE_CPU_H
34#define _RTEMS_SCORE_CPU_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40#include <rtems/score/no_cpu.h>            /* pick up machine definitions */
41#ifndef ASM
42#include <rtems/score/types.h>
43#endif
44
45/* conditional compilation parameters */
46
47/**
48 *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
49 *
50 *  If TRUE, then they are inlined.
51 *  If FALSE, then a subroutine call is made.
52 *
53 *  This conditional is an example of the classic trade-off of size
54 *  versus speed.  Inlining the call (TRUE) typically increases the
55 *  size of RTEMS while speeding up the enabling of dispatching.
56 *
57 *  @note In general, the @ref _Thread_Dispatch_disable_level will
58 *  only be 0 or 1 unless you are in an interrupt handler and that
59 *  interrupt handler invokes the executive.]  When not inlined
60 *  something calls @ref _Thread_Enable_dispatch which in turns calls
61 *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
62 *  one subroutine call is avoided entirely.
63 *
64 *  Port Specific Information:
65 *
66 *  XXX document implementation including references if appropriate
67 */
68#define CPU_INLINE_ENABLE_DISPATCH       TRUE
69
70/**
71 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
72 *  be unrolled one time?  In unrolled each iteration of the loop examines
73 *  two "nodes" on the chain being searched.  Otherwise, only one node
74 *  is examined per iteration.
75 *
76 *  If TRUE, then the loops are unrolled.
77 *  If FALSE, then the loops are not unrolled.
78 *
79 *  The primary factor in making this decision is the cost of disabling
80 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
81 *  body of the loop.  On some CPUs, the flash is more expensive than
82 *  one iteration of the loop body.  In this case, it might be desirable
83 *  to unroll the loop.  It is important to note that on some CPUs, this
84 *  code is the longest interrupt disable period in RTEMS.  So it is
85 *  necessary to strike a balance when setting this parameter.
86 *
87 *  Port Specific Information:
88 *
89 *  XXX document implementation including references if appropriate
90 */
91#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
92
93/**
94 *  Does RTEMS manage a dedicated interrupt stack in software?
95 *
96 *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
97 *  If FALSE, nothing is done.
98 *
99 *  If the CPU supports a dedicated interrupt stack in hardware,
100 *  then it is generally the responsibility of the BSP to allocate it
101 *  and set it up.
102 *
103 *  If the CPU does not support a dedicated interrupt stack, then
104 *  the porter has two options: (1) execute interrupts on the
105 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
106 *  interrupt stack.
107 *
108 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
109 *
110 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
111 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
112 *  possible that both are FALSE for a particular CPU.  Although it
113 *  is unclear what that would imply about the interrupt processing
114 *  procedure on that CPU.
115 *
116 *  Port Specific Information:
117 *
118 *  XXX document implementation including references if appropriate
119 */
120#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
121
122/**
123 *  Does the CPU follow the simple vectored interrupt model?
124 *
125 *  If TRUE, then RTEMS allocates the vector table it internally manages.
126 *  If FALSE, then the BSP is assumed to allocate and manage the vector
127 *  table
128 *
129 *  Port Specific Information:
130 *
131 *  XXX document implementation including references if appropriate
132 */
133#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
134
135/**
136 *  Does this CPU have hardware support for a dedicated interrupt stack?
137 *
138 *  If TRUE, then it must be installed during initialization.
139 *  If FALSE, then no installation is performed.
140 *
141 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
142 *
143 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
144 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
145 *  possible that both are FALSE for a particular CPU.  Although it
146 *  is unclear what that would imply about the interrupt processing
147 *  procedure on that CPU.
148 *
149 *  Port Specific Information:
150 *
151 *  XXX document implementation including references if appropriate
152 */
153#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
154
155/**
156 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
157 *
158 *  If TRUE, then the memory is allocated during initialization.
159 *  If FALSE, then the memory is allocated during initialization.
160 *
161 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
162 *
163 *  Port Specific Information:
164 *
165 *  XXX document implementation including references if appropriate
166 */
167#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
168
169/**
170 *  Does the RTEMS invoke the user's ISR with the vector number and
171 *  a pointer to the saved interrupt frame (1) or just the vector
172 *  number (0)?
173 *
174 *  Port Specific Information:
175 *
176 *  XXX document implementation including references if appropriate
177 */
178#define CPU_ISR_PASSES_FRAME_POINTER 0
179
180/**
181 *  @def CPU_HARDWARE_FP
182 *
183 *  Does the CPU have hardware floating point?
184 *
185 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
186 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
187 *
188 *  If there is a FP coprocessor such as the i387 or mc68881, then
189 *  the answer is TRUE.
190 *
191 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
192 *  It indicates whether or not this CPU model has FP support.  For
193 *  example, it would be possible to have an i386_nofp CPU model
194 *  which set this to false to indicate that you have an i386 without
195 *  an i387 and wish to leave floating point support out of RTEMS.
196 */
197
198/**
199 *  @def CPU_SOFTWARE_FP
200 *
201 *  Does the CPU have no hardware floating point and GCC provides a
202 *  software floating point implementation which must be context
203 *  switched?
204 *
205 *  This feature conditional is used to indicate whether or not there
206 *  is software implemented floating point that must be context
207 *  switched.  The determination of whether or not this applies
208 *  is very tool specific and the state saved/restored is also
209 *  compiler specific.
210 *
211 *  Port Specific Information:
212 *
213 *  XXX document implementation including references if appropriate
214 */
215#if ( NO_CPU_HAS_FPU == 1 )
216#define CPU_HARDWARE_FP     TRUE
217#else
218#define CPU_HARDWARE_FP     FALSE
219#endif
220#define CPU_SOFTWARE_FP     FALSE
221
222/**
223 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
224 *
225 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
226 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
227 *
228 *  So far, the only CPUs in which this option has been used are the
229 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
230 *  gcc both implicitly used the floating point registers to perform
231 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
232 *  seen to allocate floating point local variables and touch the FPU
233 *  even when the flow through a subroutine (like vfprintf()) might
234 *  not use floating point formats.
235 *
236 *  If a function which you would not think utilize the FP unit DOES,
237 *  then one can not easily predict which tasks will use the FP hardware.
238 *  In this case, this option should be TRUE.
239 *
240 *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
241 *
242 *  Port Specific Information:
243 *
244 *  XXX document implementation including references if appropriate
245 */
246#define CPU_ALL_TASKS_ARE_FP     TRUE
247
248/**
249 *  Should the IDLE task have a floating point context?
250 *
251 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
252 *  and it has a floating point context which is switched in and out.
253 *  If FALSE, then the IDLE task does not have a floating point context.
254 *
255 *  Setting this to TRUE negatively impacts the time required to preempt
256 *  the IDLE task from an interrupt because the floating point context
257 *  must be saved as part of the preemption.
258 *
259 *  Port Specific Information:
260 *
261 *  XXX document implementation including references if appropriate
262 */
263#define CPU_IDLE_TASK_IS_FP      FALSE
264
265/**
266 *  Should the saving of the floating point registers be deferred
267 *  until a context switch is made to another different floating point
268 *  task?
269 *
270 *  If TRUE, then the floating point context will not be stored until
271 *  necessary.  It will remain in the floating point registers and not
272 *  disturned until another floating point task is switched to.
273 *
274 *  If FALSE, then the floating point context is saved when a floating
275 *  point task is switched out and restored when the next floating point
276 *  task is restored.  The state of the floating point registers between
277 *  those two operations is not specified.
278 *
279 *  If the floating point context does NOT have to be saved as part of
280 *  interrupt dispatching, then it should be safe to set this to TRUE.
281 *
282 *  Setting this flag to TRUE results in using a different algorithm
283 *  for deciding when to save and restore the floating point context.
284 *  The deferred FP switch algorithm minimizes the number of times
285 *  the FP context is saved and restored.  The FP context is not saved
286 *  until a context switch is made to another, different FP task.
287 *  Thus in a system with only one FP task, the FP context will never
288 *  be saved or restored.
289 *
290 *  Port Specific Information:
291 *
292 *  XXX document implementation including references if appropriate
293 */
294#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
295
296/**
297 *  Does this port provide a CPU dependent IDLE task implementation?
298 *
299 *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
300 *  must be provided and is the default IDLE thread body instead of
301 *  @ref _CPU_Thread_Idle_body.
302 *
303 *  If FALSE, then use the generic IDLE thread body if the BSP does
304 *  not provide one.
305 *
306 *  This is intended to allow for supporting processors which have
307 *  a low power or idle mode.  When the IDLE thread is executed, then
308 *  the CPU can be powered down.
309 *
310 *  The order of precedence for selecting the IDLE thread body is:
311 *
312 *    -#  BSP provided
313 *    -#  CPU dependent (if provided)
314 *    -#  generic (if no BSP and no CPU dependent)
315 *
316 *  Port Specific Information:
317 *
318 *  XXX document implementation including references if appropriate
319 */
320#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
321
322/**
323 *  Does the stack grow up (toward higher addresses) or down
324 *  (toward lower addresses)?
325 *
326 *  If TRUE, then the grows upward.
327 *  If FALSE, then the grows toward smaller addresses.
328 *
329 *  Port Specific Information:
330 *
331 *  XXX document implementation including references if appropriate
332 */
333#define CPU_STACK_GROWS_UP               TRUE
334
335/**
336 *  The following is the variable attribute used to force alignment
337 *  of critical RTEMS structures.  On some processors it may make
338 *  sense to have these aligned on tighter boundaries than
339 *  the minimum requirements of the compiler in order to have as
340 *  much of the critical data area as possible in a cache line.
341 *
342 *  The placement of this macro in the declaration of the variables
343 *  is based on the syntactically requirements of the GNU C
344 *  "__attribute__" extension.  For example with GNU C, use
345 *  the following to force a structures to a 32 byte boundary.
346 *
347 *      __attribute__ ((aligned (32)))
348 *
349 *  @note Currently only the Priority Bit Map table uses this feature.
350 *        To benefit from using this, the data must be heavily
351 *        used so it will stay in the cache and used frequently enough
352 *        in the executive to justify turning this on.
353 *
354 *  Port Specific Information:
355 *
356 *  XXX document implementation including references if appropriate
357 */
358#define CPU_STRUCTURE_ALIGNMENT
359
360#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
361
362/**
363 *  @defgroup CPUEndian Processor Dependent Endianness Support
364 *
365 *  This group assists in issues related to processor endianness.
366 */
367
368/**
369 *  @ingroup CPUEndian
370 *  Define what is required to specify how the network to host conversion
371 *  routines are handled.
372 *
373 *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
374 *  same values.
375 *
376 *  @see CPU_LITTLE_ENDIAN
377 *
378 *  Port Specific Information:
379 *
380 *  XXX document implementation including references if appropriate
381 */
382#define CPU_BIG_ENDIAN                           TRUE
383
384/**
385 *  @ingroup CPUEndian
386 *  Define what is required to specify how the network to host conversion
387 *  routines are handled.
388 *
389 *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
390 *  same values.
391 *
392 *  @see CPU_BIG_ENDIAN
393 *
394 *  Port Specific Information:
395 *
396 *  XXX document implementation including references if appropriate
397 */
398#define CPU_LITTLE_ENDIAN                        FALSE
399
400/**
401 *  @ingroup CPUInterrupt
402 *  The following defines the number of bits actually used in the
403 *  interrupt field of the task mode.  How those bits map to the
404 *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
405 *
406 *  Port Specific Information:
407 *
408 *  XXX document implementation including references if appropriate
409 */
410#define CPU_MODES_INTERRUPT_MASK   0x00000001
411
412/*
413 *  Processor defined structures required for cpukit/score.
414 *
415 *  Port Specific Information:
416 *
417 *  XXX document implementation including references if appropriate
418 */
419
420/* may need to put some structures here.  */
421
422/**
423 * @defgroup CPUContext Processor Dependent Context Management
424 *
425 *  From the highest level viewpoint, there are 2 types of context to save.
426 *
427 *     -# Interrupt registers to save
428 *     -# Task level registers to save
429 *
430 *  Since RTEMS handles integer and floating point contexts separately, this
431 *  means we have the following 3 context items:
432 *
433 *     -# task level context stuff::  Context_Control
434 *     -# floating point task stuff:: Context_Control_fp
435 *     -# special interrupt level context :: CPU_Interrupt_frame
436 *
437 *  On some processors, it is cost-effective to save only the callee
438 *  preserved registers during a task context switch.  This means
439 *  that the ISR code needs to save those registers which do not
440 *  persist across function calls.  It is not mandatory to make this
441 *  distinctions between the caller/callee saves registers for the
442 *  purpose of minimizing context saved during task switch and on interrupts.
443 *  If the cost of saving extra registers is minimal, simplicity is the
444 *  choice.  Save the same context on interrupt entry as for tasks in
445 *  this case.
446 *
447 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
448 *  care should be used in designing the context area.
449 *
450 *  On some CPUs with hardware floating point support, the Context_Control_fp
451 *  structure will not be used or it simply consist of an array of a
452 *  fixed number of bytes.   This is done when the floating point context
453 *  is dumped by a "FP save context" type instruction and the format
454 *  is not really defined by the CPU.  In this case, there is no need
455 *  to figure out the exact format -- only the size.  Of course, although
456 *  this is enough information for RTEMS, it is probably not enough for
457 *  a debugger such as gdb.  But that is another problem.
458 *
459 *  Port Specific Information:
460 *
461 *  XXX document implementation including references if appropriate
462 */
463
464typedef struct {
465  /* There is no CPU specific per-CPU state */
466} CPU_Per_CPU_control;
467
468/**
469 *  @ingroup CPUContext Management
470 *  This defines the minimal set of integer and processor state registers
471 *  that must be saved during a voluntary context switch from one thread
472 *  to another.
473 */
474typedef struct {
475    /** This field is a hint that a port will have a number of integer
476     *  registers that need to be saved at a context switch.
477     */
478    uint32_t   some_integer_register;
479    /** This field is a hint that a port will have a number of system
480     *  registers that need to be saved at a context switch.
481     */
482    uint32_t   some_system_register;
483
484    /** This field is a hint that a port will have a register that
485     *  is the stack pointer.
486     */
487    uint32_t   stack_pointer;
488} Context_Control;
489
490/**
491 *  @ingroup CPUContext Management
492 *
493 *  This macro returns the stack pointer associated with @a _context.
494 *
495 *  @param[in] _context is the thread context area to access
496 *
497 *  @return This method returns the stack pointer.
498 */
499#define _CPU_Context_Get_SP( _context ) \
500  (_context)->stack_pointer
501
502/**
503 *  @ingroup CPUContext Management
504 *  This defines the complete set of floating point registers that must
505 *  be saved during any context switch from one thread to another.
506 */
507typedef struct {
508    /** FPU registers are listed here */
509    double      some_float_register;
510} Context_Control_fp;
511
512/**
513 *  @ingroup CPUContext Management
514 *  This defines the set of integer and processor state registers that must
515 *  be saved during an interrupt.  This set does not include any which are
516 *  in @ref Context_Control.
517 */
518typedef struct {
519    /** This field is a hint that a port will have a number of integer
520     *  registers that need to be saved when an interrupt occurs or
521     *  when a context switch occurs at the end of an ISR.
522     */
523    uint32_t   special_interrupt_register;
524} CPU_Interrupt_frame;
525
526/**
527 *  This variable is optional.  It is used on CPUs on which it is difficult
528 *  to generate an "uninitialized" FP context.  It is filled in by
529 *  @ref _CPU_Initialize and copied into the task's FP context area during
530 *  @ref _CPU_Context_Initialize.
531 *
532 *  Port Specific Information:
533 *
534 *  XXX document implementation including references if appropriate
535 */
536SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
537
538/**
539 *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
540 *
541 *  On some CPUs, RTEMS supports a software managed interrupt stack.
542 *  This stack is allocated by the Interrupt Manager and the switch
543 *  is performed in @ref _ISR_Handler.  These variables contain pointers
544 *  to the lowest and highest addresses in the chunk of memory allocated
545 *  for the interrupt stack.  Since it is unknown whether the stack
546 *  grows up or down (in general), this give the CPU dependent
547 *  code the option of picking the version it wants to use.
548 *
549 *  @note These two variables are required if the macro
550 *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
551 *
552 *  Port Specific Information:
553 *
554 *  XXX document implementation including references if appropriate
555 */
556
557/**
558 *  @ingroup CPUInterrupt
559 *  This variable points to the lowest physical address of the interrupt
560 *  stack.
561 */
562SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
563
564/**
565 *  @ingroup CPUInterrupt
566 *  This variable points to the lowest physical address of the interrupt
567 *  stack.
568 */
569SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
570
571/*
572 *  Nothing prevents the porter from declaring more CPU specific variables.
573 *
574 *  Port Specific Information:
575 *
576 *  XXX document implementation including references if appropriate
577 */
578
579/* XXX: if needed, put more variables here */
580
581/**
582 *  @ingroup CPUContext
583 *  The size of the floating point context area.  On some CPUs this
584 *  will not be a "sizeof" because the format of the floating point
585 *  area is not defined -- only the size is.  This is usually on
586 *  CPUs with a "floating point save context" instruction.
587 *
588 *  Port Specific Information:
589 *
590 *  XXX document implementation including references if appropriate
591 */
592#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
593
594/**
595 *  Amount of extra stack (above minimum stack size) required by
596 *  MPCI receive server thread.  Remember that in a multiprocessor
597 *  system this thread must exist and be able to process all directives.
598 *
599 *  Port Specific Information:
600 *
601 *  XXX document implementation including references if appropriate
602 */
603#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
604
605/**
606 *  @ingroup CPUInterrupt
607 *  This defines the number of entries in the @ref _ISR_Vector_table managed
608 *  by RTEMS.
609 *
610 *  Port Specific Information:
611 *
612 *  XXX document implementation including references if appropriate
613 */
614#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
615
616/**
617 *  @ingroup CPUInterrupt
618 *  This defines the highest interrupt vector number for this port.
619 */
620#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
621
622/**
623 *  @ingroup CPUInterrupt
624 *  This is defined if the port has a special way to report the ISR nesting
625 *  level.  Most ports maintain the variable @a _ISR_Nest_level.
626 */
627#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
628
629/**
630 *  @ingroup CPUContext
631 *  Should be large enough to run all RTEMS tests.  This ensures
632 *  that a "reasonable" small application should not have any problems.
633 *
634 *  Port Specific Information:
635 *
636 *  XXX document implementation including references if appropriate
637 */
638#define CPU_STACK_MINIMUM_SIZE          (1024*4)
639
640/**
641 *  CPU's worst alignment requirement for data types on a byte boundary.  This
642 *  alignment does not take into account the requirements for the stack.
643 *
644 *  Port Specific Information:
645 *
646 *  XXX document implementation including references if appropriate
647 */
648#define CPU_ALIGNMENT              8
649
650/**
651 *  This number corresponds to the byte alignment requirement for the
652 *  heap handler.  This alignment requirement may be stricter than that
653 *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
654 *  common for the heap to follow the same alignment requirement as
655 *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
656 *  the heap, then this should be set to @ref CPU_ALIGNMENT.
657 *
658 *  @note  This does not have to be a power of 2 although it should be
659 *         a multiple of 2 greater than or equal to 2.  The requirement
660 *         to be a multiple of 2 is because the heap uses the least
661 *         significant field of the front and back flags to indicate
662 *         that a block is in use or free.  So you do not want any odd
663 *         length blocks really putting length data in that bit.
664 *
665 *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
666 *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
667 *         elements allocated from the heap meet all restrictions.
668 *
669 *  Port Specific Information:
670 *
671 *  XXX document implementation including references if appropriate
672 */
673#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
674
675/**
676 *  This number corresponds to the byte alignment requirement for memory
677 *  buffers allocated by the partition manager.  This alignment requirement
678 *  may be stricter than that for the data types alignment specified by
679 *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
680 *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
681 *  strict enough for the partition, then this should be set to
682 *  @ref CPU_ALIGNMENT.
683 *
684 *  @note  This does not have to be a power of 2.  It does have to
685 *         be greater or equal to than @ref CPU_ALIGNMENT.
686 *
687 *  Port Specific Information:
688 *
689 *  XXX document implementation including references if appropriate
690 */
691#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
692
693/**
694 *  This number corresponds to the byte alignment requirement for the
695 *  stack.  This alignment requirement may be stricter than that for the
696 *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
697 *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
698 *  set to 0.
699 *
700 *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
701 *
702 *  Port Specific Information:
703 *
704 *  XXX document implementation including references if appropriate
705 */
706#define CPU_STACK_ALIGNMENT        0
707
708/*
709 *  ISR handler macros
710 */
711
712/**
713 *  @ingroup CPUInterrupt
714 *  Support routine to initialize the RTEMS vector table after it is allocated.
715 *
716 *  Port Specific Information:
717 *
718 *  XXX document implementation including references if appropriate
719 */
720#define _CPU_Initialize_vectors()
721
722/**
723 *  XXX fake cpu isr level variable
724 */
725extern int _CPU_ISR_level_on_sched_cpu;
726
727/**
728 *  @ingroup CPUInterrupt
729 *  Disable all interrupts for an RTEMS critical section.  The previous
730 *  level is returned in @a _isr_cookie.
731 *
732 *  @param[out] _isr_cookie will contain the previous level cookie
733 *
734 *  Port Specific Information:
735 *
736 *  XXX document implementation including references if appropriate
737 */
738#define _CPU_ISR_Disable( _isr_cookie ) \
739  { \
740    (_isr_cookie) = _CPU_ISR_level_on_sched_cpu; \
741    _CPU_ISR_level_on_sched_cpu = 1; \
742  }
743
744/**
745 *  @ingroup CPUInterrupt
746 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
747 *  This indicates the end of an RTEMS critical section.  The parameter
748 *  @a _isr_cookie is not modified.
749 *
750 *  @param[in] _isr_cookie contain the previous level cookie
751 *
752 *  Port Specific Information:
753 *
754 *  XXX document implementation including references if appropriate
755 */
756#define _CPU_ISR_Enable( _isr_cookie )  \
757  { \
758    _CPU_ISR_level_on_sched_cpu = (_isr_cookie); \
759  }
760
761/**
762 *  @ingroup CPUInterrupt
763 *  This temporarily restores the interrupt to @a _isr_cookie before immediately
764 *  disabling them again.  This is used to divide long RTEMS critical
765 *  sections into two or more parts.  The parameter @a _isr_cookie is not
766 *  modified.
767 *
768 *  @param[in] _isr_cookie contain the previous level cookie
769 *
770 *  Port Specific Information:
771 *
772 *  XXX document implementation including references if appropriate
773 */
774#define _CPU_ISR_Flash( _isr_cookie ) \
775  { \
776  }
777
778/**
779 *  @ingroup CPUInterrupt
780 *
781 *  This routine and @ref _CPU_ISR_Get_level
782 *  Map the interrupt level in task mode onto the hardware that the CPU
783 *  actually provides.  Currently, interrupt levels which do not
784 *  map onto the CPU in a generic fashion are undefined.  Someday,
785 *  it would be nice if these were "mapped" by the application
786 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
787 *  8 - 255 would be available for bsp/application specific meaning.
788 *  This could be used to manage a programmable interrupt controller
789 *  via the rtems_task_mode directive.
790 *
791 *  Port Specific Information:
792 *
793 *  XXX document implementation including references if appropriate
794 */
795#define _CPU_ISR_Set_level( new_level ) \
796  { \
797    _CPU_ISR_level_on_sched_cpu = (new_level); \
798  }
799
800/**
801 *  @ingroup CPUInterrupt
802 *  Return the current interrupt disable level for this task in
803 *  the format used by the interrupt level portion of the task mode.
804 *
805 *  @note This routine usually must be implemented as a subroutine.
806 *
807 *  Port Specific Information:
808 *
809 *  XXX document implementation including references if appropriate
810 */
811#define _CPU_ISR_Get_level() (uint32_t) _CPU_ISR_level_on_sched_cpu
812
813/* end of ISR handler macros */
814
815/* Context handler macros */
816
817/**
818 *  @ingroup CPUContext
819 *  Initialize the context to a state suitable for starting a
820 *  task after a context restore operation.  Generally, this
821 *  involves:
822 *
823 *     - setting a starting address
824 *     - preparing the stack
825 *     - preparing the stack and frame pointers
826 *     - setting the proper interrupt level in the context
827 *     - initializing the floating point context
828 *
829 *  This routine generally does not set any unnecessary register
830 *  in the context.  The state of the "general data" registers is
831 *  undefined at task start time.
832 *
833 *  @param[in] _the_context is the context structure to be initialized
834 *  @param[in] _stack_base is the lowest physical address of this task's stack
835 *  @param[in] _size is the size of this task's stack
836 *  @param[in] _isr is the interrupt disable level
837 *  @param[in] _entry_point is the thread's entry point.  This is
838 *         always @a _Thread_Handler
839 *  @param[in] _is_fp is TRUE if the thread is to be a floating
840 *        point thread.  This is typically only used on CPUs where the
841 *        FPU may be easily disabled by software such as on the SPARC
842 *        where the PSR contains an enable FPU bit.
843 *
844 *  Port Specific Information:
845 *
846 *  XXX document implementation including references if appropriate
847 */
848#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
849                                 _isr, _entry_point, _is_fp, tls_area ) \
850  { \
851  }
852
853/**
854 *  This routine is responsible for somehow restarting the currently
855 *  executing task.  If you are lucky, then all that is necessary
856 *  is restoring the context.  Otherwise, there will need to be
857 *  a special assembly routine which does something special in this
858 *  case.  For many ports, simply adding a label to the restore path
859 *  of @ref _CPU_Context_switch will work.  On other ports, it may be
860 *  possibly to load a few arguments and jump to the restore path. It will
861 *  not work if restarting self conflicts with the stack frame
862 *  assumptions of restoring a context.
863 *
864 *  Port Specific Information:
865 *
866 *  XXX document implementation including references if appropriate
867 */
868#define _CPU_Context_Restart_self( _the_context ) \
869   _CPU_Context_restore( (_the_context) );
870
871/**
872 *  @ingroup CPUContext
873 *  The purpose of this macro is to allow the initial pointer into
874 *  a floating point context area (used to save the floating point
875 *  context) to be at an arbitrary place in the floating point
876 *  context area.
877 *
878 *  This is necessary because some FP units are designed to have
879 *  their context saved as a stack which grows into lower addresses.
880 *  Other FP units can be saved by simply moving registers into offsets
881 *  from the base of the context area.  Finally some FP units provide
882 *  a "dump context" instruction which could fill in from high to low
883 *  or low to high based on the whim of the CPU designers.
884 *
885 *  @param[in] _base is the lowest physical address of the floating point
886 *         context area
887 *  @param[in] _offset is the offset into the floating point area
888 *
889 *  Port Specific Information:
890 *
891 *  XXX document implementation including references if appropriate
892 */
893#define _CPU_Context_Fp_start( _base, _offset ) \
894   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
895
896/**
897 *  This routine initializes the FP context area passed to it to.
898 *  There are a few standard ways in which to initialize the
899 *  floating point context.  The code included for this macro assumes
900 *  that this is a CPU in which a "initial" FP context was saved into
901 *  @a _CPU_Null_fp_context and it simply copies it to the destination
902 *  context passed to it.
903 *
904 *  Other floating point context save/restore models include:
905 *    -# not doing anything, and
906 *    -# putting a "null FP status word" in the correct place in the FP context.
907 *
908 *  @param[in] _destination is the floating point context area
909 *
910 *  Port Specific Information:
911 *
912 *  XXX document implementation including references if appropriate
913 */
914#define _CPU_Context_Initialize_fp( _destination ) \
915  { \
916   *(*(_destination)) = _CPU_Null_fp_context; \
917  }
918
919/* end of Context handler macros */
920
921/* Fatal Error manager macros */
922
923/**
924 *  This routine copies _error into a known place -- typically a stack
925 *  location or a register, optionally disables interrupts, and
926 *  halts/stops the CPU.
927 *
928 *  Port Specific Information:
929 *
930 *  XXX document implementation including references if appropriate
931 */
932#define _CPU_Fatal_halt( _error ) \
933  { \
934  }
935
936/* end of Fatal Error manager macros */
937
938/* Bitfield handler macros */
939
940/**
941 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
942 *
943 *  This set of routines are used to implement fast searches for
944 *  the most important ready task.
945 */
946
947/**
948 *  @ingroup CPUBitfield
949 *  This definition is set to TRUE if the port uses the generic bitfield
950 *  manipulation implementation.
951 */
952#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
953
954/**
955 *  @ingroup CPUBitfield
956 *  This definition is set to TRUE if the port uses the data tables provided
957 *  by the generic bitfield manipulation implementation.
958 *  This can occur when actually using the generic bitfield manipulation
959 *  implementation or when implementing the same algorithm in assembly
960 *  language for improved performance.  It is unlikely that a port will use
961 *  the data if it has a bitfield scan instruction.
962 */
963#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
964
965/**
966 *  @ingroup CPUBitfield
967 *  This routine sets @a _output to the bit number of the first bit
968 *  set in @a _value.  @a _value is of CPU dependent type
969 *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
970 *  wide although only the 16 least significant bits will be used.
971 *
972 *  There are a number of variables in using a "find first bit" type
973 *  instruction.
974 *
975 *    -# What happens when run on a value of zero?
976 *    -# Bits may be numbered from MSB to LSB or vice-versa.
977 *    -# The numbering may be zero or one based.
978 *    -# The "find first bit" instruction may search from MSB or LSB.
979 *
980 *  RTEMS guarantees that (1) will never happen so it is not a concern.
981 *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
982 *  @ref _CPU_Priority_bits_index.  These three form a set of routines
983 *  which must logically operate together.  Bits in the _value are
984 *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
985 *  The basic major and minor values calculated by @ref _Priority_Major
986 *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
987 *  to properly range between the values returned by the "find first bit"
988 *  instruction.  This makes it possible for @ref _Priority_Get_highest to
989 *  calculate the major and directly index into the minor table.
990 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
991 *  is the first bit found.
992 *
993 *  This entire "find first bit" and mapping process depends heavily
994 *  on the manner in which a priority is broken into a major and minor
995 *  components with the major being the 4 MSB of a priority and minor
996 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
997 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
998 *  to the lowest priority.
999 *
1000 *  If your CPU does not have a "find first bit" instruction, then
1001 *  there are ways to make do without it.  Here are a handful of ways
1002 *  to implement this in software:
1003 *
1004@verbatim
1005      - a series of 16 bit test instructions
1006      - a "binary search using if's"
1007      - _number = 0
1008        if _value > 0x00ff
1009          _value >>=8
1010          _number = 8;
1011
1012        if _value > 0x0000f
1013          _value >=8
1014          _number += 4
1015
1016        _number += bit_set_table[ _value ]
1017@endverbatim
1018
1019 *    where bit_set_table[ 16 ] has values which indicate the first
1020 *      bit set
1021 *
1022 *  @param[in] _value is the value to be scanned
1023 *  @param[in] _output is the first bit set
1024 *
1025 *  Port Specific Information:
1026 *
1027 *  XXX document implementation including references if appropriate
1028 */
1029
1030#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1031#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1032  { \
1033    (_output) = 0;   /* do something to prevent warnings */ \
1034  }
1035#endif
1036
1037/* end of Bitfield handler macros */
1038
1039/**
1040 *  This routine builds the mask which corresponds to the bit fields
1041 *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1042 *  for that routine.
1043 *
1044 *  Port Specific Information:
1045 *
1046 *  XXX document implementation including references if appropriate
1047 */
1048#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1049
1050#define _CPU_Priority_Mask( _bit_number ) \
1051  ( 1 << (_bit_number) )
1052
1053#endif
1054
1055/**
1056 *  @ingroup CPUBitfield
1057 *  This routine translates the bit numbers returned by
1058 *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1059 *  a major or minor component of a priority.  See the discussion
1060 *  for that routine.
1061 *
1062 *  @param[in] _priority is the major or minor number to translate
1063 *
1064 *  Port Specific Information:
1065 *
1066 *  XXX document implementation including references if appropriate
1067 */
1068#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1069
1070#define _CPU_Priority_bits_index( _priority ) \
1071  (_priority)
1072
1073#endif
1074
1075/* end of Priority handler macros */
1076
1077/* functions */
1078
1079/**
1080 *  This routine performs CPU dependent initialization.
1081 *
1082 *  Port Specific Information:
1083 *
1084 *  XXX document implementation including references if appropriate
1085 */
1086void _CPU_Initialize(void);
1087
1088/**
1089 *  @ingroup CPUInterrupt
1090 *  This routine installs a "raw" interrupt handler directly into the
1091 *  processor's vector table.
1092 *
1093 *  @param[in] vector is the vector number
1094 *  @param[in] new_handler is the raw ISR handler to install
1095 *  @param[in] old_handler is the previously installed ISR Handler
1096 *
1097 *  Port Specific Information:
1098 *
1099 *  XXX document implementation including references if appropriate
1100 */
1101void _CPU_ISR_install_raw_handler(
1102  uint32_t    vector,
1103  proc_ptr    new_handler,
1104  proc_ptr   *old_handler
1105);
1106
1107/**
1108 *  @ingroup CPUInterrupt
1109 *  This routine installs an interrupt vector.
1110 *
1111 *  @param[in] vector is the vector number
1112 *  @param[in] new_handler is the RTEMS ISR handler to install
1113 *  @param[in] old_handler is the previously installed ISR Handler
1114 *
1115 *  Port Specific Information:
1116 *
1117 *  XXX document implementation including references if appropriate
1118 */
1119void _CPU_ISR_install_vector(
1120  uint32_t    vector,
1121  proc_ptr    new_handler,
1122  proc_ptr   *old_handler
1123);
1124
1125/**
1126 *  @ingroup CPUInterrupt
1127 *  This routine installs the hardware interrupt stack pointer.
1128 *
1129 *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1130 *         is TRUE.
1131 *
1132 *  Port Specific Information:
1133 *
1134 *  XXX document implementation including references if appropriate
1135 */
1136void _CPU_Install_interrupt_stack( void );
1137
1138typedef uint32_t CPU_Counter_ticks;
1139
1140CPU_Counter_ticks _CPU_Counter_read( void );
1141
1142CPU_Counter_ticks _CPU_Counter_difference(
1143  CPU_Counter_ticks second,
1144  CPU_Counter_ticks first
1145);
1146
1147/**
1148 *  This routine is the CPU dependent IDLE thread body.
1149 *
1150 *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1151 *         is TRUE.
1152 *
1153 *  Port Specific Information:
1154 *
1155 *  XXX document implementation including references if appropriate
1156 */
1157void *_CPU_Thread_Idle_body( uintptr_t ignored );
1158
1159/**
1160 *  @ingroup CPUContext
1161 *  This routine switches from the run context to the heir context.
1162 *
1163 *  @param[in] run points to the context of the currently executing task
1164 *  @param[in] heir points to the context of the heir task
1165 *
1166 *  Port Specific Information:
1167 *
1168 *  XXX document implementation including references if appropriate
1169 */
1170void _CPU_Context_switch(
1171  Context_Control  *run,
1172  Context_Control  *heir
1173);
1174
1175/**
1176 *  @ingroup CPUContext
1177 *  This routine is generally used only to restart self in an
1178 *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1179 *
1180 *  @param[in] new_context points to the context to be restored.
1181 *
1182 *  @note May be unnecessary to reload some registers.
1183 *
1184 *  Port Specific Information:
1185 *
1186 *  XXX document implementation including references if appropriate
1187 */
1188void _CPU_Context_restore(
1189  Context_Control *new_context
1190);
1191
1192/**
1193 *  @ingroup CPUContext
1194 *  This routine saves the floating point context passed to it.
1195 *
1196 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1197 *  point context area
1198 *
1199 *  @return on output @a *fp_context_ptr will contain the address that
1200 *  should be used with @ref _CPU_Context_restore_fp to restore this context.
1201 *
1202 *  Port Specific Information:
1203 *
1204 *  XXX document implementation including references if appropriate
1205 */
1206void _CPU_Context_save_fp(
1207  Context_Control_fp **fp_context_ptr
1208);
1209
1210/**
1211 *  @ingroup CPUContext
1212 *  This routine restores the floating point context passed to it.
1213 *
1214 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1215 *  point context area to restore
1216 *
1217 *  @return on output @a *fp_context_ptr will contain the address that
1218 *  should be used with @ref _CPU_Context_save_fp to save this context.
1219 *
1220 *  Port Specific Information:
1221 *
1222 *  XXX document implementation including references if appropriate
1223 */
1224void _CPU_Context_restore_fp(
1225  Context_Control_fp **fp_context_ptr
1226);
1227
1228#ifdef RTEMS_SMP
1229  #define _CPU_Context_switch_to_first_task_smp(_context )
1230
1231  uint32_t _CPU_SMP_Get_current_processor( void );
1232  uint32_t _CPU_SMP_Initialize( void );
1233  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1234  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1235  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1236  void _CPU_SMP_Processor_event_broadcast( void );
1237  void _CPU_SMP_Processor_event_receive( void );
1238#endif
1239typedef struct {
1240  uint32_t trap;
1241  CPU_Interrupt_frame *isf;
1242} CPU_Exception_frame;
1243
1244static inline void _CPU_Exception_frame_print(
1245  const CPU_Exception_frame *frame
1246)
1247{
1248  /* printk( "Printing exception frame\n" ); */
1249}
1250/**
1251 *  @ingroup CPUEndian
1252 *  The following routine swaps the endian format of an unsigned int.
1253 *  It must be static because it is referenced indirectly.
1254 *
1255 *  This version will work on any processor, but if there is a better
1256 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1257 *
1258 *     swap least significant two bytes with 16-bit rotate
1259 *     swap upper and lower 16-bits
1260 *     swap most significant two bytes with 16-bit rotate
1261 *
1262 *  Some CPUs have special instructions which swap a 32-bit quantity in
1263 *  a single instruction (e.g. i486).  It is probably best to avoid
1264 *  an "endian swapping control bit" in the CPU.  One good reason is
1265 *  that interrupts would probably have to be disabled to ensure that
1266 *  an interrupt does not try to access the same "chunk" with the wrong
1267 *  endian.  Another good reason is that on some CPUs, the endian bit
1268 *  endianness for ALL fetches -- both code and data -- so the code
1269 *  will be fetched incorrectly.
1270 *
1271 *  @param[in] value is the value to be swapped
1272 *  @return the value after being endian swapped
1273 *
1274 *  Port Specific Information:
1275 *
1276 *  XXX document implementation including references if appropriate
1277 */
1278static inline uint32_t CPU_swap_u32(
1279  uint32_t value
1280)
1281{
1282  uint32_t byte1, byte2, byte3, byte4, swapped;
1283
1284  byte4 = (value >> 24) & 0xff;
1285  byte3 = (value >> 16) & 0xff;
1286  byte2 = (value >> 8)  & 0xff;
1287  byte1 =  value        & 0xff;
1288
1289  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1290  return swapped;
1291}
1292
1293/**
1294 *  @ingroup CPUEndian
1295 *  This routine swaps a 16 bir quantity.
1296 *
1297 *  @param[in] value is the value to be swapped
1298 *  @return the value after being endian swapped
1299 */
1300#define CPU_swap_u16( value ) \
1301  (((value&0xff) << 8) | ((value >> 8)&0xff))
1302
1303/*
1304 *  SMP Support
1305 */
1306void __SMP_cpu_swap( 
1307  uint32_t *a,
1308  uint32_t *value,
1309  uint32_t *prev
1310);
1311#define SMP_CPU_SWAP( _address, _value, _previous ) \
1312  do { \
1313    volatile unsigned int *_a = (volatile unsigned int *)_address; \
1314    _previous = *(_a); \
1315    *(_a) = _value; \
1316  } while (0)
1317
1318#ifdef __cplusplus
1319}
1320#endif
1321
1322#endif
Note: See TracBrowser for help on using the repository browser.