source: rtems-schedsim/schedsim/rtems/sched_cpu/rtems/score/cpu.h @ caee146

Last change on this file since caee146 was caee146, checked in by Joel Sherrill <joel.sherrill@…>, on May 1, 2013 at 12:05:53 AM

schedsim/.../cpu.h: Account for new types and methods

  • Property mode set to 100644
File size: 41.8 KB
RevLine 
[abb18dc]1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  BASED UPON SOURCE IN RTEMS, MODIFIED FOR SIMULATOR
7 *
8 *  This include file contains information pertaining to the XXX
9 *  processor.
10 *
11 *  @note This file is part of a porting template that is intended
12 *  to be used as the starting point when porting RTEMS to a new
13 *  CPU family.  The following needs to be done when using this as
14 *  the starting point for a new port:
15 *
16 *  + Anywhere there is an XXX, it should be replaced
17 *    with information about the CPU family being ported to.
18 *
19 *  + At the end of each comment section, there is a heading which
20 *    says "Port Specific Information:".  When porting to RTEMS,
21 *    add CPU family specific information in this section
22 */
23
24/*
25 *  COPYRIGHT (c) 1989-2010.
26 *  On-Line Applications Research Corporation (OAR).
27 *
28 *  The license and distribution terms for this file may be
29 *  found in the file LICENSE in this distribution or at
30 *  http://www.rtems.com/license/LICENSE.
31 *
32 *  $Id$
33 */
34
35#ifndef _RTEMS_SCORE_CPU_H
36#define _RTEMS_SCORE_CPU_H
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42#include <rtems/score/no_cpu.h>            /* pick up machine definitions */
43#ifndef ASM
44#include <rtems/score/types.h>
45#endif
46
47/* conditional compilation parameters */
48
49/**
50 *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
51 *
52 *  If TRUE, then they are inlined.
53 *  If FALSE, then a subroutine call is made.
54 *
55 *  This conditional is an example of the classic trade-off of size
56 *  versus speed.  Inlining the call (TRUE) typically increases the
57 *  size of RTEMS while speeding up the enabling of dispatching.
58 *
59 *  @note In general, the @ref _Thread_Dispatch_disable_level will
60 *  only be 0 or 1 unless you are in an interrupt handler and that
61 *  interrupt handler invokes the executive.]  When not inlined
62 *  something calls @ref _Thread_Enable_dispatch which in turns calls
63 *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
64 *  one subroutine call is avoided entirely.
65 *
66 *  Port Specific Information:
67 *
68 *  XXX document implementation including references if appropriate
69 */
70#define CPU_INLINE_ENABLE_DISPATCH       TRUE
71
72/**
73 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
74 *  be unrolled one time?  In unrolled each iteration of the loop examines
75 *  two "nodes" on the chain being searched.  Otherwise, only one node
76 *  is examined per iteration.
77 *
78 *  If TRUE, then the loops are unrolled.
79 *  If FALSE, then the loops are not unrolled.
80 *
81 *  The primary factor in making this decision is the cost of disabling
82 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
83 *  body of the loop.  On some CPUs, the flash is more expensive than
84 *  one iteration of the loop body.  In this case, it might be desirable
85 *  to unroll the loop.  It is important to note that on some CPUs, this
86 *  code is the longest interrupt disable period in RTEMS.  So it is
87 *  necessary to strike a balance when setting this parameter.
88 *
89 *  Port Specific Information:
90 *
91 *  XXX document implementation including references if appropriate
92 */
93#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
94
95/**
96 *  Does RTEMS manage a dedicated interrupt stack in software?
97 *
98 *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
99 *  If FALSE, nothing is done.
100 *
101 *  If the CPU supports a dedicated interrupt stack in hardware,
102 *  then it is generally the responsibility of the BSP to allocate it
103 *  and set it up.
104 *
105 *  If the CPU does not support a dedicated interrupt stack, then
106 *  the porter has two options: (1) execute interrupts on the
107 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
108 *  interrupt stack.
109 *
110 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
111 *
112 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
113 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
114 *  possible that both are FALSE for a particular CPU.  Although it
115 *  is unclear what that would imply about the interrupt processing
116 *  procedure on that CPU.
117 *
118 *  Port Specific Information:
119 *
120 *  XXX document implementation including references if appropriate
121 */
122#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
123
124/**
125 *  Does the CPU follow the simple vectored interrupt model?
126 *
127 *  If TRUE, then RTEMS allocates the vector table it internally manages.
128 *  If FALSE, then the BSP is assumed to allocate and manage the vector
129 *  table
130 *
131 *  Port Specific Information:
132 *
133 *  XXX document implementation including references if appropriate
134 */
135#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
136
137/**
138 *  Does this CPU have hardware support for a dedicated interrupt stack?
139 *
140 *  If TRUE, then it must be installed during initialization.
141 *  If FALSE, then no installation is performed.
142 *
143 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
144 *
145 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
146 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
147 *  possible that both are FALSE for a particular CPU.  Although it
148 *  is unclear what that would imply about the interrupt processing
149 *  procedure on that CPU.
150 *
151 *  Port Specific Information:
152 *
153 *  XXX document implementation including references if appropriate
154 */
155#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
156
157/**
158 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
159 *
160 *  If TRUE, then the memory is allocated during initialization.
161 *  If FALSE, then the memory is allocated during initialization.
162 *
163 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
164 *
165 *  Port Specific Information:
166 *
167 *  XXX document implementation including references if appropriate
168 */
169#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
170
171/**
172 *  Does the RTEMS invoke the user's ISR with the vector number and
173 *  a pointer to the saved interrupt frame (1) or just the vector
174 *  number (0)?
175 *
176 *  Port Specific Information:
177 *
178 *  XXX document implementation including references if appropriate
179 */
180#define CPU_ISR_PASSES_FRAME_POINTER 0
181
182/**
183 *  @def CPU_HARDWARE_FP
184 *
185 *  Does the CPU have hardware floating point?
186 *
187 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
188 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
189 *
190 *  If there is a FP coprocessor such as the i387 or mc68881, then
191 *  the answer is TRUE.
192 *
193 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
194 *  It indicates whether or not this CPU model has FP support.  For
195 *  example, it would be possible to have an i386_nofp CPU model
196 *  which set this to false to indicate that you have an i386 without
197 *  an i387 and wish to leave floating point support out of RTEMS.
198 */
199
200/**
201 *  @def CPU_SOFTWARE_FP
202 *
203 *  Does the CPU have no hardware floating point and GCC provides a
204 *  software floating point implementation which must be context
205 *  switched?
206 *
207 *  This feature conditional is used to indicate whether or not there
208 *  is software implemented floating point that must be context
209 *  switched.  The determination of whether or not this applies
210 *  is very tool specific and the state saved/restored is also
211 *  compiler specific.
212 *
213 *  Port Specific Information:
214 *
215 *  XXX document implementation including references if appropriate
216 */
217#if ( NO_CPU_HAS_FPU == 1 )
218#define CPU_HARDWARE_FP     TRUE
219#else
220#define CPU_HARDWARE_FP     FALSE
221#endif
222#define CPU_SOFTWARE_FP     FALSE
223
224/**
225 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
226 *
227 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
228 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
229 *
230 *  So far, the only CPUs in which this option has been used are the
231 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
232 *  gcc both implicitly used the floating point registers to perform
233 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
234 *  seen to allocate floating point local variables and touch the FPU
235 *  even when the flow through a subroutine (like vfprintf()) might
236 *  not use floating point formats.
237 *
238 *  If a function which you would not think utilize the FP unit DOES,
239 *  then one can not easily predict which tasks will use the FP hardware.
240 *  In this case, this option should be TRUE.
241 *
242 *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
243 *
244 *  Port Specific Information:
245 *
246 *  XXX document implementation including references if appropriate
247 */
248#define CPU_ALL_TASKS_ARE_FP     TRUE
249
250/**
251 *  Should the IDLE task have a floating point context?
252 *
253 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
254 *  and it has a floating point context which is switched in and out.
255 *  If FALSE, then the IDLE task does not have a floating point context.
256 *
257 *  Setting this to TRUE negatively impacts the time required to preempt
258 *  the IDLE task from an interrupt because the floating point context
259 *  must be saved as part of the preemption.
260 *
261 *  Port Specific Information:
262 *
263 *  XXX document implementation including references if appropriate
264 */
265#define CPU_IDLE_TASK_IS_FP      FALSE
266
267/**
268 *  Should the saving of the floating point registers be deferred
269 *  until a context switch is made to another different floating point
270 *  task?
271 *
272 *  If TRUE, then the floating point context will not be stored until
273 *  necessary.  It will remain in the floating point registers and not
274 *  disturned until another floating point task is switched to.
275 *
276 *  If FALSE, then the floating point context is saved when a floating
277 *  point task is switched out and restored when the next floating point
278 *  task is restored.  The state of the floating point registers between
279 *  those two operations is not specified.
280 *
281 *  If the floating point context does NOT have to be saved as part of
282 *  interrupt dispatching, then it should be safe to set this to TRUE.
283 *
284 *  Setting this flag to TRUE results in using a different algorithm
285 *  for deciding when to save and restore the floating point context.
286 *  The deferred FP switch algorithm minimizes the number of times
287 *  the FP context is saved and restored.  The FP context is not saved
288 *  until a context switch is made to another, different FP task.
289 *  Thus in a system with only one FP task, the FP context will never
290 *  be saved or restored.
291 *
292 *  Port Specific Information:
293 *
294 *  XXX document implementation including references if appropriate
295 */
296#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
297
298/**
299 *  Does this port provide a CPU dependent IDLE task implementation?
300 *
301 *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
302 *  must be provided and is the default IDLE thread body instead of
303 *  @ref _CPU_Thread_Idle_body.
304 *
305 *  If FALSE, then use the generic IDLE thread body if the BSP does
306 *  not provide one.
307 *
308 *  This is intended to allow for supporting processors which have
309 *  a low power or idle mode.  When the IDLE thread is executed, then
310 *  the CPU can be powered down.
311 *
312 *  The order of precedence for selecting the IDLE thread body is:
313 *
314 *    -#  BSP provided
315 *    -#  CPU dependent (if provided)
316 *    -#  generic (if no BSP and no CPU dependent)
317 *
318 *  Port Specific Information:
319 *
320 *  XXX document implementation including references if appropriate
321 */
322#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
323
324/**
325 *  Does the stack grow up (toward higher addresses) or down
326 *  (toward lower addresses)?
327 *
328 *  If TRUE, then the grows upward.
329 *  If FALSE, then the grows toward smaller addresses.
330 *
331 *  Port Specific Information:
332 *
333 *  XXX document implementation including references if appropriate
334 */
335#define CPU_STACK_GROWS_UP               TRUE
336
337/**
338 *  The following is the variable attribute used to force alignment
339 *  of critical RTEMS structures.  On some processors it may make
340 *  sense to have these aligned on tighter boundaries than
341 *  the minimum requirements of the compiler in order to have as
342 *  much of the critical data area as possible in a cache line.
343 *
344 *  The placement of this macro in the declaration of the variables
345 *  is based on the syntactically requirements of the GNU C
346 *  "__attribute__" extension.  For example with GNU C, use
347 *  the following to force a structures to a 32 byte boundary.
348 *
349 *      __attribute__ ((aligned (32)))
350 *
351 *  @note Currently only the Priority Bit Map table uses this feature.
352 *        To benefit from using this, the data must be heavily
353 *        used so it will stay in the cache and used frequently enough
354 *        in the executive to justify turning this on.
355 *
356 *  Port Specific Information:
357 *
358 *  XXX document implementation including references if appropriate
359 */
360#define CPU_STRUCTURE_ALIGNMENT
361
[caee146]362#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
363
[abb18dc]364/**
365 *  @defgroup CPUEndian Processor Dependent Endianness Support
366 *
367 *  This group assists in issues related to processor endianness.
368 */
369
370/**
371 *  @ingroup CPUEndian
372 *  Define what is required to specify how the network to host conversion
373 *  routines are handled.
374 *
375 *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
376 *  same values.
377 *
378 *  @see CPU_LITTLE_ENDIAN
379 *
380 *  Port Specific Information:
381 *
382 *  XXX document implementation including references if appropriate
383 */
384#define CPU_BIG_ENDIAN                           TRUE
385
386/**
387 *  @ingroup CPUEndian
388 *  Define what is required to specify how the network to host conversion
389 *  routines are handled.
390 *
391 *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
392 *  same values.
393 *
394 *  @see CPU_BIG_ENDIAN
395 *
396 *  Port Specific Information:
397 *
398 *  XXX document implementation including references if appropriate
399 */
400#define CPU_LITTLE_ENDIAN                        FALSE
401
402/**
403 *  @ingroup CPUInterrupt
404 *  The following defines the number of bits actually used in the
405 *  interrupt field of the task mode.  How those bits map to the
406 *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
407 *
408 *  Port Specific Information:
409 *
410 *  XXX document implementation including references if appropriate
411 */
412#define CPU_MODES_INTERRUPT_MASK   0x00000001
413
414/*
415 *  Processor defined structures required for cpukit/score.
416 *
417 *  Port Specific Information:
418 *
419 *  XXX document implementation including references if appropriate
420 */
421
422/* may need to put some structures here.  */
423
424/**
425 * @defgroup CPUContext Processor Dependent Context Management
426 *
427 *  From the highest level viewpoint, there are 2 types of context to save.
428 *
429 *     -# Interrupt registers to save
430 *     -# Task level registers to save
431 *
432 *  Since RTEMS handles integer and floating point contexts separately, this
433 *  means we have the following 3 context items:
434 *
435 *     -# task level context stuff::  Context_Control
436 *     -# floating point task stuff:: Context_Control_fp
437 *     -# special interrupt level context :: CPU_Interrupt_frame
438 *
439 *  On some processors, it is cost-effective to save only the callee
440 *  preserved registers during a task context switch.  This means
441 *  that the ISR code needs to save those registers which do not
442 *  persist across function calls.  It is not mandatory to make this
443 *  distinctions between the caller/callee saves registers for the
444 *  purpose of minimizing context saved during task switch and on interrupts.
445 *  If the cost of saving extra registers is minimal, simplicity is the
446 *  choice.  Save the same context on interrupt entry as for tasks in
447 *  this case.
448 *
449 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
450 *  care should be used in designing the context area.
451 *
452 *  On some CPUs with hardware floating point support, the Context_Control_fp
453 *  structure will not be used or it simply consist of an array of a
454 *  fixed number of bytes.   This is done when the floating point context
455 *  is dumped by a "FP save context" type instruction and the format
456 *  is not really defined by the CPU.  In this case, there is no need
457 *  to figure out the exact format -- only the size.  Of course, although
458 *  this is enough information for RTEMS, it is probably not enough for
459 *  a debugger such as gdb.  But that is another problem.
460 *
461 *  Port Specific Information:
462 *
463 *  XXX document implementation including references if appropriate
464 */
465
466/**
467 *  @ingroup CPUContext Management
468 *  This defines the minimal set of integer and processor state registers
469 *  that must be saved during a voluntary context switch from one thread
470 *  to another.
471 */
472typedef struct {
473    /** This field is a hint that a port will have a number of integer
474     *  registers that need to be saved at a context switch.
475     */
476    uint32_t   some_integer_register;
477    /** This field is a hint that a port will have a number of system
478     *  registers that need to be saved at a context switch.
479     */
480    uint32_t   some_system_register;
481
482    /** This field is a hint that a port will have a register that
483     *  is the stack pointer.
484     */
485    uint32_t   stack_pointer;
486} Context_Control;
487
488/**
489 *  @ingroup CPUContext Management
490 *
491 *  This macro returns the stack pointer associated with @a _context.
492 *
493 *  @param[in] _context is the thread context area to access
494 *
495 *  @return This method returns the stack pointer.
496 */
497#define _CPU_Context_Get_SP( _context ) \
498  (_context)->stack_pointer
499
500/**
501 *  @ingroup CPUContext Management
502 *  This defines the complete set of floating point registers that must
503 *  be saved during any context switch from one thread to another.
504 */
505typedef struct {
506    /** FPU registers are listed here */
507    double      some_float_register;
508} Context_Control_fp;
509
510/**
511 *  @ingroup CPUContext Management
512 *  This defines the set of integer and processor state registers that must
513 *  be saved during an interrupt.  This set does not include any which are
514 *  in @ref Context_Control.
515 */
516typedef struct {
517    /** This field is a hint that a port will have a number of integer
518     *  registers that need to be saved when an interrupt occurs or
519     *  when a context switch occurs at the end of an ISR.
520     */
521    uint32_t   special_interrupt_register;
522} CPU_Interrupt_frame;
523
524/**
525 *  This variable is optional.  It is used on CPUs on which it is difficult
526 *  to generate an "uninitialized" FP context.  It is filled in by
527 *  @ref _CPU_Initialize and copied into the task's FP context area during
528 *  @ref _CPU_Context_Initialize.
529 *
530 *  Port Specific Information:
531 *
532 *  XXX document implementation including references if appropriate
533 */
534SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
535
536/**
537 *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
538 *
539 *  On some CPUs, RTEMS supports a software managed interrupt stack.
540 *  This stack is allocated by the Interrupt Manager and the switch
541 *  is performed in @ref _ISR_Handler.  These variables contain pointers
542 *  to the lowest and highest addresses in the chunk of memory allocated
543 *  for the interrupt stack.  Since it is unknown whether the stack
544 *  grows up or down (in general), this give the CPU dependent
545 *  code the option of picking the version it wants to use.
546 *
547 *  @note These two variables are required if the macro
548 *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
549 *
550 *  Port Specific Information:
551 *
552 *  XXX document implementation including references if appropriate
553 */
554
555/**
556 *  @ingroup CPUInterrupt
557 *  This variable points to the lowest physical address of the interrupt
558 *  stack.
559 */
560SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
561
562/**
563 *  @ingroup CPUInterrupt
564 *  This variable points to the lowest physical address of the interrupt
565 *  stack.
566 */
567SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
568
569/*
570 *  Nothing prevents the porter from declaring more CPU specific variables.
571 *
572 *  Port Specific Information:
573 *
574 *  XXX document implementation including references if appropriate
575 */
576
577/* XXX: if needed, put more variables here */
578
579/**
580 *  @ingroup CPUContext
581 *  The size of the floating point context area.  On some CPUs this
582 *  will not be a "sizeof" because the format of the floating point
583 *  area is not defined -- only the size is.  This is usually on
584 *  CPUs with a "floating point save context" instruction.
585 *
586 *  Port Specific Information:
587 *
588 *  XXX document implementation including references if appropriate
589 */
590#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
591
592/**
593 *  Amount of extra stack (above minimum stack size) required by
594 *  MPCI receive server thread.  Remember that in a multiprocessor
595 *  system this thread must exist and be able to process all directives.
596 *
597 *  Port Specific Information:
598 *
599 *  XXX document implementation including references if appropriate
600 */
601#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
602
603/**
604 *  @ingroup CPUInterrupt
605 *  This defines the number of entries in the @ref _ISR_Vector_table managed
606 *  by RTEMS.
607 *
608 *  Port Specific Information:
609 *
610 *  XXX document implementation including references if appropriate
611 */
612#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
613
614/**
615 *  @ingroup CPUInterrupt
616 *  This defines the highest interrupt vector number for this port.
617 */
618#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
619
620/**
621 *  @ingroup CPUInterrupt
622 *  This is defined if the port has a special way to report the ISR nesting
623 *  level.  Most ports maintain the variable @a _ISR_Nest_level.
624 */
625#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
626
627/**
628 *  @ingroup CPUContext
629 *  Should be large enough to run all RTEMS tests.  This ensures
630 *  that a "reasonable" small application should not have any problems.
631 *
632 *  Port Specific Information:
633 *
634 *  XXX document implementation including references if appropriate
635 */
636#define CPU_STACK_MINIMUM_SIZE          (1024*4)
637
638/**
639 *  CPU's worst alignment requirement for data types on a byte boundary.  This
640 *  alignment does not take into account the requirements for the stack.
641 *
642 *  Port Specific Information:
643 *
644 *  XXX document implementation including references if appropriate
645 */
646#define CPU_ALIGNMENT              8
647
648/**
649 *  This number corresponds to the byte alignment requirement for the
650 *  heap handler.  This alignment requirement may be stricter than that
651 *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
652 *  common for the heap to follow the same alignment requirement as
653 *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
654 *  the heap, then this should be set to @ref CPU_ALIGNMENT.
655 *
656 *  @note  This does not have to be a power of 2 although it should be
657 *         a multiple of 2 greater than or equal to 2.  The requirement
658 *         to be a multiple of 2 is because the heap uses the least
659 *         significant field of the front and back flags to indicate
660 *         that a block is in use or free.  So you do not want any odd
661 *         length blocks really putting length data in that bit.
662 *
663 *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
664 *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
665 *         elements allocated from the heap meet all restrictions.
666 *
667 *  Port Specific Information:
668 *
669 *  XXX document implementation including references if appropriate
670 */
671#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
672
673/**
674 *  This number corresponds to the byte alignment requirement for memory
675 *  buffers allocated by the partition manager.  This alignment requirement
676 *  may be stricter than that for the data types alignment specified by
677 *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
678 *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
679 *  strict enough for the partition, then this should be set to
680 *  @ref CPU_ALIGNMENT.
681 *
682 *  @note  This does not have to be a power of 2.  It does have to
683 *         be greater or equal to than @ref CPU_ALIGNMENT.
684 *
685 *  Port Specific Information:
686 *
687 *  XXX document implementation including references if appropriate
688 */
689#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
690
691/**
692 *  This number corresponds to the byte alignment requirement for the
693 *  stack.  This alignment requirement may be stricter than that for the
694 *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
695 *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
696 *  set to 0.
697 *
698 *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
699 *
700 *  Port Specific Information:
701 *
702 *  XXX document implementation including references if appropriate
703 */
704#define CPU_STACK_ALIGNMENT        0
705
706/*
707 *  ISR handler macros
708 */
709
710/**
711 *  @ingroup CPUInterrupt
712 *  Support routine to initialize the RTEMS vector table after it is allocated.
713 *
714 *  Port Specific Information:
715 *
716 *  XXX document implementation including references if appropriate
717 */
718#define _CPU_Initialize_vectors()
719
720/**
721 *  @ingroup CPUInterrupt
722 *  Disable all interrupts for an RTEMS critical section.  The previous
723 *  level is returned in @a _isr_cookie.
724 *
725 *  @param[out] _isr_cookie will contain the previous level cookie
726 *
727 *  Port Specific Information:
728 *
729 *  XXX document implementation including references if appropriate
730 */
731#define _CPU_ISR_Disable( _isr_cookie ) \
732  { \
733    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
734  }
735
736/**
737 *  @ingroup CPUInterrupt
738 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
739 *  This indicates the end of an RTEMS critical section.  The parameter
740 *  @a _isr_cookie is not modified.
741 *
742 *  @param[in] _isr_cookie contain the previous level cookie
743 *
744 *  Port Specific Information:
745 *
746 *  XXX document implementation including references if appropriate
747 */
748#define _CPU_ISR_Enable( _isr_cookie )  \
749  { \
750  }
751
752/**
753 *  @ingroup CPUInterrupt
754 *  This temporarily restores the interrupt to @a _isr_cookie before immediately
755 *  disabling them again.  This is used to divide long RTEMS critical
756 *  sections into two or more parts.  The parameter @a _isr_cookie is not
757 *  modified.
758 *
759 *  @param[in] _isr_cookie contain the previous level cookie
760 *
761 *  Port Specific Information:
762 *
763 *  XXX document implementation including references if appropriate
764 */
765#define _CPU_ISR_Flash( _isr_cookie ) \
766  { \
767  }
768
769/**
770 *  @ingroup CPUInterrupt
771 *
772 *  This routine and @ref _CPU_ISR_Get_level
773 *  Map the interrupt level in task mode onto the hardware that the CPU
774 *  actually provides.  Currently, interrupt levels which do not
775 *  map onto the CPU in a generic fashion are undefined.  Someday,
776 *  it would be nice if these were "mapped" by the application
777 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
778 *  8 - 255 would be available for bsp/application specific meaning.
779 *  This could be used to manage a programmable interrupt controller
780 *  via the rtems_task_mode directive.
781 *
782 *  Port Specific Information:
783 *
784 *  XXX document implementation including references if appropriate
785 */
786#define _CPU_ISR_Set_level( new_level ) \
787  { \
788  }
789
790/**
791 *  @ingroup CPUInterrupt
792 *  Return the current interrupt disable level for this task in
793 *  the format used by the interrupt level portion of the task mode.
794 *
795 *  @note This routine usually must be implemented as a subroutine.
796 *
797 *  Port Specific Information:
798 *
799 *  XXX document implementation including references if appropriate
800 */
801uint32_t   _CPU_ISR_Get_level( void );
802
803/* end of ISR handler macros */
804
805/* Context handler macros */
806
807/**
808 *  @ingroup CPUContext
809 *  Initialize the context to a state suitable for starting a
810 *  task after a context restore operation.  Generally, this
811 *  involves:
812 *
813 *     - setting a starting address
814 *     - preparing the stack
815 *     - preparing the stack and frame pointers
816 *     - setting the proper interrupt level in the context
817 *     - initializing the floating point context
818 *
819 *  This routine generally does not set any unnecessary register
820 *  in the context.  The state of the "general data" registers is
821 *  undefined at task start time.
822 *
823 *  @param[in] _the_context is the context structure to be initialized
824 *  @param[in] _stack_base is the lowest physical address of this task's stack
825 *  @param[in] _size is the size of this task's stack
826 *  @param[in] _isr is the interrupt disable level
827 *  @param[in] _entry_point is the thread's entry point.  This is
828 *         always @a _Thread_Handler
829 *  @param[in] _is_fp is TRUE if the thread is to be a floating
830 *        point thread.  This is typically only used on CPUs where the
831 *        FPU may be easily disabled by software such as on the SPARC
832 *        where the PSR contains an enable FPU bit.
833 *
834 *  Port Specific Information:
835 *
836 *  XXX document implementation including references if appropriate
837 */
838#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
839                                 _isr, _entry_point, _is_fp ) \
840  { \
841  }
842
843/**
844 *  This routine is responsible for somehow restarting the currently
845 *  executing task.  If you are lucky, then all that is necessary
846 *  is restoring the context.  Otherwise, there will need to be
847 *  a special assembly routine which does something special in this
848 *  case.  For many ports, simply adding a label to the restore path
849 *  of @ref _CPU_Context_switch will work.  On other ports, it may be
850 *  possibly to load a few arguments and jump to the restore path. It will
851 *  not work if restarting self conflicts with the stack frame
852 *  assumptions of restoring a context.
853 *
854 *  Port Specific Information:
855 *
856 *  XXX document implementation including references if appropriate
857 */
858#define _CPU_Context_Restart_self( _the_context ) \
859   _CPU_Context_restore( (_the_context) );
860
861/**
862 *  @ingroup CPUContext
863 *  The purpose of this macro is to allow the initial pointer into
864 *  a floating point context area (used to save the floating point
865 *  context) to be at an arbitrary place in the floating point
866 *  context area.
867 *
868 *  This is necessary because some FP units are designed to have
869 *  their context saved as a stack which grows into lower addresses.
870 *  Other FP units can be saved by simply moving registers into offsets
871 *  from the base of the context area.  Finally some FP units provide
872 *  a "dump context" instruction which could fill in from high to low
873 *  or low to high based on the whim of the CPU designers.
874 *
875 *  @param[in] _base is the lowest physical address of the floating point
876 *         context area
877 *  @param[in] _offset is the offset into the floating point area
878 *
879 *  Port Specific Information:
880 *
881 *  XXX document implementation including references if appropriate
882 */
883#define _CPU_Context_Fp_start( _base, _offset ) \
884   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
885
886/**
887 *  This routine initializes the FP context area passed to it to.
888 *  There are a few standard ways in which to initialize the
889 *  floating point context.  The code included for this macro assumes
890 *  that this is a CPU in which a "initial" FP context was saved into
891 *  @a _CPU_Null_fp_context and it simply copies it to the destination
892 *  context passed to it.
893 *
894 *  Other floating point context save/restore models include:
895 *    -# not doing anything, and
896 *    -# putting a "null FP status word" in the correct place in the FP context.
897 *
898 *  @param[in] _destination is the floating point context area
899 *
900 *  Port Specific Information:
901 *
902 *  XXX document implementation including references if appropriate
903 */
904#define _CPU_Context_Initialize_fp( _destination ) \
905  { \
906   *(*(_destination)) = _CPU_Null_fp_context; \
907  }
908
909/* end of Context handler macros */
910
911/* Fatal Error manager macros */
912
913/**
914 *  This routine copies _error into a known place -- typically a stack
915 *  location or a register, optionally disables interrupts, and
916 *  halts/stops the CPU.
917 *
918 *  Port Specific Information:
919 *
920 *  XXX document implementation including references if appropriate
921 */
922#define _CPU_Fatal_halt( _error ) \
923  { \
924  }
925
926/* end of Fatal Error manager macros */
927
928/* Bitfield handler macros */
929
930/**
931 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
932 *
933 *  This set of routines are used to implement fast searches for
934 *  the most important ready task.
935 */
936
937/**
938 *  @ingroup CPUBitfield
939 *  This definition is set to TRUE if the port uses the generic bitfield
940 *  manipulation implementation.
941 */
942#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
943
944/**
945 *  @ingroup CPUBitfield
946 *  This definition is set to TRUE if the port uses the data tables provided
947 *  by the generic bitfield manipulation implementation.
948 *  This can occur when actually using the generic bitfield manipulation
949 *  implementation or when implementing the same algorithm in assembly
950 *  language for improved performance.  It is unlikely that a port will use
951 *  the data if it has a bitfield scan instruction.
952 */
953#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
954
955/**
956 *  @ingroup CPUBitfield
957 *  This routine sets @a _output to the bit number of the first bit
958 *  set in @a _value.  @a _value is of CPU dependent type
959 *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
960 *  wide although only the 16 least significant bits will be used.
961 *
962 *  There are a number of variables in using a "find first bit" type
963 *  instruction.
964 *
965 *    -# What happens when run on a value of zero?
966 *    -# Bits may be numbered from MSB to LSB or vice-versa.
967 *    -# The numbering may be zero or one based.
968 *    -# The "find first bit" instruction may search from MSB or LSB.
969 *
970 *  RTEMS guarantees that (1) will never happen so it is not a concern.
971 *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
972 *  @ref _CPU_Priority_bits_index.  These three form a set of routines
973 *  which must logically operate together.  Bits in the _value are
974 *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
975 *  The basic major and minor values calculated by @ref _Priority_Major
976 *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
977 *  to properly range between the values returned by the "find first bit"
978 *  instruction.  This makes it possible for @ref _Priority_Get_highest to
979 *  calculate the major and directly index into the minor table.
980 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
981 *  is the first bit found.
982 *
983 *  This entire "find first bit" and mapping process depends heavily
984 *  on the manner in which a priority is broken into a major and minor
985 *  components with the major being the 4 MSB of a priority and minor
986 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
987 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
988 *  to the lowest priority.
989 *
990 *  If your CPU does not have a "find first bit" instruction, then
991 *  there are ways to make do without it.  Here are a handful of ways
992 *  to implement this in software:
993 *
994@verbatim
995      - a series of 16 bit test instructions
996      - a "binary search using if's"
997      - _number = 0
998        if _value > 0x00ff
999          _value >>=8
1000          _number = 8;
1001
1002        if _value > 0x0000f
1003          _value >=8
1004          _number += 4
1005
1006        _number += bit_set_table[ _value ]
1007@endverbatim
1008
1009 *    where bit_set_table[ 16 ] has values which indicate the first
1010 *      bit set
1011 *
1012 *  @param[in] _value is the value to be scanned
1013 *  @param[in] _output is the first bit set
1014 *
1015 *  Port Specific Information:
1016 *
1017 *  XXX document implementation including references if appropriate
1018 */
1019
1020#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1021#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1022  { \
1023    (_output) = 0;   /* do something to prevent warnings */ \
1024  }
1025#endif
1026
1027/* end of Bitfield handler macros */
1028
1029/**
1030 *  This routine builds the mask which corresponds to the bit fields
1031 *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1032 *  for that routine.
1033 *
1034 *  Port Specific Information:
1035 *
1036 *  XXX document implementation including references if appropriate
1037 */
1038#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1039
1040#define _CPU_Priority_Mask( _bit_number ) \
1041  ( 1 << (_bit_number) )
1042
1043#endif
1044
1045/**
1046 *  @ingroup CPUBitfield
1047 *  This routine translates the bit numbers returned by
1048 *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1049 *  a major or minor component of a priority.  See the discussion
1050 *  for that routine.
1051 *
1052 *  @param[in] _priority is the major or minor number to translate
1053 *
1054 *  Port Specific Information:
1055 *
1056 *  XXX document implementation including references if appropriate
1057 */
1058#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1059
1060#define _CPU_Priority_bits_index( _priority ) \
1061  (_priority)
1062
1063#endif
1064
1065/* end of Priority handler macros */
1066
1067/* functions */
1068
1069/**
1070 *  This routine performs CPU dependent initialization.
1071 *
1072 *  Port Specific Information:
1073 *
1074 *  XXX document implementation including references if appropriate
1075 */
1076void _CPU_Initialize(void);
1077
1078/**
1079 *  @ingroup CPUInterrupt
1080 *  This routine installs a "raw" interrupt handler directly into the
1081 *  processor's vector table.
1082 *
1083 *  @param[in] vector is the vector number
1084 *  @param[in] new_handler is the raw ISR handler to install
1085 *  @param[in] old_handler is the previously installed ISR Handler
1086 *
1087 *  Port Specific Information:
1088 *
1089 *  XXX document implementation including references if appropriate
1090 */
1091void _CPU_ISR_install_raw_handler(
1092  uint32_t    vector,
1093  proc_ptr    new_handler,
1094  proc_ptr   *old_handler
1095);
1096
1097/**
1098 *  @ingroup CPUInterrupt
1099 *  This routine installs an interrupt vector.
1100 *
1101 *  @param[in] vector is the vector number
1102 *  @param[in] new_handler is the RTEMS ISR handler to install
1103 *  @param[in] old_handler is the previously installed ISR Handler
1104 *
1105 *  Port Specific Information:
1106 *
1107 *  XXX document implementation including references if appropriate
1108 */
1109void _CPU_ISR_install_vector(
1110  uint32_t    vector,
1111  proc_ptr    new_handler,
1112  proc_ptr   *old_handler
1113);
1114
1115/**
1116 *  @ingroup CPUInterrupt
1117 *  This routine installs the hardware interrupt stack pointer.
1118 *
1119 *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1120 *         is TRUE.
1121 *
1122 *  Port Specific Information:
1123 *
1124 *  XXX document implementation including references if appropriate
1125 */
1126void _CPU_Install_interrupt_stack( void );
1127
1128/**
1129 *  This routine is the CPU dependent IDLE thread body.
1130 *
1131 *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1132 *         is TRUE.
1133 *
1134 *  Port Specific Information:
1135 *
1136 *  XXX document implementation including references if appropriate
1137 */
1138void *_CPU_Thread_Idle_body( uintptr_t ignored );
1139
1140/**
1141 *  @ingroup CPUContext
1142 *  This routine switches from the run context to the heir context.
1143 *
1144 *  @param[in] run points to the context of the currently executing task
1145 *  @param[in] heir points to the context of the heir task
1146 *
1147 *  Port Specific Information:
1148 *
1149 *  XXX document implementation including references if appropriate
1150 */
1151void _CPU_Context_switch(
1152  Context_Control  *run,
1153  Context_Control  *heir
1154);
1155
1156/**
1157 *  @ingroup CPUContext
1158 *  This routine is generally used only to restart self in an
1159 *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1160 *
1161 *  @param[in] new_context points to the context to be restored.
1162 *
1163 *  @note May be unnecessary to reload some registers.
1164 *
1165 *  Port Specific Information:
1166 *
1167 *  XXX document implementation including references if appropriate
1168 */
1169void _CPU_Context_restore(
1170  Context_Control *new_context
1171);
1172
1173/**
1174 *  @ingroup CPUContext
1175 *  This routine saves the floating point context passed to it.
1176 *
1177 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1178 *  point context area
1179 *
1180 *  @return on output @a *fp_context_ptr will contain the address that
1181 *  should be used with @ref _CPU_Context_restore_fp to restore this context.
1182 *
1183 *  Port Specific Information:
1184 *
1185 *  XXX document implementation including references if appropriate
1186 */
1187void _CPU_Context_save_fp(
1188  Context_Control_fp **fp_context_ptr
1189);
1190
1191/**
1192 *  @ingroup CPUContext
1193 *  This routine restores the floating point context passed to it.
1194 *
1195 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1196 *  point context area to restore
1197 *
1198 *  @return on output @a *fp_context_ptr will contain the address that
1199 *  should be used with @ref _CPU_Context_save_fp to save this context.
1200 *
1201 *  Port Specific Information:
1202 *
1203 *  XXX document implementation including references if appropriate
1204 */
1205void _CPU_Context_restore_fp(
1206  Context_Control_fp **fp_context_ptr
1207);
1208
[caee146]1209typedef struct {
1210  uint32_t trap;
1211  CPU_Interrupt_frame *isf;
1212} CPU_Exception_frame;
1213
1214static inline void _CPU_Exception_frame_print(
1215  const CPU_Exception_frame *frame
1216)
1217{
1218  /* printk( "Printing exception frame\n" ); */
1219}
[abb18dc]1220/**
1221 *  @ingroup CPUEndian
1222 *  The following routine swaps the endian format of an unsigned int.
1223 *  It must be static because it is referenced indirectly.
1224 *
1225 *  This version will work on any processor, but if there is a better
1226 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1227 *
1228 *     swap least significant two bytes with 16-bit rotate
1229 *     swap upper and lower 16-bits
1230 *     swap most significant two bytes with 16-bit rotate
1231 *
1232 *  Some CPUs have special instructions which swap a 32-bit quantity in
1233 *  a single instruction (e.g. i486).  It is probably best to avoid
1234 *  an "endian swapping control bit" in the CPU.  One good reason is
1235 *  that interrupts would probably have to be disabled to ensure that
1236 *  an interrupt does not try to access the same "chunk" with the wrong
1237 *  endian.  Another good reason is that on some CPUs, the endian bit
1238 *  endianness for ALL fetches -- both code and data -- so the code
1239 *  will be fetched incorrectly.
1240 *
1241 *  @param[in] value is the value to be swapped
1242 *  @return the value after being endian swapped
1243 *
1244 *  Port Specific Information:
1245 *
1246 *  XXX document implementation including references if appropriate
1247 */
1248static inline uint32_t CPU_swap_u32(
1249  uint32_t value
1250)
1251{
1252  uint32_t byte1, byte2, byte3, byte4, swapped;
1253
1254  byte4 = (value >> 24) & 0xff;
1255  byte3 = (value >> 16) & 0xff;
1256  byte2 = (value >> 8)  & 0xff;
1257  byte1 =  value        & 0xff;
1258
1259  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1260  return swapped;
1261}
1262
1263/**
1264 *  @ingroup CPUEndian
1265 *  This routine swaps a 16 bir quantity.
1266 *
1267 *  @param[in] value is the value to be swapped
1268 *  @return the value after being endian swapped
1269 */
1270#define CPU_swap_u16( value ) \
1271  (((value&0xff) << 8) | ((value >> 8)&0xff))
1272
[aebb1ca]1273/*
1274 *  SMP Support
1275 */
1276void __SMP_cpu_swap( 
1277  uint32_t *a,
1278  uint32_t *value,
1279  uint32_t *prev
1280);
1281#define SMP_CPU_SWAP( _address, _value, _previous ) \
1282  do { \
1283    volatile unsigned int *_a = (volatile unsigned int *)_address; \
1284    _previous = *(_a); \
1285    *(_a) = _value; \
1286  } while (0)
1287
1288#define _CPU_Context_switch_to_first_task_smp(_ignored)
1289
[abb18dc]1290#ifdef __cplusplus
1291}
1292#endif
1293
1294#endif
Note: See TracBrowser for help on using the repository browser.