1 | /*- |
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2 | * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org> |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * 1. Redistributions of source code must retain the above copyright |
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9 | * notice, this list of conditions and the following disclaimer. |
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10 | * 2. Redistributions in binary form must reproduce the above copyright |
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11 | * notice, this list of conditions and the following disclaimer in the |
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12 | * documentation and/or other materials provided with the distribution. |
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13 | * |
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14 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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16 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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17 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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18 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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19 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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20 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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21 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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22 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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23 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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24 | * SUCH DAMAGE. |
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25 | * |
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26 | */ |
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27 | #include <machine/rtems-bsd-kernel-space.h> |
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28 | |
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29 | #include <sys/cdefs.h> |
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30 | __FBSDID("$FreeBSD$"); |
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31 | |
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32 | #include <sys/stdint.h> |
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33 | #include <sys/stddef.h> |
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34 | #include <sys/param.h> |
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35 | #include <sys/queue.h> |
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36 | #include <sys/types.h> |
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37 | #include <sys/systm.h> |
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38 | #include <sys/kernel.h> |
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39 | #include <sys/bus.h> |
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40 | #include <sys/module.h> |
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41 | #include <sys/lock.h> |
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42 | #include <sys/mutex.h> |
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43 | #include <sys/condvar.h> |
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44 | #include <sys/sysctl.h> |
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45 | #include <sys/rman.h> |
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46 | #include <sys/sx.h> |
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47 | #include <rtems/bsd/sys/unistd.h> |
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48 | #include <sys/callout.h> |
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49 | #include <sys/malloc.h> |
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50 | #include <sys/priv.h> |
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51 | |
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52 | #include <sys/kdb.h> |
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53 | |
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54 | #include <bsp.h> |
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55 | #if defined(LIBBSP_ARM_LPC32XX_BSP_H) |
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56 | |
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57 | #ifdef BSP_USB_OTG_TRANSCEIVER_I2C_ADDR |
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58 | #include <dev/usb/usb_otg_transceiver.h> |
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59 | #endif /* BSP_USB_OTG_TRANSCEIVER_I2C_ADDR */ |
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60 | |
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61 | #include <dev/usb/usb.h> |
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62 | #include <dev/usb/usbdi.h> |
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63 | |
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64 | #include <dev/usb/usb_core.h> |
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65 | #include <dev/usb/usb_busdma.h> |
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66 | #include <dev/usb/usb_process.h> |
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67 | #include <dev/usb/usb_util.h> |
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68 | |
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69 | #include <dev/usb/usb_controller.h> |
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70 | #include <dev/usb/usb_bus.h> |
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71 | #include <dev/usb/controller/ohci.h> |
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72 | #include <dev/usb/controller/ohcireg.h> |
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73 | |
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74 | #include <arm/lpc/lpcreg.h> |
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75 | #include <arm/lpc/lpcvar.h> |
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76 | |
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77 | #define I2C_START_BIT (1 << 8) |
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78 | #define I2C_STOP_BIT (1 << 9) |
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79 | #define I2C_READ 0x01 |
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80 | #define I2C_WRITE 0x00 |
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81 | #define DUMMY_BYTE 0x55 |
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82 | |
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83 | #define lpc_otg_read_4(_sc, _reg) \ |
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84 | bus_space_read_4(_sc->sc_io_tag, _sc->sc_io_hdl, _reg) |
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85 | #define lpc_otg_write_4(_sc, _reg, _value) \ |
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86 | bus_space_write_4(_sc->sc_io_tag, _sc->sc_io_hdl, _reg, _value) |
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87 | #define lpc_otg_wait_write_4(_sc, _wreg, _sreg, _value) \ |
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88 | do { \ |
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89 | lpc_otg_write_4(_sc, _wreg, _value); \ |
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90 | while ((lpc_otg_read_4(_sc, _sreg) & _value) != _value); \ |
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91 | } while (0); |
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92 | |
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93 | static int lpc_ohci_probe(device_t dev); |
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94 | static int lpc_ohci_attach(device_t dev); |
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95 | static int lpc_ohci_detach(device_t dev); |
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96 | |
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97 | static void lpc_usb_module_enable(device_t dev, struct ohci_softc *); |
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98 | static void lpc_usb_module_disable(device_t dev, struct ohci_softc *); |
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99 | static void lpc_usb_pin_config(device_t dev, struct ohci_softc *); |
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100 | static void lpc_usb_host_clock_enable(device_t dev, struct ohci_softc *); |
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101 | static void lpc_otg_status_and_control(device_t dev, struct ohci_softc *); |
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102 | static rtems_interval lpc_usb_timeout_init(void); |
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103 | static bool lpc_usb_timeout_not_expired(rtems_interval start); |
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104 | static int lpc_otg_clk_ctrl(device_t dev, struct ohci_softc *sc, uint32_t otg_clk_ctrl); |
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105 | static int lpc_otg_i2c_wait_for_receive_fifo_not_empty(struct ohci_softc *sc); |
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106 | static int lpc_otg_i2c_wait_for_transaction_done(struct ohci_softc *sc); |
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107 | static int lpc_otg_i2c_read(const struct usb_otg_transceiver *self, uint8_t reg_addr, uint8_t *value); |
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108 | static int lpc_otg_i2c_write(const struct usb_otg_transceiver *self, uint8_t reg_addr, uint8_t value); |
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109 | |
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110 | static int |
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111 | lpc_ohci_probe(device_t dev) |
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112 | { |
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113 | |
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114 | device_set_desc(dev, "LPC32x0 USB OHCI controller"); |
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115 | return (BUS_PROBE_DEFAULT); |
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116 | } |
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117 | |
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118 | static int |
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119 | lpc_ohci_attach(device_t dev) |
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120 | { |
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121 | struct ohci_softc *sc = device_get_softc(dev); |
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122 | int err; |
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123 | int eno; |
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124 | int rid; |
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125 | int i = 0; |
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126 | uint32_t usbctrl; |
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127 | uint32_t otgstatus; |
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128 | |
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129 | sc->sc_bus.parent = dev; |
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130 | sc->sc_bus.devices = sc->sc_devices; |
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131 | sc->sc_bus.devices_max = OHCI_MAX_DEVICES; |
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132 | sc->sc_bus.dma_bits = 32; |
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133 | |
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134 | if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev), |
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135 | &ohci_iterate_hw_softc)) |
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136 | return (ENOMEM); |
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137 | |
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138 | rid = 0; |
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139 | sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); |
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140 | if (!sc->sc_io_res) { |
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141 | device_printf(dev, "cannot map OHCI register space\n"); |
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142 | goto fail; |
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143 | } |
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144 | |
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145 | sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); |
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146 | sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); |
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147 | sc->sc_io_size = rman_get_size(sc->sc_io_res); |
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148 | |
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149 | rid = 0; |
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150 | sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); |
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151 | if (sc->sc_irq_res == NULL) { |
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152 | device_printf(dev, "cannot allocate interrupt\n"); |
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153 | goto fail; |
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154 | } |
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155 | |
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156 | sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); |
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157 | if (!(sc->sc_bus.bdev)) |
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158 | goto fail; |
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159 | |
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160 | device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); |
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161 | strlcpy(sc->sc_vendor, "NXP", sizeof(sc->sc_vendor)); |
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162 | |
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163 | err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, |
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164 | NULL, (void *)ohci_interrupt, sc, &sc->sc_intr_hdl); |
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165 | if (err) { |
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166 | sc->sc_intr_hdl = NULL; |
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167 | goto fail; |
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168 | } |
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169 | |
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170 | lpc_usb_module_enable(dev, sc); |
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171 | |
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172 | eno = lpc_otg_clk_ctrl(dev, sc, LPC_OTG_CLOCK_CTRL_AHB_EN | LPC_OTG_CLOCK_CTRL_I2C_EN); |
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173 | if (eno != 0) { |
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174 | goto fail; |
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175 | } |
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176 | |
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177 | lpc_usb_pin_config(dev, sc); |
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178 | |
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179 | #ifdef BSP_USB_OTG_TRANSCEIVER_I2C_ADDR |
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180 | sc->sc_otg_trans.read = lpc_otg_i2c_read; |
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181 | sc->sc_otg_trans.write = lpc_otg_i2c_write; |
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182 | sc->sc_otg_trans.i2c_addr = BSP_USB_OTG_TRANSCEIVER_I2C_ADDR; |
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183 | sc->sc_otg_trans.softc = sc; |
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184 | eno = usb_otg_transceiver_init(&sc->sc_otg_trans); |
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185 | if (eno != 0) { |
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186 | goto fail; |
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187 | } |
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188 | |
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189 | #ifdef BSP_USB_OTG_TRANSCEIVER_DUMP |
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190 | usb_otg_transceiver_dump(&sc->sc_otg_trans); |
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191 | #endif /* BSP_USB_OTG_TRANSCEIVER_DUMP */ |
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192 | |
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193 | eno = usb_otg_transceiver_resume(&sc->sc_otg_trans); |
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194 | if (eno != 0) { |
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195 | goto fail; |
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196 | } |
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197 | #endif /* BSP_USB_OTG_TRANSCEIVER_I2C_ADDR */ |
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198 | |
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199 | lpc_usb_host_clock_enable(dev, sc); |
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200 | |
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201 | eno = lpc_otg_clk_ctrl( dev, sc, |
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202 | LPC_OTG_CLOCK_CTRL_AHB_EN | LPC_OTG_CLOCK_CTRL_HOST_EN |
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203 | | LPC_OTG_CLOCK_CTRL_I2C_EN | LPC_OTG_CLOCK_CTRL_OTG_EN |
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204 | ); |
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205 | if (eno != 0) { |
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206 | goto fail; |
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207 | } |
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208 | |
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209 | lpc_otg_status_and_control(dev, sc); |
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210 | |
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211 | #if defined(BSP_USB_OTG_TRANSCEIVER_I2C_ADDR) \ |
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212 | && defined(BSP_USB_OTG_TRANSCEIVER_VBUS) |
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213 | eno = usb_otg_transceiver_set_vbus( |
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214 | &sc->sc_otg_trans, |
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215 | BSP_USB_OTG_TRANSCEIVER_VBUS |
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216 | ); |
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217 | if (eno != 0) { |
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218 | goto fail; |
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219 | } |
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220 | #endif /* defined(BSP_USB_OTG_TRANSCEIVER_I2C_ADDR) |
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221 | && defined(BSP_USB_OTG_TRANSCEIVER_VBUS) */ |
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222 | |
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223 | #if defined(BSP_USB_OTG_TRANSCEIVER_I2C_ADDR) \ |
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224 | && defined(BSP_USB_OTG_TRANSCEIVER_DUMP) |
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225 | usb_otg_transceiver_dump(&sc->sc_otg_trans); |
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226 | #endif /* defined(BSP_USB_OTG_TRANSCEIVER_I2C_ADDR) |
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227 | && defined(BSP_USB_OTG_TRANSCEIVER_DUMP) */ |
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228 | |
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229 | eno = lpc_otg_clk_ctrl(dev, sc, LPC_OTG_CLOCK_CTRL_AHB_EN | LPC_OTG_CLOCK_CTRL_HOST_EN); |
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230 | if (eno != 0) { |
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231 | goto fail; |
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232 | } |
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233 | |
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234 | err = ohci_init(sc); |
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235 | if (err) |
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236 | goto fail; |
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237 | |
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238 | err = device_probe_and_attach(sc->sc_bus.bdev); |
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239 | if (err) |
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240 | goto fail; |
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241 | |
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242 | return (0); |
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243 | |
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244 | fail: |
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245 | if (sc->sc_intr_hdl) |
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246 | bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr_hdl); |
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247 | if (sc->sc_irq_res) |
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248 | bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); |
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249 | if (sc->sc_io_res) |
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250 | bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_io_res); |
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251 | |
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252 | return (ENXIO); |
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253 | } |
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254 | |
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255 | static int |
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256 | lpc_ohci_detach(device_t dev) |
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257 | { |
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258 | return (0); |
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259 | } |
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260 | |
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261 | static void lpc_usb_module_enable(device_t dev, struct ohci_softc *sc) |
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262 | { |
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263 | uint32_t usbctrl; |
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264 | |
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265 | lpc_pwr_write(dev, LPC_CLKPWR_USBDIV_CTRL, 0xc); |
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266 | lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, |
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267 | LPC_CLKPWR_USB_CTRL_SLAVE_HCLK | |
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268 | LPC_CLKPWR_USB_CTRL_BUSKEEPER | |
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269 | LPC_CLKPWR_USB_CTRL_CLK_EN1 | |
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270 | LPC_CLKPWR_USB_CTRL_PLL_PDOWN | |
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271 | LPC_CLKPWR_USB_CTRL_POSTDIV(1) | |
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272 | LPC_CLKPWR_USB_CTRL_PREDIV(0) | |
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273 | LPC_CLKPWR_USB_CTRL_FDBKDIV(192)); |
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274 | do { |
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275 | usbctrl = lpc_pwr_read(dev, LPC_CLKPWR_USB_CTRL); |
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276 | } while ((usbctrl & LPC_CLKPWR_USB_CTRL_PLL_LOCK) == 0); |
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277 | |
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278 | usbctrl = lpc_pwr_read(dev, LPC_CLKPWR_USB_CTRL); |
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279 | usbctrl |= LPC_CLKPWR_USB_CTRL_CLK_EN2; |
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280 | lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl); |
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281 | } |
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282 | |
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283 | static void lpc_usb_module_disable(device_t dev, struct ohci_softc *sc) |
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284 | { |
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285 | lpc_otg_write_4(sc, LPC_OTG_CLOCK_CTRL, 0x0); |
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286 | lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, LPC_CLKPWR_USB_CTRL_BUSKEEPER); |
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287 | } |
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288 | |
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289 | static void lpc_usb_pin_config(device_t dev, struct ohci_softc *sc) |
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290 | { |
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291 | } |
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292 | |
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293 | static void lpc_usb_host_clock_enable(device_t dev, struct ohci_softc *sc) |
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294 | { |
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295 | uint32_t usbctrl; |
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296 | |
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297 | usbctrl = lpc_pwr_read(dev, LPC_CLKPWR_USB_CTRL); |
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298 | usbctrl |= LPC_CLKPWR_USB_CTRL_HOST_NEED_CLK_EN; |
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299 | lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl); |
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300 | } |
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301 | |
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302 | static void lpc_otg_status_and_control(device_t dev, struct ohci_softc *sc) |
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303 | { |
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304 | lpc_otg_write_4(sc, LPC_OTG_STATUS, 0x1); |
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305 | } |
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306 | |
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307 | static rtems_interval lpc_usb_timeout_init(void) |
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308 | { |
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309 | return rtems_clock_get_ticks_since_boot(); |
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310 | } |
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311 | |
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312 | static bool lpc_usb_timeout_not_expired(rtems_interval start) |
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313 | { |
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314 | rtems_interval elapsed = rtems_clock_get_ticks_since_boot() - start; |
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315 | |
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316 | return elapsed < (rtems_clock_get_ticks_per_second() / 10); |
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317 | } |
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318 | |
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319 | static int lpc_otg_clk_ctrl(device_t dev, struct ohci_softc *sc, uint32_t otg_clk_ctrl) |
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320 | { |
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321 | rtems_interval start; |
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322 | bool not_ok; |
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323 | |
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324 | lpc_otg_write_4(sc, LPC_OTG_CLOCK_CTRL, otg_clk_ctrl); |
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325 | |
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326 | start = lpc_usb_timeout_init(); |
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327 | while ( |
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328 | (not_ok = (lpc_otg_read_4(sc, LPC_OTG_CLOCK_STATUS) & otg_clk_ctrl) != otg_clk_ctrl) |
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329 | && lpc_usb_timeout_not_expired(start) |
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330 | ) { |
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331 | /* Wait */ |
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332 | } |
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333 | |
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334 | return not_ok ? EIO : 0; |
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335 | } |
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336 | |
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337 | static int lpc_otg_i2c_wait_for_receive_fifo_not_empty(struct ohci_softc *sc) |
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338 | { |
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339 | rtems_interval start; |
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340 | bool not_ok; |
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341 | |
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342 | start = lpc_usb_timeout_init(); |
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343 | while ( |
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344 | (not_ok = (lpc_otg_read_4(sc, LPC_OTG_I2C_STATUS) & LPC_OTG_I2C_STATUS_RFE) != 0) |
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345 | && lpc_usb_timeout_not_expired(start) |
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346 | ) { |
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347 | /* Wait */ |
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348 | } |
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349 | |
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350 | return not_ok ? EIO : 0; |
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351 | } |
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352 | |
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353 | static int lpc_otg_i2c_wait_for_transaction_done(struct ohci_softc *sc) |
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354 | { |
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355 | rtems_interval start; |
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356 | bool not_ok; |
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357 | |
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358 | start = lpc_usb_timeout_init(); |
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359 | while ( |
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360 | (not_ok = (lpc_otg_read_4(sc, LPC_OTG_I2C_STATUS) & LPC_OTG_I2C_STATUS_TDI) == 0) |
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361 | && lpc_usb_timeout_not_expired(start) |
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362 | ) { |
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363 | /* Wait */ |
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364 | } |
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365 | |
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366 | return not_ok ? EIO : 0; |
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367 | } |
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368 | |
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369 | static int lpc_otg_i2c_read(const struct usb_otg_transceiver *self, uint8_t reg_addr, uint8_t *value) |
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370 | { |
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371 | struct ohci_softc *sc = (struct ohci_softc *)self->softc; |
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372 | int eno; |
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373 | |
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374 | lpc_otg_write_4(sc, LPC_OTG_I2C_CTRL, LPC_OTG_I2C_CTRL_SRST); |
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375 | lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, self->i2c_addr | I2C_START_BIT); |
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376 | lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, reg_addr); |
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377 | lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, self->i2c_addr | I2C_START_BIT | I2C_READ); |
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378 | lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, I2C_STOP_BIT); |
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379 | |
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380 | eno = lpc_otg_i2c_wait_for_receive_fifo_not_empty(sc); |
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381 | |
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382 | if (eno == 0) { |
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383 | *value = (uint8_t)lpc_otg_read_4(sc, LPC_OTG_I2C_TXRX); |
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384 | } |
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385 | |
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386 | return eno; |
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387 | } |
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388 | |
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389 | static int lpc_otg_i2c_write(const struct usb_otg_transceiver *self, uint8_t reg_addr, uint8_t value) |
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390 | { |
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391 | struct ohci_softc *sc = (struct ohci_softc *)self->softc; |
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392 | int eno; |
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393 | |
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394 | lpc_otg_write_4(sc, LPC_OTG_I2C_CTRL, LPC_OTG_I2C_CTRL_SRST); |
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395 | lpc_otg_write_4(sc, LPC_OTG_I2C_STATUS, LPC_OTG_I2C_STATUS_TDI); |
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396 | lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, self->i2c_addr | I2C_START_BIT); |
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397 | lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, reg_addr); |
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398 | lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, value | I2C_STOP_BIT); |
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399 | |
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400 | eno = lpc_otg_i2c_wait_for_transaction_done(sc); |
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401 | |
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402 | return eno; |
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403 | } |
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404 | |
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405 | static int ohci_lpc_otg_transceiver_suspend(device_t dev, struct ohci_softc *sc) |
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406 | { |
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407 | int eno = 0; |
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408 | |
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409 | #ifdef BSP_USB_OTG_TRANSCEIVER_I2C_ADDR |
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410 | if (eno == 0) { |
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411 | eno = lpc_otg_clk_ctrl( dev, sc, |
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412 | LPC_OTG_CLOCK_CTRL_AHB_EN | LPC_OTG_CLOCK_CTRL_HOST_EN | LPC_OTG_CLOCK_CTRL_I2C_EN |
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413 | ); |
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414 | } |
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415 | |
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416 | if (eno == 0) { |
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417 | eno = usb_otg_transceiver_suspend(&sc->sc_otg_trans); |
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418 | } |
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419 | |
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420 | #ifdef BSP_USB_OTG_TRANSCEIVER_DUMP |
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421 | usb_otg_transceiver_dump(&sc->sc_otg_trans); |
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422 | #endif /* BSP_USB_OTG_TRANSCEIVER_DUMP */ |
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423 | |
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424 | if (eno == 0) { |
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425 | eno = lpc_otg_clk_ctrl(dev, sc, LPC_OTG_CLOCK_CTRL_AHB_EN | LPC_OTG_CLOCK_CTRL_HOST_EN); |
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426 | } |
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427 | #endif /* BSP_USB_OTG_TRANSCEIVER_I2C_ADDR */ |
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428 | |
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429 | return eno; |
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430 | } |
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431 | |
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432 | static int |
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433 | lpc_ohci_resume(device_t dev) |
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434 | { |
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435 | struct ohci_softc *sc = device_get_softc(dev); |
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436 | int eno = 0; |
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437 | |
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438 | #ifdef BSP_USB_OTG_TRANSCEIVER_I2C_ADDR |
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439 | if (eno == 0) { |
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440 | eno = lpc_otg_clk_ctrl( dev, sc, |
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441 | LPC_OTG_CLOCK_CTRL_AHB_EN | LPC_OTG_CLOCK_CTRL_HOST_EN | LPC_OTG_CLOCK_CTRL_I2C_EN |
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442 | ); |
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443 | } |
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444 | |
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445 | if (eno == 0) { |
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446 | eno = usb_otg_transceiver_resume(&sc->sc_otg_trans); |
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447 | } |
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448 | |
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449 | #ifdef BSP_USB_OTG_TRANSCEIVER_VBUS |
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450 | if (eno == 0) { |
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451 | eno = usb_otg_transceiver_set_vbus( |
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452 | &sc->sc_otg_trans, |
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453 | BSP_USB_OTG_TRANSCEIVER_VBUS |
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454 | ); |
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455 | } |
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456 | #endif /* BSP_USB_OTG_TRANSCEIVER_VBUS */ |
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457 | |
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458 | #ifdef BSP_USB_OTG_TRANSCEIVER_DUMP |
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459 | usb_otg_transceiver_dump(&sc->sc_otg_trans); |
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460 | #endif /* BSP_USB_OTG_TRANSCEIVER_DUMP */ |
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461 | |
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462 | if (eno == 0) { |
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463 | eno = lpc_otg_clk_ctrl(dev, sc, LPC_OTG_CLOCK_CTRL_AHB_EN | LPC_OTG_CLOCK_CTRL_HOST_EN); |
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464 | } |
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465 | #endif /* BSP_USB_OTG_TRANSCEIVER_I2C_ADDR */ |
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466 | |
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467 | if (eno == 0) { |
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468 | eno = bus_generic_resume(dev); |
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469 | } |
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470 | |
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471 | return (eno); |
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472 | } |
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473 | |
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474 | static device_method_t lpc_ohci_methods[] = { |
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475 | /* Device interface */ |
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476 | DEVMETHOD(device_probe, lpc_ohci_probe), |
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477 | DEVMETHOD(device_attach, lpc_ohci_attach), |
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478 | DEVMETHOD(device_detach, lpc_ohci_detach), |
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479 | DEVMETHOD(device_suspend, bus_generic_suspend), |
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480 | DEVMETHOD(device_resume, lpc_ohci_resume), |
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481 | DEVMETHOD(device_shutdown, bus_generic_shutdown), |
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482 | |
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483 | /* Bus interface */ |
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484 | DEVMETHOD(bus_print_child, bus_generic_print_child), |
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485 | { 0, 0 } |
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486 | }; |
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487 | |
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488 | static driver_t lpc_ohci_driver = { |
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489 | "ohci", |
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490 | lpc_ohci_methods, |
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491 | sizeof(struct ohci_softc), |
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492 | }; |
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493 | |
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494 | static devclass_t lpc_ohci_devclass; |
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495 | |
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496 | DRIVER_MODULE(ohci, nexus, lpc_ohci_driver, lpc_ohci_devclass, 0, 0); |
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497 | MODULE_DEPEND(ohci, usb, 1, 1, 1); |
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498 | |
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499 | #endif /* defined(LIBBSP_ARM_LPC32XX_BSP_H) */ |
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