1 | /* |
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2 | * Copyright (c) 2009, 2013 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * Redistribution and use in source and binary forms, with or without |
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11 | * modification, are permitted provided that the following conditions |
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12 | * are met: |
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13 | * 1. Redistributions of source code must retain the above copyright |
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14 | * notice, this list of conditions and the following disclaimer. |
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15 | * 2. Redistributions in binary form must reproduce the above copyright |
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16 | * notice, this list of conditions and the following disclaimer in the |
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17 | * documentation and/or other materials provided with the distribution. |
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18 | * |
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19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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28 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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29 | * SUCH DAMAGE. |
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30 | */ |
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31 | |
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32 | #include <machine/rtems-bsd-kernel-space.h> |
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33 | #include <machine/rtems-bsd-support.h> |
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34 | |
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35 | #include <bsp.h> |
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36 | |
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37 | #include <errno.h> |
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38 | |
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39 | #if defined(LIBBSP_ARM_LPC24XX_BSP_H) |
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40 | |
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41 | #include <bsp/irq.h> |
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42 | #include <bsp/io.h> |
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43 | #include <bsp/lpc24xx.h> |
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44 | |
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45 | #define LPC_USB_OHCI_BASE USBHC_BASE_ADDR |
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46 | |
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47 | #define LPC_USB_I2C_BASE USBOTG_I2C_BASE_ADDR |
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48 | |
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49 | #define LPC_OTG_CLK_CTRL OTG_CLK_CTRL |
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50 | |
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51 | #define LPC_OTG_CLK_STAT OTG_CLK_STAT |
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52 | |
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53 | #define LPC_USB_OHCI_IRQ LPC24XX_IRQ_USB |
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54 | |
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55 | static void lpc_usb_module_enable(void) |
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56 | { |
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57 | rtems_status_code sc; |
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58 | |
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59 | sc = lpc24xx_module_enable( |
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60 | LPC24XX_MODULE_USB, |
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61 | LPC24XX_MODULE_PCLK_DEFAULT |
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62 | ); |
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63 | BSD_ASSERT_SC(sc); |
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64 | } |
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65 | |
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66 | static void lpc_usb_module_disable(void) |
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67 | { |
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68 | rtems_status_code sc; |
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69 | |
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70 | sc = lpc24xx_module_disable(LPC24XX_MODULE_USB); |
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71 | BSD_ASSERT_SC(sc); |
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72 | } |
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73 | |
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74 | static void lpc_usb_pin_config(void) |
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75 | { |
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76 | static const lpc24xx_pin_range pins [] = { |
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77 | LPC24XX_PIN_USB_D_PLUS_1, |
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78 | LPC24XX_PIN_USB_D_MINUS_1, |
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79 | LPC24XX_PIN_USB_PPWR_1, |
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80 | LPC24XX_PIN_USB_SCL_1, |
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81 | LPC24XX_PIN_USB_SDA_1, |
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82 | LPC24XX_PIN_TERMINAL |
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83 | }; |
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84 | |
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85 | rtems_status_code sc; |
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86 | |
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87 | sc = lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION); |
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88 | BSD_ASSERT_SC(sc); |
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89 | } |
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90 | |
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91 | static void lpc_usb_host_clock_enable(void) |
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92 | { |
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93 | /* Nothing to do */ |
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94 | } |
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95 | |
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96 | static void lpc_otg_status_and_control(void) |
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97 | { |
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98 | OTG_STAT_CTRL = 0x3; |
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99 | } |
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100 | |
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101 | static rtems_interval lpc_usb_timeout_init(void) |
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102 | { |
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103 | return rtems_clock_get_ticks_since_boot(); |
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104 | } |
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105 | |
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106 | static bool lpc_usb_timeout_not_expired(rtems_interval start) |
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107 | { |
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108 | rtems_interval elapsed = rtems_clock_get_ticks_since_boot() - start; |
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109 | |
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110 | return elapsed < rtems_clock_get_ticks_per_second() / 10; |
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111 | } |
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112 | |
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113 | #define LPC_OTG_CLK_HOST BSP_BIT32(0) |
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114 | #define LPC_OTG_CLK_DEV BSP_BIT32(1) |
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115 | #define LPC_OTG_CLK_I2C BSP_BIT32(2) |
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116 | #define LPC_OTG_CLK_OTG BSP_BIT32(3) |
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117 | #define LPC_OTG_CLK_AHB BSP_BIT32(4) |
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118 | |
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119 | static int lpc_otg_clk_ctrl(uint32_t otg_clk_ctrl) |
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120 | { |
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121 | rtems_interval start; |
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122 | bool not_ok; |
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123 | |
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124 | LPC_OTG_CLK_CTRL = otg_clk_ctrl; |
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125 | |
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126 | start = lpc_usb_timeout_init(); |
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127 | while ( |
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128 | (not_ok = (LPC_OTG_CLK_STAT & otg_clk_ctrl) != otg_clk_ctrl) |
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129 | && lpc_usb_timeout_not_expired(start) |
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130 | ) { |
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131 | /* Wait */ |
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132 | } |
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133 | |
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134 | return not_ok ? EIO : 0; |
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135 | } |
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136 | |
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137 | #include <sys/cdefs.h> |
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138 | #include <sys/stdint.h> |
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139 | #include <sys/stddef.h> |
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140 | #include <rtems/bsd/sys/param.h> |
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141 | #include <sys/queue.h> |
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142 | #include <sys/types.h> |
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143 | #include <sys/systm.h> |
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144 | #include <sys/kernel.h> |
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145 | #include <sys/bus.h> |
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146 | #include <sys/linker_set.h> |
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147 | #include <sys/module.h> |
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148 | #include <rtems/bsd/sys/lock.h> |
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149 | #include <sys/mutex.h> |
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150 | #include <sys/condvar.h> |
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151 | #include <sys/sysctl.h> |
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152 | #include <sys/sx.h> |
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153 | #include <sys/unistd.h> |
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154 | #include <sys/callout.h> |
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155 | #include <sys/malloc.h> |
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156 | #include <sys/priv.h> |
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157 | |
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158 | #include <dev/usb/usb.h> |
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159 | #include <dev/usb/usbdi.h> |
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160 | |
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161 | #include <dev/usb/usb_core.h> |
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162 | #include <dev/usb/usb_busdma.h> |
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163 | #include <dev/usb/usb_process.h> |
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164 | #include <dev/usb/usb_util.h> |
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165 | |
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166 | #include <dev/usb/usb_controller.h> |
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167 | #include <dev/usb/usb_bus.h> |
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168 | #include <dev/usb/controller/ohci.h> |
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169 | |
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170 | #ifdef BSP_USB_OTG_TRANSCEIVER_I2C_ADDR |
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171 | |
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172 | #define I2C_CTL_SRST (1U << 8) |
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173 | |
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174 | #define I2C_TX_DATA_MASK 0xffU |
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175 | #define I2C_TX_ADDR_SHIFT 1 |
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176 | #define I2C_TX_ADDR_MASK 0x7fU |
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177 | #define I2C_TX_READ (1U << 0) |
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178 | #define I2C_TX_START (1U << 8) |
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179 | #define I2C_TX_STOP (1U << 9) |
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180 | |
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181 | #define I2C_STS_TDI (1U << 0) |
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182 | #define I2C_STS_AFI (1U << 1) |
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183 | #define I2C_STS_NAI (1U << 2) |
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184 | #define I2C_STS_RFE (1U << 9) |
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185 | |
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186 | typedef struct { |
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187 | uint32_t rx_tx; |
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188 | uint32_t sts; |
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189 | uint32_t ctl; |
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190 | uint32_t clkhi; |
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191 | uint32_t clklo; |
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192 | } i2c_regs; |
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193 | |
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194 | static volatile i2c_regs *i2c = |
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195 | (volatile i2c_regs *) LPC_USB_I2C_BASE; |
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196 | |
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197 | static int i2c_wait_for_receive_fifo_not_empty(void) |
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198 | { |
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199 | rtems_interval start; |
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200 | bool not_ok; |
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201 | |
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202 | start = lpc_usb_timeout_init(); |
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203 | while ( |
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204 | (not_ok = (i2c->sts & I2C_STS_RFE) != 0) |
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205 | && lpc_usb_timeout_not_expired(start) |
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206 | ) { |
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207 | /* Wait */ |
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208 | } |
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209 | |
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210 | return not_ok ? EIO : 0; |
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211 | } |
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212 | |
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213 | static int i2c_wait_for_transaction_done(void) |
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214 | { |
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215 | rtems_interval start; |
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216 | bool not_ok; |
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217 | |
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218 | start = lpc_usb_timeout_init(); |
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219 | while ( |
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220 | (not_ok = (i2c->sts & I2C_STS_TDI) == 0) |
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221 | && lpc_usb_timeout_not_expired(start) |
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222 | ) { |
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223 | /* Wait */ |
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224 | } |
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225 | |
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226 | return not_ok ? EIO : 0; |
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227 | } |
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228 | |
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229 | static int i2c_read( |
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230 | const struct usb_otg_transceiver *self, |
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231 | uint8_t reg_addr, |
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232 | uint8_t *value |
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233 | ) |
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234 | { |
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235 | int eno; |
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236 | |
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237 | i2c->ctl = I2C_CTL_SRST; |
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238 | |
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239 | i2c->rx_tx = self->i2c_addr | I2C_TX_START; |
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240 | i2c->rx_tx = reg_addr; |
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241 | i2c->rx_tx = self->i2c_addr | I2C_TX_READ | I2C_TX_START; |
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242 | i2c->rx_tx = I2C_TX_STOP; |
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243 | |
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244 | eno = i2c_wait_for_receive_fifo_not_empty(); |
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245 | |
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246 | if (eno == 0) { |
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247 | *value = (int) i2c->rx_tx; |
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248 | } |
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249 | |
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250 | return eno; |
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251 | } |
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252 | |
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253 | static int i2c_write( |
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254 | const struct usb_otg_transceiver *self, |
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255 | uint8_t reg_addr, |
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256 | uint8_t value |
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257 | ) |
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258 | { |
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259 | int eno; |
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260 | |
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261 | i2c->ctl = I2C_CTL_SRST; |
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262 | i2c->sts = I2C_STS_TDI; |
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263 | |
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264 | i2c->rx_tx = self->i2c_addr | I2C_TX_START; |
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265 | i2c->rx_tx = reg_addr; |
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266 | i2c->rx_tx = value | I2C_TX_STOP; |
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267 | |
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268 | eno = i2c_wait_for_transaction_done(); |
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269 | |
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270 | return eno; |
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271 | } |
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272 | |
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273 | #endif /* BSP_USB_OTG_TRANSCEIVER_I2C_ADDR */ |
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274 | |
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275 | static device_probe_t ohci_lpc_probe; |
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276 | static device_attach_t ohci_lpc_attach; |
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277 | static device_detach_t ohci_lpc_detach; |
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278 | static device_resume_t ohci_lpc_resume; |
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279 | |
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280 | static int |
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281 | ohci_lpc_otg_transceiver_suspend(ohci_softc_t *e) |
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282 | { |
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283 | int eno = 0; |
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284 | |
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285 | #ifdef BSP_USB_OTG_TRANSCEIVER_I2C_ADDR |
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286 | if (eno == 0) { |
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287 | eno = lpc_otg_clk_ctrl( |
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288 | LPC_OTG_CLK_AHB | LPC_OTG_CLK_HOST | LPC_OTG_CLK_I2C |
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289 | ); |
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290 | } |
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291 | |
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292 | if (eno == 0) { |
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293 | eno = usb_otg_transceiver_suspend(&e->sc_otg_trans); |
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294 | } |
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295 | |
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296 | #ifdef BSP_USB_OTG_TRANSCEIVER_DUMP |
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297 | usb_otg_transceiver_dump(&e->sc_otg_trans); |
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298 | #endif /* BSP_USB_OTG_TRANSCEIVER_DUMP */ |
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299 | |
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300 | if (eno == 0) { |
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301 | eno = lpc_otg_clk_ctrl(LPC_OTG_CLK_AHB | LPC_OTG_CLK_HOST); |
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302 | } |
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303 | #endif /* BSP_USB_OTG_TRANSCEIVER_I2C_ADDR */ |
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304 | |
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305 | return eno; |
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306 | } |
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307 | |
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308 | static int |
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309 | ohci_lpc_resume(device_t self) |
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310 | { |
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311 | int eno = 0; |
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312 | |
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313 | #ifdef BSP_USB_OTG_TRANSCEIVER_I2C_ADDR |
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314 | if (eno == 0) { |
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315 | eno = lpc_otg_clk_ctrl( |
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316 | LPC_OTG_CLK_AHB | LPC_OTG_CLK_HOST | LPC_OTG_CLK_I2C |
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317 | ); |
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318 | } |
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319 | |
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320 | if (eno == 0) { |
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321 | eno = usb_otg_transceiver_resume(&e->sc_otg_trans); |
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322 | } |
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323 | |
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324 | #ifdef BSP_USB_OTG_TRANSCEIVER_VBUS |
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325 | if (eno == 0) { |
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326 | eno = usb_otg_transceiver_set_vbus( |
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327 | &e->sc_otg_trans, |
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328 | BSP_USB_OTG_TRANSCEIVER_VBUS |
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329 | ); |
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330 | } |
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331 | #endif /* BSP_USB_OTG_TRANSCEIVER_VBUS */ |
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332 | |
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333 | #ifdef BSP_USB_OTG_TRANSCEIVER_DUMP |
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334 | usb_otg_transceiver_dump(&e->sc_otg_trans); |
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335 | #endif /* BSP_USB_OTG_TRANSCEIVER_DUMP */ |
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336 | |
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337 | if (eno == 0) { |
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338 | eno = lpc_otg_clk_ctrl(LPC_OTG_CLK_AHB | LPC_OTG_CLK_HOST); |
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339 | } |
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340 | #endif /* BSP_USB_OTG_TRANSCEIVER_I2C_ADDR */ |
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341 | |
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342 | if (eno == 0) { |
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343 | eno = bus_generic_resume(self); |
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344 | } |
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345 | |
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346 | return (eno); |
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347 | } |
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348 | |
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349 | static int |
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350 | ohci_lpc_probe(device_t self) |
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351 | { |
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352 | device_set_desc(self, "LPC OHCI controller"); |
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353 | |
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354 | return (0); |
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355 | } |
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356 | |
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357 | static int |
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358 | ohci_lpc_attach(device_t self) |
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359 | { |
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360 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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361 | ohci_softc_t *e = device_get_softc(self); |
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362 | usb_error_t ue = USB_ERR_NORMAL_COMPLETION; |
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363 | int eno = 0; |
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364 | |
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365 | memset(e, 0, sizeof(*e)); |
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366 | |
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367 | /* Initialize some bus fields */ |
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368 | e->sc_bus.parent = self; |
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369 | e->sc_bus.devices = e->sc_devices; |
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370 | e->sc_bus.devices_max = OHCI_MAX_DEVICES; |
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371 | e->sc_bus.dma_bits = 32; |
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372 | |
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373 | /* Get all DMA memory */ |
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374 | if (usb_bus_mem_alloc_all(&e->sc_bus, USB_GET_DMA_TAG(self), &ohci_iterate_hw_softc)) { |
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375 | return (ENOMEM); |
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376 | } |
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377 | e->sc_dev = self; |
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378 | |
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379 | /* Child device */ |
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380 | e->sc_bus.bdev = device_add_child(self, "usbus", -1); |
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381 | if (e->sc_bus.bdev == NULL) { |
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382 | device_printf(self, "Could not add USB device\n"); |
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383 | goto error; |
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384 | } |
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385 | device_set_ivars(e->sc_bus.bdev, &e->sc_bus); |
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386 | device_set_desc(e->sc_bus.bdev, "LPC OHCI bus"); |
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387 | snprintf(e->sc_vendor, sizeof(e->sc_vendor), "NXP"); |
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388 | |
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389 | /* Register space */ |
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390 | e->sc_io_tag = 0U; |
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391 | e->sc_io_hdl = LPC_USB_OHCI_BASE; |
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392 | e->sc_io_size = 0x5cU; |
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393 | |
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394 | lpc_usb_module_enable(); |
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395 | |
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396 | eno = lpc_otg_clk_ctrl(LPC_OTG_CLK_AHB | LPC_OTG_CLK_I2C); |
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397 | if (eno != 0) { |
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398 | goto error; |
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399 | } |
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400 | |
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401 | lpc_usb_pin_config(); |
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402 | |
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403 | #ifdef BSP_USB_OTG_TRANSCEIVER_I2C_ADDR |
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404 | e->sc_otg_trans.read = i2c_read; |
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405 | e->sc_otg_trans.write = i2c_write; |
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406 | e->sc_otg_trans.i2c_addr = BSP_USB_OTG_TRANSCEIVER_I2C_ADDR; |
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407 | eno = usb_otg_transceiver_init(&e->sc_otg_trans); |
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408 | if (eno != 0) { |
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409 | goto error; |
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410 | } |
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411 | |
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412 | #ifdef BSP_USB_OTG_TRANSCEIVER_DUMP |
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413 | usb_otg_transceiver_dump(&e->sc_otg_trans); |
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414 | #endif /* BSP_USB_OTG_TRANSCEIVER_DUMP */ |
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415 | |
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416 | eno = usb_otg_transceiver_resume(&e->sc_otg_trans); |
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417 | if (eno != 0) { |
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418 | goto error; |
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419 | } |
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420 | #endif /* BSP_USB_OTG_TRANSCEIVER_I2C_ADDR */ |
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421 | |
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422 | lpc_usb_host_clock_enable(); |
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423 | |
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424 | eno = lpc_otg_clk_ctrl( |
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425 | LPC_OTG_CLK_AHB | LPC_OTG_CLK_HOST |
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426 | | LPC_OTG_CLK_I2C | LPC_OTG_CLK_OTG |
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427 | ); |
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428 | if (eno != 0) { |
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429 | goto error; |
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430 | } |
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431 | |
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432 | lpc_otg_status_and_control(); |
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433 | |
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434 | #if defined(BSP_USB_OTG_TRANSCEIVER_I2C_ADDR) \ |
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435 | && defined(BSP_USB_OTG_TRANSCEIVER_VBUS) |
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436 | eno = usb_otg_transceiver_set_vbus( |
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437 | &e->sc_otg_trans, |
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438 | BSP_USB_OTG_TRANSCEIVER_VBUS |
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439 | ); |
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440 | if (eno != 0) { |
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441 | goto error; |
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442 | } |
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443 | #endif /* defined(BSP_USB_OTG_TRANSCEIVER_I2C_ADDR) |
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444 | && defined(BSP_USB_OTG_TRANSCEIVER_VBUS) */ |
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445 | |
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446 | #if defined(BSP_USB_OTG_TRANSCEIVER_I2C_ADDR) \ |
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447 | && defined(BSP_USB_OTG_TRANSCEIVER_DUMP) |
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448 | usb_otg_transceiver_dump(&e->sc_otg_trans); |
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449 | #endif /* defined(BSP_USB_OTG_TRANSCEIVER_I2C_ADDR) |
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450 | && defined(BSP_USB_OTG_TRANSCEIVER_DUMP) */ |
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451 | |
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452 | eno = lpc_otg_clk_ctrl(LPC_OTG_CLK_AHB | LPC_OTG_CLK_HOST); |
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453 | if (eno != 0) { |
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454 | goto error; |
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455 | } |
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456 | |
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457 | /* Install interrupt handler */ |
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458 | sc = rtems_interrupt_server_handler_install( |
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459 | RTEMS_ID_NONE, |
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460 | LPC_USB_OHCI_IRQ, |
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461 | "USB", |
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462 | RTEMS_INTERRUPT_UNIQUE, |
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463 | (rtems_interrupt_handler) ohci_interrupt, |
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464 | e |
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465 | ); |
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466 | BSD_ASSERT_SC(sc); |
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467 | |
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468 | /* OHCI intitialization */ |
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469 | ue = ohci_init(e); |
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470 | if (ue != USB_ERR_NORMAL_COMPLETION) { |
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471 | goto error; |
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472 | } |
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473 | e->sc_init_done = 1; |
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474 | |
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475 | /* Probe and attach child */ |
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476 | eno = device_probe_and_attach(e->sc_bus.bdev); |
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477 | if (eno != 0) { |
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478 | goto error; |
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479 | } |
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480 | |
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481 | return (0); |
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482 | |
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483 | error: |
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484 | ohci_lpc_detach(self); |
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485 | |
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486 | return (ENXIO); |
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487 | } |
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488 | |
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489 | static int |
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490 | ohci_lpc_detach(device_t self) |
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491 | { |
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492 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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493 | ohci_softc_t *e = device_get_softc(self); |
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494 | |
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495 | if (e->sc_bus.bdev) { |
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496 | device_t bdev = e->sc_bus.bdev; |
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497 | |
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498 | device_detach(bdev); |
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499 | device_delete_child(self, bdev); |
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500 | } |
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501 | |
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502 | device_delete_children(self); |
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503 | |
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504 | if (e->sc_init_done) { |
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505 | ohci_detach(e); |
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506 | } |
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507 | |
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508 | sc = rtems_interrupt_server_handler_remove( |
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509 | RTEMS_ID_NONE, |
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510 | LPC_USB_OHCI_IRQ, |
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511 | (rtems_interrupt_handler) ohci_interrupt, |
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512 | e |
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513 | ); |
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514 | BSD_ASSERT_SC(sc); |
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515 | |
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516 | ohci_lpc_otg_transceiver_suspend(e); |
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517 | |
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518 | lpc_otg_clk_ctrl(0); |
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519 | |
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520 | lpc_usb_module_disable(); |
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521 | |
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522 | usb_bus_mem_free_all(&e->sc_bus, &ohci_iterate_hw_softc); |
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523 | |
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524 | return (0); |
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525 | } |
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526 | |
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527 | static device_method_t ohci_methods [] = { |
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528 | /* Device interface */ |
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529 | DEVMETHOD(device_probe, ohci_lpc_probe), |
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530 | DEVMETHOD(device_attach, ohci_lpc_attach), |
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531 | DEVMETHOD(device_detach, ohci_lpc_detach), |
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532 | DEVMETHOD(device_suspend, bus_generic_suspend), |
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533 | DEVMETHOD(device_resume, ohci_lpc_resume), |
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534 | DEVMETHOD(device_shutdown, bus_generic_shutdown), |
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535 | |
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536 | /* Bus interface */ |
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537 | DEVMETHOD(bus_print_child, bus_generic_print_child), |
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538 | |
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539 | {0, 0} |
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540 | }; |
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541 | |
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542 | static driver_t ohci_driver = { |
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543 | .name = "ohci", |
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544 | .methods = ohci_methods, |
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545 | .size = sizeof(struct ohci_softc) |
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546 | }; |
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547 | |
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548 | static devclass_t ohci_devclass; |
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549 | |
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550 | DRIVER_MODULE(ohci, nexus, ohci_driver, ohci_devclass, 0, 0); |
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551 | MODULE_DEPEND(ohci, usb, 1, 1, 1); |
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552 | |
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553 | #endif /* defined(LIBBSP_ARM_LPC24XX_BSP_H) */ |
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