[b16eca9] | 1 | /* |
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| 2 | * Copyright (c) 2016 embedded brains GmbH. All rights reserved. |
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| 3 | * |
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| 4 | * embedded brains GmbH |
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| 5 | * Dornierstr. 4 |
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| 6 | * 82178 Puchheim |
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| 7 | * Germany |
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| 8 | * <info@embedded-brains.de> |
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| 9 | * |
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| 10 | * Redistribution and use in source and binary forms, with or without |
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| 11 | * modification, are permitted provided that the following conditions |
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| 12 | * are met: |
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| 13 | * 1. Redistributions of source code must retain the above copyright |
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| 14 | * notice, this list of conditions and the following disclaimer. |
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| 15 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 16 | * notice, this list of conditions and the following disclaimer in the |
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| 17 | * documentation and/or other materials provided with the distribution. |
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| 18 | * |
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| 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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| 20 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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| 21 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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| 22 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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| 23 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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| 24 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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| 25 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 26 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 27 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 29 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 30 | */ |
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| 31 | |
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[80a7fe6] | 32 | #include <machine/rtems-bsd-kernel-space.h> |
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[b16eca9] | 33 | |
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| 34 | #include <bsp.h> |
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[80a7fe6] | 35 | |
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| 36 | #ifdef LIBBSP_ARM_ATSAM_BSP_H |
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| 37 | |
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[b16eca9] | 38 | #include <bsp/irq.h> |
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| 39 | |
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| 40 | #include <stdio.h> |
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| 41 | |
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| 42 | #include <sys/types.h> |
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| 43 | #include <sys/param.h> |
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| 44 | #include <sys/mbuf.h> |
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| 45 | #include <sys/socket.h> |
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| 46 | #include <sys/sockio.h> |
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[80a7fe6] | 47 | #include <sys/kernel.h> |
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| 48 | #include <sys/module.h> |
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| 49 | #include <sys/bus.h> |
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[0190cfd] | 50 | #include <sys/sysctl.h> |
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[b16eca9] | 51 | |
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| 52 | #include <net/if.h> |
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| 53 | #include <net/if_var.h> |
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| 54 | #include <net/if_types.h> |
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[80a7fe6] | 55 | #include <net/if_media.h> |
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[b16eca9] | 56 | |
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| 57 | #include <netinet/in.h> |
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| 58 | #include <netinet/if_ether.h> |
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| 59 | |
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| 60 | #include <dev/mii/mii.h> |
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[80a7fe6] | 61 | #include <dev/mii/miivar.h> |
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| 62 | |
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| 63 | #include <libchip/chip.h> |
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| 64 | #include <libchip/include/gmacd.h> |
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| 65 | #include <libchip/include/pio.h> |
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| 66 | |
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| 67 | #include <rtems/rtems_mii_ioctl.h> |
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| 68 | #include <rtems/bsd/local/miibus_if.h> |
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[b16eca9] | 69 | |
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| 70 | /* |
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| 71 | * Number of interfaces supported by the driver |
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| 72 | */ |
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| 73 | #define NIFACES 1 |
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| 74 | |
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| 75 | /** Enable/Disable CopyAllFrame */ |
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| 76 | #define GMAC_CAF_DISABLE 0 |
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| 77 | #define GMAC_CAF_ENABLE 1 |
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| 78 | |
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| 79 | /** Enable/Disable NoBroadCast */ |
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| 80 | #define GMAC_NBC_DISABLE 0 |
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| 81 | #define GMAC_NBC_ENABLE 1 |
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| 82 | |
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| 83 | /** The PIN list of PIO for GMAC */ |
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| 84 | #define BOARD_GMAC_PINS \ |
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| 85 | { (PIO_PD0A_GTXCK | PIO_PD1A_GTXEN | PIO_PD2A_GTX0 | PIO_PD3A_GTX1 \ |
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| 86 | | PIO_PD4A_GRXDV | PIO_PD5A_GRX0 | PIO_PD6A_GRX1 \ |
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| 87 | | PIO_PD7A_GRXER \ |
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| 88 | | PIO_PD8A_GMDC | PIO_PD9A_GMDIO), PIOD, ID_PIOD, PIO_PERIPH_A, \ |
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| 89 | PIO_DEFAULT } |
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| 90 | /** The runtime pin configure list for GMAC */ |
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| 91 | #define BOARD_GMAC_RUN_PINS BOARD_GMAC_PINS |
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| 92 | |
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| 93 | /** Multicast Enable */ |
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| 94 | #define GMAC_MC_ENABLE (1u << 6) |
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| 95 | #define HASH_INDEX_AMOUNT 6 |
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| 96 | #define HASH_ELEMENTS_PER_INDEX 8 |
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| 97 | #define MAC_ADDR_MASK 0x0000FFFFFFFFFFFF |
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| 98 | #define MAC_IDX_MASK (1u << 0) |
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| 99 | |
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| 100 | /** Promiscuous Mode Enable */ |
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| 101 | #define GMAC_PROM_ENABLE (1u << 4) |
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| 102 | |
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| 103 | /** RX Defines */ |
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| 104 | #define GMAC_RX_BUFFER_SIZE 1536 |
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| 105 | #define GMAC_RX_BUF_DESC_ADDR_MASK 0xFFFFFFFC |
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| 106 | #define GMAC_RX_SET_OFFSET (1u << 15) |
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| 107 | #define GMAC_RX_SET_USED_WRAP ((1u << 1) | (1u << 0)) |
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| 108 | #define GMAC_RX_SET_WRAP (1u << 1) |
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| 109 | #define GMAC_RX_SET_USED (1u << 0) |
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| 110 | /** TX Defines */ |
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| 111 | #define GMAC_TX_SET_EOF (1u << 15) |
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| 112 | #define GMAC_TX_SET_WRAP (1u << 30) |
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| 113 | #define GMAC_TX_SET_USED (1u << 31) |
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| 114 | |
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| 115 | #define GMAC_DESCRIPTOR_ALIGNMENT 8 |
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| 116 | |
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| 117 | /** Events */ |
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| 118 | #define ATSAMV7_ETH_RX_EVENT_INTERRUPT RTEMS_EVENT_1 |
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| 119 | #define ATSAMV7_ETH_TX_EVENT_INTERRUPT RTEMS_EVENT_2 |
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| 120 | #define ATSAMV7_ETH_START_TRANSMIT_EVENT RTEMS_EVENT_3 |
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| 121 | |
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| 122 | #define ATSAMV7_ETH_RX_DATA_OFFSET 2 |
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| 123 | |
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| 124 | #define WATCHDOG_TIMEOUT 5 |
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| 125 | |
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[80a7fe6] | 126 | /* FIXME: Make these configurable */ |
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| 127 | #define MDIO_RETRIES 10 |
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| 128 | #define MDIO_PHY MII_PHY_ANY |
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| 129 | #define RXBUF_COUNT 8 |
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| 130 | #define TXBUF_COUNT 64 |
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| 131 | #define IGNORE_RX_ERR false |
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| 132 | |
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| 133 | |
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[b16eca9] | 134 | /** The PINs for GMAC */ |
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| 135 | static const Pin gmacPins[] = { BOARD_GMAC_RUN_PINS }; |
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| 136 | |
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| 137 | typedef struct if_atsam_gmac { |
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| 138 | /** The GMAC driver instance */ |
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| 139 | sGmacd gGmacd; |
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| 140 | uint32_t retries; |
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| 141 | } if_atsam_gmac; |
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| 142 | |
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| 143 | typedef struct ring_buffer { |
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| 144 | unsigned tx_bd_used; |
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| 145 | unsigned tx_bd_free; |
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| 146 | size_t length; |
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| 147 | } ring_buffer; |
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| 148 | |
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| 149 | /* |
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| 150 | * Per-device data |
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| 151 | */ |
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| 152 | typedef struct if_atsam_softc { |
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| 153 | /* |
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| 154 | * Data |
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| 155 | */ |
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[80a7fe6] | 156 | device_t dev; |
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| 157 | struct ifnet *ifp; |
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| 158 | struct mtx mtx; |
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[b16eca9] | 159 | if_atsam_gmac Gmac_inst; |
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| 160 | uint8_t GMacAddress[6]; |
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| 161 | rtems_id rx_daemon_tid; |
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| 162 | rtems_id tx_daemon_tid; |
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| 163 | rtems_vector_number interrupt_number; |
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| 164 | struct mbuf **rx_mbuf; |
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| 165 | struct mbuf **tx_mbuf; |
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| 166 | volatile sGmacTxDescriptor *tx_bd_base; |
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| 167 | size_t rx_bd_fill_idx; |
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| 168 | size_t amount_rx_buf; |
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| 169 | size_t amount_tx_buf; |
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| 170 | ring_buffer tx_ring; |
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[0190cfd] | 171 | struct callout tick_ch; |
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[b16eca9] | 172 | |
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[80a7fe6] | 173 | /* |
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| 174 | * mii bus |
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| 175 | */ |
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| 176 | device_t miibus; |
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| 177 | uint8_t link_speed; |
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| 178 | uint8_t link_duplex; |
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| 179 | |
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[b16eca9] | 180 | /* |
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| 181 | * Statistics |
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| 182 | */ |
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[0190cfd] | 183 | struct if_atsam_stats { |
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| 184 | /* Software */ |
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| 185 | uint32_t rx_overrun_errors; |
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| 186 | uint32_t rx_interrupts; |
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| 187 | uint32_t tx_complete_int; |
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| 188 | uint32_t tx_tur_errors; |
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| 189 | uint32_t tx_rlex_errors; |
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| 190 | uint32_t tx_tfc_errors; |
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| 191 | uint32_t tx_hresp_errors; |
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| 192 | uint32_t tx_interrupts; |
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| 193 | |
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| 194 | /* Hardware */ |
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| 195 | uint64_t octets_transm; |
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| 196 | uint32_t frames_transm; |
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| 197 | uint32_t broadcast_frames_transm; |
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| 198 | uint32_t multicast_frames_transm; |
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| 199 | uint32_t pause_frames_transm; |
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| 200 | uint32_t frames_64_byte_transm; |
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| 201 | uint32_t frames_65_to_127_byte_transm; |
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| 202 | uint32_t frames_128_to_255_byte_transm; |
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| 203 | uint32_t frames_256_to_511_byte_transm; |
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| 204 | uint32_t frames_512_to_1023_byte_transm; |
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| 205 | uint32_t frames_1024_to_1518_byte_transm; |
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| 206 | uint32_t frames_greater_1518_byte_transm; |
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| 207 | uint32_t transmit_underruns; |
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| 208 | uint32_t single_collision_frames; |
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| 209 | uint32_t multiple_collision_frames; |
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| 210 | uint32_t excessive_collisions; |
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| 211 | uint32_t late_collisions; |
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| 212 | uint32_t deferred_transmission_frames; |
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| 213 | uint32_t carrier_sense_errors; |
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| 214 | uint64_t octets_rec; |
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| 215 | uint32_t frames_rec; |
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| 216 | uint32_t broadcast_frames_rec; |
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| 217 | uint32_t multicast_frames_rec; |
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| 218 | uint32_t pause_frames_rec; |
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| 219 | uint32_t frames_64_byte_rec; |
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| 220 | uint32_t frames_65_to_127_byte_rec; |
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| 221 | uint32_t frames_128_to_255_byte_rec; |
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| 222 | uint32_t frames_256_to_511_byte_rec; |
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| 223 | uint32_t frames_512_to_1023_byte_rec; |
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| 224 | uint32_t frames_1024_to_1518_byte_rec; |
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| 225 | uint32_t frames_1519_to_maximum_byte_rec; |
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| 226 | uint32_t undersize_frames_rec; |
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| 227 | uint32_t oversize_frames_rec; |
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| 228 | uint32_t jabbers_rec; |
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| 229 | uint32_t frame_check_sequence_errors; |
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| 230 | uint32_t length_field_frame_errors; |
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| 231 | uint32_t receive_symbol_errors; |
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| 232 | uint32_t alignment_errors; |
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| 233 | uint32_t receive_resource_errors; |
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| 234 | uint32_t receive_overrun; |
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| 235 | uint32_t ip_header_checksum_errors; |
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| 236 | uint32_t tcp_checksum_errors; |
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| 237 | uint32_t udp_checksum_errors; |
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| 238 | } stats; |
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[b16eca9] | 239 | } if_atsam_softc; |
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| 240 | |
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[0190cfd] | 241 | static void if_atsam_poll_hw_stats(struct if_atsam_softc *sc); |
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[80a7fe6] | 242 | |
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| 243 | #define IF_ATSAM_LOCK(sc) mtx_lock(&(sc)->mtx) |
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| 244 | |
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| 245 | #define IF_ATSAM_UNLOCK(sc) mtx_unlock(&(sc)->mtx) |
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| 246 | |
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| 247 | static void if_atsam_event_send(rtems_id task, rtems_event_set event) |
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| 248 | { |
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| 249 | rtems_event_send(task, event); |
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| 250 | } |
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| 251 | |
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| 252 | |
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| 253 | static void if_atsam_event_receive(if_atsam_softc *sc, rtems_event_set in) |
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| 254 | { |
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| 255 | rtems_event_set out; |
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| 256 | |
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| 257 | IF_ATSAM_UNLOCK(sc); |
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| 258 | rtems_event_receive( |
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| 259 | in, |
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| 260 | RTEMS_EVENT_ANY | RTEMS_WAIT, |
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| 261 | RTEMS_NO_TIMEOUT, |
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| 262 | &out |
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| 263 | ); |
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| 264 | IF_ATSAM_LOCK(sc); |
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| 265 | } |
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| 266 | |
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[b16eca9] | 267 | |
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| 268 | static struct mbuf *if_atsam_new_mbuf(struct ifnet *ifp) |
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| 269 | { |
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| 270 | struct mbuf *m; |
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| 271 | |
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[80a7fe6] | 272 | MGETHDR(m, M_NOWAIT, MT_DATA); |
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[b16eca9] | 273 | if (m != NULL) { |
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[80a7fe6] | 274 | MCLGET(m, M_NOWAIT); |
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[b16eca9] | 275 | if ((m->m_flags & M_EXT) != 0) { |
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| 276 | m->m_pkthdr.rcvif = ifp; |
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| 277 | m->m_data = mtod(m, char *); |
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| 278 | rtems_cache_invalidate_multiple_data_lines(mtod(m, void *), |
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| 279 | GMAC_RX_BUFFER_SIZE); |
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| 280 | } else { |
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| 281 | m_free(m); |
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| 282 | m = NULL; |
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| 283 | } |
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| 284 | } |
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| 285 | return (m); |
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| 286 | } |
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| 287 | |
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| 288 | |
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| 289 | static uint8_t if_atsam_wait_phy(Gmac *pHw, uint32_t retry) |
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| 290 | { |
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| 291 | volatile uint32_t retry_count = 0; |
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| 292 | |
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| 293 | while (!GMAC_IsIdle(pHw)) { |
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| 294 | if (retry == 0) { |
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| 295 | continue; |
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| 296 | } |
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| 297 | retry_count++; |
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| 298 | |
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| 299 | if (retry_count >= retry) { |
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| 300 | return (1); |
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| 301 | } |
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| 302 | rtems_task_wake_after(1); |
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| 303 | } |
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| 304 | |
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| 305 | return (0); |
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| 306 | } |
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| 307 | |
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| 308 | |
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| 309 | static uint8_t |
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| 310 | if_atsam_write_phy(Gmac *pHw, uint8_t PhyAddress, uint8_t Address, |
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| 311 | uint32_t Value, uint32_t retry) |
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| 312 | { |
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| 313 | GMAC_PHYMaintain(pHw, PhyAddress, Address, 0, (uint16_t)Value); |
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| 314 | if (if_atsam_wait_phy(pHw, retry) == 1) { |
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| 315 | return (1); |
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| 316 | } |
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| 317 | return (0); |
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| 318 | } |
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| 319 | |
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| 320 | |
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| 321 | static uint8_t |
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| 322 | if_atsam_read_phy(Gmac *pHw, |
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| 323 | uint8_t PhyAddress, uint8_t Address, uint32_t *pvalue, uint32_t retry) |
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| 324 | { |
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| 325 | GMAC_PHYMaintain(pHw, PhyAddress, Address, 1, 0); |
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| 326 | if (if_atsam_wait_phy(pHw, retry) == 1) { |
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| 327 | return (1); |
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| 328 | } |
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| 329 | *pvalue = GMAC_PHYData(pHw); |
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| 330 | return (0); |
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| 331 | } |
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| 332 | |
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| 333 | |
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| 334 | static uint8_t |
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| 335 | if_atsam_init_phy(if_atsam_gmac *gmac_inst, uint32_t mck, |
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| 336 | const Pin *pResetPins, uint32_t nbResetPins, const Pin *pGmacPins, |
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| 337 | uint32_t nbGmacPins) |
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| 338 | { |
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| 339 | uint8_t rc = 1; |
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| 340 | Gmac *pHw = gmac_inst->gGmacd.pHw; |
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| 341 | |
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| 342 | /* Perform RESET */ |
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| 343 | if (pResetPins) { |
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| 344 | /* Configure PINS */ |
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| 345 | PIO_Configure(pResetPins, nbResetPins); |
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| 346 | PIO_Clear(pResetPins); |
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| 347 | rtems_task_wake_after(1); |
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| 348 | PIO_Set(pResetPins); |
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| 349 | } |
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| 350 | /* Configure GMAC runtime pins */ |
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| 351 | if (rc) { |
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| 352 | PIO_Configure(pGmacPins, nbGmacPins); |
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| 353 | rc = GMAC_SetMdcClock(pHw, mck); |
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| 354 | |
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| 355 | if (!rc) { |
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| 356 | return (0); |
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| 357 | } |
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| 358 | } |
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| 359 | return (rc); |
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| 360 | } |
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| 361 | |
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| 362 | |
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[80a7fe6] | 363 | static int |
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| 364 | if_atsam_miibus_readreg(device_t dev, int phy, int reg) |
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[b16eca9] | 365 | { |
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[80a7fe6] | 366 | uint32_t val; |
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| 367 | uint8_t err; |
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| 368 | if_atsam_softc *sc = device_get_softc(dev); |
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[b16eca9] | 369 | |
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[80a7fe6] | 370 | IF_ATSAM_LOCK(sc); |
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| 371 | err = if_atsam_read_phy(sc->Gmac_inst.gGmacd.pHw, |
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| 372 | (uint8_t)phy, (uint8_t)reg, &val, sc->Gmac_inst.retries); |
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| 373 | IF_ATSAM_UNLOCK(sc); |
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[b16eca9] | 374 | |
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[80a7fe6] | 375 | return (err == 0 ? val : 0); |
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[b16eca9] | 376 | } |
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| 377 | |
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| 378 | |
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[80a7fe6] | 379 | static int |
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| 380 | if_atsam_miibus_writereg(device_t dev, int phy, int reg, int data) |
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[b16eca9] | 381 | { |
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[80a7fe6] | 382 | uint8_t err; |
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| 383 | if_atsam_softc *sc = device_get_softc(dev); |
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[b16eca9] | 384 | |
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[80a7fe6] | 385 | IF_ATSAM_LOCK(sc); |
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| 386 | err = if_atsam_write_phy(sc->Gmac_inst.gGmacd.pHw, |
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| 387 | (uint8_t)phy, (uint8_t)reg, data, sc->Gmac_inst.retries); |
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| 388 | IF_ATSAM_UNLOCK(sc); |
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[b16eca9] | 389 | |
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[80a7fe6] | 390 | return 0; |
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[b16eca9] | 391 | } |
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| 392 | |
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| 393 | |
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| 394 | /* |
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| 395 | * Interrupt Handler for the network driver |
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| 396 | */ |
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| 397 | static void if_atsam_interrupt_handler(void *arg) |
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| 398 | { |
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| 399 | if_atsam_softc *sc = (if_atsam_softc *)arg; |
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| 400 | uint32_t irq_status_val; |
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| 401 | rtems_event_set rx_event = 0; |
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| 402 | rtems_event_set tx_event = 0; |
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| 403 | Gmac *pHw = sc->Gmac_inst.gGmacd.pHw; |
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| 404 | |
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| 405 | /* Get interrupt status */ |
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| 406 | irq_status_val = GMAC_GetItStatus(pHw, 0); |
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| 407 | |
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| 408 | /* Check receive interrupts */ |
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| 409 | if ((irq_status_val & GMAC_IER_ROVR) != 0) { |
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[0190cfd] | 410 | ++sc->stats.rx_overrun_errors; |
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[b16eca9] | 411 | rx_event = ATSAMV7_ETH_RX_EVENT_INTERRUPT; |
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| 412 | } |
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| 413 | if ((irq_status_val & GMAC_IER_RCOMP) != 0) { |
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| 414 | rx_event = ATSAMV7_ETH_RX_EVENT_INTERRUPT; |
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| 415 | } |
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| 416 | /* Send events to receive task and switch off rx interrupts */ |
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| 417 | if (rx_event != 0) { |
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[0190cfd] | 418 | ++sc->stats.rx_interrupts; |
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[b16eca9] | 419 | /* Erase the interrupts for RX completion and errors */ |
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| 420 | GMAC_DisableIt(pHw, GMAC_IER_RCOMP | GMAC_IER_ROVR, 0); |
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[80a7fe6] | 421 | (void)if_atsam_event_send(sc->rx_daemon_tid, rx_event); |
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[b16eca9] | 422 | } |
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| 423 | if ((irq_status_val & GMAC_IER_TUR) != 0) { |
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[0190cfd] | 424 | ++sc->stats.tx_tur_errors; |
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[b16eca9] | 425 | tx_event = ATSAMV7_ETH_TX_EVENT_INTERRUPT; |
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| 426 | } |
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| 427 | if ((irq_status_val & GMAC_IER_RLEX) != 0) { |
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[0190cfd] | 428 | ++sc->stats.tx_rlex_errors; |
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[b16eca9] | 429 | tx_event = ATSAMV7_ETH_TX_EVENT_INTERRUPT; |
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| 430 | } |
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| 431 | if ((irq_status_val & GMAC_IER_TFC) != 0) { |
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[0190cfd] | 432 | ++sc->stats.tx_tfc_errors; |
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[b16eca9] | 433 | tx_event = ATSAMV7_ETH_TX_EVENT_INTERRUPT; |
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| 434 | } |
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| 435 | if ((irq_status_val & GMAC_IER_HRESP) != 0) { |
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[0190cfd] | 436 | ++sc->stats.tx_hresp_errors; |
---|
[b16eca9] | 437 | tx_event = ATSAMV7_ETH_TX_EVENT_INTERRUPT; |
---|
| 438 | } |
---|
| 439 | if ((irq_status_val & GMAC_IER_TCOMP) != 0) { |
---|
[0190cfd] | 440 | ++sc->stats.tx_complete_int; |
---|
[b16eca9] | 441 | tx_event = ATSAMV7_ETH_TX_EVENT_INTERRUPT; |
---|
| 442 | } |
---|
| 443 | /* Send events to transmit task and switch off tx interrupts */ |
---|
| 444 | if (tx_event != 0) { |
---|
[0190cfd] | 445 | ++sc->stats.tx_interrupts; |
---|
[b16eca9] | 446 | /* Erase the interrupts for TX completion and errors */ |
---|
| 447 | GMAC_DisableIt(pHw, GMAC_INT_TX_BITS, 0); |
---|
[80a7fe6] | 448 | (void)if_atsam_event_send(sc->tx_daemon_tid, tx_event); |
---|
[b16eca9] | 449 | } |
---|
| 450 | } |
---|
| 451 | /* |
---|
| 452 | * Receive daemon |
---|
| 453 | */ |
---|
| 454 | static void if_atsam_rx_daemon(void *arg) |
---|
| 455 | { |
---|
| 456 | if_atsam_softc *sc = (if_atsam_softc *)arg; |
---|
[80a7fe6] | 457 | struct ifnet *ifp = sc->ifp; |
---|
[b16eca9] | 458 | rtems_event_set events = 0; |
---|
| 459 | void *rx_bd_base; |
---|
| 460 | struct mbuf *m; |
---|
| 461 | struct mbuf *n; |
---|
| 462 | volatile sGmacRxDescriptor *buffer_desc; |
---|
| 463 | int frame_len; |
---|
| 464 | uint32_t tmp_rx_bd_address; |
---|
[80a7fe6] | 465 | size_t i; |
---|
[b16eca9] | 466 | Gmac *pHw = sc->Gmac_inst.gGmacd.pHw; |
---|
| 467 | |
---|
[80a7fe6] | 468 | IF_ATSAM_LOCK(sc); |
---|
| 469 | |
---|
| 470 | if (IGNORE_RX_ERR) { |
---|
| 471 | pHw->GMAC_NCFGR |= GMAC_NCFGR_IRXER; |
---|
| 472 | } else { |
---|
| 473 | pHw->GMAC_NCFGR &= ~GMAC_NCFGR_IRXER; |
---|
| 474 | } |
---|
| 475 | |
---|
[b16eca9] | 476 | /* Allocate memory space for priority queue descriptor list */ |
---|
| 477 | rx_bd_base = rtems_cache_coherent_allocate(sizeof(sGmacRxDescriptor), |
---|
| 478 | GMAC_DESCRIPTOR_ALIGNMENT, 0); |
---|
| 479 | assert(rx_bd_base != NULL); |
---|
| 480 | |
---|
| 481 | buffer_desc = (sGmacRxDescriptor *)rx_bd_base; |
---|
| 482 | buffer_desc->addr.val = GMAC_RX_SET_USED_WRAP; |
---|
| 483 | buffer_desc->status.val = 0; |
---|
| 484 | |
---|
| 485 | GMAC_SetRxQueue(pHw, (uint32_t)buffer_desc, 1); |
---|
| 486 | GMAC_SetRxQueue(pHw, (uint32_t)buffer_desc, 2); |
---|
| 487 | |
---|
| 488 | /* Allocate memory space for buffer descriptor list */ |
---|
| 489 | rx_bd_base = rtems_cache_coherent_allocate( |
---|
| 490 | sc->amount_rx_buf * sizeof(sGmacRxDescriptor), |
---|
| 491 | GMAC_DESCRIPTOR_ALIGNMENT, 0); |
---|
| 492 | assert(rx_bd_base != NULL); |
---|
| 493 | buffer_desc = (sGmacRxDescriptor *)rx_bd_base; |
---|
| 494 | |
---|
| 495 | /* Create descriptor list and mark as empty */ |
---|
| 496 | for (sc->rx_bd_fill_idx = 0; sc->rx_bd_fill_idx < sc->amount_rx_buf; |
---|
| 497 | ++sc->rx_bd_fill_idx) { |
---|
[80a7fe6] | 498 | m = if_atsam_new_mbuf(ifp); |
---|
[b16eca9] | 499 | assert(m != NULL); |
---|
| 500 | sc->rx_mbuf[sc->rx_bd_fill_idx] = m; |
---|
| 501 | buffer_desc->addr.val = ((uint32_t)m->m_data) & |
---|
| 502 | GMAC_RX_BUF_DESC_ADDR_MASK; |
---|
| 503 | buffer_desc->status.val = 0; |
---|
| 504 | if (sc->rx_bd_fill_idx == (sc->amount_rx_buf - 1)) { |
---|
| 505 | buffer_desc->addr.bm.bWrap = 1; |
---|
| 506 | } else { |
---|
| 507 | buffer_desc++; |
---|
| 508 | } |
---|
| 509 | } |
---|
| 510 | buffer_desc = (sGmacRxDescriptor *)rx_bd_base; |
---|
| 511 | |
---|
| 512 | /* Set 2 Byte Receive Buffer Offset */ |
---|
| 513 | pHw->GMAC_NCFGR |= GMAC_RX_SET_OFFSET; |
---|
| 514 | |
---|
| 515 | /* Write Buffer Queue Base Address Register */ |
---|
| 516 | GMAC_ReceiveEnable(pHw, 0); |
---|
| 517 | GMAC_SetRxQueue(pHw, (uint32_t)buffer_desc, 0); |
---|
| 518 | |
---|
| 519 | /* Set address for address matching */ |
---|
| 520 | GMAC_SetAddress(pHw, 0, sc->GMacAddress); |
---|
| 521 | |
---|
| 522 | /* Enable Receiving of data */ |
---|
| 523 | GMAC_ReceiveEnable(pHw, 1); |
---|
| 524 | |
---|
| 525 | /* Setup the interrupts for RX completion and errors */ |
---|
| 526 | GMAC_EnableIt(pHw, GMAC_IER_RCOMP | GMAC_IER_ROVR, 0); |
---|
| 527 | |
---|
| 528 | sc->rx_bd_fill_idx = 0; |
---|
| 529 | |
---|
| 530 | while (true) { |
---|
| 531 | /* Wait for events */ |
---|
[80a7fe6] | 532 | if_atsam_event_receive(sc, ATSAMV7_ETH_RX_EVENT_INTERRUPT); |
---|
[b16eca9] | 533 | |
---|
| 534 | /* |
---|
| 535 | * Check for all packets with a set ownership bit |
---|
| 536 | */ |
---|
| 537 | while (buffer_desc->addr.bm.bOwnership == 1) { |
---|
| 538 | if (buffer_desc->status.bm.bEof == 1) { |
---|
| 539 | m = sc->rx_mbuf[sc->rx_bd_fill_idx]; |
---|
| 540 | |
---|
| 541 | /* New mbuf for desc */ |
---|
[80a7fe6] | 542 | n = if_atsam_new_mbuf(ifp); |
---|
[b16eca9] | 543 | if (n != NULL) { |
---|
| 544 | frame_len = (int) |
---|
| 545 | (buffer_desc->status.bm.len); |
---|
| 546 | |
---|
| 547 | /* Update mbuf */ |
---|
[80a7fe6] | 548 | m->m_data = mtod(m, char*)+ETHER_ALIGN; |
---|
| 549 | m->m_len = frame_len; |
---|
| 550 | m->m_pkthdr.len = frame_len; |
---|
| 551 | IF_ATSAM_UNLOCK(sc); |
---|
| 552 | sc->ifp->if_input(ifp, m); |
---|
| 553 | IF_ATSAM_LOCK(sc); |
---|
[b16eca9] | 554 | m = n; |
---|
| 555 | } else { |
---|
[80a7fe6] | 556 | (void)if_atsam_event_send( |
---|
[b16eca9] | 557 | sc->tx_daemon_tid, ATSAMV7_ETH_START_TRANSMIT_EVENT); |
---|
| 558 | } |
---|
| 559 | sc->rx_mbuf[sc->rx_bd_fill_idx] = m; |
---|
| 560 | tmp_rx_bd_address = (uint32_t)m->m_data & |
---|
| 561 | GMAC_RX_BUF_DESC_ADDR_MASK; |
---|
| 562 | |
---|
| 563 | /* Switch pointer to next buffer descriptor */ |
---|
| 564 | if (sc->rx_bd_fill_idx == |
---|
| 565 | (sc->amount_rx_buf - 1)) { |
---|
| 566 | tmp_rx_bd_address |= GMAC_RX_SET_WRAP; |
---|
| 567 | sc->rx_bd_fill_idx = 0; |
---|
| 568 | } else { |
---|
| 569 | ++sc->rx_bd_fill_idx; |
---|
| 570 | } |
---|
| 571 | |
---|
| 572 | /* |
---|
| 573 | * Give ownership to GMAC for further processing |
---|
| 574 | */ |
---|
| 575 | tmp_rx_bd_address &= ~GMAC_RX_SET_USED; |
---|
| 576 | _ARM_Data_synchronization_barrier(); |
---|
| 577 | buffer_desc->addr.val = tmp_rx_bd_address; |
---|
| 578 | |
---|
| 579 | buffer_desc = (sGmacRxDescriptor *)rx_bd_base |
---|
| 580 | + sc->rx_bd_fill_idx; |
---|
| 581 | } |
---|
| 582 | } |
---|
| 583 | /* Setup the interrupts for RX completion and errors */ |
---|
| 584 | GMAC_EnableIt(pHw, GMAC_IER_RCOMP | GMAC_IER_ROVR, 0); |
---|
| 585 | } |
---|
| 586 | } |
---|
| 587 | |
---|
| 588 | /* |
---|
| 589 | * Update of current transmit buffer position. |
---|
| 590 | */ |
---|
| 591 | static void if_atsam_tx_bd_pos_update(size_t *pos, size_t amount_tx_buf) |
---|
| 592 | { |
---|
| 593 | *pos = (*pos + 1) % amount_tx_buf; |
---|
| 594 | } |
---|
| 595 | |
---|
| 596 | /* |
---|
| 597 | * Is RingBuffer empty |
---|
| 598 | */ |
---|
| 599 | static bool if_atsam_ring_buffer_empty(ring_buffer *ring_buffer) |
---|
| 600 | { |
---|
| 601 | return (ring_buffer->tx_bd_used == ring_buffer->tx_bd_free); |
---|
| 602 | } |
---|
| 603 | |
---|
| 604 | /* |
---|
| 605 | * Is RingBuffer full |
---|
| 606 | */ |
---|
| 607 | static bool if_atsam_ring_buffer_full(ring_buffer *ring_buffer) |
---|
| 608 | { |
---|
| 609 | size_t tx_bd_used_next = ring_buffer->tx_bd_used; |
---|
| 610 | |
---|
| 611 | if_atsam_tx_bd_pos_update(&tx_bd_used_next, ring_buffer->length); |
---|
| 612 | return (tx_bd_used_next == ring_buffer->tx_bd_free); |
---|
| 613 | } |
---|
| 614 | |
---|
| 615 | /* |
---|
| 616 | * Cleanup transmit file descriptors by freeing mbufs which are not needed any |
---|
| 617 | * longer due to correct transmission. |
---|
| 618 | */ |
---|
| 619 | static void if_atsam_tx_bd_cleanup(if_atsam_softc *sc) |
---|
| 620 | { |
---|
| 621 | struct mbuf *m; |
---|
| 622 | volatile sGmacTxDescriptor *cur; |
---|
| 623 | bool eof_needed = false; |
---|
| 624 | |
---|
| 625 | while (!if_atsam_ring_buffer_empty(&sc->tx_ring)){ |
---|
| 626 | cur = sc->tx_bd_base + sc->tx_ring.tx_bd_free; |
---|
| 627 | if (((cur->status.bm.bUsed == 1) && !eof_needed) || eof_needed) { |
---|
| 628 | eof_needed = true; |
---|
| 629 | cur->status.val |= GMAC_TX_SET_USED; |
---|
| 630 | m = sc->tx_mbuf[sc->tx_ring.tx_bd_free]; |
---|
| 631 | m_free(m); |
---|
| 632 | sc->tx_mbuf[sc->tx_ring.tx_bd_free] = 0; |
---|
| 633 | if_atsam_tx_bd_pos_update(&sc->tx_ring.tx_bd_free, |
---|
| 634 | sc->tx_ring.length); |
---|
| 635 | if (cur->status.bm.bLastBuffer) { |
---|
| 636 | eof_needed = false; |
---|
| 637 | } |
---|
| 638 | } else { |
---|
| 639 | break; |
---|
| 640 | } |
---|
| 641 | } |
---|
| 642 | } |
---|
| 643 | |
---|
| 644 | /* |
---|
| 645 | * Prepare Ethernet frame to start transmission. |
---|
| 646 | */ |
---|
| 647 | static bool if_atsam_send_packet(if_atsam_softc *sc, struct mbuf *m) |
---|
| 648 | { |
---|
| 649 | volatile sGmacTxDescriptor *cur; |
---|
| 650 | volatile sGmacTxDescriptor *start_packet_tx_bd = 0; |
---|
| 651 | int pos = 0; |
---|
| 652 | uint32_t tmp_val = 0; |
---|
| 653 | Gmac *pHw = sc->Gmac_inst.gGmacd.pHw; |
---|
| 654 | bool success; |
---|
| 655 | |
---|
| 656 | if_atsam_tx_bd_cleanup(sc); |
---|
| 657 | /* Wait for interrupt in case no buffer descriptors are available */ |
---|
| 658 | /* Wait for events */ |
---|
| 659 | while (true) { |
---|
| 660 | if (if_atsam_ring_buffer_full(&sc->tx_ring)) { |
---|
| 661 | /* Setup the interrupts for TX completion and errors */ |
---|
| 662 | GMAC_EnableIt(pHw, GMAC_INT_TX_BITS, 0); |
---|
| 663 | success = false; |
---|
| 664 | break; |
---|
| 665 | } |
---|
| 666 | |
---|
| 667 | /* |
---|
| 668 | * Get current mbuf for data fill |
---|
| 669 | */ |
---|
| 670 | cur = &sc->tx_bd_base[sc->tx_ring.tx_bd_used]; |
---|
| 671 | /* Set the transfer data */ |
---|
| 672 | if (m->m_len) { |
---|
| 673 | uintptr_t cache_adjustment = mtod(m, uintptr_t) % 32; |
---|
| 674 | |
---|
| 675 | rtems_cache_flush_multiple_data_lines( |
---|
| 676 | mtod(m, const char *) - cache_adjustment, |
---|
| 677 | (size_t)(m->m_len + cache_adjustment)); |
---|
| 678 | |
---|
| 679 | cur->addr = mtod(m, uint32_t); |
---|
| 680 | tmp_val = (uint32_t)m->m_len | GMAC_TX_SET_USED; |
---|
| 681 | if (sc->tx_ring.tx_bd_used == (sc->tx_ring.length - 1)) { |
---|
| 682 | tmp_val |= GMAC_TX_SET_WRAP; |
---|
| 683 | } |
---|
| 684 | if (pos == 0) { |
---|
| 685 | start_packet_tx_bd = cur; |
---|
| 686 | } |
---|
| 687 | sc->tx_mbuf[sc->tx_ring.tx_bd_used] = m; |
---|
| 688 | m = m->m_next; |
---|
| 689 | if_atsam_tx_bd_pos_update(&sc->tx_ring.tx_bd_used, |
---|
| 690 | sc->tx_ring.length); |
---|
| 691 | } else { |
---|
| 692 | /* Discard empty mbufs */ |
---|
| 693 | m = m_free(m); |
---|
| 694 | } |
---|
| 695 | |
---|
| 696 | /* |
---|
| 697 | * Send out the buffer once the complete mbuf_chain has been |
---|
| 698 | * processed |
---|
| 699 | */ |
---|
| 700 | if (m == NULL) { |
---|
| 701 | tmp_val |= GMAC_TX_SET_EOF; |
---|
| 702 | tmp_val &= ~GMAC_TX_SET_USED; |
---|
| 703 | _ARM_Data_synchronization_barrier(); |
---|
| 704 | cur->status.val = tmp_val; |
---|
| 705 | start_packet_tx_bd->status.val &= ~GMAC_TX_SET_USED; |
---|
| 706 | _ARM_Data_synchronization_barrier(); |
---|
| 707 | GMAC_TransmissionStart(pHw); |
---|
| 708 | success = true; |
---|
| 709 | break; |
---|
| 710 | } else { |
---|
| 711 | if (pos > 0) { |
---|
| 712 | tmp_val &= ~GMAC_TX_SET_USED; |
---|
| 713 | } |
---|
| 714 | pos++; |
---|
| 715 | cur->status.val = tmp_val; |
---|
| 716 | } |
---|
| 717 | } |
---|
| 718 | return success; |
---|
| 719 | } |
---|
| 720 | |
---|
| 721 | |
---|
| 722 | /* |
---|
| 723 | * Transmit daemon |
---|
| 724 | */ |
---|
| 725 | static void if_atsam_tx_daemon(void *arg) |
---|
| 726 | { |
---|
| 727 | if_atsam_softc *sc = (if_atsam_softc *)arg; |
---|
| 728 | rtems_event_set events = 0; |
---|
| 729 | sGmacTxDescriptor *buffer_desc; |
---|
| 730 | int bd_number; |
---|
| 731 | void *tx_bd_base; |
---|
| 732 | struct mbuf *m; |
---|
| 733 | bool success; |
---|
| 734 | |
---|
[80a7fe6] | 735 | IF_ATSAM_LOCK(sc); |
---|
| 736 | |
---|
[b16eca9] | 737 | Gmac *pHw = sc->Gmac_inst.gGmacd.pHw; |
---|
[80a7fe6] | 738 | struct ifnet *ifp = sc->ifp; |
---|
[b16eca9] | 739 | |
---|
| 740 | GMAC_TransmitEnable(pHw, 0); |
---|
| 741 | |
---|
| 742 | /* Allocate memory space for priority queue descriptor list */ |
---|
| 743 | tx_bd_base = rtems_cache_coherent_allocate(sizeof(sGmacTxDescriptor), |
---|
| 744 | GMAC_DESCRIPTOR_ALIGNMENT, 0); |
---|
| 745 | assert(tx_bd_base != NULL); |
---|
| 746 | |
---|
| 747 | buffer_desc = (sGmacTxDescriptor *)tx_bd_base; |
---|
| 748 | buffer_desc->addr = 0; |
---|
| 749 | buffer_desc->status.val = GMAC_TX_SET_USED | GMAC_TX_SET_WRAP; |
---|
| 750 | |
---|
| 751 | GMAC_SetTxQueue(pHw, (uint32_t)buffer_desc, 1); |
---|
| 752 | GMAC_SetTxQueue(pHw, (uint32_t)buffer_desc, 2); |
---|
| 753 | |
---|
| 754 | /* Allocate memory space for buffer descriptor list */ |
---|
| 755 | tx_bd_base = rtems_cache_coherent_allocate( |
---|
| 756 | sc->amount_tx_buf * sizeof(sGmacTxDescriptor), |
---|
| 757 | GMAC_DESCRIPTOR_ALIGNMENT, 0); |
---|
| 758 | assert(tx_bd_base != NULL); |
---|
| 759 | buffer_desc = (sGmacTxDescriptor *)tx_bd_base; |
---|
| 760 | |
---|
| 761 | /* Create descriptor list and mark as empty */ |
---|
| 762 | for (bd_number = 0; bd_number < sc->amount_tx_buf; bd_number++) { |
---|
| 763 | buffer_desc->addr = 0; |
---|
| 764 | buffer_desc->status.val = GMAC_TX_SET_USED; |
---|
| 765 | if (bd_number == (sc->amount_tx_buf - 1)) { |
---|
| 766 | buffer_desc->status.bm.bWrap = 1; |
---|
| 767 | } else { |
---|
| 768 | buffer_desc++; |
---|
| 769 | } |
---|
| 770 | } |
---|
| 771 | buffer_desc = (sGmacTxDescriptor *)tx_bd_base; |
---|
| 772 | |
---|
| 773 | /* Write Buffer Queue Base Address Register */ |
---|
| 774 | GMAC_SetTxQueue(pHw, (uint32_t)buffer_desc, 0); |
---|
| 775 | |
---|
| 776 | /* Enable Transmission of data */ |
---|
| 777 | GMAC_TransmitEnable(pHw, 1); |
---|
| 778 | |
---|
| 779 | /* Set variables in context */ |
---|
| 780 | sc->tx_bd_base = tx_bd_base; |
---|
| 781 | |
---|
| 782 | while (true) { |
---|
| 783 | /* Wait for events */ |
---|
[80a7fe6] | 784 | if_atsam_event_receive(sc, |
---|
| 785 | ATSAMV7_ETH_START_TRANSMIT_EVENT | |
---|
| 786 | ATSAMV7_ETH_TX_EVENT_INTERRUPT); |
---|
[b16eca9] | 787 | //printf("TX Transmit Event received\n"); |
---|
| 788 | |
---|
| 789 | /* |
---|
| 790 | * Send packets till queue is empty |
---|
| 791 | */ |
---|
| 792 | while (true) { |
---|
| 793 | /* |
---|
| 794 | * Get the mbuf chain to transmit |
---|
| 795 | */ |
---|
| 796 | if_atsam_tx_bd_cleanup(sc); |
---|
[80a7fe6] | 797 | IF_DEQUEUE(&ifp->if_snd, m); |
---|
[b16eca9] | 798 | if (!m) { |
---|
[80a7fe6] | 799 | ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; |
---|
[b16eca9] | 800 | break; |
---|
| 801 | } |
---|
| 802 | success = if_atsam_send_packet(sc, m); |
---|
| 803 | if (!success){ |
---|
| 804 | break; |
---|
| 805 | } |
---|
| 806 | } |
---|
| 807 | } |
---|
| 808 | } |
---|
| 809 | |
---|
| 810 | |
---|
| 811 | /* |
---|
| 812 | * Send packet (caller provides header). |
---|
| 813 | */ |
---|
| 814 | static void if_atsam_enet_start(struct ifnet *ifp) |
---|
| 815 | { |
---|
| 816 | if_atsam_softc *sc = (if_atsam_softc *)ifp->if_softc; |
---|
| 817 | |
---|
[80a7fe6] | 818 | ifp->if_drv_flags |= IFF_DRV_OACTIVE; |
---|
| 819 | if_atsam_event_send(sc->tx_daemon_tid, |
---|
[b16eca9] | 820 | ATSAMV7_ETH_START_TRANSMIT_EVENT); |
---|
| 821 | } |
---|
| 822 | |
---|
| 823 | |
---|
[80a7fe6] | 824 | static void if_atsam_miibus_statchg(device_t dev) |
---|
[b16eca9] | 825 | { |
---|
[80a7fe6] | 826 | uint8_t link_speed = GMAC_SPEED_100M; |
---|
| 827 | uint8_t link_duplex = GMAC_DUPLEX_FULL; |
---|
| 828 | if_atsam_softc *sc = device_get_softc(dev); |
---|
| 829 | struct mii_data *mii = device_get_softc(sc->miibus); |
---|
[b16eca9] | 830 | |
---|
| 831 | Gmac *pHw = sc->Gmac_inst.gGmacd.pHw; |
---|
| 832 | |
---|
[80a7fe6] | 833 | if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) { |
---|
| 834 | link_duplex = GMAC_DUPLEX_FULL; |
---|
| 835 | } else { |
---|
| 836 | link_duplex = GMAC_DUPLEX_HALF; |
---|
[b16eca9] | 837 | } |
---|
[80a7fe6] | 838 | |
---|
| 839 | switch (IFM_SUBTYPE(mii->mii_media_active)) { |
---|
| 840 | case IFM_10_T: |
---|
| 841 | link_speed = GMAC_SPEED_10M; |
---|
| 842 | break; |
---|
| 843 | case IFM_100_TX: |
---|
| 844 | link_speed = GMAC_SPEED_100M; |
---|
| 845 | break; |
---|
| 846 | case IFM_1000_T: |
---|
| 847 | link_speed = GMAC_SPEED_1000M; |
---|
| 848 | break; |
---|
| 849 | default: |
---|
| 850 | /* FIXME: What to do in that case? */ |
---|
| 851 | break; |
---|
| 852 | } |
---|
| 853 | |
---|
| 854 | if (sc->link_speed != link_speed || sc->link_duplex != link_duplex) { |
---|
| 855 | GMAC_SetLinkSpeed(pHw, link_speed, link_duplex); |
---|
| 856 | sc->link_speed = link_speed; |
---|
| 857 | sc->link_duplex = link_duplex; |
---|
[b16eca9] | 858 | } |
---|
[80a7fe6] | 859 | } |
---|
| 860 | |
---|
| 861 | |
---|
| 862 | static int |
---|
| 863 | if_atsam_mii_ifmedia_upd(struct ifnet *ifp) |
---|
| 864 | { |
---|
| 865 | if_atsam_softc *sc; |
---|
| 866 | struct mii_data *mii; |
---|
| 867 | |
---|
| 868 | sc = ifp->if_softc; |
---|
| 869 | if (sc->miibus == NULL) |
---|
| 870 | return (ENXIO); |
---|
| 871 | |
---|
| 872 | mii = device_get_softc(sc->miibus); |
---|
| 873 | return (mii_mediachg(mii)); |
---|
| 874 | } |
---|
| 875 | |
---|
| 876 | |
---|
| 877 | static void |
---|
| 878 | if_atsam_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) |
---|
| 879 | { |
---|
| 880 | if_atsam_softc *sc; |
---|
| 881 | struct mii_data *mii; |
---|
| 882 | |
---|
| 883 | sc = ifp->if_softc; |
---|
| 884 | if (sc->miibus == NULL) |
---|
| 885 | return; |
---|
| 886 | |
---|
| 887 | mii = device_get_softc(sc->miibus); |
---|
| 888 | mii_pollstat(mii); |
---|
| 889 | ifmr->ifm_active = mii->mii_media_active; |
---|
| 890 | ifmr->ifm_status = mii->mii_media_status; |
---|
| 891 | } |
---|
| 892 | |
---|
| 893 | |
---|
| 894 | static void |
---|
[0190cfd] | 895 | if_atsam_tick(void *context) |
---|
[80a7fe6] | 896 | { |
---|
| 897 | if_atsam_softc *sc = context; |
---|
| 898 | |
---|
[0190cfd] | 899 | if_atsam_poll_hw_stats(sc); |
---|
[80a7fe6] | 900 | |
---|
| 901 | IF_ATSAM_UNLOCK(sc); |
---|
| 902 | |
---|
| 903 | mii_tick(device_get_softc(sc->miibus)); |
---|
[0190cfd] | 904 | callout_reset(&sc->tick_ch, hz, if_atsam_tick, sc); |
---|
[b16eca9] | 905 | } |
---|
| 906 | |
---|
| 907 | |
---|
| 908 | /* |
---|
| 909 | * Sets up the hardware and chooses the interface to be used |
---|
| 910 | */ |
---|
| 911 | static void if_atsam_init(void *arg) |
---|
| 912 | { |
---|
| 913 | rtems_status_code status; |
---|
| 914 | |
---|
| 915 | if_atsam_softc *sc = (if_atsam_softc *)arg; |
---|
[80a7fe6] | 916 | struct ifnet *ifp = sc->ifp; |
---|
[b16eca9] | 917 | uint32_t dmac_cfg = 0; |
---|
| 918 | uint32_t gmii_val = 0; |
---|
| 919 | |
---|
[80a7fe6] | 920 | if (ifp->if_flags & IFF_DRV_RUNNING) { |
---|
[b16eca9] | 921 | return; |
---|
| 922 | } |
---|
[80a7fe6] | 923 | ifp->if_flags |= IFF_DRV_RUNNING; |
---|
[b16eca9] | 924 | sc->interrupt_number = GMAC_IRQn; |
---|
| 925 | |
---|
| 926 | /* Disable Watchdog */ |
---|
| 927 | WDT_Disable(WDT); |
---|
| 928 | |
---|
| 929 | /* Enable Peripheral Clock */ |
---|
| 930 | if ((PMC->PMC_PCSR1 & (1u << 7)) != (1u << 7)) { |
---|
| 931 | PMC->PMC_PCER1 = 1 << 7; |
---|
| 932 | } |
---|
| 933 | /* Setup interrupts */ |
---|
| 934 | NVIC_ClearPendingIRQ(GMAC_IRQn); |
---|
| 935 | NVIC_EnableIRQ(GMAC_IRQn); |
---|
| 936 | |
---|
| 937 | /* Configuration of DMAC */ |
---|
| 938 | dmac_cfg = (GMAC_DCFGR_DRBS(GMAC_RX_BUFFER_SIZE >> 6)) | |
---|
| 939 | GMAC_DCFGR_RXBMS(3) | GMAC_DCFGR_TXPBMS | GMAC_DCFGR_FBLDO_INCR16; |
---|
| 940 | GMAC_SetDMAConfig(sc->Gmac_inst.gGmacd.pHw, dmac_cfg, 0); |
---|
| 941 | |
---|
| 942 | /* Shut down Transmit and Receive */ |
---|
| 943 | GMAC_ReceiveEnable(sc->Gmac_inst.gGmacd.pHw, 0); |
---|
| 944 | GMAC_TransmitEnable(sc->Gmac_inst.gGmacd.pHw, 0); |
---|
| 945 | |
---|
| 946 | GMAC_StatisticsWriteEnable(sc->Gmac_inst.gGmacd.pHw, 1); |
---|
| 947 | |
---|
| 948 | /* |
---|
| 949 | * Allocate mbuf pointers |
---|
| 950 | */ |
---|
| 951 | sc->rx_mbuf = malloc(sc->amount_rx_buf * sizeof *sc->rx_mbuf, |
---|
[80a7fe6] | 952 | M_TEMP, M_NOWAIT); |
---|
[b16eca9] | 953 | sc->tx_mbuf = malloc(sc->amount_tx_buf * sizeof *sc->tx_mbuf, |
---|
[80a7fe6] | 954 | M_TEMP, M_NOWAIT); |
---|
[b16eca9] | 955 | |
---|
| 956 | /* Install interrupt handler */ |
---|
| 957 | status = rtems_interrupt_handler_install(sc->interrupt_number, |
---|
| 958 | "Ethernet", |
---|
| 959 | RTEMS_INTERRUPT_UNIQUE, |
---|
| 960 | if_atsam_interrupt_handler, |
---|
| 961 | sc); |
---|
| 962 | assert(status == RTEMS_SUCCESSFUL); |
---|
| 963 | |
---|
| 964 | /* |
---|
| 965 | * Start driver tasks |
---|
| 966 | */ |
---|
| 967 | sc->rx_daemon_tid = rtems_bsdnet_newproc("SCrx", 4096, |
---|
| 968 | if_atsam_rx_daemon, sc); |
---|
| 969 | sc->tx_daemon_tid = rtems_bsdnet_newproc("SCtx", 4096, |
---|
| 970 | if_atsam_tx_daemon, sc); |
---|
| 971 | |
---|
[0190cfd] | 972 | callout_reset(&sc->tick_ch, hz, if_atsam_tick, sc); |
---|
[80a7fe6] | 973 | |
---|
| 974 | ifp->if_drv_flags |= IFF_DRV_RUNNING; |
---|
[b16eca9] | 975 | } |
---|
| 976 | |
---|
| 977 | |
---|
| 978 | /* |
---|
| 979 | * Stop the device |
---|
| 980 | */ |
---|
| 981 | static void if_atsam_stop(struct if_atsam_softc *sc) |
---|
| 982 | { |
---|
[80a7fe6] | 983 | struct ifnet *ifp = sc->ifp; |
---|
[b16eca9] | 984 | Gmac *pHw = sc->Gmac_inst.gGmacd.pHw; |
---|
| 985 | |
---|
[80a7fe6] | 986 | ifp->if_flags &= ~IFF_DRV_RUNNING; |
---|
[b16eca9] | 987 | |
---|
| 988 | /* Disable MDIO interface and TX/RX */ |
---|
| 989 | pHw->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); |
---|
| 990 | pHw->GMAC_NCR &= ~GMAC_NCR_MPE; |
---|
| 991 | } |
---|
| 992 | |
---|
| 993 | |
---|
[0190cfd] | 994 | static void |
---|
| 995 | if_atsam_poll_hw_stats(struct if_atsam_softc *sc) |
---|
[b16eca9] | 996 | { |
---|
[0190cfd] | 997 | uint64_t octets; |
---|
| 998 | Gmac *pHw = sc->Gmac_inst.gGmacd.pHw; |
---|
| 999 | |
---|
| 1000 | octets = pHw->GMAC_OTLO; |
---|
| 1001 | octets |= pHw->GMAC_OTHI << 32; |
---|
| 1002 | sc->stats.octets_transm += octets; |
---|
| 1003 | sc->stats.frames_transm += pHw->GMAC_FT; |
---|
| 1004 | sc->stats.broadcast_frames_transm += pHw->GMAC_BCFT; |
---|
| 1005 | sc->stats.multicast_frames_transm += pHw->GMAC_MFT; |
---|
| 1006 | sc->stats.pause_frames_transm += pHw->GMAC_PFT; |
---|
| 1007 | sc->stats.frames_64_byte_transm += pHw->GMAC_BFT64; |
---|
| 1008 | sc->stats.frames_65_to_127_byte_transm += pHw->GMAC_TBFT127; |
---|
| 1009 | sc->stats.frames_128_to_255_byte_transm += pHw->GMAC_TBFT255; |
---|
| 1010 | sc->stats.frames_256_to_511_byte_transm += pHw->GMAC_TBFT511; |
---|
| 1011 | sc->stats.frames_512_to_1023_byte_transm += pHw->GMAC_TBFT1023; |
---|
| 1012 | sc->stats.frames_1024_to_1518_byte_transm += pHw->GMAC_TBFT1518; |
---|
| 1013 | sc->stats.frames_greater_1518_byte_transm += pHw->GMAC_GTBFT1518; |
---|
| 1014 | sc->stats.transmit_underruns += pHw->GMAC_TUR; |
---|
| 1015 | sc->stats.single_collision_frames += pHw->GMAC_SCF; |
---|
| 1016 | sc->stats.multiple_collision_frames += pHw->GMAC_MCF; |
---|
| 1017 | sc->stats.excessive_collisions += pHw->GMAC_EC; |
---|
| 1018 | sc->stats.late_collisions += pHw->GMAC_LC; |
---|
| 1019 | sc->stats.deferred_transmission_frames += pHw->GMAC_DTF; |
---|
| 1020 | sc->stats.carrier_sense_errors += pHw->GMAC_CSE; |
---|
| 1021 | |
---|
| 1022 | octets = pHw->GMAC_ORLO; |
---|
| 1023 | octets |= pHw->GMAC_ORHI << 32; |
---|
| 1024 | sc->stats.octets_rec += octets; |
---|
| 1025 | sc->stats.frames_rec += pHw->GMAC_FR; |
---|
| 1026 | sc->stats.broadcast_frames_rec += pHw->GMAC_BCFR; |
---|
| 1027 | sc->stats.multicast_frames_rec += pHw->GMAC_MFR; |
---|
| 1028 | sc->stats.pause_frames_rec += pHw->GMAC_PFR; |
---|
| 1029 | sc->stats.frames_64_byte_rec += pHw->GMAC_BFR64; |
---|
| 1030 | sc->stats.frames_65_to_127_byte_rec += pHw->GMAC_TBFR127; |
---|
| 1031 | sc->stats.frames_128_to_255_byte_rec += pHw->GMAC_TBFR255; |
---|
| 1032 | sc->stats.frames_256_to_511_byte_rec += pHw->GMAC_TBFR511; |
---|
| 1033 | sc->stats.frames_512_to_1023_byte_rec += pHw->GMAC_TBFR1023; |
---|
| 1034 | sc->stats.frames_1024_to_1518_byte_rec += pHw->GMAC_TBFR1518; |
---|
| 1035 | sc->stats.frames_1519_to_maximum_byte_rec += pHw->GMAC_TMXBFR; |
---|
| 1036 | sc->stats.undersize_frames_rec += pHw->GMAC_UFR; |
---|
| 1037 | sc->stats.oversize_frames_rec += pHw->GMAC_OFR; |
---|
| 1038 | sc->stats.jabbers_rec += pHw->GMAC_JR; |
---|
| 1039 | sc->stats.frame_check_sequence_errors += pHw->GMAC_FCSE; |
---|
| 1040 | sc->stats.length_field_frame_errors += pHw->GMAC_LFFE; |
---|
| 1041 | sc->stats.receive_symbol_errors += pHw->GMAC_RSE; |
---|
| 1042 | sc->stats.alignment_errors += pHw->GMAC_AE; |
---|
| 1043 | sc->stats.receive_resource_errors += pHw->GMAC_RRE; |
---|
| 1044 | sc->stats.receive_overrun += pHw->GMAC_ROE; |
---|
| 1045 | |
---|
| 1046 | sc->stats.ip_header_checksum_errors += pHw->GMAC_IHCE; |
---|
| 1047 | sc->stats.tcp_checksum_errors += pHw->GMAC_TCE; |
---|
| 1048 | sc->stats.udp_checksum_errors += pHw->GMAC_UCE; |
---|
| 1049 | } |
---|
| 1050 | |
---|
| 1051 | |
---|
| 1052 | static void |
---|
| 1053 | if_atsam_add_sysctls(device_t dev) |
---|
| 1054 | { |
---|
| 1055 | struct if_atsam_softc *sc = device_get_softc(dev); |
---|
| 1056 | struct sysctl_ctx_list *ctx; |
---|
| 1057 | struct sysctl_oid_list *statsnode; |
---|
| 1058 | struct sysctl_oid_list *hwstatsnode; |
---|
| 1059 | struct sysctl_oid_list *child; |
---|
| 1060 | struct sysctl_oid *tree; |
---|
| 1061 | |
---|
| 1062 | ctx = device_get_sysctl_ctx(dev); |
---|
| 1063 | child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); |
---|
| 1064 | |
---|
| 1065 | tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, |
---|
| 1066 | NULL, "if_atsam statistics"); |
---|
| 1067 | statsnode = SYSCTL_CHILDREN(tree); |
---|
| 1068 | |
---|
| 1069 | tree = SYSCTL_ADD_NODE(ctx, statsnode, OID_AUTO, "sw", CTLFLAG_RD, |
---|
| 1070 | NULL, "if_atsam software statistics"); |
---|
| 1071 | child = SYSCTL_CHILDREN(tree); |
---|
| 1072 | |
---|
| 1073 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_overrun_errors", |
---|
| 1074 | CTLFLAG_RD, &sc->stats.rx_overrun_errors, 0, |
---|
| 1075 | "RX overrun errors"); |
---|
| 1076 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_interrupts", |
---|
| 1077 | CTLFLAG_RD, &sc->stats.rx_interrupts, 0, |
---|
| 1078 | "Rx interrupts"); |
---|
| 1079 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_complete_int", |
---|
| 1080 | CTLFLAG_RD, &sc->stats.tx_complete_int, 0, |
---|
| 1081 | "Tx complete interrupts"); |
---|
| 1082 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_tur_errors", |
---|
| 1083 | CTLFLAG_RD, &sc->stats.tx_tur_errors, 0, |
---|
| 1084 | "Error Tur Tx interrupts"); |
---|
| 1085 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_rlex_errors", |
---|
| 1086 | CTLFLAG_RD, &sc->stats.tx_rlex_errors, 0, |
---|
| 1087 | "Error Rlex Tx interrupts"); |
---|
| 1088 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_tfc_errors", |
---|
| 1089 | CTLFLAG_RD, &sc->stats.tx_tfc_errors, 0, |
---|
| 1090 | "Error Tfc Tx interrupts"); |
---|
| 1091 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_hresp_errors", |
---|
| 1092 | CTLFLAG_RD, &sc->stats.tx_hresp_errors, 0, |
---|
| 1093 | "Error Hresp Tx interrupts"); |
---|
| 1094 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_interrupts", |
---|
| 1095 | CTLFLAG_RD, &sc->stats.tx_interrupts, 0, |
---|
| 1096 | "Tx interrupts"); |
---|
| 1097 | |
---|
| 1098 | tree = SYSCTL_ADD_NODE(ctx, statsnode, OID_AUTO, "hw", CTLFLAG_RD, |
---|
| 1099 | NULL, "if_atsam hardware statistics"); |
---|
| 1100 | hwstatsnode = SYSCTL_CHILDREN(tree); |
---|
| 1101 | |
---|
| 1102 | tree = SYSCTL_ADD_NODE(ctx, hwstatsnode, OID_AUTO, "tx", CTLFLAG_RD, |
---|
| 1103 | NULL, "if_atsam hardware transmit statistics"); |
---|
| 1104 | child = SYSCTL_CHILDREN(tree); |
---|
| 1105 | |
---|
| 1106 | SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "octets_transm", |
---|
| 1107 | CTLFLAG_RD, &sc->stats.octets_transm, |
---|
| 1108 | "Octets Transmitted"); |
---|
| 1109 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_transm", |
---|
| 1110 | CTLFLAG_RD, &sc->stats.frames_transm, 0, |
---|
| 1111 | "Frames Transmitted"); |
---|
| 1112 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "broadcast_frames_transm", |
---|
| 1113 | CTLFLAG_RD, &sc->stats.broadcast_frames_transm, 0, |
---|
| 1114 | "Broadcast Frames Transmitted"); |
---|
| 1115 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "multicast_frames_transm", |
---|
| 1116 | CTLFLAG_RD, &sc->stats.multicast_frames_transm, 0, |
---|
| 1117 | "Multicast Frames Transmitted"); |
---|
| 1118 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "pause_frames_transm", |
---|
| 1119 | CTLFLAG_RD, &sc->stats.pause_frames_transm, 0, |
---|
| 1120 | "Pause Frames Transmitted"); |
---|
| 1121 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_64_byte_transm", |
---|
| 1122 | CTLFLAG_RD, &sc->stats.frames_64_byte_transm, 0, |
---|
| 1123 | "64 Byte Frames Transmitted"); |
---|
| 1124 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_65_to_127_byte_transm", |
---|
| 1125 | CTLFLAG_RD, &sc->stats.frames_65_to_127_byte_transm, 0, |
---|
| 1126 | "65 to 127 Byte Frames Transmitted"); |
---|
| 1127 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_128_to_255_byte_transm", |
---|
| 1128 | CTLFLAG_RD, &sc->stats.frames_128_to_255_byte_transm, 0, |
---|
| 1129 | "128 to 255 Byte Frames Transmitted"); |
---|
| 1130 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_256_to_511_byte_transm", |
---|
| 1131 | CTLFLAG_RD, &sc->stats.frames_256_to_511_byte_transm, 0, |
---|
| 1132 | "256 to 511 Byte Frames Transmitted"); |
---|
| 1133 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_512_to_1023_byte_transm", |
---|
| 1134 | CTLFLAG_RD, &sc->stats.frames_512_to_1023_byte_transm, 0, |
---|
| 1135 | "512 to 1023 Byte Frames Transmitted"); |
---|
| 1136 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_1024_to_1518_byte_transm", |
---|
| 1137 | CTLFLAG_RD, &sc->stats.frames_1024_to_1518_byte_transm, 0, |
---|
| 1138 | "1024 to 1518 Byte Frames Transmitted"); |
---|
| 1139 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_greater_1518_byte_transm", |
---|
| 1140 | CTLFLAG_RD, &sc->stats.frames_greater_1518_byte_transm, 0, |
---|
| 1141 | "Greater Than 1518 Byte Frames Transmitted"); |
---|
| 1142 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "transmit_underruns", |
---|
| 1143 | CTLFLAG_RD, &sc->stats.transmit_underruns, 0, |
---|
| 1144 | "Transmit Underruns"); |
---|
| 1145 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "single_collision_frames", |
---|
| 1146 | CTLFLAG_RD, &sc->stats.single_collision_frames, 0, |
---|
| 1147 | "Single Collision Frames"); |
---|
| 1148 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "multiple_collision_frames", |
---|
| 1149 | CTLFLAG_RD, &sc->stats.multiple_collision_frames, 0, |
---|
| 1150 | "Multiple Collision Frames"); |
---|
| 1151 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "excessive_collisions", |
---|
| 1152 | CTLFLAG_RD, &sc->stats.excessive_collisions, 0, |
---|
| 1153 | "Excessive Collisions"); |
---|
| 1154 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "late_collisions", |
---|
| 1155 | CTLFLAG_RD, &sc->stats.late_collisions, 0, |
---|
| 1156 | "Late Collisions"); |
---|
| 1157 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "deferred_transmission_frames", |
---|
| 1158 | CTLFLAG_RD, &sc->stats.deferred_transmission_frames, 0, |
---|
| 1159 | "Deferred Transmission Frames"); |
---|
| 1160 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "carrier_sense_errors", |
---|
| 1161 | CTLFLAG_RD, &sc->stats.carrier_sense_errors, 0, |
---|
| 1162 | "Carrier Sense Errors"); |
---|
| 1163 | |
---|
| 1164 | tree = SYSCTL_ADD_NODE(ctx, hwstatsnode, OID_AUTO, "rx", CTLFLAG_RD, |
---|
| 1165 | NULL, "if_atsam hardware receive statistics"); |
---|
| 1166 | child = SYSCTL_CHILDREN(tree); |
---|
| 1167 | |
---|
| 1168 | SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "octets_rec", |
---|
| 1169 | CTLFLAG_RD, &sc->stats.octets_rec, |
---|
| 1170 | "Octets Received"); |
---|
| 1171 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_rec", |
---|
| 1172 | CTLFLAG_RD, &sc->stats.frames_rec, 0, |
---|
| 1173 | "Frames Received"); |
---|
| 1174 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "broadcast_frames_rec", |
---|
| 1175 | CTLFLAG_RD, &sc->stats.broadcast_frames_rec, 0, |
---|
| 1176 | "Broadcast Frames Received"); |
---|
| 1177 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "multicast_frames_rec", |
---|
| 1178 | CTLFLAG_RD, &sc->stats.multicast_frames_rec, 0, |
---|
| 1179 | "Multicast Frames Received"); |
---|
| 1180 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "pause_frames_rec", |
---|
| 1181 | CTLFLAG_RD, &sc->stats.pause_frames_rec, 0, |
---|
| 1182 | "Pause Frames Received"); |
---|
| 1183 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_64_byte_rec", |
---|
| 1184 | CTLFLAG_RD, &sc->stats.frames_64_byte_rec, 0, |
---|
| 1185 | "64 Byte Frames Received"); |
---|
| 1186 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_65_to_127_byte_rec", |
---|
| 1187 | CTLFLAG_RD, &sc->stats.frames_65_to_127_byte_rec, 0, |
---|
| 1188 | "65 to 127 Byte Frames Received"); |
---|
| 1189 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_128_to_255_byte_rec", |
---|
| 1190 | CTLFLAG_RD, &sc->stats.frames_128_to_255_byte_rec, 0, |
---|
| 1191 | "128 to 255 Byte Frames Received"); |
---|
| 1192 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_256_to_511_byte_rec", |
---|
| 1193 | CTLFLAG_RD, &sc->stats.frames_256_to_511_byte_rec, 0, |
---|
| 1194 | "256 to 511 Byte Frames Received"); |
---|
| 1195 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_512_to_1023_byte_rec", |
---|
| 1196 | CTLFLAG_RD, &sc->stats.frames_512_to_1023_byte_rec, 0, |
---|
| 1197 | "512 to 1023 Byte Frames Received"); |
---|
| 1198 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_1024_to_1518_byte_rec", |
---|
| 1199 | CTLFLAG_RD, &sc->stats.frames_1024_to_1518_byte_rec, 0, |
---|
| 1200 | "1024 to 1518 Byte Frames Received"); |
---|
| 1201 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frames_1519_to_maximum_byte_rec", |
---|
| 1202 | CTLFLAG_RD, &sc->stats.frames_1519_to_maximum_byte_rec, 0, |
---|
| 1203 | "1519 to Maximum Byte Frames Received"); |
---|
| 1204 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "undersize_frames_rec", |
---|
| 1205 | CTLFLAG_RD, &sc->stats.undersize_frames_rec, 0, |
---|
| 1206 | "Undersize Frames Received"); |
---|
| 1207 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "oversize_frames_rec", |
---|
| 1208 | CTLFLAG_RD, &sc->stats.oversize_frames_rec, 0, |
---|
| 1209 | "Oversize Frames Received"); |
---|
| 1210 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "jabbers_rec", |
---|
| 1211 | CTLFLAG_RD, &sc->stats.jabbers_rec, 0, |
---|
| 1212 | "Jabbers Received"); |
---|
| 1213 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "frame_check_sequence_errors", |
---|
| 1214 | CTLFLAG_RD, &sc->stats.frame_check_sequence_errors, 0, |
---|
| 1215 | "Frame Check Sequence Errors"); |
---|
| 1216 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "length_field_frame_errors", |
---|
| 1217 | CTLFLAG_RD, &sc->stats.length_field_frame_errors, 0, |
---|
| 1218 | "Length Field Frame Errors"); |
---|
| 1219 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "receive_symbol_errors", |
---|
| 1220 | CTLFLAG_RD, &sc->stats.receive_symbol_errors, 0, |
---|
| 1221 | "Receive Symbol Errors"); |
---|
| 1222 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "alignment_errors", |
---|
| 1223 | CTLFLAG_RD, &sc->stats.alignment_errors, 0, |
---|
| 1224 | "Alignment Errors"); |
---|
| 1225 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "receive_resource_errors", |
---|
| 1226 | CTLFLAG_RD, &sc->stats.receive_resource_errors, 0, |
---|
| 1227 | "Receive Resource Errors"); |
---|
| 1228 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "receive_overrun", |
---|
| 1229 | CTLFLAG_RD, &sc->stats.receive_overrun, 0, |
---|
| 1230 | "Receive Overrun"); |
---|
| 1231 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ip_header_checksum_errors", |
---|
| 1232 | CTLFLAG_RD, &sc->stats.ip_header_checksum_errors, 0, |
---|
| 1233 | "IP Header Checksum Errors"); |
---|
| 1234 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tcp_checksum_errors", |
---|
| 1235 | CTLFLAG_RD, &sc->stats.tcp_checksum_errors, 0, |
---|
| 1236 | "TCP Checksum Errors"); |
---|
| 1237 | SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "udp_checksum_errors", |
---|
| 1238 | CTLFLAG_RD, &sc->stats.udp_checksum_errors, 0, |
---|
| 1239 | "UDP Checksum Errors"); |
---|
[b16eca9] | 1240 | } |
---|
| 1241 | |
---|
| 1242 | |
---|
| 1243 | /* |
---|
| 1244 | * Calculates the index that is to be sent into the hash registers |
---|
| 1245 | */ |
---|
| 1246 | static void if_atsam_get_hash_index(uint64_t addr, uint32_t *val) |
---|
| 1247 | { |
---|
| 1248 | uint64_t tmp_val; |
---|
| 1249 | uint8_t i, j; |
---|
| 1250 | uint64_t idx; |
---|
| 1251 | int offset = 0; |
---|
| 1252 | |
---|
| 1253 | addr &= MAC_ADDR_MASK; |
---|
| 1254 | |
---|
| 1255 | for (i = 0; i < HASH_INDEX_AMOUNT; ++i) { |
---|
| 1256 | tmp_val = 0; |
---|
| 1257 | offset = 0; |
---|
| 1258 | for (j = 0; j < HASH_ELEMENTS_PER_INDEX; j++) { |
---|
| 1259 | idx = (addr >> (offset + i)) & MAC_IDX_MASK; |
---|
| 1260 | tmp_val ^= idx; |
---|
| 1261 | offset += HASH_INDEX_AMOUNT; |
---|
| 1262 | } |
---|
| 1263 | if (tmp_val > 0) { |
---|
| 1264 | *val |= (1u << i); |
---|
| 1265 | } |
---|
| 1266 | } |
---|
| 1267 | } |
---|
| 1268 | |
---|
| 1269 | |
---|
| 1270 | /* |
---|
| 1271 | * Dis/Enable promiscuous Mode |
---|
| 1272 | */ |
---|
| 1273 | static void if_atsam_promiscuous_mode(if_atsam_softc *sc, bool enable) |
---|
| 1274 | { |
---|
| 1275 | Gmac *pHw = sc->Gmac_inst.gGmacd.pHw; |
---|
| 1276 | |
---|
| 1277 | if (enable) { |
---|
| 1278 | pHw->GMAC_NCFGR |= GMAC_PROM_ENABLE; |
---|
| 1279 | } else { |
---|
| 1280 | pHw->GMAC_NCFGR &= ~GMAC_PROM_ENABLE; |
---|
| 1281 | } |
---|
| 1282 | } |
---|
| 1283 | |
---|
| 1284 | |
---|
| 1285 | static int |
---|
[80a7fe6] | 1286 | if_atsam_mediaioctl(if_atsam_softc *sc, struct ifreq *ifr, u_long command) |
---|
[b16eca9] | 1287 | { |
---|
[80a7fe6] | 1288 | struct mii_data *mii; |
---|
[b16eca9] | 1289 | |
---|
[80a7fe6] | 1290 | if (sc->miibus == NULL) |
---|
| 1291 | return (EINVAL); |
---|
[b16eca9] | 1292 | |
---|
[80a7fe6] | 1293 | mii = device_get_softc(sc->miibus); |
---|
| 1294 | return (ifmedia_ioctl(sc->ifp, ifr, &mii->mii_media, command)); |
---|
[b16eca9] | 1295 | } |
---|
| 1296 | |
---|
| 1297 | |
---|
| 1298 | /* |
---|
| 1299 | * Driver ioctl handler |
---|
| 1300 | */ |
---|
| 1301 | static int |
---|
| 1302 | if_atsam_ioctl(struct ifnet *ifp, ioctl_command_t command, caddr_t data) |
---|
| 1303 | { |
---|
[80a7fe6] | 1304 | if_atsam_softc *sc = (if_atsam_softc *)ifp->if_softc; |
---|
[b16eca9] | 1305 | struct ifreq *ifr = (struct ifreq *)data; |
---|
| 1306 | int rv = 0; |
---|
| 1307 | bool prom_enable; |
---|
[80a7fe6] | 1308 | struct mii_data *mii; |
---|
[b16eca9] | 1309 | |
---|
| 1310 | switch (command) { |
---|
| 1311 | case SIOCGIFMEDIA: |
---|
| 1312 | case SIOCSIFMEDIA: |
---|
[80a7fe6] | 1313 | rv = if_atsam_mediaioctl(sc, ifr, command); |
---|
[b16eca9] | 1314 | break; |
---|
| 1315 | case SIOCSIFFLAGS: |
---|
| 1316 | if (ifp->if_flags & IFF_UP) { |
---|
[80a7fe6] | 1317 | if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { |
---|
[b16eca9] | 1318 | if_atsam_init(sc); |
---|
| 1319 | } |
---|
| 1320 | prom_enable = ((ifp->if_flags & IFF_PROMISC) != 0); |
---|
| 1321 | if_atsam_promiscuous_mode(sc, prom_enable); |
---|
| 1322 | } else { |
---|
[80a7fe6] | 1323 | if (ifp->if_drv_flags & IFF_DRV_RUNNING) { |
---|
[b16eca9] | 1324 | if_atsam_stop(sc); |
---|
| 1325 | } |
---|
| 1326 | } |
---|
| 1327 | break; |
---|
| 1328 | default: |
---|
[80a7fe6] | 1329 | rv = ether_ioctl(ifp, command, data); |
---|
[b16eca9] | 1330 | break; |
---|
| 1331 | } |
---|
| 1332 | return (rv); |
---|
| 1333 | } |
---|
| 1334 | |
---|
| 1335 | /* |
---|
| 1336 | * Attach an SAMV71 driver to the system |
---|
| 1337 | */ |
---|
[80a7fe6] | 1338 | static int if_atsam_driver_attach(device_t dev) |
---|
[b16eca9] | 1339 | { |
---|
[80a7fe6] | 1340 | if_atsam_softc *sc; |
---|
| 1341 | struct ifnet *ifp; |
---|
| 1342 | int unit; |
---|
[b16eca9] | 1343 | char *unitName; |
---|
[80a7fe6] | 1344 | uint8_t eaddr[ETHER_ADDR_LEN]; |
---|
[b16eca9] | 1345 | |
---|
[80a7fe6] | 1346 | sc = device_get_softc(dev); |
---|
| 1347 | unit = device_get_unit(dev); |
---|
| 1348 | assert(unit == 0); |
---|
[b16eca9] | 1349 | |
---|
[80a7fe6] | 1350 | sc->dev = dev; |
---|
| 1351 | sc->ifp = ifp = if_alloc(IFT_ETHER); |
---|
[b16eca9] | 1352 | |
---|
[80a7fe6] | 1353 | mtx_init(&sc->mtx, device_get_nameunit(sc->dev), MTX_NETWORK_LOCK, |
---|
| 1354 | MTX_DEF); |
---|
[b16eca9] | 1355 | |
---|
[80a7fe6] | 1356 | rtems_bsd_get_mac_address(device_get_name(sc->dev), unit, eaddr); |
---|
[b16eca9] | 1357 | |
---|
[80a7fe6] | 1358 | sc->Gmac_inst.retries = MDIO_RETRIES; |
---|
[b16eca9] | 1359 | |
---|
[80a7fe6] | 1360 | memcpy(sc->GMacAddress, eaddr, ETHER_ADDR_LEN); |
---|
[b16eca9] | 1361 | |
---|
[80a7fe6] | 1362 | sc->amount_rx_buf = RXBUF_COUNT; |
---|
| 1363 | sc->amount_tx_buf = TXBUF_COUNT; |
---|
[b16eca9] | 1364 | |
---|
| 1365 | sc->tx_ring.tx_bd_used = 0; |
---|
| 1366 | sc->tx_ring.tx_bd_free = 0; |
---|
| 1367 | sc->tx_ring.length = sc->amount_tx_buf; |
---|
| 1368 | |
---|
[80a7fe6] | 1369 | /* Set Initial Link Speed */ |
---|
| 1370 | sc->link_speed = GMAC_SPEED_100M; |
---|
| 1371 | sc->link_duplex = GMAC_DUPLEX_FULL; |
---|
| 1372 | |
---|
| 1373 | GMACD_Init(&sc->Gmac_inst.gGmacd, GMAC, ID_GMAC, GMAC_CAF_ENABLE, |
---|
| 1374 | GMAC_NBC_DISABLE); |
---|
| 1375 | |
---|
| 1376 | /* Enable MDIO interface */ |
---|
| 1377 | GMAC_EnableMdio(sc->Gmac_inst.gGmacd.pHw); |
---|
| 1378 | |
---|
| 1379 | /* PHY initialize */ |
---|
| 1380 | if_atsam_init_phy(&sc->Gmac_inst, BOARD_MCK, NULL, 0, |
---|
| 1381 | gmacPins, PIO_LISTSIZE(gmacPins)); |
---|
| 1382 | |
---|
| 1383 | /* |
---|
| 1384 | * MII Bus |
---|
| 1385 | */ |
---|
[0190cfd] | 1386 | callout_init_mtx(&sc->tick_ch, &sc->mtx, CALLOUT_RETURNUNLOCKED); |
---|
[80a7fe6] | 1387 | mii_attach(dev, &sc->miibus, ifp, |
---|
| 1388 | if_atsam_mii_ifmedia_upd, if_atsam_mii_ifmedia_sts, BMSR_DEFCAPMASK, |
---|
| 1389 | MDIO_PHY, MII_OFFSET_ANY, 0); |
---|
| 1390 | |
---|
[b16eca9] | 1391 | /* |
---|
| 1392 | * Set up network interface values |
---|
| 1393 | */ |
---|
| 1394 | ifp->if_softc = sc; |
---|
[80a7fe6] | 1395 | if_initname(ifp, device_get_name(dev), device_get_unit(dev)); |
---|
[b16eca9] | 1396 | ifp->if_init = if_atsam_init; |
---|
| 1397 | ifp->if_ioctl = if_atsam_ioctl; |
---|
| 1398 | ifp->if_start = if_atsam_enet_start; |
---|
[80a7fe6] | 1399 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; |
---|
| 1400 | IFQ_SET_MAXLEN(&ifp->if_snd, TXBUF_COUNT - 1); |
---|
| 1401 | ifp->if_snd.ifq_drv_maxlen = TXBUF_COUNT - 1; |
---|
| 1402 | IFQ_SET_READY(&ifp->if_snd); |
---|
[b16eca9] | 1403 | |
---|
| 1404 | /* |
---|
| 1405 | * Attach the interface |
---|
| 1406 | */ |
---|
[80a7fe6] | 1407 | ether_ifattach(ifp, eaddr); |
---|
[b16eca9] | 1408 | |
---|
[0190cfd] | 1409 | if_atsam_add_sysctls(dev); |
---|
| 1410 | |
---|
[80a7fe6] | 1411 | return (0); |
---|
| 1412 | } |
---|
[b16eca9] | 1413 | |
---|
[80a7fe6] | 1414 | static int |
---|
| 1415 | if_atsam_probe(device_t dev) |
---|
[b16eca9] | 1416 | { |
---|
[80a7fe6] | 1417 | int unit = device_get_unit(dev); |
---|
| 1418 | int error; |
---|
| 1419 | |
---|
| 1420 | if (unit >= 0 && unit < NIFACES) { |
---|
| 1421 | error = BUS_PROBE_DEFAULT; |
---|
| 1422 | } else { |
---|
| 1423 | error = ENXIO; |
---|
| 1424 | } |
---|
| 1425 | |
---|
| 1426 | return (error); |
---|
[b16eca9] | 1427 | } |
---|
[80a7fe6] | 1428 | |
---|
| 1429 | static device_method_t if_atsam_methods[] = { |
---|
| 1430 | DEVMETHOD(device_probe, if_atsam_probe), |
---|
| 1431 | DEVMETHOD(device_attach, if_atsam_driver_attach), |
---|
| 1432 | DEVMETHOD(miibus_readreg, if_atsam_miibus_readreg), |
---|
| 1433 | DEVMETHOD(miibus_writereg, if_atsam_miibus_writereg), |
---|
| 1434 | DEVMETHOD(miibus_statchg, if_atsam_miibus_statchg), |
---|
| 1435 | DEVMETHOD_END |
---|
| 1436 | }; |
---|
| 1437 | |
---|
| 1438 | static driver_t if_atsam_nexus_driver = { |
---|
| 1439 | "if_atsam", |
---|
| 1440 | if_atsam_methods, |
---|
| 1441 | sizeof(struct if_atsam_softc) |
---|
| 1442 | }; |
---|
| 1443 | |
---|
| 1444 | static devclass_t if_atsam_devclass; |
---|
| 1445 | DRIVER_MODULE(if_atsam, nexus, if_atsam_nexus_driver, if_atsam_devclass, 0, 0); |
---|
| 1446 | MODULE_DEPEND(if_atsam, miibus, 1, 1, 1); |
---|
| 1447 | MODULE_DEPEND(if_atsam, nexus, 1, 1, 1); |
---|
| 1448 | MODULE_DEPEND(if_atsam, ether, 1, 1, 1); |
---|
| 1449 | DRIVER_MODULE(miibus, if_atsam, miibus_driver, miibus_devclass, NULL, NULL); |
---|
| 1450 | |
---|
| 1451 | #endif /* LIBBSP_ARM_ATSAM_BSP_H */ |
---|