source: rtems-libbsd/rtemsbsd/sys/arm64/xilinx/versal_slcr.h @ 25a8832

6-freebsd-12
Last change on this file since 25a8832 was 25a8832, checked in by Chris Johns <chrisj@…>, on Oct 20, 2021 at 3:15:28 AM

Add support for Xilinx Versal APAC

  • Property mode set to 100644
File size: 3.6 KB
Line 
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2021 Chris Johns <chrisj@rtems.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * Defines for Xilinx Versal ACAP SLCR registers.
31 *
32 * Reference:
33 *  https://www.xilinx.com/html_docs/registers/am012/mod___crl.html
34 */
35
36#ifndef _VERSAL_SLCR_H_
37#define _VERSAL_SLCR_H_
38
39#define VERSAL_SLCR_CRF_OFFSET          0x01260000
40#define VERSAL_SLCR_CRL_OFFSET          0x0f5e0000
41
42/*
43 * PLL controls
44 *
45 * P = PPLL = PMCPLL = PMCPLL_CTRL : PMC PLL Clock
46 * N = NPLL = NOCPLL = NOCPLL_CTRL : NOC PLL Clock
47 * R = RPLL = RPLL_CTRL            : Low Power Domain clock
48 */
49#define VERSAL_SLCR_P_PLL_CTRL          (VERSAL_SLCR_CRF_OFFSET + 0x40)
50#define VERSAL_SLCR_N_PLL_CTRL          (VERSAL_SLCR_CRF_OFFSET + 0x50)
51#define VERSAL_SLCR_R_PLL_CTRL          (VERSAL_SLCR_CRL_OFFSET + 0x40)
52#define   VERSAL_SLCR_PLL_CTRL_RESET            (1<<0)
53#define   VERSAL_SLCR_PLL_CTRL_BYPASS           (1<<3)
54#define   VERSAL_SLCR_PLL_CTRL_FBDIV_SHIFT      8
55#define   VERSAL_SLCR_PLL_CTRL_FBDIV_MAX        0xff
56#define   VERSAL_SLCR_PLL_CTRL_FBDIV_MASK       (VERSAL_SLCR_PLL_CTRL_FBDIV_MAX<<8)
57#define   VERSAL_SLCR_PLL_CTRL_DIV_SHIFT        (16)
58#define   VERSAL_SLCR_PLL_CTRL_DIV_MASK (0x3<<16)
59#define   VERSAL_SLCR_PLL_CTRL_PRE_SRC_SHIFT    20
60#define   VERSAL_SLCR_PLL_CTRL_PRE_SRC_MASK     (0x7<<20)
61#define   VERSAL_SLCR_PLL_CTRL_POST_SRC_SHIFT   24
62#define   VERSAL_SLCR_PLL_CTRL_POST_SRC_MASK    (0x7<<24)
63#define     VERSAL_SLCR_PLL_CTRL_SRC_REF_CLK            0x0
64#define     VERSAL_SLCR_PLL_CTRL_SRC_REF_CLK_MASK       0x2
65#define     VERSAL_SLCR_PLL_CTRL_SRC_PL_PMC_ALT_REF_CLK_MASK    0x3
66
67/* Clock controls. */
68#define VERSAL_SLCR_GEM0_CLK_CTRL               (VERSAL_SLCR_CRL_OFFSET + 0x118)
69#define VERSAL_SLCR_GEM1_CLK_CTRL               (VERSAL_SLCR_CRL_OFFSET + 0x11c)
70#define   VERSAL_SLCR_GEM_CLK_CTRL_CLKACT_RX            (1<<27)
71#define   VERSAL_SLCR_GEM_CLK_CTRL_CLKACT_TX            (1<<26)
72#define   VERSAL_SLCR_GEM_CLK_CTRL_CLKACT               (1<<25)
73#define   VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MAX          0x3ff
74#define   VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MASK (VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MAX<<8)
75#define   VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT        8
76#define   VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_MASK          (7<<0)
77#define   VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_P_PLL         (0<<0)
78#define   VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_R_PLL         (1<<0)
79#define   VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_N_PLL         (3<<0)
80
81#define VERSAL_DEFAULT_PS_CLK_FREQUENCY 33333333
82
83#ifdef _KERNEL
84extern int cgem_set_ref_clk(int unit, int frequency);
85#endif
86#endif /* _VERSAL_SLCR_H_ */
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