[25a8832] | 1 | /*- |
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| 2 | * SPDX-License-Identifier: BSD-2-Clause-FreeBSD |
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| 3 | * |
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| 4 | * Copyright (c) 2021 Chris Johns <chrisj@rtems.org> |
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| 5 | * All rights reserved. |
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| 6 | * |
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| 7 | * Redistribution and use in source and binary forms, with or without |
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| 8 | * modification, are permitted provided that the following conditions |
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| 9 | * are met: |
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| 10 | * 1. Redistributions of source code must retain the above copyright |
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| 11 | * notice, this list of conditions and the following disclaimer. |
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| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 13 | * notice, this list of conditions and the following disclaimer in the |
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| 14 | * documentation and/or other materials provided with the distribution. |
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| 15 | * |
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| 16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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| 17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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| 20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 26 | * SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |
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| 29 | /* |
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| 30 | * Defines for Xilinx Versal ACAP SLCR registers. |
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| 31 | * |
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| 32 | * Reference: |
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| 33 | * https://www.xilinx.com/html_docs/registers/am012/mod___crl.html |
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| 34 | */ |
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| 35 | |
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| 36 | #ifndef _VERSAL_SLCR_H_ |
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| 37 | #define _VERSAL_SLCR_H_ |
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| 38 | |
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| 39 | #define VERSAL_SLCR_CRF_OFFSET 0x01260000 |
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| 40 | #define VERSAL_SLCR_CRL_OFFSET 0x0f5e0000 |
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| 41 | |
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| 42 | /* |
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| 43 | * PLL controls |
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| 44 | * |
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| 45 | * P = PPLL = PMCPLL = PMCPLL_CTRL : PMC PLL Clock |
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| 46 | * N = NPLL = NOCPLL = NOCPLL_CTRL : NOC PLL Clock |
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| 47 | * R = RPLL = RPLL_CTRL : Low Power Domain clock |
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| 48 | */ |
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| 49 | #define VERSAL_SLCR_P_PLL_CTRL (VERSAL_SLCR_CRF_OFFSET + 0x40) |
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| 50 | #define VERSAL_SLCR_N_PLL_CTRL (VERSAL_SLCR_CRF_OFFSET + 0x50) |
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| 51 | #define VERSAL_SLCR_R_PLL_CTRL (VERSAL_SLCR_CRL_OFFSET + 0x40) |
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| 52 | #define VERSAL_SLCR_PLL_CTRL_RESET (1<<0) |
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| 53 | #define VERSAL_SLCR_PLL_CTRL_BYPASS (1<<3) |
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| 54 | #define VERSAL_SLCR_PLL_CTRL_FBDIV_SHIFT 8 |
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| 55 | #define VERSAL_SLCR_PLL_CTRL_FBDIV_MAX 0xff |
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| 56 | #define VERSAL_SLCR_PLL_CTRL_FBDIV_MASK (VERSAL_SLCR_PLL_CTRL_FBDIV_MAX<<8) |
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| 57 | #define VERSAL_SLCR_PLL_CTRL_DIV_SHIFT (16) |
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| 58 | #define VERSAL_SLCR_PLL_CTRL_DIV_MASK (0x3<<16) |
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| 59 | #define VERSAL_SLCR_PLL_CTRL_PRE_SRC_SHIFT 20 |
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| 60 | #define VERSAL_SLCR_PLL_CTRL_PRE_SRC_MASK (0x7<<20) |
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| 61 | #define VERSAL_SLCR_PLL_CTRL_POST_SRC_SHIFT 24 |
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| 62 | #define VERSAL_SLCR_PLL_CTRL_POST_SRC_MASK (0x7<<24) |
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| 63 | #define VERSAL_SLCR_PLL_CTRL_SRC_REF_CLK 0x0 |
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| 64 | #define VERSAL_SLCR_PLL_CTRL_SRC_REF_CLK_MASK 0x2 |
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| 65 | #define VERSAL_SLCR_PLL_CTRL_SRC_PL_PMC_ALT_REF_CLK_MASK 0x3 |
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| 66 | |
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| 67 | /* Clock controls. */ |
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| 68 | #define VERSAL_SLCR_GEM0_CLK_CTRL (VERSAL_SLCR_CRL_OFFSET + 0x118) |
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| 69 | #define VERSAL_SLCR_GEM1_CLK_CTRL (VERSAL_SLCR_CRL_OFFSET + 0x11c) |
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| 70 | #define VERSAL_SLCR_GEM_CLK_CTRL_CLKACT_RX (1<<27) |
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| 71 | #define VERSAL_SLCR_GEM_CLK_CTRL_CLKACT_TX (1<<26) |
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| 72 | #define VERSAL_SLCR_GEM_CLK_CTRL_CLKACT (1<<25) |
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| 73 | #define VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MAX 0x3ff |
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| 74 | #define VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MASK (VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MAX<<8) |
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| 75 | #define VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT 8 |
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| 76 | #define VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_MASK (7<<0) |
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| 77 | #define VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_P_PLL (0<<0) |
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| 78 | #define VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_R_PLL (1<<0) |
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| 79 | #define VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_N_PLL (3<<0) |
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| 80 | |
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| 81 | #define VERSAL_DEFAULT_PS_CLK_FREQUENCY 33333333 |
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| 82 | |
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| 83 | #ifdef _KERNEL |
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| 84 | extern int cgem_set_ref_clk(int unit, int frequency); |
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| 85 | #endif |
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| 86 | #endif /* _VERSAL_SLCR_H_ */ |
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