1 | /* |
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2 | * Copyright (c) 2015, 2017 embedded brains GmbH |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * 1. Redistributions of source code must retain the above copyright |
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9 | * notice, this list of conditions and the following disclaimer. |
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10 | * 2. Redistributions in binary form must reproduce the above copyright |
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11 | * notice, this list of conditions and the following disclaimer in the |
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12 | * documentation and/or other materials provided with the distribution. |
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13 | * |
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14 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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15 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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16 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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17 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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18 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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19 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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20 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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22 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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24 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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25 | */ |
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26 | |
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27 | #ifndef _LINUX_PHY_H |
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28 | #define _LINUX_PHY_H |
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29 | |
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30 | #include <sys/queue.h> |
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31 | #include <linux/device.h> |
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32 | #include <linux/list.h> |
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33 | #include <linux/netdevice.h> |
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34 | |
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35 | #ifdef __cplusplus |
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36 | extern "C" { |
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37 | #endif /* __cplusplus */ |
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38 | |
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39 | typedef enum { |
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40 | PHY_INTERFACE_MODE_NA, |
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41 | PHY_INTERFACE_MODE_MII, |
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42 | PHY_INTERFACE_MODE_GMII, |
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43 | PHY_INTERFACE_MODE_SGMII, |
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44 | PHY_INTERFACE_MODE_TBI, |
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45 | PHY_INTERFACE_MODE_REVMII, |
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46 | PHY_INTERFACE_MODE_RMII, |
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47 | PHY_INTERFACE_MODE_RGMII, |
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48 | PHY_INTERFACE_MODE_RGMII_ID, |
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49 | PHY_INTERFACE_MODE_RGMII_RXID, |
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50 | PHY_INTERFACE_MODE_RGMII_TXID, |
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51 | PHY_INTERFACE_MODE_RTBI, |
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52 | PHY_INTERFACE_MODE_SMII, |
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53 | PHY_INTERFACE_MODE_XGMII, |
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54 | PHY_INTERFACE_MODE_MOCA, |
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55 | PHY_INTERFACE_MODE_QSGMII, |
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56 | PHY_INTERFACE_MODE_MAX |
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57 | } phy_interface_t; |
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58 | |
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59 | #define SPEED_10 10 |
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60 | #define SPEED_100 100 |
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61 | #define SPEED_1000 1000 |
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62 | #define SPEED_2500 2500 |
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63 | #define SPEED_5000 5000 |
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64 | #define SPEED_10000 10000 |
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65 | #define SPEED_20000 20000 |
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66 | #define SPEED_25000 25000 |
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67 | #define SPEED_40000 40000 |
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68 | #define SPEED_50000 50000 |
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69 | #define SPEED_56000 56000 |
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70 | #define SPEED_100000 100000 |
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71 | |
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72 | #define SUPPORTED_10000baseT_Full (1U << 0) |
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73 | #define SUPPORTED_1000baseT_Full (1U << 1) |
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74 | #define SUPPORTED_100baseT_Full (1U << 2) |
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75 | #define SUPPORTED_100baseT_Half (1U << 3) |
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76 | #define SUPPORTED_10baseT_Full (1U << 4) |
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77 | #define SUPPORTED_10baseT_Half (1U << 5) |
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78 | #define SUPPORTED_Asym_Pause (1U << 6) |
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79 | #define SUPPORTED_Autoneg (1U << 7) |
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80 | #define SUPPORTED_MII (1U << 8) |
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81 | #define SUPPORTED_Pause (1U << 9) |
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82 | |
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83 | #define MII_ADDR_C45 (1 << 30) |
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84 | |
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85 | struct mdio_bus { |
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86 | int (*read)(struct mdio_bus *bus, int addr, int reg); |
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87 | int (*write)(struct mdio_bus *bus, int addr, int reg, int val); |
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88 | SLIST_ENTRY(mdio_bus) next; |
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89 | int node; |
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90 | }; |
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91 | |
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92 | struct phy_device { |
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93 | struct { |
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94 | struct device dev; |
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95 | int addr; |
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96 | int is_c45; |
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97 | struct mdio_bus *bus; |
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98 | } mdio; |
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99 | }; |
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100 | |
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101 | int phy_read(struct phy_device *phy_dev, int reg); |
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102 | |
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103 | int phy_write(struct phy_device *phy_dev, int reg, int val); |
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104 | |
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105 | #ifdef __cplusplus |
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106 | } |
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107 | #endif /* __cplusplus */ |
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108 | |
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109 | #endif /* _LINUX_PHY_H */ |
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