1 | /*- |
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2 | * Copyright (c) 2010 Isilon Systems, Inc. |
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3 | * Copyright (c) 2010 iX Systems, Inc. |
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4 | * Copyright (c) 2010 Panasas, Inc. |
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5 | * Copyright (c) 2013, 2014 Mellanox Technologies, Ltd. |
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6 | * All rights reserved. |
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7 | * |
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8 | * Redistribution and use in source and binary forms, with or without |
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9 | * modification, are permitted provided that the following conditions |
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10 | * are met: |
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11 | * 1. Redistributions of source code must retain the above copyright |
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12 | * notice unmodified, this list of conditions, and the following |
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13 | * disclaimer. |
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14 | * 2. Redistributions in binary form must reproduce the above copyright |
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15 | * notice, this list of conditions and the following disclaimer in the |
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16 | * documentation and/or other materials provided with the distribution. |
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17 | * |
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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28 | * |
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29 | * $FreeBSD$ |
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30 | */ |
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31 | #ifndef _LINUX_IO_H_ |
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32 | #define _LINUX_IO_H_ |
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33 | |
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34 | #include <machine/vm.h> |
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35 | #include <sys/endian.h> |
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36 | #include <linux/types.h> |
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37 | |
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38 | static inline uint8_t |
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39 | __raw_readb(const volatile void *addr) |
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40 | { |
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41 | return *(const volatile uint8_t *)addr; |
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42 | } |
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43 | |
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44 | static inline void |
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45 | __raw_writeb(uint8_t b, volatile void *addr) |
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46 | { |
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47 | *(volatile uint8_t *)addr = b; |
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48 | } |
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49 | |
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50 | static inline uint32_t |
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51 | __raw_readl(const volatile void *addr) |
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52 | { |
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53 | return *(const volatile uint32_t *)addr; |
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54 | } |
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55 | |
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56 | static inline void |
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57 | __raw_writel(uint32_t b, volatile void *addr) |
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58 | { |
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59 | *(volatile uint32_t *)addr = b; |
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60 | } |
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61 | |
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62 | static inline uint64_t |
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63 | __raw_readq(const volatile void *addr) |
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64 | { |
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65 | return *(const volatile uint64_t *)addr; |
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66 | } |
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67 | |
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68 | static inline void |
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69 | __raw_writeq(uint64_t b, volatile void *addr) |
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70 | { |
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71 | *(volatile uint64_t *)addr = b; |
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72 | } |
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73 | |
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74 | /* |
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75 | * XXX This is all x86 specific. It should be bus space access. |
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76 | */ |
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77 | #define mmiowb() |
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78 | |
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79 | #undef writel |
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80 | static inline void |
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81 | writel(uint32_t b, void *addr) |
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82 | { |
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83 | *(volatile uint32_t *)addr = b; |
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84 | } |
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85 | |
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86 | #undef writeq |
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87 | static inline void |
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88 | writeq(uint64_t b, void *addr) |
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89 | { |
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90 | *(volatile uint64_t *)addr = b; |
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91 | } |
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92 | |
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93 | #undef writeb |
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94 | static inline void |
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95 | writeb(uint8_t b, void *addr) |
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96 | { |
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97 | *(volatile uint8_t *)addr = b; |
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98 | } |
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99 | |
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100 | #undef writew |
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101 | static inline void |
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102 | writew(uint16_t b, void *addr) |
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103 | { |
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104 | *(volatile uint16_t *)addr = b; |
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105 | } |
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106 | |
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107 | #undef ioread32be |
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108 | static inline uint32_t |
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109 | ioread32be(const volatile void *addr) |
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110 | { |
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111 | return be32toh(*(const volatile uint32_t *)addr); |
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112 | } |
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113 | |
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114 | #define in_be32(x) ioread32be(x) |
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115 | |
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116 | #undef iowrite32be |
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117 | static inline void |
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118 | iowrite32be(uint32_t v, volatile void *addr) |
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119 | { |
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120 | *(volatile uint32_t *)addr = htobe32(v); |
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121 | } |
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122 | |
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123 | #define out_be32(x, y) iowrite32be(y, x) |
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124 | |
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125 | void *_ioremap_attr(vm_paddr_t phys_addr, unsigned long size, int attr); |
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126 | #define ioremap_nocache(addr, size) \ |
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127 | _ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE) |
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128 | #define ioremap_wc(addr, size) \ |
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129 | _ioremap_attr((addr), (size), VM_MEMATTR_WRITE_COMBINING) |
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130 | #define ioremap ioremap_nocache |
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131 | void iounmap(void *addr); |
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132 | |
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133 | #define memset_io(a, b, c) memset((a), (b), (c)) |
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134 | #define memcpy_fromio(a, b, c) memcpy((a), (b), (c)) |
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135 | #define memcpy_toio(a, b, c) memcpy((a), (b), (c)) |
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136 | |
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137 | static inline void |
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138 | __iowrite64_copy(void *to, void *from, size_t count) |
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139 | { |
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140 | #ifdef __LP64__ |
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141 | uint64_t *src; |
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142 | uint64_t *dst; |
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143 | int i; |
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144 | |
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145 | for (i = 0, src = from, dst = to; i < count; i++, src++, dst++) |
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146 | __raw_writeq(*src, dst); |
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147 | #else |
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148 | uint32_t *src; |
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149 | uint32_t *dst; |
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150 | int i; |
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151 | |
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152 | count *= 2; |
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153 | for (i = 0, src = from, dst = to; i < count; i++, src++, dst++) |
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154 | __raw_writel(*src, dst); |
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155 | #endif |
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156 | } |
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157 | |
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158 | static inline unsigned long |
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159 | virt_to_phys(volatile void *address) |
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160 | { |
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161 | |
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162 | return ((unsigned long)address); |
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163 | } |
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164 | |
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165 | static inline void * |
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166 | phys_to_virt(unsigned long address) |
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167 | { |
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168 | return ((void *)address); |
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169 | } |
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170 | |
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171 | #endif /* _LINUX_IO_H_ */ |
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