| 1 | /* $FreeBSD$ */ |
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| 2 | |
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| 3 | /* |
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| 4 | * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. |
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| 5 | * |
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| 6 | * generated from: |
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| 7 | * FreeBSD |
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| 8 | */ |
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| 9 | /*$NetBSD: miidevs,v 1.105 2011/11/25 23:28:14 jakllsch Exp $*/ |
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| 10 | |
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| 11 | /*- |
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| 12 | * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. |
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| 13 | * All rights reserved. |
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| 14 | * |
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| 15 | * This code is derived from software contributed to The NetBSD Foundation |
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| 16 | * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, |
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| 17 | * NASA Ames Research Center. |
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| 18 | * |
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| 19 | * Redistribution and use in source and binary forms, with or without |
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| 20 | * modification, are permitted provided that the following conditions |
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| 21 | * are met: |
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| 22 | * 1. Redistributions of source code must retain the above copyright |
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| 23 | * notice, this list of conditions and the following disclaimer. |
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| 24 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 25 | * notice, this list of conditions and the following disclaimer in the |
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| 26 | * documentation and/or other materials provided with the distribution. |
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| 27 | * |
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| 28 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
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| 29 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
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| 30 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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| 31 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
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| 32 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 33 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 34 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 35 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 36 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 37 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 38 | * POSSIBILITY OF SUCH DAMAGE. |
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| 39 | */ |
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| 40 | |
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| 41 | /* |
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| 42 | * List of known MII OUIs. |
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| 43 | * For a complete list see http://standards.ieee.org/regauth/oui/ |
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| 44 | * |
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| 45 | * XXX Vendors do obviously not agree how OUIs (24 bit) are mapped |
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| 46 | * to the 22 bits available in the id registers. |
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| 47 | * IEEE 802.3u-1995, subclause 22.2.4.3.1, figure 22-12, depicts the right |
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| 48 | * mapping; the bit positions are defined in IEEE 802-1990, figure 5.2. |
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| 49 | * (There is a formal 802.3 interpretation, number 1-07/98 of July 09 1998, |
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| 50 | * about this.) |
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| 51 | * The MII_OUI() macro in "mii.h" reflects this. |
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| 52 | * If a vendor uses a different mapping, an "xx" prefixed OUI is defined here |
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| 53 | * which is mangled accordingly to compensate. |
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| 54 | */ |
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| 55 | |
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| 56 | #define MII_OUI_AGERE 0x00053d /* Agere Systems */ |
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| 57 | #define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */ |
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| 58 | #define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */ |
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| 59 | #define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */ |
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| 60 | #define MII_OUI_BROADCOM2 0x000af7 /* Broadcom Corporation */ |
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| 61 | #define MII_OUI_BROADCOM3 0x001be9 /* Broadcom Corporation */ |
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| 62 | #define MII_OUI_BROADCOM4 0x18c086 /* Broadcom Corporation */ |
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| 63 | #define MII_OUI_CICADA 0x0003f1 /* Cicada Semiconductor */ |
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| 64 | #define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */ |
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| 65 | #define MII_OUI_ENABLESEMI 0x0010dd /* Enable Semiconductor */ |
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| 66 | #define MII_OUI_ICPLUS 0x0090c3 /* IC Plus Corp. */ |
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| 67 | #define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */ |
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| 68 | #define MII_OUI_INTEL 0x00aa00 /* Intel Corporation */ |
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| 69 | #define MII_OUI_JMICRON 0x00d831 /* JMicron Technologies */ |
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| 70 | #define MII_OUI_LEVEL1 0x00207b /* Level 1 */ |
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| 71 | #define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */ |
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| 72 | #define MII_OUI_MICREL 0x0010a1 /* Micrel */ |
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| 73 | #define MII_OUI_MYSON 0x00c0b4 /* Myson Technology */ |
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| 74 | #define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */ |
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| 75 | #define MII_OUI_PMCSIERRA 0x00e004 /* PMC-Sierra */ |
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| 76 | #define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */ |
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| 77 | #define MII_OUI_RDC 0x00d02d /* RDC Semiconductor */ |
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| 78 | #define MII_OUI_REALTEK 0x00e04c /* RealTek Semicondctor */ |
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| 79 | #define MII_OUI_SEEQ 0x00a07d /* Seeq Technology */ |
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| 80 | #define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */ |
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| 81 | #define MII_OUI_SMC 0x00800f /* SMC */ |
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| 82 | #define MII_OUI_TI 0x080028 /* Texas Instruments */ |
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| 83 | #define MII_OUI_TSC 0x00c039 /* TDK Semiconductor */ |
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| 84 | #define MII_OUI_VITESSE 0x0001c1 /* Vitesse Semiconductor */ |
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| 85 | #define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */ |
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| 86 | |
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| 87 | /* Some Intel 82553's use an alternative OUI. */ |
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| 88 | #define MII_OUI_xxINTEL 0x001f00 /* Intel Corporation */ |
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| 89 | |
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| 90 | /* Some VIA 6122's use an alternative OUI. */ |
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| 91 | #define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor */ |
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| 92 | |
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| 93 | /* bad bitorder (bits "g" and "h" (= MSBs byte 1) lost) */ |
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| 94 | #define MII_OUI_yyAMD 0x000058 /* Advanced Micro Devices */ |
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| 95 | #define MII_OUI_xxATHEROS 0x00c82e /* Atheros Communications */ |
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| 96 | #define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */ |
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| 97 | #define MII_OUI_xxBROADCOM_ALT1 0x0050ef /* Broadcom Corporation */ |
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| 98 | #define MII_OUI_xxDAVICOM 0x000676 /* Davicom Semiconductor */ |
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| 99 | #define MII_OUI_yyINTEL 0x005500 /* Intel Corporation */ |
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| 100 | #define MII_OUI_xxJATO 0x0007c1 /* Jato Technologies */ |
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| 101 | #define MII_OUI_xxMARVELL 0x000ac2 /* Marvell Semiconductor */ |
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| 102 | #define MII_OUI_xxMYSON 0x00032d /* Myson Technology */ |
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| 103 | #define MII_OUI_xxNATSEMI 0x1000e8 /* National Semiconductor */ |
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| 104 | #define MII_OUI_xxQUALSEMI 0x00068a /* Quality Semiconductor */ |
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| 105 | #define MII_OUI_xxTSC 0x00039c /* TDK Semiconductor */ |
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| 106 | #define MII_OUI_xxVITESSE 0x008083 /* Vitesse Semiconductor */ |
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| 107 | |
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| 108 | /* bad byteorder (bits "q" and "r" (= LSBs byte 3) lost) */ |
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| 109 | #define MII_OUI_xxLEVEL1 0x782000 /* Level 1 */ |
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| 110 | #define MII_OUI_xxXAQTI 0xace000 /* XaQti Corp. */ |
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| 111 | |
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| 112 | /* Don't know what's going on here. */ |
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| 113 | #define MII_OUI_xxASIX 0x000674 /* Asix Semiconductor */ |
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| 114 | #define MII_OUI_yyDAVICOM 0x000602 /* Davicom Semiconductor */ |
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| 115 | #define MII_OUI_xxICPLUS 0x0009c3 /* IC Plus Corp. */ |
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| 116 | #define MII_OUI_xxPMCSIERRA 0x0009c0 /* PMC-Sierra */ |
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| 117 | #define MII_OUI_xxPMCSIERRA2 0x009057 /* PMC-Sierra */ |
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| 118 | #define MII_OUI_xxREALTEK 0x000732 /* RealTek Semicondctor */ |
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| 119 | #define MII_OUI_yyREALTEK 0x000004 /* RealTek Semicondctor */ |
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| 120 | |
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| 121 | /* |
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| 122 | * List of known models. Grouped by oui. |
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| 123 | */ |
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| 124 | |
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| 125 | /* Agere Systems PHYs */ |
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| 126 | #define MII_MODEL_AGERE_ET1011 0x0001 |
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| 127 | #define MII_STR_AGERE_ET1011 "ET1011 10/100/1000baseT PHY" |
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| 128 | #define MII_MODEL_AGERE_ET1011C 0x0004 |
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| 129 | #define MII_STR_AGERE_ET1011C "ET1011C 10/100/1000baseT PHY" |
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| 130 | |
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| 131 | /* Altima Communications PHYs */ |
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| 132 | #define MII_MODEL_ALTIMA_ACXXX 0x0001 |
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| 133 | #define MII_STR_ALTIMA_ACXXX "ACXXX 10/100 media interface" |
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| 134 | #define MII_MODEL_ALTIMA_AC101L 0x0012 |
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| 135 | #define MII_STR_ALTIMA_AC101L "AC101L 10/100 media interface" |
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| 136 | #define MII_MODEL_ALTIMA_AC101 0x0021 |
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| 137 | #define MII_STR_ALTIMA_AC101 "AC101 10/100 media interface" |
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| 138 | /* AMD Am79C87[45] have ALTIMA OUI */ |
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| 139 | #define MII_MODEL_ALTIMA_Am79C875 0x0014 |
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| 140 | #define MII_STR_ALTIMA_Am79C875 "Am79C875 10/100 media interface" |
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| 141 | #define MII_MODEL_ALTIMA_Am79C874 0x0021 |
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| 142 | #define MII_STR_ALTIMA_Am79C874 "Am79C874 10/100 media interface" |
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| 143 | |
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| 144 | /* Advanced Micro Devices PHYs */ |
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| 145 | /* see Davicom DM9101 for Am79C873 */ |
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| 146 | #define MII_MODEL_yyAMD_79C972_10T 0x0001 |
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| 147 | #define MII_STR_yyAMD_79C972_10T "Am79C972 internal 10BASE-T interface" |
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| 148 | #define MII_MODEL_yyAMD_79c973phy 0x0036 |
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| 149 | #define MII_STR_yyAMD_79c973phy "Am79C973 internal 10/100 media interface" |
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| 150 | #define MII_MODEL_yyAMD_79c901 0x0037 |
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| 151 | #define MII_STR_yyAMD_79c901 "Am79C901 10BASE-T interface" |
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| 152 | #define MII_MODEL_yyAMD_79c901home 0x0039 |
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| 153 | #define MII_STR_yyAMD_79c901home "Am79C901 HomePNA 1.0 interface" |
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| 154 | |
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| 155 | /* Atheros Communications/Attansic PHYs */ |
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| 156 | #define MII_MODEL_xxATHEROS_F1 0x0001 |
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| 157 | #define MII_STR_xxATHEROS_F1 "Atheros F1 10/100/1000 PHY" |
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| 158 | #define MII_MODEL_xxATHEROS_F2 0x0002 |
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| 159 | #define MII_STR_xxATHEROS_F2 "Atheros F2 10/100 PHY" |
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| 160 | #define MII_MODEL_xxATHEROS_AR8021 0x0004 |
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| 161 | #define MII_STR_xxATHEROS_AR8021 "Atheros AR8021 10/100/1000 PHY" |
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| 162 | #define MII_MODEL_xxATHEROS_F1_7 0x0007 |
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| 163 | #define MII_STR_xxATHEROS_F1_7 "Atheros F1 10/100/1000 PHY" |
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| 164 | |
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| 165 | /* Asix semiconductor PHYs */ |
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| 166 | #define MII_MODEL_xxASIX_AX88X9X 0x0031 |
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| 167 | #define MII_STR_xxASIX_AX88X9X "Ax88x9x internal PHY" |
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| 168 | |
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| 169 | /* Broadcom Corp. PHYs */ |
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| 170 | #define MII_MODEL_xxBROADCOM_3C905B 0x0012 |
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| 171 | #define MII_STR_xxBROADCOM_3C905B "Broadcom 3c905B internal PHY" |
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| 172 | #define MII_MODEL_xxBROADCOM_3C905C 0x0017 |
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| 173 | #define MII_STR_xxBROADCOM_3C905C "Broadcom 3c905C internal PHY" |
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| 174 | #define MII_MODEL_xxBROADCOM_BCM5201 0x0021 |
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| 175 | #define MII_STR_xxBROADCOM_BCM5201 "BCM5201 10/100 media interface" |
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| 176 | #define MII_MODEL_xxBROADCOM_BCM5214 0x0028 |
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| 177 | #define MII_STR_xxBROADCOM_BCM5214 "BCM5214 Quad 10/100 media interface" |
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| 178 | #define MII_MODEL_xxBROADCOM_BCM5221 0x001e |
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| 179 | #define MII_STR_xxBROADCOM_BCM5221 "BCM5221 10/100 media interface" |
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| 180 | #define MII_MODEL_xxBROADCOM_BCM5222 0x0032 |
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| 181 | #define MII_STR_xxBROADCOM_BCM5222 "BCM5222 Dual 10/100 media interface" |
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| 182 | #define MII_MODEL_xxBROADCOM_BCM4401 0x0036 |
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| 183 | #define MII_STR_xxBROADCOM_BCM4401 "BCM4401 10/100 media interface" |
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| 184 | #define MII_MODEL_xxBROADCOM_BCM5365 0x0037 |
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| 185 | #define MII_STR_xxBROADCOM_BCM5365 "BCM5365 10/100 5-port PHY switch" |
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| 186 | #define MII_MODEL_BROADCOM_BCM5400 0x0004 |
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| 187 | #define MII_STR_BROADCOM_BCM5400 "BCM5400 1000BASE-T media interface" |
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| 188 | #define MII_MODEL_BROADCOM_BCM5401 0x0005 |
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| 189 | #define MII_STR_BROADCOM_BCM5401 "BCM5401 1000BASE-T media interface" |
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| 190 | #define MII_MODEL_BROADCOM_BCM5411 0x0007 |
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| 191 | #define MII_STR_BROADCOM_BCM5411 "BCM5411 1000BASE-T media interface" |
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| 192 | #define MII_MODEL_BROADCOM_BCM5464 0x000b |
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| 193 | #define MII_STR_BROADCOM_BCM5464 "BCM5464 1000BASE-T media interface" |
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| 194 | #define MII_MODEL_BROADCOM_BCM5461 0x000c |
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| 195 | #define MII_STR_BROADCOM_BCM5461 "BCM5461 1000BASE-T media interface" |
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| 196 | #define MII_MODEL_BROADCOM_BCM5462 0x000d |
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| 197 | #define MII_STR_BROADCOM_BCM5462 "BCM5462 1000BASE-T media interface" |
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| 198 | #define MII_MODEL_BROADCOM_BCM5421 0x000e |
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| 199 | #define MII_STR_BROADCOM_BCM5421 "BCM5421 1000BASE-T media interface" |
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| 200 | #define MII_MODEL_BROADCOM_BCM5752 0x0010 |
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| 201 | #define MII_STR_BROADCOM_BCM5752 "BCM5752 1000BASE-T media interface" |
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| 202 | #define MII_MODEL_BROADCOM_BCM5701 0x0011 |
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| 203 | #define MII_STR_BROADCOM_BCM5701 "BCM5701 1000BASE-T media interface" |
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| 204 | #define MII_MODEL_BROADCOM_BCM5706 0x0015 |
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| 205 | #define MII_STR_BROADCOM_BCM5706 "BCM5706 1000BASE-T/SX media interface" |
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| 206 | #define MII_MODEL_BROADCOM_BCM5703 0x0016 |
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| 207 | #define MII_STR_BROADCOM_BCM5703 "BCM5703 1000BASE-T media interface" |
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| 208 | #define MII_MODEL_BROADCOM_BCM5750 0x0018 |
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| 209 | #define MII_STR_BROADCOM_BCM5750 "BCM5750 1000BASE-T media interface" |
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| 210 | #define MII_MODEL_BROADCOM_BCM5704 0x0019 |
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| 211 | #define MII_STR_BROADCOM_BCM5704 "BCM5704 1000BASE-T media interface" |
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| 212 | #define MII_MODEL_BROADCOM_BCM5705 0x001a |
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| 213 | #define MII_STR_BROADCOM_BCM5705 "BCM5705 1000BASE-T media interface" |
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| 214 | #define MII_MODEL_BROADCOM_BCM54K2 0x002e |
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| 215 | #define MII_STR_BROADCOM_BCM54K2 "BCM54K2 1000BASE-T media interface" |
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| 216 | #define MII_MODEL_BROADCOM_BCM5714 0x0034 |
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| 217 | #define MII_STR_BROADCOM_BCM5714 "BCM5714 1000BASE-T media interface" |
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| 218 | #define MII_MODEL_BROADCOM_BCM5780 0x0035 |
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| 219 | #define MII_STR_BROADCOM_BCM5780 "BCM5780 1000BASE-T media interface" |
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| 220 | #define MII_MODEL_BROADCOM_BCM5708C 0x0036 |
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| 221 | #define MII_STR_BROADCOM_BCM5708C "BCM5708C 1000BASE-T media interface" |
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| 222 | #define MII_MODEL_BROADCOM2_BCM5325 0x0003 |
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| 223 | #define MII_STR_BROADCOM2_BCM5325 "BCM5325 10/100 5-port PHY switch" |
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| 224 | #define MII_MODEL_BROADCOM2_BCM5906 0x0004 |
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| 225 | #define MII_STR_BROADCOM2_BCM5906 "BCM5906 10/100baseTX media interface" |
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| 226 | #define MII_MODEL_BROADCOM2_BCM5481 0x000a |
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| 227 | #define MII_STR_BROADCOM2_BCM5481 "BCM5481 1000BASE-T media interface" |
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| 228 | #define MII_MODEL_BROADCOM2_BCM5482 0x000b |
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| 229 | #define MII_STR_BROADCOM2_BCM5482 "BCM5482 1000BASE-T media interface" |
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| 230 | #define MII_MODEL_BROADCOM2_BCM5755 0x000c |
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| 231 | #define MII_STR_BROADCOM2_BCM5755 "BCM5755 1000BASE-T media interface" |
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| 232 | #define MII_MODEL_BROADCOM2_BCM5754 0x000e |
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| 233 | #define MII_STR_BROADCOM2_BCM5754 "BCM5754/5787 1000BASE-T media interface" |
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| 234 | #define MII_MODEL_BROADCOM2_BCM5708S 0x0015 |
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| 235 | #define MII_STR_BROADCOM2_BCM5708S "BCM5708S 1000/2500baseSX PHY" |
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| 236 | #define MII_MODEL_BROADCOM2_BCM5785 0x0016 |
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| 237 | #define MII_STR_BROADCOM2_BCM5785 "BCM5785 1000BASE-T media interface" |
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| 238 | #define MII_MODEL_BROADCOM2_BCM5709CAX 0x002c |
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| 239 | #define MII_STR_BROADCOM2_BCM5709CAX "BCM5709CAX 10/100/1000baseT PHY" |
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| 240 | #define MII_MODEL_BROADCOM2_BCM5722 0x002d |
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| 241 | #define MII_STR_BROADCOM2_BCM5722 "BCM5722 1000BASE-T media interface" |
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| 242 | #define MII_MODEL_BROADCOM2_BCM5784 0x003a |
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| 243 | #define MII_STR_BROADCOM2_BCM5784 "BCM5784 10/100/1000baseT PHY" |
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| 244 | #define MII_MODEL_BROADCOM2_BCM5709C 0x003c |
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| 245 | #define MII_STR_BROADCOM2_BCM5709C "BCM5709 10/100/1000baseT PHY" |
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| 246 | #define MII_MODEL_BROADCOM2_BCM5761 0x003d |
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| 247 | #define MII_STR_BROADCOM2_BCM5761 "BCM5761 10/100/1000baseT PHY" |
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| 248 | #define MII_MODEL_BROADCOM2_BCM5709S 0x003f |
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| 249 | #define MII_STR_BROADCOM2_BCM5709S "BCM5709S/5720S 1000/2500baseSX PHY" |
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| 250 | #define MII_MODEL_BROADCOM3_BCM57780 0x0019 |
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| 251 | #define MII_STR_BROADCOM3_BCM57780 "BCM57780 1000BASE-T media interface" |
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| 252 | #define MII_MODEL_BROADCOM3_BCM5717C 0x0020 |
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| 253 | #define MII_STR_BROADCOM3_BCM5717C "BCM5717C 1000BASE-T media interface" |
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| 254 | #define MII_MODEL_BROADCOM3_BCM5719C 0x0022 |
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| 255 | #define MII_STR_BROADCOM3_BCM5719C "BCM5719C 1000BASE-T media interface" |
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| 256 | #define MII_MODEL_BROADCOM3_BCM57765 0x0024 |
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| 257 | #define MII_STR_BROADCOM3_BCM57765 "BCM57765 1000BASE-T media interface" |
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| 258 | #define MII_MODEL_BROADCOM3_BCM5720C 0x0036 |
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| 259 | #define MII_STR_BROADCOM3_BCM5720C "BCM5720C 1000BASE-T media interface" |
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| 260 | #define MII_MODEL_BROADCOM4_BCM5725C 0x0038 |
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| 261 | #define MII_STR_BROADCOM4_BCM5725C "BCM5725C 1000BASE-T media interface" |
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| 262 | #define MII_MODEL_xxBROADCOM_ALT1_BCM5906 0x0004 |
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| 263 | #define MII_STR_xxBROADCOM_ALT1_BCM5906 "BCM5906 10/100baseTX media interface" |
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| 264 | |
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| 265 | /* Cicada Semiconductor PHYs (now owned by Vitesse?) */ |
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| 266 | #define MII_MODEL_xxCICADA_CS8201 0x0001 |
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| 267 | #define MII_STR_xxCICADA_CS8201 "Cicada CS8201 10/100/1000TX PHY" |
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| 268 | #define MII_MODEL_xxCICADA_CS8204 0x0004 |
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| 269 | #define MII_STR_xxCICADA_CS8204 "Cicada CS8204 10/100/1000TX PHY" |
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| 270 | #define MII_MODEL_xxCICADA_VSC8211 0x000b |
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| 271 | #define MII_STR_xxCICADA_VSC8211 "Cicada VSC8211 10/100/1000TX PHY" |
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| 272 | #define MII_MODEL_xxCICADA_VSC8221 0x0015 |
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| 273 | #define MII_STR_xxCICADA_VSC8221 "Cicada CS8201 10/100/1000TX PHY" |
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| 274 | #define MII_MODEL_xxCICADA_CS8201A 0x0020 |
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| 275 | #define MII_STR_xxCICADA_CS8201A "Cicada CS8201 10/100/1000TX PHY" |
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| 276 | #define MII_MODEL_xxCICADA_CS8201B 0x0021 |
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| 277 | #define MII_STR_xxCICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY" |
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| 278 | #define MII_MODEL_xxCICADA_CS8244 0x002c |
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| 279 | #define MII_STR_xxCICADA_CS8244 "Cicada CS8244 10/100/1000TX PHY" |
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| 280 | #define MII_MODEL_xxVITESSE_VSC8601 0x0002 |
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| 281 | #define MII_STR_xxVITESSE_VSC8601 "Vitesse VSC8601 10/100/1000TX PHY" |
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| 282 | |
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| 283 | /* Davicom Semiconductor PHYs */ |
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| 284 | /* AMD Am79C873 seems to be a relabeled DM9101 */ |
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| 285 | #define MII_MODEL_xxDAVICOM_DM9101 0x0000 |
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| 286 | #define MII_STR_xxDAVICOM_DM9101 "DM9101 (AMD Am79C873) 10/100 media interface" |
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| 287 | #define MII_MODEL_xxDAVICOM_DM9102 0x0004 |
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| 288 | #define MII_STR_xxDAVICOM_DM9102 "DM9102 10/100 media interface" |
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| 289 | #define MII_MODEL_yyDAVICOM_DM9101 0x0000 |
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| 290 | #define MII_STR_yyDAVICOM_DM9101 "DM9101 10/100 media interface" |
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| 291 | |
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| 292 | /* IC Plus Corp. PHYs */ |
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| 293 | #define MII_MODEL_xxICPLUS_IP101 0x0005 |
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| 294 | #define MII_STR_xxICPLUS_IP101 "IP101 10/100 PHY" |
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| 295 | #define MII_MODEL_xxICPLUS_IP1000A 0x0008 |
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| 296 | #define MII_STR_xxICPLUS_IP1000A "IP100A 10/100/1000 media interface" |
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| 297 | #define MII_MODEL_xxICPLUS_IP1001 0x0019 |
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| 298 | #define MII_STR_xxICPLUS_IP1001 "IP1001 10/100/1000 media interface" |
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| 299 | |
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| 300 | /* Integrated Circuit Systems PHYs */ |
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| 301 | #define MII_MODEL_ICS_1889 0x0001 |
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| 302 | #define MII_STR_ICS_1889 "ICS1889 10/100 media interface" |
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| 303 | #define MII_MODEL_ICS_1890 0x0002 |
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| 304 | #define MII_STR_ICS_1890 "ICS1890 10/100 media interface" |
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| 305 | #define MII_MODEL_ICS_1892 0x0003 |
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| 306 | #define MII_STR_ICS_1892 "ICS1892 10/100 media interface" |
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| 307 | #define MII_MODEL_ICS_1893 0x0004 |
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| 308 | #define MII_STR_ICS_1893 "ICS1893 10/100 media interface" |
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| 309 | |
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| 310 | /* Intel Corporation PHYs */ |
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| 311 | #define MII_MODEL_xxINTEL_I82553 0x0000 |
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| 312 | #define MII_STR_xxINTEL_I82553 "i82553 10/100 media interface" |
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| 313 | #define MII_MODEL_yyINTEL_I82555 0x0015 |
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| 314 | #define MII_STR_yyINTEL_I82555 "i82555 10/100 media interface" |
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| 315 | #define MII_MODEL_yyINTEL_I82562EH 0x0017 |
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| 316 | #define MII_STR_yyINTEL_I82562EH "i82562EH HomePNA interface" |
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| 317 | #define MII_MODEL_yyINTEL_I82562G 0x0031 |
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| 318 | #define MII_STR_yyINTEL_I82562G "i82562G 10/100 media interface" |
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| 319 | #define MII_MODEL_yyINTEL_I82562EM 0x0032 |
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| 320 | #define MII_STR_yyINTEL_I82562EM "i82562EM 10/100 media interface" |
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| 321 | #define MII_MODEL_yyINTEL_I82562ET 0x0033 |
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| 322 | #define MII_STR_yyINTEL_I82562ET "i82562ET 10/100 media interface" |
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| 323 | #define MII_MODEL_yyINTEL_I82553 0x0035 |
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| 324 | #define MII_STR_yyINTEL_I82553 "i82553 10/100 media interface" |
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| 325 | #define MII_MODEL_yyINTEL_I82566 0x0039 |
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| 326 | #define MII_STR_yyINTEL_I82566 "i82566 10/100/1000 media interface" |
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| 327 | #define MII_MODEL_INTEL_I82577 0x0005 |
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| 328 | #define MII_STR_INTEL_I82577 "i82577 10/100/1000 media interface" |
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| 329 | #define MII_MODEL_INTEL_I82579 0x0009 |
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| 330 | #define MII_STR_INTEL_I82579 "i82579 10/100/1000 media interface" |
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| 331 | #define MII_MODEL_xxMARVELL_I82563 0x000a |
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| 332 | #define MII_STR_xxMARVELL_I82563 "i82563 10/100/1000 media interface" |
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| 333 | |
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| 334 | #define MII_MODEL_yyINTEL_IGP01E1000 0x0038 |
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| 335 | #define MII_STR_yyINTEL_IGP01E1000 "Intel IGP01E1000 Gigabit PHY" |
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| 336 | |
|---|
| 337 | /* Jato Technologies PHYs */ |
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| 338 | #define MII_MODEL_xxJATO_BASEX 0x0000 |
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| 339 | #define MII_STR_xxJATO_BASEX "Jato 1000baseX media interface" |
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| 340 | |
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| 341 | /* JMicron Technologies PHYs */ |
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| 342 | #define MII_MODEL_JMICRON_JMP211 0x0021 |
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| 343 | #define MII_STR_JMICRON_JMP211 "JMP211 10/100/1000 media interface" |
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| 344 | #define MII_MODEL_JMICRON_JMP202 0x0022 |
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| 345 | #define MII_STR_JMICRON_JMP202 "JMP202 10/100 media interface" |
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| 346 | |
|---|
| 347 | /* Level 1 PHYs */ |
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| 348 | #define MII_MODEL_xxLEVEL1_LXT970 0x0000 |
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| 349 | #define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface" |
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| 350 | #define MII_MODEL_LEVEL1_LXT971 0x000e |
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| 351 | #define MII_STR_LEVEL1_LXT971 "LXT971/2 10/100 media interface" |
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| 352 | #define MII_MODEL_LEVEL1_LXT973 0x0021 |
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| 353 | #define MII_STR_LEVEL1_LXT973 "LXT973 10/100 Dual PHY" |
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| 354 | #define MII_MODEL_LEVEL1_LXT974 0x0004 |
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| 355 | #define MII_STR_LEVEL1_LXT974 "LXT974 10/100 Quad PHY" |
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| 356 | #define MII_MODEL_LEVEL1_LXT975 0x0005 |
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| 357 | #define MII_STR_LEVEL1_LXT975 "LXT975 10/100 Quad PHY" |
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| 358 | #define MII_MODEL_LEVEL1_LXT1000_OLD 0x0003 |
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| 359 | #define MII_STR_LEVEL1_LXT1000_OLD "LXT1000 1000BASE-T media interface" |
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| 360 | #define MII_MODEL_LEVEL1_LXT1000 0x000c |
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| 361 | #define MII_STR_LEVEL1_LXT1000 "LXT1000 1000BASE-T media interface" |
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| 362 | |
|---|
| 363 | /* Marvell Semiconductor PHYs */ |
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| 364 | #define MII_MODEL_xxMARVELL_E1000 0x0000 |
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| 365 | #define MII_STR_xxMARVELL_E1000 "Marvell 88E1000 Gigabit PHY" |
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| 366 | #define MII_MODEL_xxMARVELL_E1011 0x0002 |
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| 367 | #define MII_STR_xxMARVELL_E1011 "Marvell 88E1011 Gigabit PHY" |
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| 368 | #define MII_MODEL_xxMARVELL_E1000_3 0x0003 |
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| 369 | #define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY" |
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| 370 | #define MII_MODEL_xxMARVELL_E1000S 0x0004 |
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| 371 | #define MII_STR_xxMARVELL_E1000S "Marvell 88E1000S Gigabit PHY" |
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| 372 | #define MII_MODEL_xxMARVELL_E1000_5 0x0005 |
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| 373 | #define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY" |
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| 374 | #define MII_MODEL_xxMARVELL_E1101 0x0006 |
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| 375 | #define MII_STR_xxMARVELL_E1101 "Marvell 88E1101 Gigabit PHY" |
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| 376 | #define MII_MODEL_xxMARVELL_E3082 0x0008 |
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| 377 | #define MII_STR_xxMARVELL_E3082 "Marvell 88E3082 10/100 Fast Ethernet PHY" |
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| 378 | #define MII_MODEL_xxMARVELL_E1112 0x0009 |
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| 379 | #define MII_STR_xxMARVELL_E1112 "Marvell 88E1112 Gigabit PHY" |
|---|
| 380 | #define MII_MODEL_xxMARVELL_E1149 0x000b |
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| 381 | #define MII_STR_xxMARVELL_E1149 "Marvell 88E1149 Gigabit PHY" |
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| 382 | #define MII_MODEL_xxMARVELL_E1111 0x000c |
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| 383 | #define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY" |
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| 384 | #define MII_MODEL_xxMARVELL_E1145 0x000d |
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| 385 | #define MII_STR_xxMARVELL_E1145 "Marvell 88E1145 Quad Gigabit PHY" |
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| 386 | #define MII_MODEL_xxMARVELL_E1116 0x0021 |
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| 387 | #define MII_STR_xxMARVELL_E1116 "Marvell 88E1116 Gigabit PHY" |
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| 388 | #define MII_MODEL_xxMARVELL_E1116R 0x0024 |
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| 389 | #define MII_STR_xxMARVELL_E1116R "Marvell 88E1116R Gigabit PHY" |
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| 390 | #define MII_MODEL_xxMARVELL_E1118 0x0022 |
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| 391 | #define MII_STR_xxMARVELL_E1118 "Marvell 88E1118 Gigabit PHY" |
|---|
| 392 | #define MII_MODEL_xxMARVELL_E1149R 0x0025 |
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| 393 | #define MII_STR_xxMARVELL_E1149R "Marvell 88E1149R Quad Gigabit PHY" |
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| 394 | #define MII_MODEL_xxMARVELL_E3016 0x0026 |
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| 395 | #define MII_STR_xxMARVELL_E3016 "Marvell 88E3016 10/100 Fast Ethernet PHY" |
|---|
| 396 | #define MII_MODEL_xxMARVELL_PHYG65G 0x0027 |
|---|
| 397 | #define MII_STR_xxMARVELL_PHYG65G "Marvell PHYG65G Gigabit PHY" |
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| 398 | #define MII_MODEL_xxMARVELL_E1116R_29 0x0029 |
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| 399 | #define MII_STR_xxMARVELL_E1116R_29 "Marvell 88E1116R Gigabit PHY" |
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| 400 | #define MII_MODEL_MARVELL_E1000 0x0005 |
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| 401 | #define MII_STR_MARVELL_E1000 "Marvell 88E1000 Gigabit PHY" |
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| 402 | #define MII_MODEL_MARVELL_E1011 0x0002 |
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| 403 | #define MII_STR_MARVELL_E1011 "Marvell 88E1011 Gigabit PHY" |
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| 404 | #define MII_MODEL_MARVELL_E1000_3 0x0003 |
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| 405 | #define MII_STR_MARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY" |
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| 406 | #define MII_MODEL_MARVELL_E1000_5 0x0005 |
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| 407 | #define MII_STR_MARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY" |
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| 408 | #define MII_MODEL_MARVELL_E1111 0x000c |
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| 409 | #define MII_STR_MARVELL_E1111 "Marvell 88E1111 Gigabit PHY" |
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| 410 | |
|---|
| 411 | /* Micrel PHYs */ |
|---|
| 412 | #define MII_MODEL_MICREL_KSZ9021 0x0021 |
|---|
| 413 | #define MII_STR_MICREL_KSZ9021 "Micrel KSZ9021 10/100/1000 PHY" |
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| 414 | |
|---|
| 415 | /* Myson Technology PHYs */ |
|---|
| 416 | #define MII_MODEL_xxMYSON_MTD972 0x0000 |
|---|
| 417 | #define MII_STR_xxMYSON_MTD972 "MTD972 10/100 media interface" |
|---|
| 418 | #define MII_MODEL_MYSON_MTD803 0x0000 |
|---|
| 419 | #define MII_STR_MYSON_MTD803 "MTD803 3-in-1 media interface" |
|---|
| 420 | |
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| 421 | /* National Semiconductor PHYs */ |
|---|
| 422 | #define MII_MODEL_xxNATSEMI_DP83840 0x0000 |
|---|
| 423 | #define MII_STR_xxNATSEMI_DP83840 "DP83840 10/100 media interface" |
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| 424 | #define MII_MODEL_xxNATSEMI_DP83843 0x0001 |
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| 425 | #define MII_STR_xxNATSEMI_DP83843 "DP83843 10/100 media interface" |
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| 426 | #define MII_MODEL_xxNATSEMI_DP83815 0x0002 |
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| 427 | #define MII_STR_xxNATSEMI_DP83815 "DP83815 10/100 media interface" |
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| 428 | #define MII_MODEL_xxNATSEMI_DP83847 0x0003 |
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| 429 | #define MII_STR_xxNATSEMI_DP83847 "DP83847 10/100 media interface" |
|---|
| 430 | #define MII_MODEL_xxNATSEMI_DP83891 0x0005 |
|---|
| 431 | #define MII_STR_xxNATSEMI_DP83891 "DP83891 1000BASE-T media interface" |
|---|
| 432 | #define MII_MODEL_xxNATSEMI_DP83861 0x0006 |
|---|
| 433 | #define MII_STR_xxNATSEMI_DP83861 "DP83861 1000BASE-T media interface" |
|---|
| 434 | #define MII_MODEL_xxNATSEMI_DP83865 0x0007 |
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| 435 | #define MII_STR_xxNATSEMI_DP83865 "DP83865 1000BASE-T media interface" |
|---|
| 436 | #define MII_MODEL_xxNATSEMI_DP83849 0x000a |
|---|
| 437 | #define MII_STR_xxNATSEMI_DP83849 "DP83849 10/100 media interface" |
|---|
| 438 | |
|---|
| 439 | /* PMC Sierra PHYs */ |
|---|
| 440 | #define MII_MODEL_xxPMCSIERRA_PM8351 0x0000 |
|---|
| 441 | #define MII_STR_xxPMCSIERRA_PM8351 "PM8351 OctalPHY Gigabit interface" |
|---|
| 442 | #define MII_MODEL_xxPMCSIERRA2_PM8352 0x0002 |
|---|
| 443 | #define MII_STR_xxPMCSIERRA2_PM8352 "PM8352 OctalPHY Gigabit interface" |
|---|
| 444 | #define MII_MODEL_xxPMCSIERRA2_PM8353 0x0003 |
|---|
| 445 | #define MII_STR_xxPMCSIERRA2_PM8353 "PM8353 QuadPHY Gigabit interface" |
|---|
| 446 | #define MII_MODEL_PMCSIERRA_PM8354 0x0004 |
|---|
| 447 | #define MII_STR_PMCSIERRA_PM8354 "PM8354 QuadPHY Gigabit interface" |
|---|
| 448 | |
|---|
| 449 | /* Quality Semiconductor PHYs */ |
|---|
| 450 | #define MII_MODEL_xxQUALSEMI_QS6612 0x0000 |
|---|
| 451 | #define MII_STR_xxQUALSEMI_QS6612 "QS6612 10/100 media interface" |
|---|
| 452 | |
|---|
| 453 | /* RDC Semiconductor PHYs */ |
|---|
| 454 | #define MII_MODEL_RDC_R6040 0x0003 |
|---|
| 455 | #define MII_STR_RDC_R6040 "R6040 10/100 media interface" |
|---|
| 456 | |
|---|
| 457 | /* RealTek Semicondctor PHYs */ |
|---|
| 458 | #define MII_MODEL_yyREALTEK_RTL8201L 0x0020 |
|---|
| 459 | #define MII_STR_yyREALTEK_RTL8201L "RTL8201L 10/100 media interface" |
|---|
| 460 | #define MII_MODEL_xxREALTEK_RTL8169S 0x0011 |
|---|
| 461 | #define MII_STR_xxREALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface" |
|---|
| 462 | #define MII_MODEL_REALTEK_RTL8305SC 0x0005 |
|---|
| 463 | #define MII_STR_REALTEK_RTL8305SC "RTL8305SC 10/100 802.1q switch" |
|---|
| 464 | #define MII_MODEL_REALTEK_RTL8201E 0x0008 |
|---|
| 465 | #define MII_STR_REALTEK_RTL8201E "RTL8201E 10/100 media interface" |
|---|
| 466 | #define MII_MODEL_REALTEK_RTL8251 0x0000 |
|---|
| 467 | #define MII_STR_REALTEK_RTL8251 "RTL8251 1000BASE-T media interface" |
|---|
| 468 | #define MII_MODEL_REALTEK_RTL8169S 0x0011 |
|---|
| 469 | #define MII_STR_REALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface" |
|---|
| 470 | |
|---|
| 471 | /* Seeq Seeq PHYs */ |
|---|
| 472 | #define MII_MODEL_SEEQ_80220 0x0003 |
|---|
| 473 | #define MII_STR_SEEQ_80220 "Seeq 80220 10/100 media interface" |
|---|
| 474 | #define MII_MODEL_SEEQ_84220 0x0004 |
|---|
| 475 | #define MII_STR_SEEQ_84220 "Seeq 84220 10/100 media interface" |
|---|
| 476 | #define MII_MODEL_SEEQ_80225 0x0008 |
|---|
| 477 | #define MII_STR_SEEQ_80225 "Seeq 80225 10/100 media interface" |
|---|
| 478 | |
|---|
| 479 | /* Silicon Integrated Systems PHYs */ |
|---|
| 480 | #define MII_MODEL_SIS_900 0x0000 |
|---|
| 481 | #define MII_STR_SIS_900 "SiS 900 10/100 media interface" |
|---|
| 482 | |
|---|
| 483 | /* Texas Instruments PHYs */ |
|---|
| 484 | #define MII_MODEL_TI_TLAN10T 0x0001 |
|---|
| 485 | #define MII_STR_TI_TLAN10T "ThunderLAN 10BASE-T media interface" |
|---|
| 486 | #define MII_MODEL_TI_100VGPMI 0x0002 |
|---|
| 487 | #define MII_STR_TI_100VGPMI "ThunderLAN 100VG-AnyLan media interface" |
|---|
| 488 | #define MII_MODEL_TI_TNETE2101 0x0003 |
|---|
| 489 | #define MII_STR_TI_TNETE2101 "TNETE2101 media interface" |
|---|
| 490 | |
|---|
| 491 | /* TDK Semiconductor PHYs */ |
|---|
| 492 | #define MII_MODEL_xxTSC_78Q2120 0x0014 |
|---|
| 493 | #define MII_STR_xxTSC_78Q2120 "78Q2120 10/100 media interface" |
|---|
| 494 | #define MII_MODEL_xxTSC_78Q2121 0x0015 |
|---|
| 495 | #define MII_STR_xxTSC_78Q2121 "78Q2121 100BASE-TX media interface" |
|---|
| 496 | |
|---|
| 497 | /* Vitesse Semiconductor */ |
|---|
| 498 | #define MII_MODEL_xxVITESSE_VSC8641 0x0003 |
|---|
| 499 | #define MII_STR_xxVITESSE_VSC8641 "Vitesse VSC8641 10/100/1000TX PHY" |
|---|
| 500 | |
|---|
| 501 | /* XaQti Corp. PHYs */ |
|---|
| 502 | #define MII_MODEL_xxXAQTI_XMACII 0x0000 |
|---|
| 503 | #define MII_STR_xxXAQTI_XMACII "XaQti Corp. XMAC II gigabit interface" |
|---|
| 504 | |
|---|
| 505 | /* SMC */ |
|---|
| 506 | #define MII_MODEL_SMC_LAN8710A 0x000F |
|---|
| 507 | #define MII_STR_SMC_LAN8710A "SMC LAN8710A 10/100 interface" |
|---|
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