[cd089b9] | 1 | /* Copyright 2008 - 2016 Freescale Semiconductor, Inc. |
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[28ee86a] | 2 | * |
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| 3 | * Redistribution and use in source and binary forms, with or without |
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| 4 | * modification, are permitted provided that the following conditions are met: |
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| 5 | * * Redistributions of source code must retain the above copyright |
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| 6 | * notice, this list of conditions and the following disclaimer. |
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| 7 | * * Redistributions in binary form must reproduce the above copyright |
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| 8 | * notice, this list of conditions and the following disclaimer in the |
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| 9 | * documentation and/or other materials provided with the distribution. |
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| 10 | * * Neither the name of Freescale Semiconductor nor the |
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| 11 | * names of its contributors may be used to endorse or promote products |
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| 12 | * derived from this software without specific prior written permission. |
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| 13 | * |
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| 14 | * ALTERNATIVELY, this software may be distributed under the terms of the |
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| 15 | * GNU General Public License ("GPL") as published by the Free Software |
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| 16 | * Foundation, either version 2 of that License or (at your option) any |
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| 17 | * later version. |
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| 18 | * |
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| 19 | * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
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| 20 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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| 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 22 | * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
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| 23 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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| 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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| 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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| 26 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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| 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 29 | */ |
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| 30 | |
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| 31 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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| 32 | |
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| 33 | #include "dpaa_sys.h" |
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| 34 | |
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| 35 | #include <soc/fsl/qman.h> |
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[cf40770] | 36 | #include <linux/dma-mapping.h> |
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[28ee86a] | 37 | #include <linux/iommu.h> |
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[cd089b9] | 38 | |
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| 39 | #if defined(CONFIG_FSL_PAMU) |
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[28ee86a] | 40 | #include <asm/fsl_pamu_stash.h> |
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[cd089b9] | 41 | #endif |
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| 42 | |
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| 43 | struct qm_mcr_querywq { |
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| 44 | u8 verb; |
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| 45 | u8 result; |
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| 46 | u16 channel_wq; /* ignores wq (3 lsbits): _res[0-2] */ |
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| 47 | u8 __reserved[28]; |
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| 48 | u32 wq_len[8]; |
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| 49 | } __packed; |
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| 50 | |
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| 51 | static inline u16 qm_mcr_querywq_get_chan(const struct qm_mcr_querywq *wq) |
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| 52 | { |
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| 53 | return wq->channel_wq >> 3; |
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| 54 | } |
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| 55 | |
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| 56 | struct __qm_mcr_querycongestion { |
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| 57 | u32 state[8]; |
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| 58 | }; |
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| 59 | |
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| 60 | /* "Query Congestion Group State" */ |
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| 61 | struct qm_mcr_querycongestion { |
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| 62 | u8 verb; |
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| 63 | u8 result; |
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| 64 | u8 __reserved[30]; |
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| 65 | /* Access this struct using qman_cgrs_get() */ |
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| 66 | struct __qm_mcr_querycongestion state; |
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| 67 | } __packed; |
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| 68 | |
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| 69 | /* "Query CGR" */ |
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| 70 | struct qm_mcr_querycgr { |
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| 71 | u8 verb; |
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| 72 | u8 result; |
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| 73 | u16 __reserved1; |
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| 74 | struct __qm_mc_cgr cgr; /* CGR fields */ |
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| 75 | u8 __reserved2[6]; |
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| 76 | u8 i_bcnt_hi; /* high 8-bits of 40-bit "Instant" */ |
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| 77 | __be32 i_bcnt_lo; /* low 32-bits of 40-bit */ |
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| 78 | u8 __reserved3[3]; |
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| 79 | u8 a_bcnt_hi; /* high 8-bits of 40-bit "Average" */ |
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| 80 | __be32 a_bcnt_lo; /* low 32-bits of 40-bit */ |
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| 81 | __be32 cscn_targ_swp[4]; |
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| 82 | } __packed; |
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| 83 | |
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| 84 | static inline u64 qm_mcr_querycgr_i_get64(const struct qm_mcr_querycgr *q) |
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| 85 | { |
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| 86 | return ((u64)q->i_bcnt_hi << 32) | be32_to_cpu(q->i_bcnt_lo); |
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| 87 | } |
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| 88 | static inline u64 qm_mcr_querycgr_a_get64(const struct qm_mcr_querycgr *q) |
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| 89 | { |
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| 90 | return ((u64)q->a_bcnt_hi << 32) | be32_to_cpu(q->a_bcnt_lo); |
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| 91 | } |
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| 92 | |
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[28ee86a] | 93 | /* Congestion Groups */ |
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| 94 | |
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[cd089b9] | 95 | /* |
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| 96 | * This wrapper represents a bit-array for the state of the 256 QMan congestion |
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[28ee86a] | 97 | * groups. Is also used as a *mask* for congestion groups, eg. so we ignore |
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| 98 | * those that don't concern us. We harness the structure and accessor details |
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| 99 | * already used in the management command to query congestion groups. |
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| 100 | */ |
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[cd089b9] | 101 | #define CGR_BITS_PER_WORD 5 |
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| 102 | #define CGR_WORD(x) ((x) >> CGR_BITS_PER_WORD) |
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| 103 | #define CGR_BIT(x) (BIT(31) >> ((x) & 0x1f)) |
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| 104 | #define CGR_NUM (sizeof(struct __qm_mcr_querycongestion) << 3) |
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| 105 | |
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[28ee86a] | 106 | struct qman_cgrs { |
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| 107 | struct __qm_mcr_querycongestion q; |
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| 108 | }; |
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[cd089b9] | 109 | |
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[28ee86a] | 110 | static inline void qman_cgrs_init(struct qman_cgrs *c) |
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| 111 | { |
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| 112 | memset(c, 0, sizeof(*c)); |
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| 113 | } |
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[cd089b9] | 114 | |
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[28ee86a] | 115 | static inline void qman_cgrs_fill(struct qman_cgrs *c) |
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| 116 | { |
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| 117 | memset(c, 0xff, sizeof(*c)); |
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| 118 | } |
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[cd089b9] | 119 | |
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| 120 | static inline int qman_cgrs_get(struct qman_cgrs *c, u8 cgr) |
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[28ee86a] | 121 | { |
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[cd089b9] | 122 | return c->q.state[CGR_WORD(cgr)] & CGR_BIT(cgr); |
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[28ee86a] | 123 | } |
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[cd089b9] | 124 | |
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[28ee86a] | 125 | static inline void qman_cgrs_cp(struct qman_cgrs *dest, |
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| 126 | const struct qman_cgrs *src) |
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| 127 | { |
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| 128 | *dest = *src; |
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| 129 | } |
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[cd089b9] | 130 | |
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[28ee86a] | 131 | static inline void qman_cgrs_and(struct qman_cgrs *dest, |
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| 132 | const struct qman_cgrs *a, const struct qman_cgrs *b) |
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| 133 | { |
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| 134 | int ret; |
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[cd089b9] | 135 | u32 *_d = dest->q.state; |
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| 136 | const u32 *_a = a->q.state; |
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| 137 | const u32 *_b = b->q.state; |
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[28ee86a] | 138 | |
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| 139 | for (ret = 0; ret < 8; ret++) |
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[cd089b9] | 140 | *_d++ = *_a++ & *_b++; |
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[28ee86a] | 141 | } |
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[cd089b9] | 142 | |
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[28ee86a] | 143 | static inline void qman_cgrs_xor(struct qman_cgrs *dest, |
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| 144 | const struct qman_cgrs *a, const struct qman_cgrs *b) |
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| 145 | { |
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| 146 | int ret; |
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[cd089b9] | 147 | u32 *_d = dest->q.state; |
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| 148 | const u32 *_a = a->q.state; |
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| 149 | const u32 *_b = b->q.state; |
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[28ee86a] | 150 | |
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| 151 | for (ret = 0; ret < 8; ret++) |
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[cd089b9] | 152 | *_d++ = *_a++ ^ *_b++; |
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[28ee86a] | 153 | } |
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| 154 | |
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[cd089b9] | 155 | void qman_init_cgr_all(void); |
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[28ee86a] | 156 | |
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| 157 | struct qm_portal_config { |
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[cd089b9] | 158 | /* |
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| 159 | * Corenet portal addresses; |
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| 160 | * [0]==cache-enabled, [1]==cache-inhibited. |
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| 161 | */ |
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| 162 | void __iomem *addr_virt[2]; |
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[28ee86a] | 163 | #ifndef __rtems__ |
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[cd089b9] | 164 | struct device *dev; |
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[28ee86a] | 165 | struct iommu_domain *iommu_domain; |
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| 166 | /* Allow these to be joined in lists */ |
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| 167 | struct list_head list; |
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| 168 | #endif /* __rtems__ */ |
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| 169 | /* User-visible portal configuration settings */ |
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[cd089b9] | 170 | /* portal is affined to this cpu */ |
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| 171 | int cpu; |
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| 172 | /* portal interrupt line */ |
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| 173 | int irq; |
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| 174 | /* |
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| 175 | * the portal's dedicated channel id, used initialising |
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| 176 | * frame queues to target this portal when scheduled |
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| 177 | */ |
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| 178 | u16 channel; |
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| 179 | /* |
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| 180 | * mask of pool channels this portal has dequeue access to |
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| 181 | * (using QM_SDQCR_CHANNELS_POOL(n) for the bitmask) |
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| 182 | */ |
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| 183 | u32 pools; |
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[28ee86a] | 184 | }; |
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| 185 | |
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| 186 | /* Revision info (for errata and feature handling) */ |
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| 187 | #define QMAN_REV11 0x0101 |
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| 188 | #define QMAN_REV12 0x0102 |
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| 189 | #define QMAN_REV20 0x0200 |
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| 190 | #define QMAN_REV30 0x0300 |
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| 191 | #define QMAN_REV31 0x0301 |
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| 192 | extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */ |
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| 193 | |
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[cd089b9] | 194 | #define QM_FQID_RANGE_START 1 /* FQID 0 reserved for internal use */ |
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| 195 | extern struct gen_pool *qm_fqalloc; /* FQID allocator */ |
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| 196 | extern struct gen_pool *qm_qpalloc; /* pool-channel allocator */ |
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| 197 | extern struct gen_pool *qm_cgralloc; /* CGR ID allocator */ |
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| 198 | u32 qm_get_pools_sdqcr(void); |
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[28ee86a] | 199 | |
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[cd089b9] | 200 | int qman_wq_alloc(void); |
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[28ee86a] | 201 | void qman_liodn_fixup(u16 channel); |
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[cd089b9] | 202 | void qman_set_sdest(u16 channel, unsigned int cpu_idx); |
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[28ee86a] | 203 | |
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| 204 | struct qman_portal *qman_create_affine_portal( |
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| 205 | const struct qm_portal_config *config, |
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| 206 | const struct qman_cgrs *cgrs); |
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| 207 | const struct qm_portal_config *qman_destroy_affine_portal(void); |
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| 208 | |
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[cd089b9] | 209 | /* |
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| 210 | * qman_query_fq - Queries FQD fields (via h/w query command) |
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| 211 | * @fq: the frame queue object to be queried |
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| 212 | * @fqd: storage for the queried FQD fields |
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| 213 | */ |
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| 214 | int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd); |
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[28ee86a] | 215 | |
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[cd089b9] | 216 | int qman_alloc_fq_table(u32 num_fqids); |
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| 217 | |
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| 218 | /* QMan s/w corenet portal, low-level i/face */ |
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[28ee86a] | 219 | |
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[cd089b9] | 220 | /* |
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| 221 | * For qm_dqrr_sdqcr_set(); Choose one SOURCE. Choose one COUNT. Choose one |
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[28ee86a] | 222 | * dequeue TYPE. Choose TOKEN (8-bit). |
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| 223 | * If SOURCE == CHANNELS, |
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| 224 | * Choose CHANNELS_DEDICATED and/or CHANNELS_POOL(n). |
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| 225 | * You can choose DEDICATED_PRECEDENCE if the portal channel should have |
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| 226 | * priority. |
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| 227 | * If SOURCE == SPECIFICWQ, |
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| 228 | * Either select the work-queue ID with SPECIFICWQ_WQ(), or select the |
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| 229 | * channel (SPECIFICWQ_DEDICATED or SPECIFICWQ_POOL()) and specify the |
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| 230 | * work-queue priority (0-7) with SPECIFICWQ_WQ() - either way, you get the |
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| 231 | * same value. |
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| 232 | */ |
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| 233 | #define QM_SDQCR_SOURCE_CHANNELS 0x0 |
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| 234 | #define QM_SDQCR_SOURCE_SPECIFICWQ 0x40000000 |
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| 235 | #define QM_SDQCR_COUNT_EXACT1 0x0 |
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| 236 | #define QM_SDQCR_COUNT_UPTO3 0x20000000 |
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| 237 | #define QM_SDQCR_DEDICATED_PRECEDENCE 0x10000000 |
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| 238 | #define QM_SDQCR_TYPE_MASK 0x03000000 |
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| 239 | #define QM_SDQCR_TYPE_NULL 0x0 |
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| 240 | #define QM_SDQCR_TYPE_PRIO_QOS 0x01000000 |
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| 241 | #define QM_SDQCR_TYPE_ACTIVE_QOS 0x02000000 |
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| 242 | #define QM_SDQCR_TYPE_ACTIVE 0x03000000 |
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| 243 | #define QM_SDQCR_TOKEN_MASK 0x00ff0000 |
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| 244 | #define QM_SDQCR_TOKEN_SET(v) (((v) & 0xff) << 16) |
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| 245 | #define QM_SDQCR_TOKEN_GET(v) (((v) >> 16) & 0xff) |
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| 246 | #define QM_SDQCR_CHANNELS_DEDICATED 0x00008000 |
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| 247 | #define QM_SDQCR_SPECIFICWQ_MASK 0x000000f7 |
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| 248 | #define QM_SDQCR_SPECIFICWQ_DEDICATED 0x00000000 |
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| 249 | #define QM_SDQCR_SPECIFICWQ_POOL(n) ((n) << 4) |
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| 250 | #define QM_SDQCR_SPECIFICWQ_WQ(n) (n) |
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| 251 | |
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| 252 | /* For qm_dqrr_vdqcr_set(): use FQID(n) to fill in the frame queue ID */ |
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| 253 | #define QM_VDQCR_FQID_MASK 0x00ffffff |
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| 254 | #define QM_VDQCR_FQID(n) ((n) & QM_VDQCR_FQID_MASK) |
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| 255 | |
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[cd089b9] | 256 | /* |
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| 257 | * Used by all portal interrupt registers except 'inhibit' |
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[28ee86a] | 258 | * Channels with frame availability |
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| 259 | */ |
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| 260 | #define QM_PIRQ_DQAVAIL 0x0000ffff |
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| 261 | |
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| 262 | /* The DQAVAIL interrupt fields break down into these bits; */ |
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| 263 | #define QM_DQAVAIL_PORTAL 0x8000 /* Portal channel */ |
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| 264 | #define QM_DQAVAIL_POOL(n) (0x8000 >> (n)) /* Pool channel, n==[1..15] */ |
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| 265 | #define QM_DQAVAIL_MASK 0xffff |
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| 266 | /* This mask contains all the "irqsource" bits visible to API users */ |
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| 267 | #define QM_PIRQ_VISIBLE (QM_PIRQ_SLOW | QM_PIRQ_DQRI) |
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| 268 | |
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[cd089b9] | 269 | extern struct qman_portal *affine_portals[NR_CPUS]; |
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| 270 | extern struct qman_portal *qman_dma_portal; |
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[28ee86a] | 271 | const struct qm_portal_config *qman_get_qm_portal_config( |
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| 272 | struct qman_portal *portal); |
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[cd089b9] | 273 | #ifdef __rtems__ |
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| 274 | void qman_sysinit_portals(void); |
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| 275 | #endif /* __rtems__ */ |
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