[28ee86a] | 1 | #include <machine/rtems-bsd-kernel-space.h> |
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| 2 | |
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| 3 | #include <rtems/bsd/local/opt_dpaa.h> |
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| 4 | |
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[cd089b9] | 5 | /* Copyright 2008 - 2016 Freescale Semiconductor, Inc. |
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[28ee86a] | 6 | * |
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| 7 | * Redistribution and use in source and binary forms, with or without |
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| 8 | * modification, are permitted provided that the following conditions are met: |
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| 9 | * * Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * * Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * * Neither the name of Freescale Semiconductor nor the |
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| 15 | * names of its contributors may be used to endorse or promote products |
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| 16 | * derived from this software without specific prior written permission. |
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| 17 | * |
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| 18 | * ALTERNATIVELY, this software may be distributed under the terms of the |
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| 19 | * GNU General Public License ("GPL") as published by the Free Software |
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| 20 | * Foundation, either version 2 of that License or (at your option) any |
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| 21 | * later version. |
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| 22 | * |
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| 23 | * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
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| 24 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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| 25 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 26 | * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
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| 27 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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| 28 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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| 29 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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| 30 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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| 32 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 33 | */ |
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| 34 | |
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| 35 | #include "qman_priv.h" |
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| 36 | #ifdef __rtems__ |
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[cd089b9] | 37 | #undef dev_crit |
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| 38 | #undef dev_info |
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| 39 | #define dev_crit(dev, fmt, ...) printf(fmt, ##__VA_ARGS__) |
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| 40 | #define dev_info dev_crit |
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| 41 | #endif /* __rtems__ */ |
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| 42 | |
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| 43 | #ifndef __rtems__ |
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| 44 | struct qman_portal *qman_dma_portal; |
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| 45 | EXPORT_SYMBOL(qman_dma_portal); |
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[28ee86a] | 46 | #endif /* __rtems__ */ |
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| 47 | |
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| 48 | /* Enable portal interupts (as opposed to polling mode) */ |
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| 49 | #define CONFIG_FSL_DPA_PIRQ_SLOW 1 |
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| 50 | #define CONFIG_FSL_DPA_PIRQ_FAST 1 |
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| 51 | |
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| 52 | #ifndef __rtems__ |
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[cd089b9] | 53 | static struct cpumask portal_cpus; |
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| 54 | /* protect qman global registers and global data shared among portals */ |
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| 55 | static DEFINE_SPINLOCK(qman_lock); |
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[28ee86a] | 56 | #endif /* __rtems__ */ |
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| 57 | |
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| 58 | static void portal_set_cpu(struct qm_portal_config *pcfg, int cpu) |
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| 59 | { |
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| 60 | #ifdef CONFIG_FSL_PAMU |
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[cd089b9] | 61 | struct device *dev = pcfg->dev; |
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[28ee86a] | 62 | int window_count = 1; |
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| 63 | struct iommu_domain_geometry geom_attr; |
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| 64 | struct pamu_stash_attribute stash_attr; |
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[cd089b9] | 65 | int ret; |
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[28ee86a] | 66 | |
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| 67 | pcfg->iommu_domain = iommu_domain_alloc(&platform_bus_type); |
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| 68 | if (!pcfg->iommu_domain) { |
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[cd089b9] | 69 | dev_err(dev, "%s(): iommu_domain_alloc() failed", __func__); |
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| 70 | goto no_iommu; |
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[28ee86a] | 71 | } |
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| 72 | geom_attr.aperture_start = 0; |
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| 73 | geom_attr.aperture_end = |
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| 74 | ((dma_addr_t)1 << min(8 * sizeof(dma_addr_t), (size_t)36)) - 1; |
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| 75 | geom_attr.force_aperture = true; |
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| 76 | ret = iommu_domain_set_attr(pcfg->iommu_domain, DOMAIN_ATTR_GEOMETRY, |
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| 77 | &geom_attr); |
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| 78 | if (ret < 0) { |
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[cd089b9] | 79 | dev_err(dev, "%s(): iommu_domain_set_attr() = %d", __func__, |
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| 80 | ret); |
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| 81 | goto out_domain_free; |
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[28ee86a] | 82 | } |
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| 83 | ret = iommu_domain_set_attr(pcfg->iommu_domain, DOMAIN_ATTR_WINDOWS, |
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| 84 | &window_count); |
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| 85 | if (ret < 0) { |
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[cd089b9] | 86 | dev_err(dev, "%s(): iommu_domain_set_attr() = %d", __func__, |
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| 87 | ret); |
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| 88 | goto out_domain_free; |
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[28ee86a] | 89 | } |
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| 90 | stash_attr.cpu = cpu; |
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| 91 | stash_attr.cache = PAMU_ATTR_CACHE_L1; |
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| 92 | ret = iommu_domain_set_attr(pcfg->iommu_domain, |
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| 93 | DOMAIN_ATTR_FSL_PAMU_STASH, |
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| 94 | &stash_attr); |
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| 95 | if (ret < 0) { |
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[cd089b9] | 96 | dev_err(dev, "%s(): iommu_domain_set_attr() = %d", |
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| 97 | __func__, ret); |
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| 98 | goto out_domain_free; |
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[28ee86a] | 99 | } |
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| 100 | ret = iommu_domain_window_enable(pcfg->iommu_domain, 0, 0, 1ULL << 36, |
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| 101 | IOMMU_READ | IOMMU_WRITE); |
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| 102 | if (ret < 0) { |
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[cd089b9] | 103 | dev_err(dev, "%s(): iommu_domain_window_enable() = %d", |
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| 104 | __func__, ret); |
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| 105 | goto out_domain_free; |
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[28ee86a] | 106 | } |
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[cd089b9] | 107 | ret = iommu_attach_device(pcfg->iommu_domain, dev); |
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[28ee86a] | 108 | if (ret < 0) { |
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[cd089b9] | 109 | dev_err(dev, "%s(): iommu_device_attach() = %d", __func__, |
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| 110 | ret); |
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| 111 | goto out_domain_free; |
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[28ee86a] | 112 | } |
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| 113 | ret = iommu_domain_set_attr(pcfg->iommu_domain, |
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| 114 | DOMAIN_ATTR_FSL_PAMU_ENABLE, |
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| 115 | &window_count); |
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| 116 | if (ret < 0) { |
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[cd089b9] | 117 | dev_err(dev, "%s(): iommu_domain_set_attr() = %d", __func__, |
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| 118 | ret); |
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| 119 | goto out_detach_device; |
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[28ee86a] | 120 | } |
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| 121 | |
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[cd089b9] | 122 | no_iommu: |
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[28ee86a] | 123 | #endif |
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[cd089b9] | 124 | qman_set_sdest(pcfg->channel, cpu); |
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[28ee86a] | 125 | |
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| 126 | return; |
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| 127 | |
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| 128 | #ifdef CONFIG_FSL_PAMU |
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[cd089b9] | 129 | out_detach_device: |
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[28ee86a] | 130 | iommu_detach_device(pcfg->iommu_domain, NULL); |
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[cd089b9] | 131 | out_domain_free: |
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[28ee86a] | 132 | iommu_domain_free(pcfg->iommu_domain); |
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| 133 | pcfg->iommu_domain = NULL; |
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| 134 | #endif |
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| 135 | } |
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| 136 | |
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| 137 | static struct qman_portal *init_pcfg(struct qm_portal_config *pcfg) |
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| 138 | { |
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| 139 | struct qman_portal *p; |
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[cd089b9] | 140 | u32 irq_sources = 0; |
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| 141 | |
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| 142 | /* We need the same LIODN offset for all portals */ |
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| 143 | qman_liodn_fixup(pcfg->channel); |
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[28ee86a] | 144 | |
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| 145 | #ifndef __rtems__ |
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| 146 | pcfg->iommu_domain = NULL; |
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| 147 | #endif /* __rtems__ */ |
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[cd089b9] | 148 | portal_set_cpu(pcfg, pcfg->cpu); |
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[28ee86a] | 149 | p = qman_create_affine_portal(pcfg, NULL); |
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[cd089b9] | 150 | if (!p) { |
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| 151 | dev_crit(pcfg->dev, "%s: Portal failure on cpu %d\n", |
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| 152 | __func__, pcfg->cpu); |
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| 153 | return NULL; |
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| 154 | } |
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| 155 | |
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| 156 | /* Determine what should be interrupt-vs-poll driven */ |
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[28ee86a] | 157 | #ifdef CONFIG_FSL_DPA_PIRQ_SLOW |
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[cd089b9] | 158 | irq_sources |= QM_PIRQ_EQCI | QM_PIRQ_EQRI | QM_PIRQ_MRI | |
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| 159 | QM_PIRQ_CSCI; |
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[28ee86a] | 160 | #endif |
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| 161 | #ifdef CONFIG_FSL_DPA_PIRQ_FAST |
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[cd089b9] | 162 | irq_sources |= QM_PIRQ_DQRI; |
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[28ee86a] | 163 | #endif |
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[cd089b9] | 164 | qman_p_irqsource_add(p, irq_sources); |
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[28ee86a] | 165 | |
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| 166 | #ifndef __rtems__ |
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[cd089b9] | 167 | spin_lock(&qman_lock); |
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| 168 | if (cpumask_equal(&portal_cpus, cpu_possible_mask)) { |
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| 169 | /* all assigned portals are initialized now */ |
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| 170 | qman_init_cgr_all(); |
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| 171 | } |
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[28ee86a] | 172 | |
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[cd089b9] | 173 | if (!qman_dma_portal) |
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| 174 | qman_dma_portal = p; |
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[28ee86a] | 175 | |
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[cd089b9] | 176 | spin_unlock(&qman_lock); |
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| 177 | #endif /* __rtems__ */ |
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| 178 | |
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| 179 | dev_info(pcfg->dev, "Portal initialised, cpu %d\n", pcfg->cpu); |
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| 180 | |
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| 181 | return p; |
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[28ee86a] | 182 | } |
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| 183 | |
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| 184 | static void qman_portal_update_sdest(const struct qm_portal_config *pcfg, |
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| 185 | unsigned int cpu) |
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| 186 | { |
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[cd089b9] | 187 | #ifdef CONFIG_FSL_PAMU /* TODO */ |
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[28ee86a] | 188 | struct pamu_stash_attribute stash_attr; |
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| 189 | int ret; |
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| 190 | |
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| 191 | if (pcfg->iommu_domain) { |
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| 192 | stash_attr.cpu = cpu; |
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| 193 | stash_attr.cache = PAMU_ATTR_CACHE_L1; |
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| 194 | ret = iommu_domain_set_attr(pcfg->iommu_domain, |
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| 195 | DOMAIN_ATTR_FSL_PAMU_STASH, &stash_attr); |
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| 196 | if (ret < 0) { |
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[cd089b9] | 197 | dev_err(pcfg->dev, |
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| 198 | "Failed to update pamu stash setting\n"); |
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[28ee86a] | 199 | return; |
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| 200 | } |
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| 201 | } |
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| 202 | #endif |
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[cd089b9] | 203 | qman_set_sdest(pcfg->channel, cpu); |
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[28ee86a] | 204 | } |
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| 205 | |
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[cd089b9] | 206 | #ifndef __rtems__ |
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| 207 | static int qman_offline_cpu(unsigned int cpu) |
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[28ee86a] | 208 | { |
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| 209 | struct qman_portal *p; |
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| 210 | const struct qm_portal_config *pcfg; |
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| 211 | |
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[cd089b9] | 212 | p = affine_portals[cpu]; |
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[28ee86a] | 213 | if (p) { |
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| 214 | pcfg = qman_get_qm_portal_config(p); |
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| 215 | if (pcfg) { |
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[cd089b9] | 216 | irq_set_affinity(pcfg->irq, cpumask_of(0)); |
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[28ee86a] | 217 | qman_portal_update_sdest(pcfg, 0); |
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| 218 | } |
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| 219 | } |
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[cd089b9] | 220 | return 0; |
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[28ee86a] | 221 | } |
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| 222 | |
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[cd089b9] | 223 | static int qman_online_cpu(unsigned int cpu) |
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[28ee86a] | 224 | { |
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| 225 | struct qman_portal *p; |
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| 226 | const struct qm_portal_config *pcfg; |
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| 227 | |
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[cd089b9] | 228 | p = affine_portals[cpu]; |
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[28ee86a] | 229 | if (p) { |
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| 230 | pcfg = qman_get_qm_portal_config(p); |
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| 231 | if (pcfg) { |
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[cd089b9] | 232 | irq_set_affinity(pcfg->irq, cpumask_of(cpu)); |
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[28ee86a] | 233 | qman_portal_update_sdest(pcfg, cpu); |
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| 234 | } |
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| 235 | } |
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[cd089b9] | 236 | return 0; |
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[28ee86a] | 237 | } |
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| 238 | |
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[cd089b9] | 239 | static int qman_portal_probe(struct platform_device *pdev) |
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[28ee86a] | 240 | { |
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[cd089b9] | 241 | struct device *dev = &pdev->dev; |
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| 242 | struct device_node *node = dev->of_node; |
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| 243 | struct qm_portal_config *pcfg; |
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| 244 | struct resource *addr_phys[2]; |
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| 245 | void __iomem *va; |
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| 246 | int irq, cpu, err; |
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| 247 | u32 val; |
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| 248 | |
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| 249 | pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL); |
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| 250 | if (!pcfg) |
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| 251 | return -ENOMEM; |
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| 252 | |
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| 253 | pcfg->dev = dev; |
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| 254 | |
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| 255 | addr_phys[0] = platform_get_resource(pdev, IORESOURCE_MEM, |
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| 256 | DPAA_PORTAL_CE); |
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| 257 | if (!addr_phys[0]) { |
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| 258 | dev_err(dev, "Can't get %s property 'reg::CE'\n", |
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| 259 | node->full_name); |
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| 260 | return -ENXIO; |
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| 261 | } |
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| 262 | |
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| 263 | addr_phys[1] = platform_get_resource(pdev, IORESOURCE_MEM, |
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| 264 | DPAA_PORTAL_CI); |
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| 265 | if (!addr_phys[1]) { |
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| 266 | dev_err(dev, "Can't get %s property 'reg::CI'\n", |
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| 267 | node->full_name); |
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| 268 | return -ENXIO; |
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| 269 | } |
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| 270 | |
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| 271 | err = of_property_read_u32(node, "cell-index", &val); |
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| 272 | if (err) { |
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| 273 | dev_err(dev, "Can't get %s property 'cell-index'\n", |
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| 274 | node->full_name); |
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| 275 | return err; |
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| 276 | } |
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| 277 | pcfg->channel = val; |
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| 278 | pcfg->cpu = -1; |
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| 279 | irq = platform_get_irq(pdev, 0); |
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[721b1c1] | 280 | if (irq < 0) { |
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[cd089b9] | 281 | dev_err(dev, "Can't get %s IRQ\n", node->full_name); |
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| 282 | return -ENXIO; |
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| 283 | } |
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| 284 | pcfg->irq = irq; |
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| 285 | |
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| 286 | va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0); |
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| 287 | if (!va) { |
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| 288 | dev_err(dev, "ioremap::CE failed\n"); |
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| 289 | goto err_ioremap1; |
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| 290 | } |
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| 291 | |
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| 292 | pcfg->addr_virt[DPAA_PORTAL_CE] = va; |
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| 293 | |
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| 294 | va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]), |
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| 295 | _PAGE_GUARDED | _PAGE_NO_CACHE); |
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| 296 | if (!va) { |
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| 297 | dev_err(dev, "ioremap::CI failed\n"); |
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| 298 | goto err_ioremap2; |
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| 299 | } |
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| 300 | |
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| 301 | pcfg->addr_virt[DPAA_PORTAL_CI] = va; |
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| 302 | |
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| 303 | pcfg->pools = qm_get_pools_sdqcr(); |
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| 304 | |
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| 305 | spin_lock(&qman_lock); |
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| 306 | cpu = cpumask_next_zero(-1, &portal_cpus); |
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| 307 | if (cpu >= nr_cpu_ids) { |
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| 308 | /* unassigned portal, skip init */ |
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| 309 | spin_unlock(&qman_lock); |
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| 310 | return 0; |
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| 311 | } |
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| 312 | |
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| 313 | cpumask_set_cpu(cpu, &portal_cpus); |
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| 314 | spin_unlock(&qman_lock); |
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| 315 | pcfg->cpu = cpu; |
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| 316 | |
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| 317 | if (dma_set_mask(dev, DMA_BIT_MASK(40))) { |
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| 318 | dev_err(dev, "dma_set_mask() failed\n"); |
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| 319 | goto err_portal_init; |
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| 320 | } |
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| 321 | |
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| 322 | if (!init_pcfg(pcfg)) { |
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| 323 | dev_err(dev, "portal init failed\n"); |
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| 324 | goto err_portal_init; |
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[28ee86a] | 325 | } |
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[cd089b9] | 326 | |
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| 327 | /* clear irq affinity if assigned cpu is offline */ |
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| 328 | if (!cpu_online(cpu)) |
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| 329 | qman_offline_cpu(cpu); |
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| 330 | |
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| 331 | return 0; |
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| 332 | |
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| 333 | err_portal_init: |
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| 334 | iounmap(pcfg->addr_virt[DPAA_PORTAL_CI]); |
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| 335 | err_ioremap2: |
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| 336 | iounmap(pcfg->addr_virt[DPAA_PORTAL_CE]); |
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| 337 | err_ioremap1: |
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| 338 | return -ENXIO; |
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[28ee86a] | 339 | } |
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| 340 | |
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[cd089b9] | 341 | static const struct of_device_id qman_portal_ids[] = { |
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| 342 | { |
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| 343 | .compatible = "fsl,qman-portal", |
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| 344 | }, |
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| 345 | {} |
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| 346 | }; |
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| 347 | MODULE_DEVICE_TABLE(of, qman_portal_ids); |
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| 348 | |
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| 349 | static struct platform_driver qman_portal_driver = { |
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| 350 | .driver = { |
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| 351 | .name = KBUILD_MODNAME, |
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| 352 | .of_match_table = qman_portal_ids, |
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| 353 | }, |
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| 354 | .probe = qman_portal_probe, |
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[28ee86a] | 355 | }; |
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| 356 | |
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[cd089b9] | 357 | static int __init qman_portal_driver_register(struct platform_driver *drv) |
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| 358 | { |
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| 359 | int ret; |
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| 360 | |
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| 361 | ret = platform_driver_register(drv); |
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| 362 | if (ret < 0) |
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| 363 | return ret; |
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| 364 | |
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| 365 | ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, |
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| 366 | "soc/qman_portal:online", |
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| 367 | qman_online_cpu, qman_offline_cpu); |
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| 368 | if (ret < 0) { |
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| 369 | pr_err("qman: failed to register hotplug callbacks.\n"); |
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| 370 | platform_driver_unregister(drv); |
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| 371 | return ret; |
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| 372 | } |
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| 373 | return 0; |
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| 374 | } |
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| 375 | |
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| 376 | module_driver(qman_portal_driver, |
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| 377 | qman_portal_driver_register, platform_driver_unregister); |
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| 378 | #else /* __rtems__ */ |
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[28ee86a] | 379 | #include <bsp/fdt.h> |
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[cd089b9] | 380 | #include <linux/of_address.h> |
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| 381 | #include <linux/of_irq.h> |
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| 382 | |
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[e818128] | 383 | #define MAX_QMAN_PORTALS 50 |
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| 384 | |
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| 385 | static struct qm_portal_config qman_configs[MAX_QMAN_PORTALS]; |
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| 386 | |
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[de5791b] | 387 | static LIST_HEAD(qman_free_portals); |
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| 388 | |
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| 389 | struct qman_portal * |
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| 390 | qman_get_dedicated_portal(int cpu) |
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| 391 | { |
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| 392 | struct qm_portal_config *pcfg; |
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| 393 | struct qman_portal *p; |
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| 394 | u32 irq_sources; |
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| 395 | |
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| 396 | if (list_empty(&qman_free_portals)) |
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| 397 | return (NULL); |
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| 398 | |
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| 399 | pcfg = list_first_entry(&qman_free_portals, struct qm_portal_config, |
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| 400 | node); |
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| 401 | pcfg->cpu = cpu; |
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| 402 | p = qman_create_dedicated_portal(pcfg, NULL); |
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| 403 | if (p == NULL) |
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| 404 | return (NULL); |
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| 405 | |
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| 406 | list_del(&pcfg->node); |
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| 407 | |
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| 408 | irq_sources = QM_PIRQ_EQCI | QM_PIRQ_EQRI | QM_PIRQ_MRI | QM_PIRQ_CSCI |
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| 409 | | QM_PIRQ_DQRI; |
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| 410 | qman_p_irqsource_add(p, irq_sources); |
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| 411 | return (p); |
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| 412 | } |
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| 413 | |
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[e818128] | 414 | static bool |
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| 415 | is_dequeue_enabled(const struct device_node *dn) |
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| 416 | { |
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| 417 | const char *dequeue; |
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| 418 | int len; |
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| 419 | |
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| 420 | dequeue = of_get_property(dn, "libbsd,dequeue", &len); |
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| 421 | return (len <= 0 || strcmp(dequeue, "disabled") != 0); |
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| 422 | } |
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[cd089b9] | 423 | |
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[33356a8] | 424 | static void |
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| 425 | do_init_pcfg(struct device_node *dn, struct qm_portal_config *pcfg, |
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| 426 | int cpu_count) |
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| 427 | { |
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| 428 | struct qman_portal *portal; |
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| 429 | struct resource res; |
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| 430 | int ret; |
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| 431 | u32 val; |
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| 432 | |
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| 433 | ret = of_address_to_resource(dn, 0, &res); |
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| 434 | if (ret != 0) |
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| 435 | panic("qman: no portal CE address"); |
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[45149ec] | 436 | #if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) |
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[33356a8] | 437 | pcfg->addr_virt[0] = (__iomem void *) |
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| 438 | ((uintptr_t)&qoriq_qman_portal[0][0] + (uintptr_t)res.start); |
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| 439 | BSD_ASSERT((uintptr_t)pcfg->addr_virt[0] >= |
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| 440 | (uintptr_t)&qoriq_qman_portal[0][0]); |
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| 441 | BSD_ASSERT((uintptr_t)pcfg->addr_virt[0] < |
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| 442 | (uintptr_t)&qoriq_qman_portal[1][0]); |
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[45149ec] | 443 | #endif |
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[33356a8] | 444 | |
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| 445 | ret = of_address_to_resource(dn, 1, &res); |
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| 446 | if (ret != 0) |
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| 447 | panic("qman: no portal CI address"); |
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[45149ec] | 448 | #if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) |
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[33356a8] | 449 | pcfg->addr_virt[1] = (__iomem void *) |
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| 450 | ((uintptr_t)&qoriq_qman_portal[0][0] + (uintptr_t)res.start); |
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| 451 | BSD_ASSERT((uintptr_t)pcfg->addr_virt[1] >= |
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| 452 | (uintptr_t)&qoriq_qman_portal[1][0]); |
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| 453 | BSD_ASSERT((uintptr_t)pcfg->addr_virt[1] < |
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| 454 | (uintptr_t)&qoriq_qman_portal[2][0]); |
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[45149ec] | 455 | #endif |
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[33356a8] | 456 | |
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| 457 | ret = of_property_read_u32(dn, "cell-index", &val); |
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| 458 | if (ret != 0) |
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| 459 | panic("qman: no cell-index"); |
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| 460 | pcfg->channel = val; |
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| 461 | |
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| 462 | pcfg->irq = of_irq_to_resource(dn, 0, NULL); |
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| 463 | if (pcfg->irq == NO_IRQ) |
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| 464 | panic("qman: no portal interrupt"); |
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| 465 | |
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| 466 | if (val < cpu_count) { |
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| 467 | pcfg->cpu = val; |
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| 468 | |
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| 469 | if (is_dequeue_enabled(dn)) { |
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| 470 | pcfg->pools = qm_get_pools_sdqcr(); |
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| 471 | } |
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| 472 | |
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| 473 | portal = init_pcfg(pcfg); |
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| 474 | if (portal == NULL) |
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| 475 | panic("qman: cannot create portal"); |
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| 476 | |
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| 477 | qman_portal_update_sdest(pcfg, val); |
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| 478 | } else { |
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| 479 | pcfg->cpu = -1; |
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| 480 | list_add_tail(&pcfg->node, &qman_free_portals); |
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| 481 | } |
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| 482 | } |
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| 483 | |
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[cd089b9] | 484 | void |
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| 485 | qman_sysinit_portals(void) |
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[28ee86a] | 486 | { |
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| 487 | const char *fdt = bsp_fdt_get(); |
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| 488 | struct device_node dn; |
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| 489 | const char *name; |
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| 490 | int cpu_count = (int)rtems_get_processor_count(); |
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[e818128] | 491 | int i; |
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[28ee86a] | 492 | int node; |
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| 493 | int parent; |
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| 494 | |
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| 495 | memset(&dn, 0, sizeof(dn)); |
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| 496 | |
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| 497 | name = "fsl,qman-portal"; |
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| 498 | node = fdt_node_offset_by_compatible(fdt, 0, name); |
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| 499 | if (node < 0) |
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| 500 | panic("qman: no portals in FDT"); |
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| 501 | parent = fdt_parent_offset(fdt, node); |
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| 502 | if (parent < 0) |
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| 503 | panic("qman: no parent of portals in FDT"); |
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| 504 | node = fdt_first_subnode(fdt, parent); |
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| 505 | |
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| 506 | dn.full_name = name; |
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| 507 | dn.offset = node; |
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| 508 | |
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[45149ec] | 509 | #if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) |
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[28ee86a] | 510 | qoriq_clear_ce_portal(&qoriq_qman_portal[0][0], |
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| 511 | sizeof(qoriq_qman_portal[0])); |
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| 512 | qoriq_clear_ci_portal(&qoriq_qman_portal[1][0], |
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| 513 | sizeof(qoriq_qman_portal[1])); |
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[45149ec] | 514 | #endif |
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[28ee86a] | 515 | |
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[33356a8] | 516 | i = 0; |
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| 517 | while (node >= 0 && i < MAX_QMAN_PORTALS) { |
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| 518 | if (fdt_node_check_compatible(fdt, node, name) == 0) { |
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| 519 | do_init_pcfg(&dn, &qman_configs[i], cpu_count); |
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| 520 | ++i; |
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[e818128] | 521 | } |
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[cd089b9] | 522 | |
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[28ee86a] | 523 | node = fdt_next_subnode(fdt, node); |
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| 524 | dn.offset = node; |
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| 525 | } |
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| 526 | |
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[e818128] | 527 | if (i < cpu_count) |
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| 528 | panic("qman: not enough portals in FDT"); |
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| 529 | |
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[cd089b9] | 530 | /* all assigned portals are initialized now */ |
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| 531 | qman_init_cgr_all(); |
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[28ee86a] | 532 | } |
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| 533 | #endif /* __rtems__ */ |
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