[cd089b9] | 1 | #include <machine/rtems-bsd-kernel-space.h> |
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| 2 | |
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| 3 | #include <rtems/bsd/local/opt_dpaa.h> |
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| 4 | |
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| 5 | /* Copyright 2008 - 2016 Freescale Semiconductor, Inc. |
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| 6 | * |
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| 7 | * Redistribution and use in source and binary forms, with or without |
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| 8 | * modification, are permitted provided that the following conditions are met: |
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| 9 | * * Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * * Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * * Neither the name of Freescale Semiconductor nor the |
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| 15 | * names of its contributors may be used to endorse or promote products |
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| 16 | * derived from this software without specific prior written permission. |
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| 17 | * |
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| 18 | * ALTERNATIVELY, this software may be distributed under the terms of the |
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| 19 | * GNU General Public License ("GPL") as published by the Free Software |
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| 20 | * Foundation, either version 2 of that License or (at your option) any |
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| 21 | * later version. |
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| 22 | * |
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| 23 | * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
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| 24 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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| 25 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 26 | * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
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| 27 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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| 28 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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| 29 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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| 30 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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| 32 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 33 | */ |
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| 34 | |
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| 35 | #include "qman_priv.h" |
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| 36 | #ifdef __rtems__ |
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| 37 | #undef dev_crit |
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| 38 | #undef dev_dbg |
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| 39 | #undef dev_err |
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| 40 | #define dev_crit(dev, fmt, ...) printf(fmt, ##__VA_ARGS__) |
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| 41 | #define dev_dbg dev_crit |
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| 42 | #define dev_err dev_crit |
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| 43 | #endif /* __rtems__ */ |
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| 44 | |
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| 45 | u16 qman_ip_rev; |
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| 46 | EXPORT_SYMBOL(qman_ip_rev); |
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| 47 | u16 qm_channel_pool1 = QMAN_CHANNEL_POOL1; |
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| 48 | EXPORT_SYMBOL(qm_channel_pool1); |
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[cf40770] | 49 | u16 qm_channel_caam = QMAN_CHANNEL_CAAM; |
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| 50 | EXPORT_SYMBOL(qm_channel_caam); |
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[cd089b9] | 51 | |
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| 52 | /* Register offsets */ |
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| 53 | #define REG_QCSP_LIO_CFG(n) (0x0000 + ((n) * 0x10)) |
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| 54 | #define REG_QCSP_IO_CFG(n) (0x0004 + ((n) * 0x10)) |
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| 55 | #define REG_QCSP_DD_CFG(n) (0x000c + ((n) * 0x10)) |
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| 56 | #define REG_DD_CFG 0x0200 |
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| 57 | #define REG_DCP_CFG(n) (0x0300 + ((n) * 0x10)) |
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| 58 | #define REG_DCP_DD_CFG(n) (0x0304 + ((n) * 0x10)) |
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| 59 | #define REG_DCP_DLM_AVG(n) (0x030c + ((n) * 0x10)) |
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| 60 | #define REG_PFDR_FPC 0x0400 |
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| 61 | #define REG_PFDR_FP_HEAD 0x0404 |
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| 62 | #define REG_PFDR_FP_TAIL 0x0408 |
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| 63 | #define REG_PFDR_FP_LWIT 0x0410 |
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| 64 | #define REG_PFDR_CFG 0x0414 |
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| 65 | #define REG_SFDR_CFG 0x0500 |
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| 66 | #define REG_SFDR_IN_USE 0x0504 |
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| 67 | #define REG_WQ_CS_CFG(n) (0x0600 + ((n) * 0x04)) |
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| 68 | #define REG_WQ_DEF_ENC_WQID 0x0630 |
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| 69 | #define REG_WQ_SC_DD_CFG(n) (0x640 + ((n) * 0x04)) |
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| 70 | #define REG_WQ_PC_DD_CFG(n) (0x680 + ((n) * 0x04)) |
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| 71 | #define REG_WQ_DC0_DD_CFG(n) (0x6c0 + ((n) * 0x04)) |
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| 72 | #define REG_WQ_DC1_DD_CFG(n) (0x700 + ((n) * 0x04)) |
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| 73 | #define REG_WQ_DCn_DD_CFG(n) (0x6c0 + ((n) * 0x40)) /* n=2,3 */ |
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| 74 | #define REG_CM_CFG 0x0800 |
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| 75 | #define REG_ECSR 0x0a00 |
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| 76 | #define REG_ECIR 0x0a04 |
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| 77 | #define REG_EADR 0x0a08 |
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| 78 | #define REG_ECIR2 0x0a0c |
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| 79 | #define REG_EDATA(n) (0x0a10 + ((n) * 0x04)) |
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| 80 | #define REG_SBEC(n) (0x0a80 + ((n) * 0x04)) |
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| 81 | #define REG_MCR 0x0b00 |
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| 82 | #define REG_MCP(n) (0x0b04 + ((n) * 0x04)) |
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| 83 | #define REG_MISC_CFG 0x0be0 |
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| 84 | #define REG_HID_CFG 0x0bf0 |
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| 85 | #define REG_IDLE_STAT 0x0bf4 |
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| 86 | #define REG_IP_REV_1 0x0bf8 |
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| 87 | #define REG_IP_REV_2 0x0bfc |
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| 88 | #define REG_FQD_BARE 0x0c00 |
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| 89 | #define REG_PFDR_BARE 0x0c20 |
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| 90 | #define REG_offset_BAR 0x0004 /* relative to REG_[FQD|PFDR]_BARE */ |
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| 91 | #define REG_offset_AR 0x0010 /* relative to REG_[FQD|PFDR]_BARE */ |
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| 92 | #define REG_QCSP_BARE 0x0c80 |
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| 93 | #define REG_QCSP_BAR 0x0c84 |
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| 94 | #define REG_CI_SCHED_CFG 0x0d00 |
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| 95 | #define REG_SRCIDR 0x0d04 |
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| 96 | #define REG_LIODNR 0x0d08 |
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| 97 | #define REG_CI_RLM_AVG 0x0d14 |
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| 98 | #define REG_ERR_ISR 0x0e00 |
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| 99 | #define REG_ERR_IER 0x0e04 |
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| 100 | #define REG_REV3_QCSP_LIO_CFG(n) (0x1000 + ((n) * 0x10)) |
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| 101 | #define REG_REV3_QCSP_IO_CFG(n) (0x1004 + ((n) * 0x10)) |
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| 102 | #define REG_REV3_QCSP_DD_CFG(n) (0x100c + ((n) * 0x10)) |
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| 103 | |
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| 104 | /* Assists for QMAN_MCR */ |
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| 105 | #define MCR_INIT_PFDR 0x01000000 |
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| 106 | #define MCR_get_rslt(v) (u8)((v) >> 24) |
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| 107 | #define MCR_rslt_idle(r) (!(r) || ((r) >= 0xf0)) |
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| 108 | #define MCR_rslt_ok(r) ((r) == 0xf0) |
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| 109 | #define MCR_rslt_eaccess(r) ((r) == 0xf8) |
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| 110 | #define MCR_rslt_inval(r) ((r) == 0xff) |
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| 111 | |
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| 112 | /* |
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| 113 | * Corenet initiator settings. Stash request queues are 4-deep to match cores |
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| 114 | * ability to snarf. Stash priority is 3, other priorities are 2. |
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| 115 | */ |
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| 116 | #define QM_CI_SCHED_CFG_SRCCIV 4 |
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| 117 | #define QM_CI_SCHED_CFG_SRQ_W 3 |
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| 118 | #define QM_CI_SCHED_CFG_RW_W 2 |
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| 119 | #define QM_CI_SCHED_CFG_BMAN_W 2 |
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| 120 | /* write SRCCIV enable */ |
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| 121 | #define QM_CI_SCHED_CFG_SRCCIV_EN BIT(31) |
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| 122 | |
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| 123 | /* Follows WQ_CS_CFG0-5 */ |
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| 124 | enum qm_wq_class { |
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| 125 | qm_wq_portal = 0, |
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| 126 | qm_wq_pool = 1, |
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| 127 | qm_wq_fman0 = 2, |
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| 128 | qm_wq_fman1 = 3, |
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| 129 | qm_wq_caam = 4, |
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| 130 | qm_wq_pme = 5, |
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| 131 | qm_wq_first = qm_wq_portal, |
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| 132 | qm_wq_last = qm_wq_pme |
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| 133 | }; |
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| 134 | |
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| 135 | /* Follows FQD_[BARE|BAR|AR] and PFDR_[BARE|BAR|AR] */ |
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| 136 | enum qm_memory { |
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| 137 | qm_memory_fqd, |
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| 138 | qm_memory_pfdr |
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| 139 | }; |
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| 140 | |
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| 141 | /* Used by all error interrupt registers except 'inhibit' */ |
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| 142 | #define QM_EIRQ_CIDE 0x20000000 /* Corenet Initiator Data Error */ |
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| 143 | #define QM_EIRQ_CTDE 0x10000000 /* Corenet Target Data Error */ |
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| 144 | #define QM_EIRQ_CITT 0x08000000 /* Corenet Invalid Target Transaction */ |
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| 145 | #define QM_EIRQ_PLWI 0x04000000 /* PFDR Low Watermark */ |
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| 146 | #define QM_EIRQ_MBEI 0x02000000 /* Multi-bit ECC Error */ |
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| 147 | #define QM_EIRQ_SBEI 0x01000000 /* Single-bit ECC Error */ |
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| 148 | #define QM_EIRQ_PEBI 0x00800000 /* PFDR Enqueues Blocked Interrupt */ |
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| 149 | #define QM_EIRQ_IFSI 0x00020000 /* Invalid FQ Flow Control State */ |
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| 150 | #define QM_EIRQ_ICVI 0x00010000 /* Invalid Command Verb */ |
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| 151 | #define QM_EIRQ_IDDI 0x00000800 /* Invalid Dequeue (Direct-connect) */ |
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| 152 | #define QM_EIRQ_IDFI 0x00000400 /* Invalid Dequeue FQ */ |
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| 153 | #define QM_EIRQ_IDSI 0x00000200 /* Invalid Dequeue Source */ |
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| 154 | #define QM_EIRQ_IDQI 0x00000100 /* Invalid Dequeue Queue */ |
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| 155 | #define QM_EIRQ_IECE 0x00000010 /* Invalid Enqueue Configuration */ |
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| 156 | #define QM_EIRQ_IEOI 0x00000008 /* Invalid Enqueue Overflow */ |
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| 157 | #define QM_EIRQ_IESI 0x00000004 /* Invalid Enqueue State */ |
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| 158 | #define QM_EIRQ_IECI 0x00000002 /* Invalid Enqueue Channel */ |
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| 159 | #define QM_EIRQ_IEQI 0x00000001 /* Invalid Enqueue Queue */ |
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| 160 | |
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| 161 | /* QMAN_ECIR valid error bit */ |
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| 162 | #define PORTAL_ECSR_ERR (QM_EIRQ_IEQI | QM_EIRQ_IESI | QM_EIRQ_IEOI | \ |
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| 163 | QM_EIRQ_IDQI | QM_EIRQ_IDSI | QM_EIRQ_IDFI | \ |
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| 164 | QM_EIRQ_IDDI | QM_EIRQ_ICVI | QM_EIRQ_IFSI) |
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| 165 | #define FQID_ECSR_ERR (QM_EIRQ_IEQI | QM_EIRQ_IECI | QM_EIRQ_IESI | \ |
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| 166 | QM_EIRQ_IEOI | QM_EIRQ_IDQI | QM_EIRQ_IDFI | \ |
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| 167 | QM_EIRQ_IFSI) |
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| 168 | |
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| 169 | struct qm_ecir { |
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| 170 | u32 info; /* res[30-31], ptyp[29], pnum[24-28], fqid[0-23] */ |
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| 171 | }; |
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| 172 | |
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| 173 | static bool qm_ecir_is_dcp(const struct qm_ecir *p) |
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| 174 | { |
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| 175 | return p->info & BIT(29); |
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| 176 | } |
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| 177 | |
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| 178 | static int qm_ecir_get_pnum(const struct qm_ecir *p) |
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| 179 | { |
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| 180 | return (p->info >> 24) & 0x1f; |
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| 181 | } |
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| 182 | |
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| 183 | static int qm_ecir_get_fqid(const struct qm_ecir *p) |
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| 184 | { |
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| 185 | return p->info & (BIT(24) - 1); |
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| 186 | } |
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| 187 | |
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| 188 | struct qm_ecir2 { |
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| 189 | u32 info; /* ptyp[31], res[10-30], pnum[0-9] */ |
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| 190 | }; |
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| 191 | |
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| 192 | static bool qm_ecir2_is_dcp(const struct qm_ecir2 *p) |
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| 193 | { |
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| 194 | return p->info & BIT(31); |
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| 195 | } |
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| 196 | |
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| 197 | static int qm_ecir2_get_pnum(const struct qm_ecir2 *p) |
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| 198 | { |
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| 199 | return p->info & (BIT(10) - 1); |
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| 200 | } |
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| 201 | |
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| 202 | struct qm_eadr { |
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| 203 | u32 info; /* memid[24-27], eadr[0-11] */ |
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| 204 | /* v3: memid[24-28], eadr[0-15] */ |
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| 205 | }; |
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| 206 | |
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| 207 | static int qm_eadr_get_memid(const struct qm_eadr *p) |
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| 208 | { |
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| 209 | return (p->info >> 24) & 0xf; |
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| 210 | } |
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| 211 | |
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| 212 | static int qm_eadr_get_eadr(const struct qm_eadr *p) |
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| 213 | { |
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| 214 | return p->info & (BIT(12) - 1); |
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| 215 | } |
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| 216 | |
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| 217 | static int qm_eadr_v3_get_memid(const struct qm_eadr *p) |
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| 218 | { |
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| 219 | return (p->info >> 24) & 0x1f; |
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| 220 | } |
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| 221 | |
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| 222 | static int qm_eadr_v3_get_eadr(const struct qm_eadr *p) |
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| 223 | { |
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| 224 | return p->info & (BIT(16) - 1); |
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| 225 | } |
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| 226 | |
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| 227 | struct qman_hwerr_txt { |
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| 228 | u32 mask; |
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| 229 | const char *txt; |
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| 230 | }; |
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| 231 | |
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| 232 | |
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| 233 | static const struct qman_hwerr_txt qman_hwerr_txts[] = { |
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| 234 | { QM_EIRQ_CIDE, "Corenet Initiator Data Error" }, |
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| 235 | { QM_EIRQ_CTDE, "Corenet Target Data Error" }, |
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| 236 | { QM_EIRQ_CITT, "Corenet Invalid Target Transaction" }, |
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| 237 | { QM_EIRQ_PLWI, "PFDR Low Watermark" }, |
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| 238 | { QM_EIRQ_MBEI, "Multi-bit ECC Error" }, |
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| 239 | { QM_EIRQ_SBEI, "Single-bit ECC Error" }, |
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| 240 | { QM_EIRQ_PEBI, "PFDR Enqueues Blocked Interrupt" }, |
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| 241 | { QM_EIRQ_ICVI, "Invalid Command Verb" }, |
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| 242 | { QM_EIRQ_IFSI, "Invalid Flow Control State" }, |
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| 243 | { QM_EIRQ_IDDI, "Invalid Dequeue (Direct-connect)" }, |
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| 244 | { QM_EIRQ_IDFI, "Invalid Dequeue FQ" }, |
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| 245 | { QM_EIRQ_IDSI, "Invalid Dequeue Source" }, |
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| 246 | { QM_EIRQ_IDQI, "Invalid Dequeue Queue" }, |
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| 247 | { QM_EIRQ_IECE, "Invalid Enqueue Configuration" }, |
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| 248 | { QM_EIRQ_IEOI, "Invalid Enqueue Overflow" }, |
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| 249 | { QM_EIRQ_IESI, "Invalid Enqueue State" }, |
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| 250 | { QM_EIRQ_IECI, "Invalid Enqueue Channel" }, |
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| 251 | { QM_EIRQ_IEQI, "Invalid Enqueue Queue" }, |
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| 252 | }; |
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| 253 | |
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| 254 | struct qman_error_info_mdata { |
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| 255 | u16 addr_mask; |
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| 256 | u16 bits; |
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| 257 | const char *txt; |
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| 258 | }; |
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| 259 | |
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| 260 | static const struct qman_error_info_mdata error_mdata[] = { |
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| 261 | { 0x01FF, 24, "FQD cache tag memory 0" }, |
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| 262 | { 0x01FF, 24, "FQD cache tag memory 1" }, |
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| 263 | { 0x01FF, 24, "FQD cache tag memory 2" }, |
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| 264 | { 0x01FF, 24, "FQD cache tag memory 3" }, |
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| 265 | { 0x0FFF, 512, "FQD cache memory" }, |
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| 266 | { 0x07FF, 128, "SFDR memory" }, |
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| 267 | { 0x01FF, 72, "WQ context memory" }, |
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| 268 | { 0x00FF, 240, "CGR memory" }, |
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| 269 | { 0x00FF, 302, "Internal Order Restoration List memory" }, |
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| 270 | { 0x01FF, 256, "SW portal ring memory" }, |
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| 271 | }; |
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| 272 | |
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| 273 | #define QMAN_ERRS_TO_DISABLE (QM_EIRQ_PLWI | QM_EIRQ_PEBI) |
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| 274 | |
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| 275 | /* |
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| 276 | * TODO: unimplemented registers |
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| 277 | * |
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| 278 | * Keeping a list here of QMan registers I have not yet covered; |
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| 279 | * QCSP_DD_IHRSR, QCSP_DD_IHRFR, QCSP_DD_HASR, |
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| 280 | * DCP_DD_IHRSR, DCP_DD_IHRFR, DCP_DD_HASR, CM_CFG, |
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| 281 | * QMAN_EECC, QMAN_SBET, QMAN_EINJ, QMAN_SBEC0-12 |
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| 282 | */ |
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| 283 | |
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| 284 | /* Pointer to the start of the QMan's CCSR space */ |
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| 285 | static u32 __iomem *qm_ccsr_start; |
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| 286 | /* A SDQCR mask comprising all the available/visible pool channels */ |
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| 287 | static u32 qm_pools_sdqcr; |
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| 288 | |
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| 289 | static inline u32 qm_ccsr_in(u32 offset) |
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| 290 | { |
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| 291 | return ioread32be(qm_ccsr_start + offset/4); |
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| 292 | } |
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| 293 | |
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| 294 | static inline void qm_ccsr_out(u32 offset, u32 val) |
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| 295 | { |
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| 296 | iowrite32be(val, qm_ccsr_start + offset/4); |
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| 297 | } |
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| 298 | |
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| 299 | u32 qm_get_pools_sdqcr(void) |
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| 300 | { |
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| 301 | return qm_pools_sdqcr; |
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| 302 | } |
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| 303 | |
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| 304 | enum qm_dc_portal { |
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| 305 | qm_dc_portal_fman0 = 0, |
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| 306 | qm_dc_portal_fman1 = 1 |
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| 307 | }; |
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| 308 | |
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| 309 | static void qm_set_dc(enum qm_dc_portal portal, int ed, u8 sernd) |
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| 310 | { |
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| 311 | DPAA_ASSERT(!ed || portal == qm_dc_portal_fman0 || |
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| 312 | portal == qm_dc_portal_fman1); |
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| 313 | if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) |
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| 314 | qm_ccsr_out(REG_DCP_CFG(portal), |
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| 315 | (ed ? 0x1000 : 0) | (sernd & 0x3ff)); |
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| 316 | else |
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| 317 | qm_ccsr_out(REG_DCP_CFG(portal), |
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| 318 | (ed ? 0x100 : 0) | (sernd & 0x1f)); |
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| 319 | } |
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| 320 | |
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| 321 | static void qm_set_wq_scheduling(enum qm_wq_class wq_class, |
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| 322 | u8 cs_elev, u8 csw2, u8 csw3, u8 csw4, |
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| 323 | u8 csw5, u8 csw6, u8 csw7) |
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| 324 | { |
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| 325 | qm_ccsr_out(REG_WQ_CS_CFG(wq_class), ((cs_elev & 0xff) << 24) | |
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| 326 | ((csw2 & 0x7) << 20) | ((csw3 & 0x7) << 16) | |
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| 327 | ((csw4 & 0x7) << 12) | ((csw5 & 0x7) << 8) | |
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| 328 | ((csw6 & 0x7) << 4) | (csw7 & 0x7)); |
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| 329 | } |
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| 330 | |
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| 331 | static void qm_set_hid(void) |
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| 332 | { |
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| 333 | qm_ccsr_out(REG_HID_CFG, 0); |
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| 334 | } |
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| 335 | |
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| 336 | static void qm_set_corenet_initiator(void) |
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| 337 | { |
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| 338 | qm_ccsr_out(REG_CI_SCHED_CFG, QM_CI_SCHED_CFG_SRCCIV_EN | |
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| 339 | (QM_CI_SCHED_CFG_SRCCIV << 24) | |
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| 340 | (QM_CI_SCHED_CFG_SRQ_W << 8) | |
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| 341 | (QM_CI_SCHED_CFG_RW_W << 4) | |
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| 342 | QM_CI_SCHED_CFG_BMAN_W); |
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| 343 | } |
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| 344 | |
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| 345 | static void qm_get_version(u16 *id, u8 *major, u8 *minor) |
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| 346 | { |
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| 347 | u32 v = qm_ccsr_in(REG_IP_REV_1); |
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| 348 | *id = (v >> 16); |
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| 349 | *major = (v >> 8) & 0xff; |
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| 350 | *minor = v & 0xff; |
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| 351 | } |
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| 352 | |
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| 353 | #define PFDR_AR_EN BIT(31) |
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| 354 | static void qm_set_memory(enum qm_memory memory, u64 ba, u32 size) |
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| 355 | { |
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| 356 | u32 offset = (memory == qm_memory_fqd) ? REG_FQD_BARE : REG_PFDR_BARE; |
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| 357 | u32 exp = ilog2(size); |
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| 358 | |
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| 359 | /* choke if size isn't within range */ |
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| 360 | DPAA_ASSERT((size >= 4096) && (size <= 1024*1024*1024) && |
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| 361 | is_power_of_2(size)); |
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| 362 | /* choke if 'ba' has lower-alignment than 'size' */ |
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| 363 | DPAA_ASSERT(!(ba & (size - 1))); |
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| 364 | qm_ccsr_out(offset, upper_32_bits(ba)); |
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| 365 | qm_ccsr_out(offset + REG_offset_BAR, lower_32_bits(ba)); |
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| 366 | qm_ccsr_out(offset + REG_offset_AR, PFDR_AR_EN | (exp - 1)); |
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| 367 | } |
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| 368 | |
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| 369 | static void qm_set_pfdr_threshold(u32 th, u8 k) |
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| 370 | { |
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| 371 | qm_ccsr_out(REG_PFDR_FP_LWIT, th & 0xffffff); |
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| 372 | qm_ccsr_out(REG_PFDR_CFG, k); |
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| 373 | } |
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| 374 | |
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| 375 | static void qm_set_sfdr_threshold(u16 th) |
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| 376 | { |
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| 377 | qm_ccsr_out(REG_SFDR_CFG, th & 0x3ff); |
---|
| 378 | } |
---|
| 379 | |
---|
| 380 | static int qm_init_pfdr(struct device *dev, u32 pfdr_start, u32 num) |
---|
| 381 | { |
---|
| 382 | u8 rslt = MCR_get_rslt(qm_ccsr_in(REG_MCR)); |
---|
| 383 | |
---|
| 384 | DPAA_ASSERT(pfdr_start && !(pfdr_start & 7) && !(num & 7) && num); |
---|
| 385 | /* Make sure the command interface is 'idle' */ |
---|
| 386 | if (!MCR_rslt_idle(rslt)) { |
---|
| 387 | dev_crit(dev, "QMAN_MCR isn't idle"); |
---|
| 388 | WARN_ON(1); |
---|
| 389 | } |
---|
| 390 | |
---|
| 391 | /* Write the MCR command params then the verb */ |
---|
| 392 | qm_ccsr_out(REG_MCP(0), pfdr_start); |
---|
| 393 | /* |
---|
| 394 | * TODO: remove this - it's a workaround for a model bug that is |
---|
| 395 | * corrected in more recent versions. We use the workaround until |
---|
| 396 | * everyone has upgraded. |
---|
| 397 | */ |
---|
| 398 | qm_ccsr_out(REG_MCP(1), pfdr_start + num - 16); |
---|
| 399 | dma_wmb(); |
---|
| 400 | qm_ccsr_out(REG_MCR, MCR_INIT_PFDR); |
---|
| 401 | /* Poll for the result */ |
---|
| 402 | do { |
---|
| 403 | rslt = MCR_get_rslt(qm_ccsr_in(REG_MCR)); |
---|
| 404 | } while (!MCR_rslt_idle(rslt)); |
---|
| 405 | if (MCR_rslt_ok(rslt)) |
---|
| 406 | return 0; |
---|
| 407 | if (MCR_rslt_eaccess(rslt)) |
---|
| 408 | return -EACCES; |
---|
| 409 | if (MCR_rslt_inval(rslt)) |
---|
| 410 | return -EINVAL; |
---|
| 411 | dev_crit(dev, "Unexpected result from MCR_INIT_PFDR: %02x\n", rslt); |
---|
| 412 | return -ENODEV; |
---|
| 413 | } |
---|
| 414 | |
---|
| 415 | /* |
---|
| 416 | * Ideally we would use the DMA API to turn rmem->base into a DMA address |
---|
| 417 | * (especially if iommu translations ever get involved). Unfortunately, the |
---|
| 418 | * DMA API currently does not allow mapping anything that is not backed with |
---|
| 419 | * a struct page. |
---|
| 420 | */ |
---|
| 421 | #ifndef __rtems__ |
---|
| 422 | static dma_addr_t fqd_a, pfdr_a; |
---|
| 423 | static size_t fqd_sz, pfdr_sz; |
---|
| 424 | |
---|
| 425 | static int qman_fqd(struct reserved_mem *rmem) |
---|
| 426 | { |
---|
| 427 | fqd_a = rmem->base; |
---|
| 428 | fqd_sz = rmem->size; |
---|
| 429 | |
---|
| 430 | WARN_ON(!(fqd_a && fqd_sz)); |
---|
| 431 | |
---|
| 432 | return 0; |
---|
| 433 | } |
---|
| 434 | RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd); |
---|
| 435 | |
---|
| 436 | static int qman_pfdr(struct reserved_mem *rmem) |
---|
| 437 | { |
---|
| 438 | pfdr_a = rmem->base; |
---|
| 439 | pfdr_sz = rmem->size; |
---|
| 440 | |
---|
| 441 | WARN_ON(!(pfdr_a && pfdr_sz)); |
---|
| 442 | |
---|
| 443 | return 0; |
---|
| 444 | } |
---|
| 445 | RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr); |
---|
| 446 | #else /* __rtems__ */ |
---|
| 447 | static DPAA_NOCACHENOLOAD_ALIGNED_REGION(fqd, 4194304); |
---|
| 448 | #define fqd_a ((uintptr_t)&fqd[0]) |
---|
| 449 | #define fqd_sz sizeof(fqd) |
---|
[24866e6] | 450 | static DPAA_NOCACHENOLOAD_ALIGNED_REGION(pfdr, 16777216); |
---|
[cd089b9] | 451 | #define pfdr_a ((uintptr_t)&pfdr[0]) |
---|
| 452 | #define pfdr_sz sizeof(pfdr) |
---|
| 453 | #endif /* __rtems__ */ |
---|
| 454 | |
---|
| 455 | static unsigned int qm_get_fqid_maxcnt(void) |
---|
| 456 | { |
---|
| 457 | return fqd_sz / 64; |
---|
| 458 | } |
---|
| 459 | |
---|
| 460 | /* |
---|
| 461 | * Flush this memory range from data cache so that QMAN originated |
---|
| 462 | * transactions for this memory region could be marked non-coherent. |
---|
| 463 | */ |
---|
| 464 | static int zero_priv_mem(struct device *dev, struct device_node *node, |
---|
| 465 | phys_addr_t addr, size_t sz) |
---|
| 466 | { |
---|
| 467 | #ifndef __rtems__ |
---|
| 468 | /* map as cacheable, non-guarded */ |
---|
| 469 | void __iomem *tmpp = ioremap_prot(addr, sz, 0); |
---|
| 470 | |
---|
| 471 | if (!tmpp) |
---|
| 472 | return -ENOMEM; |
---|
| 473 | |
---|
| 474 | memset_io(tmpp, 0, sz); |
---|
| 475 | flush_dcache_range((unsigned long)tmpp, |
---|
| 476 | (unsigned long)tmpp + sz); |
---|
| 477 | iounmap(tmpp); |
---|
| 478 | |
---|
| 479 | #else /* __rtems__ */ |
---|
| 480 | memset((void *)(uintptr_t)addr, 0, sz); |
---|
| 481 | #endif /* __rtems__ */ |
---|
| 482 | return 0; |
---|
| 483 | } |
---|
| 484 | |
---|
| 485 | static void log_edata_bits(struct device *dev, u32 bit_count) |
---|
| 486 | { |
---|
| 487 | u32 i, j, mask = 0xffffffff; |
---|
| 488 | |
---|
| 489 | dev_warn(dev, "ErrInt, EDATA:\n"); |
---|
| 490 | i = bit_count / 32; |
---|
| 491 | if (bit_count % 32) { |
---|
| 492 | i++; |
---|
| 493 | mask = ~(mask << bit_count % 32); |
---|
| 494 | } |
---|
| 495 | j = 16 - i; |
---|
| 496 | dev_warn(dev, " 0x%08x\n", qm_ccsr_in(REG_EDATA(j)) & mask); |
---|
| 497 | j++; |
---|
| 498 | for (; j < 16; j++) |
---|
| 499 | dev_warn(dev, " 0x%08x\n", qm_ccsr_in(REG_EDATA(j))); |
---|
| 500 | } |
---|
| 501 | |
---|
| 502 | static void log_additional_error_info(struct device *dev, u32 isr_val, |
---|
| 503 | u32 ecsr_val) |
---|
| 504 | { |
---|
| 505 | struct qm_ecir ecir_val; |
---|
| 506 | struct qm_eadr eadr_val; |
---|
| 507 | int memid; |
---|
| 508 | |
---|
| 509 | ecir_val.info = qm_ccsr_in(REG_ECIR); |
---|
| 510 | /* Is portal info valid */ |
---|
| 511 | if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) { |
---|
| 512 | struct qm_ecir2 ecir2_val; |
---|
| 513 | |
---|
| 514 | ecir2_val.info = qm_ccsr_in(REG_ECIR2); |
---|
| 515 | if (ecsr_val & PORTAL_ECSR_ERR) { |
---|
| 516 | dev_warn(dev, "ErrInt: %s id %d\n", |
---|
| 517 | qm_ecir2_is_dcp(&ecir2_val) ? "DCP" : "SWP", |
---|
| 518 | qm_ecir2_get_pnum(&ecir2_val)); |
---|
| 519 | } |
---|
| 520 | if (ecsr_val & (FQID_ECSR_ERR | QM_EIRQ_IECE)) |
---|
| 521 | dev_warn(dev, "ErrInt: ecir.fqid 0x%x\n", |
---|
| 522 | qm_ecir_get_fqid(&ecir_val)); |
---|
| 523 | |
---|
| 524 | if (ecsr_val & (QM_EIRQ_SBEI|QM_EIRQ_MBEI)) { |
---|
| 525 | eadr_val.info = qm_ccsr_in(REG_EADR); |
---|
| 526 | memid = qm_eadr_v3_get_memid(&eadr_val); |
---|
| 527 | dev_warn(dev, "ErrInt: EADR Memory: %s, 0x%x\n", |
---|
| 528 | error_mdata[memid].txt, |
---|
| 529 | error_mdata[memid].addr_mask |
---|
| 530 | & qm_eadr_v3_get_eadr(&eadr_val)); |
---|
| 531 | log_edata_bits(dev, error_mdata[memid].bits); |
---|
| 532 | } |
---|
| 533 | } else { |
---|
| 534 | if (ecsr_val & PORTAL_ECSR_ERR) { |
---|
| 535 | dev_warn(dev, "ErrInt: %s id %d\n", |
---|
| 536 | qm_ecir_is_dcp(&ecir_val) ? "DCP" : "SWP", |
---|
| 537 | qm_ecir_get_pnum(&ecir_val)); |
---|
| 538 | } |
---|
| 539 | if (ecsr_val & FQID_ECSR_ERR) |
---|
| 540 | dev_warn(dev, "ErrInt: ecir.fqid 0x%x\n", |
---|
| 541 | qm_ecir_get_fqid(&ecir_val)); |
---|
| 542 | |
---|
| 543 | if (ecsr_val & (QM_EIRQ_SBEI|QM_EIRQ_MBEI)) { |
---|
| 544 | eadr_val.info = qm_ccsr_in(REG_EADR); |
---|
| 545 | memid = qm_eadr_get_memid(&eadr_val); |
---|
| 546 | dev_warn(dev, "ErrInt: EADR Memory: %s, 0x%x\n", |
---|
| 547 | error_mdata[memid].txt, |
---|
| 548 | error_mdata[memid].addr_mask |
---|
| 549 | & qm_eadr_get_eadr(&eadr_val)); |
---|
| 550 | log_edata_bits(dev, error_mdata[memid].bits); |
---|
| 551 | } |
---|
| 552 | } |
---|
| 553 | } |
---|
| 554 | |
---|
| 555 | static irqreturn_t qman_isr(int irq, void *ptr) |
---|
| 556 | { |
---|
| 557 | u32 isr_val, ier_val, ecsr_val, isr_mask, i; |
---|
| 558 | struct device *dev = ptr; |
---|
| 559 | |
---|
| 560 | ier_val = qm_ccsr_in(REG_ERR_IER); |
---|
| 561 | isr_val = qm_ccsr_in(REG_ERR_ISR); |
---|
| 562 | ecsr_val = qm_ccsr_in(REG_ECSR); |
---|
| 563 | isr_mask = isr_val & ier_val; |
---|
| 564 | |
---|
| 565 | if (!isr_mask) |
---|
| 566 | return IRQ_NONE; |
---|
| 567 | |
---|
| 568 | for (i = 0; i < ARRAY_SIZE(qman_hwerr_txts); i++) { |
---|
| 569 | if (qman_hwerr_txts[i].mask & isr_mask) { |
---|
| 570 | #ifndef __rtems__ |
---|
| 571 | dev_err_ratelimited(dev, "ErrInt: %s\n", |
---|
| 572 | qman_hwerr_txts[i].txt); |
---|
| 573 | #endif /* __rtems__ */ |
---|
| 574 | if (qman_hwerr_txts[i].mask & ecsr_val) { |
---|
| 575 | log_additional_error_info(dev, isr_mask, |
---|
| 576 | ecsr_val); |
---|
| 577 | /* Re-arm error capture registers */ |
---|
| 578 | qm_ccsr_out(REG_ECSR, ecsr_val); |
---|
| 579 | } |
---|
| 580 | if (qman_hwerr_txts[i].mask & QMAN_ERRS_TO_DISABLE) { |
---|
| 581 | dev_dbg(dev, "Disabling error 0x%x\n", |
---|
| 582 | qman_hwerr_txts[i].mask); |
---|
| 583 | ier_val &= ~qman_hwerr_txts[i].mask; |
---|
| 584 | qm_ccsr_out(REG_ERR_IER, ier_val); |
---|
| 585 | } |
---|
| 586 | } |
---|
| 587 | } |
---|
| 588 | qm_ccsr_out(REG_ERR_ISR, isr_val); |
---|
| 589 | |
---|
| 590 | return IRQ_HANDLED; |
---|
| 591 | } |
---|
| 592 | |
---|
| 593 | static int qman_init_ccsr(struct device *dev) |
---|
| 594 | { |
---|
| 595 | int i, err; |
---|
| 596 | |
---|
| 597 | /* FQD memory */ |
---|
| 598 | qm_set_memory(qm_memory_fqd, fqd_a, fqd_sz); |
---|
| 599 | /* PFDR memory */ |
---|
| 600 | qm_set_memory(qm_memory_pfdr, pfdr_a, pfdr_sz); |
---|
| 601 | err = qm_init_pfdr(dev, 8, pfdr_sz / 64 - 8); |
---|
| 602 | if (err) |
---|
| 603 | return err; |
---|
| 604 | /* thresholds */ |
---|
| 605 | qm_set_pfdr_threshold(512, 64); |
---|
| 606 | qm_set_sfdr_threshold(128); |
---|
| 607 | /* clear stale PEBI bit from interrupt status register */ |
---|
| 608 | qm_ccsr_out(REG_ERR_ISR, QM_EIRQ_PEBI); |
---|
| 609 | /* corenet initiator settings */ |
---|
| 610 | qm_set_corenet_initiator(); |
---|
| 611 | /* HID settings */ |
---|
| 612 | qm_set_hid(); |
---|
| 613 | /* Set scheduling weights to defaults */ |
---|
| 614 | for (i = qm_wq_first; i <= qm_wq_last; i++) |
---|
| 615 | qm_set_wq_scheduling(i, 0, 0, 0, 0, 0, 0, 0); |
---|
| 616 | /* We are not prepared to accept ERNs for hardware enqueues */ |
---|
| 617 | qm_set_dc(qm_dc_portal_fman0, 1, 0); |
---|
| 618 | qm_set_dc(qm_dc_portal_fman1, 1, 0); |
---|
| 619 | return 0; |
---|
| 620 | } |
---|
| 621 | |
---|
| 622 | #define LIO_CFG_LIODN_MASK 0x0fff0000 |
---|
| 623 | void qman_liodn_fixup(u16 channel) |
---|
| 624 | { |
---|
| 625 | static int done; |
---|
| 626 | static u32 liodn_offset; |
---|
| 627 | u32 before, after; |
---|
| 628 | int idx = channel - QM_CHANNEL_SWPORTAL0; |
---|
| 629 | |
---|
| 630 | if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) |
---|
| 631 | before = qm_ccsr_in(REG_REV3_QCSP_LIO_CFG(idx)); |
---|
| 632 | else |
---|
| 633 | before = qm_ccsr_in(REG_QCSP_LIO_CFG(idx)); |
---|
| 634 | if (!done) { |
---|
| 635 | liodn_offset = before & LIO_CFG_LIODN_MASK; |
---|
| 636 | done = 1; |
---|
| 637 | return; |
---|
| 638 | } |
---|
| 639 | after = (before & (~LIO_CFG_LIODN_MASK)) | liodn_offset; |
---|
| 640 | if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) |
---|
| 641 | qm_ccsr_out(REG_REV3_QCSP_LIO_CFG(idx), after); |
---|
| 642 | else |
---|
| 643 | qm_ccsr_out(REG_QCSP_LIO_CFG(idx), after); |
---|
| 644 | } |
---|
| 645 | |
---|
| 646 | #define IO_CFG_SDEST_MASK 0x00ff0000 |
---|
| 647 | void qman_set_sdest(u16 channel, unsigned int cpu_idx) |
---|
| 648 | { |
---|
| 649 | int idx = channel - QM_CHANNEL_SWPORTAL0; |
---|
| 650 | u32 before, after; |
---|
| 651 | |
---|
| 652 | if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) { |
---|
| 653 | before = qm_ccsr_in(REG_REV3_QCSP_IO_CFG(idx)); |
---|
| 654 | /* Each pair of vcpu share the same SRQ(SDEST) */ |
---|
| 655 | cpu_idx /= 2; |
---|
| 656 | after = (before & (~IO_CFG_SDEST_MASK)) | (cpu_idx << 16); |
---|
| 657 | qm_ccsr_out(REG_REV3_QCSP_IO_CFG(idx), after); |
---|
| 658 | } else { |
---|
| 659 | before = qm_ccsr_in(REG_QCSP_IO_CFG(idx)); |
---|
| 660 | after = (before & (~IO_CFG_SDEST_MASK)) | (cpu_idx << 16); |
---|
| 661 | qm_ccsr_out(REG_QCSP_IO_CFG(idx), after); |
---|
| 662 | } |
---|
| 663 | } |
---|
| 664 | |
---|
| 665 | static int qman_resource_init(struct device *dev) |
---|
| 666 | { |
---|
| 667 | int pool_chan_num, cgrid_num; |
---|
| 668 | int ret, i; |
---|
| 669 | |
---|
| 670 | switch (qman_ip_rev >> 8) { |
---|
| 671 | case 1: |
---|
| 672 | pool_chan_num = 15; |
---|
| 673 | cgrid_num = 256; |
---|
| 674 | break; |
---|
| 675 | case 2: |
---|
| 676 | pool_chan_num = 3; |
---|
| 677 | cgrid_num = 64; |
---|
| 678 | break; |
---|
| 679 | case 3: |
---|
| 680 | pool_chan_num = 15; |
---|
| 681 | cgrid_num = 256; |
---|
| 682 | break; |
---|
| 683 | default: |
---|
| 684 | return -ENODEV; |
---|
| 685 | } |
---|
| 686 | |
---|
| 687 | ret = gen_pool_add(qm_qpalloc, qm_channel_pool1 | DPAA_GENALLOC_OFF, |
---|
| 688 | pool_chan_num, -1); |
---|
| 689 | if (ret) { |
---|
| 690 | dev_err(dev, "Failed to seed pool channels (%d)\n", ret); |
---|
| 691 | return ret; |
---|
| 692 | } |
---|
| 693 | |
---|
| 694 | ret = gen_pool_add(qm_cgralloc, DPAA_GENALLOC_OFF, cgrid_num, -1); |
---|
| 695 | if (ret) { |
---|
| 696 | dev_err(dev, "Failed to seed CGRID range (%d)\n", ret); |
---|
| 697 | return ret; |
---|
| 698 | } |
---|
| 699 | |
---|
| 700 | /* parse pool channels into the SDQCR mask */ |
---|
| 701 | for (i = 0; i < cgrid_num; i++) |
---|
| 702 | qm_pools_sdqcr |= QM_SDQCR_CHANNELS_POOL_CONV(i); |
---|
| 703 | |
---|
| 704 | ret = gen_pool_add(qm_fqalloc, QM_FQID_RANGE_START | DPAA_GENALLOC_OFF, |
---|
| 705 | qm_get_fqid_maxcnt() - QM_FQID_RANGE_START, -1); |
---|
| 706 | if (ret) { |
---|
| 707 | dev_err(dev, "Failed to seed FQID range (%d)\n", ret); |
---|
| 708 | return ret; |
---|
| 709 | } |
---|
| 710 | |
---|
| 711 | return 0; |
---|
| 712 | } |
---|
| 713 | |
---|
| 714 | static int fsl_qman_probe(struct platform_device *pdev) |
---|
| 715 | { |
---|
| 716 | struct device *dev = &pdev->dev; |
---|
| 717 | struct device_node *node = dev->of_node; |
---|
| 718 | #ifdef __rtems__ |
---|
| 719 | struct resource res_storage; |
---|
| 720 | #endif /* __rtems__ */ |
---|
| 721 | struct resource *res; |
---|
| 722 | int ret, err_irq; |
---|
| 723 | u16 id; |
---|
| 724 | u8 major, minor; |
---|
| 725 | |
---|
| 726 | #ifndef __rtems__ |
---|
| 727 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
---|
| 728 | #else /* __rtems__ */ |
---|
| 729 | res = platform_get_resource(&res_storage, pdev, IORESOURCE_MEM, 0); |
---|
| 730 | #endif /* __rtems__ */ |
---|
| 731 | if (!res) { |
---|
| 732 | dev_err(dev, "Can't get %s property 'IORESOURCE_MEM'\n", |
---|
| 733 | node->full_name); |
---|
| 734 | return -ENXIO; |
---|
| 735 | } |
---|
| 736 | qm_ccsr_start = devm_ioremap(dev, res->start, resource_size(res)); |
---|
| 737 | if (!qm_ccsr_start) |
---|
| 738 | return -ENXIO; |
---|
| 739 | |
---|
| 740 | qm_get_version(&id, &major, &minor); |
---|
| 741 | if (major == 1 && minor == 0) { |
---|
| 742 | dev_err(dev, "Rev1.0 on P4080 rev1 is not supported!\n"); |
---|
| 743 | return -ENODEV; |
---|
| 744 | } else if (major == 1 && minor == 1) |
---|
| 745 | qman_ip_rev = QMAN_REV11; |
---|
| 746 | else if (major == 1 && minor == 2) |
---|
| 747 | qman_ip_rev = QMAN_REV12; |
---|
| 748 | else if (major == 2 && minor == 0) |
---|
| 749 | qman_ip_rev = QMAN_REV20; |
---|
| 750 | else if (major == 3 && minor == 0) |
---|
| 751 | qman_ip_rev = QMAN_REV30; |
---|
| 752 | else if (major == 3 && minor == 1) |
---|
| 753 | qman_ip_rev = QMAN_REV31; |
---|
| 754 | else { |
---|
| 755 | dev_err(dev, "Unknown QMan version\n"); |
---|
| 756 | return -ENODEV; |
---|
| 757 | } |
---|
| 758 | |
---|
[cf40770] | 759 | if ((qman_ip_rev & 0xff00) >= QMAN_REV30) { |
---|
[cd089b9] | 760 | qm_channel_pool1 = QMAN_CHANNEL_POOL1_REV3; |
---|
[cf40770] | 761 | qm_channel_caam = QMAN_CHANNEL_CAAM_REV3; |
---|
| 762 | } |
---|
[cd089b9] | 763 | |
---|
| 764 | ret = zero_priv_mem(dev, node, fqd_a, fqd_sz); |
---|
| 765 | WARN_ON(ret); |
---|
| 766 | if (ret) |
---|
| 767 | return -ENODEV; |
---|
| 768 | |
---|
| 769 | ret = qman_init_ccsr(dev); |
---|
| 770 | if (ret) { |
---|
| 771 | dev_err(dev, "CCSR setup failed\n"); |
---|
| 772 | return ret; |
---|
| 773 | } |
---|
| 774 | |
---|
| 775 | err_irq = platform_get_irq(pdev, 0); |
---|
[721b1c1] | 776 | if (err_irq < 0) { |
---|
[cd089b9] | 777 | dev_info(dev, "Can't get %s property 'interrupts'\n", |
---|
| 778 | node->full_name); |
---|
| 779 | return -ENODEV; |
---|
| 780 | } |
---|
| 781 | ret = devm_request_irq(dev, err_irq, qman_isr, IRQF_SHARED, "qman-err", |
---|
| 782 | dev); |
---|
| 783 | if (ret) { |
---|
| 784 | dev_err(dev, "devm_request_irq() failed %d for '%s'\n", |
---|
| 785 | ret, node->full_name); |
---|
| 786 | return ret; |
---|
| 787 | } |
---|
| 788 | |
---|
| 789 | /* |
---|
| 790 | * Write-to-clear any stale bits, (eg. starvation being asserted prior |
---|
| 791 | * to resource allocation during driver init). |
---|
| 792 | */ |
---|
| 793 | qm_ccsr_out(REG_ERR_ISR, 0xffffffff); |
---|
| 794 | /* Enable Error Interrupts */ |
---|
| 795 | qm_ccsr_out(REG_ERR_IER, 0xffffffff); |
---|
| 796 | |
---|
| 797 | qm_fqalloc = devm_gen_pool_create(dev, 0, -1, "qman-fqalloc"); |
---|
| 798 | if (IS_ERR(qm_fqalloc)) { |
---|
| 799 | ret = PTR_ERR(qm_fqalloc); |
---|
| 800 | dev_err(dev, "qman-fqalloc pool init failed (%d)\n", ret); |
---|
| 801 | return ret; |
---|
| 802 | } |
---|
| 803 | |
---|
| 804 | qm_qpalloc = devm_gen_pool_create(dev, 0, -1, "qman-qpalloc"); |
---|
| 805 | if (IS_ERR(qm_qpalloc)) { |
---|
| 806 | ret = PTR_ERR(qm_qpalloc); |
---|
| 807 | dev_err(dev, "qman-qpalloc pool init failed (%d)\n", ret); |
---|
| 808 | return ret; |
---|
| 809 | } |
---|
| 810 | |
---|
| 811 | qm_cgralloc = devm_gen_pool_create(dev, 0, -1, "qman-cgralloc"); |
---|
| 812 | if (IS_ERR(qm_cgralloc)) { |
---|
| 813 | ret = PTR_ERR(qm_cgralloc); |
---|
| 814 | dev_err(dev, "qman-cgralloc pool init failed (%d)\n", ret); |
---|
| 815 | return ret; |
---|
| 816 | } |
---|
| 817 | |
---|
| 818 | ret = qman_resource_init(dev); |
---|
| 819 | if (ret) |
---|
| 820 | return ret; |
---|
| 821 | |
---|
| 822 | ret = qman_alloc_fq_table(qm_get_fqid_maxcnt()); |
---|
| 823 | if (ret) |
---|
| 824 | return ret; |
---|
| 825 | |
---|
| 826 | ret = qman_wq_alloc(); |
---|
| 827 | if (ret) |
---|
| 828 | return ret; |
---|
| 829 | |
---|
| 830 | return 0; |
---|
| 831 | } |
---|
| 832 | |
---|
| 833 | #ifndef __rtems__ |
---|
| 834 | static const struct of_device_id fsl_qman_ids[] = { |
---|
| 835 | { |
---|
| 836 | .compatible = "fsl,qman", |
---|
| 837 | }, |
---|
| 838 | {} |
---|
| 839 | }; |
---|
| 840 | |
---|
| 841 | static struct platform_driver fsl_qman_driver = { |
---|
| 842 | .driver = { |
---|
| 843 | .name = KBUILD_MODNAME, |
---|
| 844 | .of_match_table = fsl_qman_ids, |
---|
| 845 | .suppress_bind_attrs = true, |
---|
| 846 | }, |
---|
| 847 | .probe = fsl_qman_probe, |
---|
| 848 | }; |
---|
| 849 | |
---|
| 850 | builtin_platform_driver(fsl_qman_driver); |
---|
| 851 | #else /* __rtems__ */ |
---|
| 852 | #include <bsp/fdt.h> |
---|
| 853 | |
---|
| 854 | SYSINIT_REFERENCE(bman); |
---|
| 855 | |
---|
| 856 | static void |
---|
| 857 | qman_sysinit(void) |
---|
| 858 | { |
---|
| 859 | const char *fdt = bsp_fdt_get(); |
---|
| 860 | struct { |
---|
| 861 | struct platform_device pdev; |
---|
| 862 | struct device_node of_node; |
---|
| 863 | } dev; |
---|
| 864 | const char *name; |
---|
| 865 | int node; |
---|
| 866 | int ret; |
---|
| 867 | |
---|
| 868 | name = "fsl,qman"; |
---|
| 869 | node = fdt_node_offset_by_compatible(fdt, 0, name); |
---|
| 870 | if (node < 0) |
---|
| 871 | panic("qman: no qman in FDT"); |
---|
| 872 | |
---|
| 873 | memset(&dev, 0, sizeof(dev)); |
---|
| 874 | dev.pdev.dev.of_node = &dev.of_node; |
---|
| 875 | dev.of_node.offset = node; |
---|
| 876 | dev.of_node.full_name = name; |
---|
| 877 | |
---|
| 878 | ret = fsl_qman_probe(&dev.pdev); |
---|
| 879 | if (ret != 0) |
---|
| 880 | panic("qman: init failed"); |
---|
| 881 | |
---|
| 882 | qman_sysinit_portals(); |
---|
| 883 | } |
---|
| 884 | SYSINIT(qman, SI_SUB_CPU, SI_ORDER_SECOND, qman_sysinit, NULL); |
---|
| 885 | #endif /* __rtems__ */ |
---|