1 | #include <machine/rtems-bsd-kernel-space.h> |
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2 | |
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3 | #include <rtems/bsd/local/opt_dpaa.h> |
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4 | |
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5 | /* |
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6 | * Copyright 2008-2015 Freescale Semiconductor Inc. |
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7 | * |
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8 | * Redistribution and use in source and binary forms, with or without |
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9 | * modification, are permitted provided that the following conditions are met: |
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10 | * * Redistributions of source code must retain the above copyright |
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11 | * notice, this list of conditions and the following disclaimer. |
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12 | * * Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * * Neither the name of Freescale Semiconductor nor the |
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16 | * names of its contributors may be used to endorse or promote products |
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17 | * derived from this software without specific prior written permission. |
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18 | * |
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19 | * |
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20 | * ALTERNATIVELY, this software may be distributed under the terms of the |
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21 | * GNU General Public License ("GPL") as published by the Free Software |
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22 | * Foundation, either version 2 of that License or (at your option) any |
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23 | * later version. |
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24 | * |
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25 | * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
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26 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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27 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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28 | * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
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29 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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30 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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31 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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32 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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33 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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34 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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35 | */ |
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36 | |
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37 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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38 | |
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39 | #include "fman.h" |
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40 | #include "fman_muram.h" |
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41 | |
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42 | #include <linux/fsl/guts.h> |
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43 | #include <linux/slab.h> |
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44 | #include <linux/delay.h> |
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45 | #include <linux/module.h> |
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46 | #include <linux/of_platform.h> |
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47 | #include <linux/clk.h> |
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48 | #include <linux/of_address.h> |
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49 | #include <linux/of_irq.h> |
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50 | #include <linux/interrupt.h> |
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51 | #include <linux/libfdt_env.h> |
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52 | #ifdef __rtems__ |
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53 | #include <bsp/fdt.h> |
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54 | #endif /* __rtems__ */ |
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55 | |
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56 | /* General defines */ |
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57 | #define FMAN_LIODN_TBL 64 /* size of LIODN table */ |
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58 | #define MAX_NUM_OF_MACS 10 |
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59 | #define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4 |
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60 | #define BASE_RX_PORTID 0x08 |
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61 | #define BASE_TX_PORTID 0x28 |
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62 | |
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63 | /* Modules registers offsets */ |
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64 | #define BMI_OFFSET 0x00080000 |
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65 | #define QMI_OFFSET 0x00080400 |
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66 | #define DMA_OFFSET 0x000C2000 |
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67 | #define FPM_OFFSET 0x000C3000 |
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68 | #define IMEM_OFFSET 0x000C4000 |
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69 | #define HWP_OFFSET 0x000C7000 |
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70 | #define CGP_OFFSET 0x000DB000 |
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71 | |
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72 | /* Exceptions bit map */ |
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73 | #define EX_DMA_BUS_ERROR 0x80000000 |
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74 | #define EX_DMA_READ_ECC 0x40000000 |
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75 | #define EX_DMA_SYSTEM_WRITE_ECC 0x20000000 |
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76 | #define EX_DMA_FM_WRITE_ECC 0x10000000 |
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77 | #define EX_FPM_STALL_ON_TASKS 0x08000000 |
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78 | #define EX_FPM_SINGLE_ECC 0x04000000 |
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79 | #define EX_FPM_DOUBLE_ECC 0x02000000 |
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80 | #define EX_QMI_SINGLE_ECC 0x01000000 |
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81 | #define EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000 |
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82 | #define EX_QMI_DOUBLE_ECC 0x00400000 |
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83 | #define EX_BMI_LIST_RAM_ECC 0x00200000 |
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84 | #define EX_BMI_STORAGE_PROFILE_ECC 0x00100000 |
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85 | #define EX_BMI_STATISTICS_RAM_ECC 0x00080000 |
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86 | #define EX_IRAM_ECC 0x00040000 |
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87 | #define EX_MURAM_ECC 0x00020000 |
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88 | #define EX_BMI_DISPATCH_RAM_ECC 0x00010000 |
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89 | #define EX_DMA_SINGLE_PORT_ECC 0x00008000 |
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90 | |
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91 | /* DMA defines */ |
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92 | /* masks */ |
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93 | #define DMA_MODE_BER 0x00200000 |
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94 | #define DMA_MODE_ECC 0x00000020 |
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95 | #define DMA_MODE_SECURE_PROT 0x00000800 |
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96 | #define DMA_MODE_AXI_DBG_MASK 0x0F000000 |
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97 | |
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98 | #define DMA_TRANSFER_PORTID_MASK 0xFF000000 |
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99 | #define DMA_TRANSFER_TNUM_MASK 0x00FF0000 |
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100 | #define DMA_TRANSFER_LIODN_MASK 0x00000FFF |
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101 | |
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102 | #define DMA_STATUS_BUS_ERR 0x08000000 |
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103 | #define DMA_STATUS_READ_ECC 0x04000000 |
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104 | #define DMA_STATUS_SYSTEM_WRITE_ECC 0x02000000 |
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105 | #define DMA_STATUS_FM_WRITE_ECC 0x01000000 |
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106 | #define DMA_STATUS_FM_SPDAT_ECC 0x00080000 |
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107 | |
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108 | #define DMA_MODE_CACHE_OR_SHIFT 30 |
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109 | #define DMA_MODE_AXI_DBG_SHIFT 24 |
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110 | #define DMA_MODE_CEN_SHIFT 13 |
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111 | #define DMA_MODE_CEN_MASK 0x00000007 |
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112 | #define DMA_MODE_DBG_SHIFT 7 |
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113 | #define DMA_MODE_AID_MODE_SHIFT 4 |
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114 | |
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115 | #define DMA_THRESH_COMMQ_SHIFT 24 |
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116 | #define DMA_THRESH_READ_INT_BUF_SHIFT 16 |
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117 | #define DMA_THRESH_READ_INT_BUF_MASK 0x0000003f |
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118 | #define DMA_THRESH_WRITE_INT_BUF_MASK 0x0000003f |
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119 | |
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120 | #define DMA_TRANSFER_PORTID_SHIFT 24 |
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121 | #define DMA_TRANSFER_TNUM_SHIFT 16 |
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122 | |
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123 | #define DMA_CAM_SIZEOF_ENTRY 0x40 |
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124 | #define DMA_CAM_UNITS 8 |
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125 | |
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126 | #define DMA_LIODN_SHIFT 16 |
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127 | #define DMA_LIODN_BASE_MASK 0x00000FFF |
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128 | |
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129 | /* FPM defines */ |
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130 | #define FPM_EV_MASK_DOUBLE_ECC 0x80000000 |
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131 | #define FPM_EV_MASK_STALL 0x40000000 |
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132 | #define FPM_EV_MASK_SINGLE_ECC 0x20000000 |
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133 | #define FPM_EV_MASK_RELEASE_FM 0x00010000 |
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134 | #define FPM_EV_MASK_DOUBLE_ECC_EN 0x00008000 |
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135 | #define FPM_EV_MASK_STALL_EN 0x00004000 |
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136 | #define FPM_EV_MASK_SINGLE_ECC_EN 0x00002000 |
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137 | #define FPM_EV_MASK_EXTERNAL_HALT 0x00000008 |
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138 | #define FPM_EV_MASK_ECC_ERR_HALT 0x00000004 |
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139 | |
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140 | #define FPM_RAM_MURAM_ECC 0x00008000 |
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141 | #define FPM_RAM_IRAM_ECC 0x00004000 |
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142 | #define FPM_IRAM_ECC_ERR_EX_EN 0x00020000 |
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143 | #define FPM_MURAM_ECC_ERR_EX_EN 0x00040000 |
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144 | #define FPM_RAM_IRAM_ECC_EN 0x40000000 |
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145 | #define FPM_RAM_RAMS_ECC_EN 0x80000000 |
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146 | #define FPM_RAM_RAMS_ECC_EN_SRC_SEL 0x08000000 |
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147 | |
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148 | #define FPM_REV1_MAJOR_MASK 0x0000FF00 |
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149 | #define FPM_REV1_MINOR_MASK 0x000000FF |
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150 | |
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151 | #define FPM_DISP_LIMIT_SHIFT 24 |
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152 | |
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153 | #define FPM_PRT_FM_CTL1 0x00000001 |
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154 | #define FPM_PRT_FM_CTL2 0x00000002 |
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155 | #define FPM_PORT_FM_CTL_PORTID_SHIFT 24 |
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156 | #define FPM_PRC_ORA_FM_CTL_SEL_SHIFT 16 |
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157 | |
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158 | #define FPM_THR1_PRS_SHIFT 24 |
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159 | #define FPM_THR1_KG_SHIFT 16 |
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160 | #define FPM_THR1_PLCR_SHIFT 8 |
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161 | #define FPM_THR1_BMI_SHIFT 0 |
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162 | |
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163 | #define FPM_THR2_QMI_ENQ_SHIFT 24 |
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164 | #define FPM_THR2_QMI_DEQ_SHIFT 0 |
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165 | #define FPM_THR2_FM_CTL1_SHIFT 16 |
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166 | #define FPM_THR2_FM_CTL2_SHIFT 8 |
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167 | |
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168 | #define FPM_EV_MASK_CAT_ERR_SHIFT 1 |
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169 | #define FPM_EV_MASK_DMA_ERR_SHIFT 0 |
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170 | |
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171 | #define FPM_REV1_MAJOR_SHIFT 8 |
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172 | |
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173 | #define FPM_RSTC_FM_RESET 0x80000000 |
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174 | #define FPM_RSTC_MAC0_RESET 0x40000000 |
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175 | #define FPM_RSTC_MAC1_RESET 0x20000000 |
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176 | #define FPM_RSTC_MAC2_RESET 0x10000000 |
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177 | #define FPM_RSTC_MAC3_RESET 0x08000000 |
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178 | #define FPM_RSTC_MAC8_RESET 0x04000000 |
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179 | #define FPM_RSTC_MAC4_RESET 0x02000000 |
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180 | #define FPM_RSTC_MAC5_RESET 0x01000000 |
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181 | #define FPM_RSTC_MAC6_RESET 0x00800000 |
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182 | #define FPM_RSTC_MAC7_RESET 0x00400000 |
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183 | #define FPM_RSTC_MAC9_RESET 0x00200000 |
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184 | |
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185 | #define FPM_TS_INT_SHIFT 16 |
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186 | #define FPM_TS_CTL_EN 0x80000000 |
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187 | |
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188 | /* BMI defines */ |
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189 | #define BMI_INIT_START 0x80000000 |
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190 | #define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC 0x80000000 |
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191 | #define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000 |
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192 | #define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000 |
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193 | #define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000 |
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194 | #define BMI_NUM_OF_TASKS_MASK 0x3F000000 |
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195 | #define BMI_NUM_OF_EXTRA_TASKS_MASK 0x000F0000 |
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196 | #define BMI_NUM_OF_DMAS_MASK 0x00000F00 |
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197 | #define BMI_NUM_OF_EXTRA_DMAS_MASK 0x0000000F |
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198 | #define BMI_FIFO_SIZE_MASK 0x000003FF |
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199 | #define BMI_EXTRA_FIFO_SIZE_MASK 0x03FF0000 |
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200 | #define BMI_CFG2_DMAS_MASK 0x0000003F |
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201 | #define BMI_CFG2_TASKS_MASK 0x0000003F |
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202 | |
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203 | #define BMI_CFG2_TASKS_SHIFT 16 |
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204 | #define BMI_CFG2_DMAS_SHIFT 0 |
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205 | #define BMI_CFG1_FIFO_SIZE_SHIFT 16 |
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206 | #define BMI_NUM_OF_TASKS_SHIFT 24 |
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207 | #define BMI_EXTRA_NUM_OF_TASKS_SHIFT 16 |
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208 | #define BMI_NUM_OF_DMAS_SHIFT 8 |
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209 | #define BMI_EXTRA_NUM_OF_DMAS_SHIFT 0 |
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210 | |
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211 | #define BMI_FIFO_ALIGN 0x100 |
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212 | |
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213 | #define BMI_EXTRA_FIFO_SIZE_SHIFT 16 |
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214 | |
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215 | /* QMI defines */ |
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216 | #define QMI_CFG_ENQ_EN 0x80000000 |
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217 | #define QMI_CFG_DEQ_EN 0x40000000 |
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218 | #define QMI_CFG_EN_COUNTERS 0x10000000 |
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219 | #define QMI_CFG_DEQ_MASK 0x0000003F |
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220 | #define QMI_CFG_ENQ_MASK 0x00003F00 |
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221 | #define QMI_CFG_ENQ_SHIFT 8 |
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222 | |
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223 | #define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000 |
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224 | #define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000 |
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225 | #define QMI_INTR_EN_SINGLE_ECC 0x80000000 |
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226 | |
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227 | #define QMI_GS_HALT_NOT_BUSY 0x00000002 |
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228 | |
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229 | /* HWP defines */ |
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230 | #define HWP_RPIMAC_PEN 0x00000001 |
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231 | |
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232 | /* IRAM defines */ |
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233 | #define IRAM_IADD_AIE 0x80000000 |
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234 | #define IRAM_READY 0x80000000 |
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235 | |
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236 | /* Default values */ |
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237 | #define DEFAULT_CATASTROPHIC_ERR 0 |
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238 | #define DEFAULT_DMA_ERR 0 |
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239 | #define DEFAULT_AID_MODE FMAN_DMA_AID_OUT_TNUM |
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240 | #define DEFAULT_DMA_COMM_Q_LOW 0x2A |
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241 | #define DEFAULT_DMA_COMM_Q_HIGH 0x3F |
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242 | #define DEFAULT_CACHE_OVERRIDE 0 |
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243 | #define DEFAULT_DMA_CAM_NUM_OF_ENTRIES 64 |
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244 | #define DEFAULT_DMA_DBG_CNT_MODE 0 |
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245 | #define DEFAULT_DMA_SOS_EMERGENCY 0 |
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246 | #define DEFAULT_DMA_WATCHDOG 0 |
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247 | #define DEFAULT_DISP_LIMIT 0 |
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248 | #define DEFAULT_PRS_DISP_TH 16 |
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249 | #define DEFAULT_PLCR_DISP_TH 16 |
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250 | #define DEFAULT_KG_DISP_TH 16 |
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251 | #define DEFAULT_BMI_DISP_TH 16 |
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252 | #define DEFAULT_QMI_ENQ_DISP_TH 16 |
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253 | #define DEFAULT_QMI_DEQ_DISP_TH 16 |
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254 | #define DEFAULT_FM_CTL1_DISP_TH 16 |
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255 | #define DEFAULT_FM_CTL2_DISP_TH 16 |
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256 | |
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257 | #define DFLT_AXI_DBG_NUM_OF_BEATS 1 |
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258 | |
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259 | #define DFLT_DMA_READ_INT_BUF_LOW(dma_thresh_max_buf) \ |
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260 | ((dma_thresh_max_buf + 1) / 2) |
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261 | #define DFLT_DMA_READ_INT_BUF_HIGH(dma_thresh_max_buf) \ |
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262 | ((dma_thresh_max_buf + 1) * 3 / 4) |
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263 | #define DFLT_DMA_WRITE_INT_BUF_LOW(dma_thresh_max_buf) \ |
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264 | ((dma_thresh_max_buf + 1) / 2) |
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265 | #define DFLT_DMA_WRITE_INT_BUF_HIGH(dma_thresh_max_buf)\ |
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266 | ((dma_thresh_max_buf + 1) * 3 / 4) |
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267 | |
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268 | #define DMA_COMM_Q_LOW_FMAN_V3 0x2A |
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269 | #define DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq) \ |
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270 | ((dma_thresh_max_commq + 1) / 2) |
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271 | #define DFLT_DMA_COMM_Q_LOW(major, dma_thresh_max_commq) \ |
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272 | ((major == 6) ? DMA_COMM_Q_LOW_FMAN_V3 : \ |
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273 | DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq)) |
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274 | |
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275 | #define DMA_COMM_Q_HIGH_FMAN_V3 0x3f |
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276 | #define DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq) \ |
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277 | ((dma_thresh_max_commq + 1) * 3 / 4) |
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278 | #define DFLT_DMA_COMM_Q_HIGH(major, dma_thresh_max_commq) \ |
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279 | ((major == 6) ? DMA_COMM_Q_HIGH_FMAN_V3 : \ |
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280 | DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq)) |
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281 | |
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282 | #define TOTAL_NUM_OF_TASKS_FMAN_V3L 59 |
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283 | #define TOTAL_NUM_OF_TASKS_FMAN_V3H 124 |
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284 | #define DFLT_TOTAL_NUM_OF_TASKS(major, minor, bmi_max_num_of_tasks) \ |
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285 | ((major == 6) ? ((minor == 1 || minor == 4) ? \ |
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286 | TOTAL_NUM_OF_TASKS_FMAN_V3L : TOTAL_NUM_OF_TASKS_FMAN_V3H) : \ |
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287 | bmi_max_num_of_tasks) |
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288 | |
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289 | #define DMA_CAM_NUM_OF_ENTRIES_FMAN_V3 64 |
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290 | #define DMA_CAM_NUM_OF_ENTRIES_FMAN_V2 32 |
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291 | #define DFLT_DMA_CAM_NUM_OF_ENTRIES(major) \ |
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292 | (major == 6 ? DMA_CAM_NUM_OF_ENTRIES_FMAN_V3 : \ |
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293 | DMA_CAM_NUM_OF_ENTRIES_FMAN_V2) |
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294 | |
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295 | #define FM_TIMESTAMP_1_USEC_BIT 8 |
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296 | |
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297 | /* Defines used for enabling/disabling FMan interrupts */ |
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298 | #define ERR_INTR_EN_DMA 0x00010000 |
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299 | #define ERR_INTR_EN_FPM 0x80000000 |
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300 | #define ERR_INTR_EN_BMI 0x00800000 |
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301 | #define ERR_INTR_EN_QMI 0x00400000 |
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302 | #define ERR_INTR_EN_MURAM 0x00040000 |
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303 | #define ERR_INTR_EN_MAC0 0x00004000 |
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304 | #define ERR_INTR_EN_MAC1 0x00002000 |
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305 | #define ERR_INTR_EN_MAC2 0x00001000 |
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306 | #define ERR_INTR_EN_MAC3 0x00000800 |
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307 | #define ERR_INTR_EN_MAC4 0x00000400 |
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308 | #define ERR_INTR_EN_MAC5 0x00000200 |
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309 | #define ERR_INTR_EN_MAC6 0x00000100 |
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310 | #define ERR_INTR_EN_MAC7 0x00000080 |
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311 | #define ERR_INTR_EN_MAC8 0x00008000 |
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312 | #define ERR_INTR_EN_MAC9 0x00000040 |
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313 | |
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314 | #define INTR_EN_QMI 0x40000000 |
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315 | #define INTR_EN_MAC0 0x00080000 |
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316 | #define INTR_EN_MAC1 0x00040000 |
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317 | #define INTR_EN_MAC2 0x00020000 |
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318 | #define INTR_EN_MAC3 0x00010000 |
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319 | #define INTR_EN_MAC4 0x00000040 |
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320 | #define INTR_EN_MAC5 0x00000020 |
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321 | #define INTR_EN_MAC6 0x00000008 |
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322 | #define INTR_EN_MAC7 0x00000002 |
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323 | #define INTR_EN_MAC8 0x00200000 |
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324 | #define INTR_EN_MAC9 0x00100000 |
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325 | #define INTR_EN_REV0 0x00008000 |
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326 | #define INTR_EN_REV1 0x00004000 |
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327 | #define INTR_EN_REV2 0x00002000 |
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328 | #define INTR_EN_REV3 0x00001000 |
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329 | #define INTR_EN_TMR 0x01000000 |
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330 | |
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331 | enum fman_dma_aid_mode { |
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332 | FMAN_DMA_AID_OUT_PORT_ID = 0, /* 4 LSB of PORT_ID */ |
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333 | FMAN_DMA_AID_OUT_TNUM /* 4 LSB of TNUM */ |
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334 | }; |
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335 | |
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336 | struct fman_iram_regs { |
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337 | u32 iadd; /* FM IRAM instruction address register */ |
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338 | u32 idata; /* FM IRAM instruction data register */ |
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339 | u32 itcfg; /* FM IRAM timing config register */ |
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340 | u32 iready; /* FM IRAM ready register */ |
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341 | }; |
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342 | |
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343 | struct fman_fpm_regs { |
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344 | u32 fmfp_tnc; /* FPM TNUM Control 0x00 */ |
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345 | u32 fmfp_prc; /* FPM Port_ID FmCtl Association 0x04 */ |
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346 | u32 fmfp_brkc; /* FPM Breakpoint Control 0x08 */ |
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347 | u32 fmfp_mxd; /* FPM Flush Control 0x0c */ |
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348 | u32 fmfp_dist1; /* FPM Dispatch Thresholds1 0x10 */ |
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349 | u32 fmfp_dist2; /* FPM Dispatch Thresholds2 0x14 */ |
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350 | u32 fm_epi; /* FM Error Pending Interrupts 0x18 */ |
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351 | u32 fm_rie; /* FM Error Interrupt Enable 0x1c */ |
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352 | u32 fmfp_fcev[4]; /* FPM FMan-Controller Event 1-4 0x20-0x2f */ |
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353 | u32 res0030[4]; /* res 0x30 - 0x3f */ |
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354 | u32 fmfp_cee[4]; /* PM FMan-Controller Event 1-4 0x40-0x4f */ |
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355 | u32 res0050[4]; /* res 0x50-0x5f */ |
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356 | u32 fmfp_tsc1; /* FPM TimeStamp Control1 0x60 */ |
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357 | u32 fmfp_tsc2; /* FPM TimeStamp Control2 0x64 */ |
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358 | u32 fmfp_tsp; /* FPM Time Stamp 0x68 */ |
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359 | u32 fmfp_tsf; /* FPM Time Stamp Fraction 0x6c */ |
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360 | u32 fm_rcr; /* FM Rams Control 0x70 */ |
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361 | u32 fmfp_extc; /* FPM External Requests Control 0x74 */ |
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362 | u32 fmfp_ext1; /* FPM External Requests Config1 0x78 */ |
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363 | u32 fmfp_ext2; /* FPM External Requests Config2 0x7c */ |
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364 | u32 fmfp_drd[16]; /* FPM Data_Ram Data 0-15 0x80 - 0xbf */ |
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365 | u32 fmfp_dra; /* FPM Data Ram Access 0xc0 */ |
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366 | u32 fm_ip_rev_1; /* FM IP Block Revision 1 0xc4 */ |
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367 | u32 fm_ip_rev_2; /* FM IP Block Revision 2 0xc8 */ |
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368 | u32 fm_rstc; /* FM Reset Command 0xcc */ |
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369 | u32 fm_cld; /* FM Classifier Debug 0xd0 */ |
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370 | u32 fm_npi; /* FM Normal Pending Interrupts 0xd4 */ |
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371 | u32 fmfp_exte; /* FPM External Requests Enable 0xd8 */ |
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372 | u32 fmfp_ee; /* FPM Event&Mask 0xdc */ |
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373 | u32 fmfp_cev[4]; /* FPM CPU Event 1-4 0xe0-0xef */ |
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374 | u32 res00f0[4]; /* res 0xf0-0xff */ |
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375 | u32 fmfp_ps[50]; /* FPM Port Status 0x100-0x1c7 */ |
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376 | u32 res01c8[14]; /* res 0x1c8-0x1ff */ |
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377 | u32 fmfp_clfabc; /* FPM CLFABC 0x200 */ |
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378 | u32 fmfp_clfcc; /* FPM CLFCC 0x204 */ |
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379 | u32 fmfp_clfaval; /* FPM CLFAVAL 0x208 */ |
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380 | u32 fmfp_clfbval; /* FPM CLFBVAL 0x20c */ |
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381 | u32 fmfp_clfcval; /* FPM CLFCVAL 0x210 */ |
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382 | u32 fmfp_clfamsk; /* FPM CLFAMSK 0x214 */ |
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383 | u32 fmfp_clfbmsk; /* FPM CLFBMSK 0x218 */ |
---|
384 | u32 fmfp_clfcmsk; /* FPM CLFCMSK 0x21c */ |
---|
385 | u32 fmfp_clfamc; /* FPM CLFAMC 0x220 */ |
---|
386 | u32 fmfp_clfbmc; /* FPM CLFBMC 0x224 */ |
---|
387 | u32 fmfp_clfcmc; /* FPM CLFCMC 0x228 */ |
---|
388 | u32 fmfp_decceh; /* FPM DECCEH 0x22c */ |
---|
389 | u32 res0230[116]; /* res 0x230 - 0x3ff */ |
---|
390 | u32 fmfp_ts[128]; /* 0x400: FPM Task Status 0x400 - 0x5ff */ |
---|
391 | u32 res0600[0x400 - 384]; |
---|
392 | }; |
---|
393 | |
---|
394 | struct fman_bmi_regs { |
---|
395 | u32 fmbm_init; /* BMI Initialization 0x00 */ |
---|
396 | u32 fmbm_cfg1; /* BMI Configuration 1 0x04 */ |
---|
397 | u32 fmbm_cfg2; /* BMI Configuration 2 0x08 */ |
---|
398 | u32 res000c[5]; /* 0x0c - 0x1f */ |
---|
399 | u32 fmbm_ievr; /* Interrupt Event Register 0x20 */ |
---|
400 | u32 fmbm_ier; /* Interrupt Enable Register 0x24 */ |
---|
401 | u32 fmbm_ifr; /* Interrupt Force Register 0x28 */ |
---|
402 | u32 res002c[5]; /* 0x2c - 0x3f */ |
---|
403 | u32 fmbm_arb[8]; /* BMI Arbitration 0x40 - 0x5f */ |
---|
404 | u32 res0060[12]; /* 0x60 - 0x8f */ |
---|
405 | u32 fmbm_dtc[3]; /* Debug Trap Counter 0x90 - 0x9b */ |
---|
406 | u32 res009c; /* 0x9c */ |
---|
407 | u32 fmbm_dcv[3][4]; /* Debug Compare val 0xa0-0xcf */ |
---|
408 | u32 fmbm_dcm[3][4]; /* Debug Compare Mask 0xd0-0xff */ |
---|
409 | u32 fmbm_gde; /* BMI Global Debug Enable 0x100 */ |
---|
410 | u32 fmbm_pp[63]; /* BMI Port Parameters 0x104 - 0x1ff */ |
---|
411 | u32 res0200; /* 0x200 */ |
---|
412 | u32 fmbm_pfs[63]; /* BMI Port FIFO Size 0x204 - 0x2ff */ |
---|
413 | u32 res0300; /* 0x300 */ |
---|
414 | u32 fmbm_spliodn[63]; /* Port Partition ID 0x304 - 0x3ff */ |
---|
415 | }; |
---|
416 | |
---|
417 | struct fman_qmi_regs { |
---|
418 | u32 fmqm_gc; /* General Configuration Register 0x00 */ |
---|
419 | u32 res0004; /* 0x04 */ |
---|
420 | u32 fmqm_eie; /* Error Interrupt Event Register 0x08 */ |
---|
421 | u32 fmqm_eien; /* Error Interrupt Enable Register 0x0c */ |
---|
422 | u32 fmqm_eif; /* Error Interrupt Force Register 0x10 */ |
---|
423 | u32 fmqm_ie; /* Interrupt Event Register 0x14 */ |
---|
424 | u32 fmqm_ien; /* Interrupt Enable Register 0x18 */ |
---|
425 | u32 fmqm_if; /* Interrupt Force Register 0x1c */ |
---|
426 | u32 fmqm_gs; /* Global Status Register 0x20 */ |
---|
427 | u32 fmqm_ts; /* Task Status Register 0x24 */ |
---|
428 | u32 fmqm_etfc; /* Enqueue Total Frame Counter 0x28 */ |
---|
429 | u32 fmqm_dtfc; /* Dequeue Total Frame Counter 0x2c */ |
---|
430 | u32 fmqm_dc0; /* Dequeue Counter 0 0x30 */ |
---|
431 | u32 fmqm_dc1; /* Dequeue Counter 1 0x34 */ |
---|
432 | u32 fmqm_dc2; /* Dequeue Counter 2 0x38 */ |
---|
433 | u32 fmqm_dc3; /* Dequeue Counter 3 0x3c */ |
---|
434 | u32 fmqm_dfdc; /* Dequeue FQID from Default Counter 0x40 */ |
---|
435 | u32 fmqm_dfcc; /* Dequeue FQID from Context Counter 0x44 */ |
---|
436 | u32 fmqm_dffc; /* Dequeue FQID from FD Counter 0x48 */ |
---|
437 | u32 fmqm_dcc; /* Dequeue Confirm Counter 0x4c */ |
---|
438 | u32 res0050[7]; /* 0x50 - 0x6b */ |
---|
439 | u32 fmqm_tapc; /* Tnum Aging Period Control 0x6c */ |
---|
440 | u32 fmqm_dmcvc; /* Dequeue MAC Command Valid Counter 0x70 */ |
---|
441 | u32 fmqm_difdcc; /* Dequeue Invalid FD Command Counter 0x74 */ |
---|
442 | u32 fmqm_da1v; /* Dequeue A1 Valid Counter 0x78 */ |
---|
443 | u32 res007c; /* 0x7c */ |
---|
444 | u32 fmqm_dtc; /* 0x80 Debug Trap Counter 0x80 */ |
---|
445 | u32 fmqm_efddd; /* 0x84 Enqueue Frame desc Dynamic dbg 0x84 */ |
---|
446 | u32 res0088[2]; /* 0x88 - 0x8f */ |
---|
447 | struct { |
---|
448 | u32 fmqm_dtcfg1; /* 0x90 dbg trap cfg 1 Register 0x00 */ |
---|
449 | u32 fmqm_dtval1; /* Debug Trap Value 1 Register 0x04 */ |
---|
450 | u32 fmqm_dtm1; /* Debug Trap Mask 1 Register 0x08 */ |
---|
451 | u32 fmqm_dtc1; /* Debug Trap Counter 1 Register 0x0c */ |
---|
452 | u32 fmqm_dtcfg2; /* dbg Trap cfg 2 Register 0x10 */ |
---|
453 | u32 fmqm_dtval2; /* Debug Trap Value 2 Register 0x14 */ |
---|
454 | u32 fmqm_dtm2; /* Debug Trap Mask 2 Register 0x18 */ |
---|
455 | u32 res001c; /* 0x1c */ |
---|
456 | } dbg_traps[3]; /* 0x90 - 0xef */ |
---|
457 | u8 res00f0[0x400 - 0xf0]; /* 0xf0 - 0x3ff */ |
---|
458 | }; |
---|
459 | |
---|
460 | struct fman_dma_regs { |
---|
461 | u32 fmdmsr; /* FM DMA status register 0x00 */ |
---|
462 | u32 fmdmmr; /* FM DMA mode register 0x04 */ |
---|
463 | u32 fmdmtr; /* FM DMA bus threshold register 0x08 */ |
---|
464 | u32 fmdmhy; /* FM DMA bus hysteresis register 0x0c */ |
---|
465 | u32 fmdmsetr; /* FM DMA SOS emergency Threshold Register 0x10 */ |
---|
466 | u32 fmdmtah; /* FM DMA transfer bus address high reg 0x14 */ |
---|
467 | u32 fmdmtal; /* FM DMA transfer bus address low reg 0x18 */ |
---|
468 | u32 fmdmtcid; /* FM DMA transfer bus communication ID reg 0x1c */ |
---|
469 | u32 fmdmra; /* FM DMA bus internal ram address register 0x20 */ |
---|
470 | u32 fmdmrd; /* FM DMA bus internal ram data register 0x24 */ |
---|
471 | u32 fmdmwcr; /* FM DMA CAM watchdog counter value 0x28 */ |
---|
472 | u32 fmdmebcr; /* FM DMA CAM base in MURAM register 0x2c */ |
---|
473 | u32 fmdmccqdr; /* FM DMA CAM and CMD Queue Debug reg 0x30 */ |
---|
474 | u32 fmdmccqvr1; /* FM DMA CAM and CMD Queue Value reg #1 0x34 */ |
---|
475 | u32 fmdmccqvr2; /* FM DMA CAM and CMD Queue Value reg #2 0x38 */ |
---|
476 | u32 fmdmcqvr3; /* FM DMA CMD Queue Value register #3 0x3c */ |
---|
477 | u32 fmdmcqvr4; /* FM DMA CMD Queue Value register #4 0x40 */ |
---|
478 | u32 fmdmcqvr5; /* FM DMA CMD Queue Value register #5 0x44 */ |
---|
479 | u32 fmdmsefrc; /* FM DMA Semaphore Entry Full Reject Cntr 0x48 */ |
---|
480 | u32 fmdmsqfrc; /* FM DMA Semaphore Queue Full Reject Cntr 0x4c */ |
---|
481 | u32 fmdmssrc; /* FM DMA Semaphore SYNC Reject Counter 0x50 */ |
---|
482 | u32 fmdmdcr; /* FM DMA Debug Counter 0x54 */ |
---|
483 | u32 fmdmemsr; /* FM DMA Emergency Smoother Register 0x58 */ |
---|
484 | u32 res005c; /* 0x5c */ |
---|
485 | u32 fmdmplr[FMAN_LIODN_TBL / 2]; /* DMA LIODN regs 0x60-0xdf */ |
---|
486 | u32 res00e0[0x400 - 56]; |
---|
487 | }; |
---|
488 | |
---|
489 | struct fman_hwp_regs { |
---|
490 | u32 res0000[0x844 / 4]; /* 0x000..0x843 */ |
---|
491 | u32 fmprrpimac; /* FM Parser Internal memory access control */ |
---|
492 | u32 res[(0x1000 - 0x848) / 4]; /* 0x848..0xFFF */ |
---|
493 | }; |
---|
494 | |
---|
495 | /* Structure that holds current FMan state. |
---|
496 | * Used for saving run time information. |
---|
497 | */ |
---|
498 | struct fman_state_struct { |
---|
499 | u8 fm_id; |
---|
500 | u16 fm_clk_freq; |
---|
501 | struct fman_rev_info rev_info; |
---|
502 | bool enabled_time_stamp; |
---|
503 | u8 count1_micro_bit; |
---|
504 | u8 total_num_of_tasks; |
---|
505 | u8 accumulated_num_of_tasks; |
---|
506 | u32 accumulated_fifo_size; |
---|
507 | u8 accumulated_num_of_open_dmas; |
---|
508 | u8 accumulated_num_of_deq_tnums; |
---|
509 | u32 exceptions; |
---|
510 | u32 extra_fifo_pool_size; |
---|
511 | u8 extra_tasks_pool_size; |
---|
512 | u8 extra_open_dmas_pool_size; |
---|
513 | u16 port_mfl[MAX_NUM_OF_MACS]; |
---|
514 | u16 mac_mfl[MAX_NUM_OF_MACS]; |
---|
515 | |
---|
516 | /* SOC specific */ |
---|
517 | u32 fm_iram_size; |
---|
518 | /* DMA */ |
---|
519 | u32 dma_thresh_max_commq; |
---|
520 | u32 dma_thresh_max_buf; |
---|
521 | u32 max_num_of_open_dmas; |
---|
522 | /* QMI */ |
---|
523 | u32 qmi_max_num_of_tnums; |
---|
524 | u32 qmi_def_tnums_thresh; |
---|
525 | /* BMI */ |
---|
526 | u32 bmi_max_num_of_tasks; |
---|
527 | u32 bmi_max_fifo_size; |
---|
528 | /* General */ |
---|
529 | u32 fm_port_num_of_cg; |
---|
530 | u32 num_of_rx_ports; |
---|
531 | u32 total_fifo_size; |
---|
532 | |
---|
533 | u32 qman_channel_base; |
---|
534 | u32 num_of_qman_channels; |
---|
535 | |
---|
536 | struct resource *res; |
---|
537 | }; |
---|
538 | |
---|
539 | /* Structure that holds FMan initial configuration */ |
---|
540 | struct fman_cfg { |
---|
541 | u8 disp_limit_tsh; |
---|
542 | u8 prs_disp_tsh; |
---|
543 | u8 plcr_disp_tsh; |
---|
544 | u8 kg_disp_tsh; |
---|
545 | u8 bmi_disp_tsh; |
---|
546 | u8 qmi_enq_disp_tsh; |
---|
547 | u8 qmi_deq_disp_tsh; |
---|
548 | u8 fm_ctl1_disp_tsh; |
---|
549 | u8 fm_ctl2_disp_tsh; |
---|
550 | int dma_cache_override; |
---|
551 | enum fman_dma_aid_mode dma_aid_mode; |
---|
552 | u32 dma_axi_dbg_num_of_beats; |
---|
553 | u32 dma_cam_num_of_entries; |
---|
554 | u32 dma_watchdog; |
---|
555 | u8 dma_comm_qtsh_asrt_emer; |
---|
556 | u32 dma_write_buf_tsh_asrt_emer; |
---|
557 | u32 dma_read_buf_tsh_asrt_emer; |
---|
558 | u8 dma_comm_qtsh_clr_emer; |
---|
559 | u32 dma_write_buf_tsh_clr_emer; |
---|
560 | u32 dma_read_buf_tsh_clr_emer; |
---|
561 | u32 dma_sos_emergency; |
---|
562 | int dma_dbg_cnt_mode; |
---|
563 | int catastrophic_err; |
---|
564 | int dma_err; |
---|
565 | u32 exceptions; |
---|
566 | u16 clk_freq; |
---|
567 | u32 cam_base_addr; |
---|
568 | u32 fifo_base_addr; |
---|
569 | u32 total_fifo_size; |
---|
570 | u32 total_num_of_tasks; |
---|
571 | u32 qmi_def_tnums_thresh; |
---|
572 | }; |
---|
573 | |
---|
574 | /* Structure that holds information received from device tree */ |
---|
575 | struct fman_dts_params { |
---|
576 | void __iomem *base_addr; /* FMan virtual address */ |
---|
577 | #ifndef __rtems__ |
---|
578 | struct resource *res; /* FMan memory resource */ |
---|
579 | #endif /* __rtems__ */ |
---|
580 | u8 id; /* FMan ID */ |
---|
581 | |
---|
582 | int err_irq; /* FMan Error IRQ */ |
---|
583 | |
---|
584 | u16 clk_freq; /* FMan clock freq (In Mhz) */ |
---|
585 | |
---|
586 | u32 qman_channel_base; /* QMan channels base */ |
---|
587 | u32 num_of_qman_channels; /* Number of QMan channels */ |
---|
588 | |
---|
589 | struct resource muram_res; /* MURAM resource */ |
---|
590 | }; |
---|
591 | |
---|
592 | /** fman_exceptions_cb |
---|
593 | * fman - Pointer to FMan |
---|
594 | * exception - The exception. |
---|
595 | * |
---|
596 | * Exceptions user callback routine, will be called upon an exception |
---|
597 | * passing the exception identification. |
---|
598 | * |
---|
599 | * Return: irq status |
---|
600 | */ |
---|
601 | typedef irqreturn_t (fman_exceptions_cb)(struct fman *fman, |
---|
602 | enum fman_exceptions exception); |
---|
603 | |
---|
604 | /** fman_bus_error_cb |
---|
605 | * fman - Pointer to FMan |
---|
606 | * port_id - Port id |
---|
607 | * addr - Address that caused the error |
---|
608 | * tnum - Owner of error |
---|
609 | * liodn - Logical IO device number |
---|
610 | * |
---|
611 | * Bus error user callback routine, will be called upon bus error, |
---|
612 | * passing parameters describing the errors and the owner. |
---|
613 | * |
---|
614 | * Return: IRQ status |
---|
615 | */ |
---|
616 | typedef irqreturn_t (fman_bus_error_cb)(struct fman *fman, u8 port_id, |
---|
617 | u64 addr, u8 tnum, u16 liodn); |
---|
618 | |
---|
619 | struct fman { |
---|
620 | struct device *dev; |
---|
621 | void __iomem *base_addr; |
---|
622 | struct fman_intr_src intr_mng[FMAN_EV_CNT]; |
---|
623 | |
---|
624 | struct fman_fpm_regs __iomem *fpm_regs; |
---|
625 | struct fman_bmi_regs __iomem *bmi_regs; |
---|
626 | struct fman_qmi_regs __iomem *qmi_regs; |
---|
627 | struct fman_dma_regs __iomem *dma_regs; |
---|
628 | struct fman_hwp_regs __iomem *hwp_regs; |
---|
629 | fman_exceptions_cb *exception_cb; |
---|
630 | fman_bus_error_cb *bus_error_cb; |
---|
631 | /* Spinlock for FMan use */ |
---|
632 | spinlock_t spinlock; |
---|
633 | struct fman_state_struct *state; |
---|
634 | |
---|
635 | struct fman_cfg *cfg; |
---|
636 | struct muram_info *muram; |
---|
637 | /* cam section in muram */ |
---|
638 | unsigned long cam_offset; |
---|
639 | size_t cam_size; |
---|
640 | /* Fifo in MURAM */ |
---|
641 | unsigned long fifo_offset; |
---|
642 | size_t fifo_size; |
---|
643 | |
---|
644 | u32 liodn_base[64]; |
---|
645 | u32 liodn_offset[64]; |
---|
646 | |
---|
647 | struct fman_dts_params dts_params; |
---|
648 | }; |
---|
649 | |
---|
650 | static irqreturn_t fman_exceptions(struct fman *fman, |
---|
651 | enum fman_exceptions exception) |
---|
652 | { |
---|
653 | dev_dbg(fman->dev, "%s: FMan[%d] exception %d\n", |
---|
654 | __func__, fman->state->fm_id, exception); |
---|
655 | |
---|
656 | return IRQ_HANDLED; |
---|
657 | } |
---|
658 | |
---|
659 | static irqreturn_t fman_bus_error(struct fman *fman, u8 __maybe_unused port_id, |
---|
660 | u64 __maybe_unused addr, |
---|
661 | u8 __maybe_unused tnum, |
---|
662 | u16 __maybe_unused liodn) |
---|
663 | { |
---|
664 | dev_dbg(fman->dev, "%s: FMan[%d] bus error: port_id[%d]\n", |
---|
665 | __func__, fman->state->fm_id, port_id); |
---|
666 | |
---|
667 | return IRQ_HANDLED; |
---|
668 | } |
---|
669 | |
---|
670 | static inline irqreturn_t call_mac_isr(struct fman *fman, u8 id) |
---|
671 | { |
---|
672 | if (fman->intr_mng[id].isr_cb) { |
---|
673 | fman->intr_mng[id].isr_cb(fman->intr_mng[id].src_handle); |
---|
674 | |
---|
675 | return IRQ_HANDLED; |
---|
676 | } |
---|
677 | |
---|
678 | return IRQ_NONE; |
---|
679 | } |
---|
680 | |
---|
681 | static inline u8 hw_port_id_to_sw_port_id(u8 major, u8 hw_port_id) |
---|
682 | { |
---|
683 | u8 sw_port_id = 0; |
---|
684 | |
---|
685 | if (hw_port_id >= BASE_TX_PORTID) |
---|
686 | sw_port_id = hw_port_id - BASE_TX_PORTID; |
---|
687 | else if (hw_port_id >= BASE_RX_PORTID) |
---|
688 | sw_port_id = hw_port_id - BASE_RX_PORTID; |
---|
689 | else |
---|
690 | sw_port_id = 0; |
---|
691 | |
---|
692 | return sw_port_id; |
---|
693 | } |
---|
694 | |
---|
695 | static void set_port_order_restoration(struct fman_fpm_regs __iomem *fpm_rg, |
---|
696 | u8 port_id) |
---|
697 | { |
---|
698 | u32 tmp = 0; |
---|
699 | |
---|
700 | tmp = port_id << FPM_PORT_FM_CTL_PORTID_SHIFT; |
---|
701 | |
---|
702 | tmp |= FPM_PRT_FM_CTL2 | FPM_PRT_FM_CTL1; |
---|
703 | |
---|
704 | /* order restoration */ |
---|
705 | if (port_id % 2) |
---|
706 | tmp |= FPM_PRT_FM_CTL1 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT; |
---|
707 | else |
---|
708 | tmp |= FPM_PRT_FM_CTL2 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT; |
---|
709 | |
---|
710 | iowrite32be(tmp, &fpm_rg->fmfp_prc); |
---|
711 | } |
---|
712 | |
---|
713 | static void set_port_liodn(struct fman *fman, u8 port_id, |
---|
714 | u32 liodn_base, u32 liodn_ofst) |
---|
715 | { |
---|
716 | u32 tmp; |
---|
717 | |
---|
718 | /* set LIODN base for this port */ |
---|
719 | tmp = ioread32be(&fman->dma_regs->fmdmplr[port_id / 2]); |
---|
720 | if (port_id % 2) { |
---|
721 | tmp &= ~DMA_LIODN_BASE_MASK; |
---|
722 | tmp |= liodn_base; |
---|
723 | } else { |
---|
724 | tmp &= ~(DMA_LIODN_BASE_MASK << DMA_LIODN_SHIFT); |
---|
725 | tmp |= liodn_base << DMA_LIODN_SHIFT; |
---|
726 | } |
---|
727 | iowrite32be(tmp, &fman->dma_regs->fmdmplr[port_id / 2]); |
---|
728 | iowrite32be(liodn_ofst, &fman->bmi_regs->fmbm_spliodn[port_id - 1]); |
---|
729 | } |
---|
730 | |
---|
731 | static void enable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg) |
---|
732 | { |
---|
733 | u32 tmp; |
---|
734 | |
---|
735 | tmp = ioread32be(&fpm_rg->fm_rcr); |
---|
736 | if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL) |
---|
737 | iowrite32be(tmp | FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr); |
---|
738 | else |
---|
739 | iowrite32be(tmp | FPM_RAM_RAMS_ECC_EN | |
---|
740 | FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr); |
---|
741 | } |
---|
742 | |
---|
743 | static void disable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg) |
---|
744 | { |
---|
745 | u32 tmp; |
---|
746 | |
---|
747 | tmp = ioread32be(&fpm_rg->fm_rcr); |
---|
748 | if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL) |
---|
749 | iowrite32be(tmp & ~FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr); |
---|
750 | else |
---|
751 | iowrite32be(tmp & ~(FPM_RAM_RAMS_ECC_EN | FPM_RAM_IRAM_ECC_EN), |
---|
752 | &fpm_rg->fm_rcr); |
---|
753 | } |
---|
754 | |
---|
755 | static void fman_defconfig(struct fman_cfg *cfg) |
---|
756 | { |
---|
757 | memset(cfg, 0, sizeof(struct fman_cfg)); |
---|
758 | |
---|
759 | cfg->catastrophic_err = DEFAULT_CATASTROPHIC_ERR; |
---|
760 | cfg->dma_err = DEFAULT_DMA_ERR; |
---|
761 | cfg->dma_aid_mode = DEFAULT_AID_MODE; |
---|
762 | cfg->dma_comm_qtsh_clr_emer = DEFAULT_DMA_COMM_Q_LOW; |
---|
763 | cfg->dma_comm_qtsh_asrt_emer = DEFAULT_DMA_COMM_Q_HIGH; |
---|
764 | cfg->dma_cache_override = DEFAULT_CACHE_OVERRIDE; |
---|
765 | cfg->dma_cam_num_of_entries = DEFAULT_DMA_CAM_NUM_OF_ENTRIES; |
---|
766 | cfg->dma_dbg_cnt_mode = DEFAULT_DMA_DBG_CNT_MODE; |
---|
767 | cfg->dma_sos_emergency = DEFAULT_DMA_SOS_EMERGENCY; |
---|
768 | cfg->dma_watchdog = DEFAULT_DMA_WATCHDOG; |
---|
769 | cfg->disp_limit_tsh = DEFAULT_DISP_LIMIT; |
---|
770 | cfg->prs_disp_tsh = DEFAULT_PRS_DISP_TH; |
---|
771 | cfg->plcr_disp_tsh = DEFAULT_PLCR_DISP_TH; |
---|
772 | cfg->kg_disp_tsh = DEFAULT_KG_DISP_TH; |
---|
773 | cfg->bmi_disp_tsh = DEFAULT_BMI_DISP_TH; |
---|
774 | cfg->qmi_enq_disp_tsh = DEFAULT_QMI_ENQ_DISP_TH; |
---|
775 | cfg->qmi_deq_disp_tsh = DEFAULT_QMI_DEQ_DISP_TH; |
---|
776 | cfg->fm_ctl1_disp_tsh = DEFAULT_FM_CTL1_DISP_TH; |
---|
777 | cfg->fm_ctl2_disp_tsh = DEFAULT_FM_CTL2_DISP_TH; |
---|
778 | } |
---|
779 | |
---|
780 | static int dma_init(struct fman *fman) |
---|
781 | { |
---|
782 | struct fman_dma_regs __iomem *dma_rg = fman->dma_regs; |
---|
783 | struct fman_cfg *cfg = fman->cfg; |
---|
784 | u32 tmp_reg; |
---|
785 | |
---|
786 | /* Init DMA Registers */ |
---|
787 | |
---|
788 | /* clear status reg events */ |
---|
789 | tmp_reg = (DMA_STATUS_BUS_ERR | DMA_STATUS_READ_ECC | |
---|
790 | DMA_STATUS_SYSTEM_WRITE_ECC | DMA_STATUS_FM_WRITE_ECC); |
---|
791 | iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg, &dma_rg->fmdmsr); |
---|
792 | |
---|
793 | /* configure mode register */ |
---|
794 | tmp_reg = 0; |
---|
795 | tmp_reg |= cfg->dma_cache_override << DMA_MODE_CACHE_OR_SHIFT; |
---|
796 | if (cfg->exceptions & EX_DMA_BUS_ERROR) |
---|
797 | tmp_reg |= DMA_MODE_BER; |
---|
798 | if ((cfg->exceptions & EX_DMA_SYSTEM_WRITE_ECC) | |
---|
799 | (cfg->exceptions & EX_DMA_READ_ECC) | |
---|
800 | (cfg->exceptions & EX_DMA_FM_WRITE_ECC)) |
---|
801 | tmp_reg |= DMA_MODE_ECC; |
---|
802 | if (cfg->dma_axi_dbg_num_of_beats) |
---|
803 | tmp_reg |= (DMA_MODE_AXI_DBG_MASK & |
---|
804 | ((cfg->dma_axi_dbg_num_of_beats - 1) |
---|
805 | << DMA_MODE_AXI_DBG_SHIFT)); |
---|
806 | |
---|
807 | tmp_reg |= (((cfg->dma_cam_num_of_entries / DMA_CAM_UNITS) - 1) & |
---|
808 | DMA_MODE_CEN_MASK) << DMA_MODE_CEN_SHIFT; |
---|
809 | tmp_reg |= DMA_MODE_SECURE_PROT; |
---|
810 | tmp_reg |= cfg->dma_dbg_cnt_mode << DMA_MODE_DBG_SHIFT; |
---|
811 | tmp_reg |= cfg->dma_aid_mode << DMA_MODE_AID_MODE_SHIFT; |
---|
812 | |
---|
813 | iowrite32be(tmp_reg, &dma_rg->fmdmmr); |
---|
814 | |
---|
815 | /* configure thresholds register */ |
---|
816 | tmp_reg = ((u32)cfg->dma_comm_qtsh_asrt_emer << |
---|
817 | DMA_THRESH_COMMQ_SHIFT); |
---|
818 | tmp_reg |= (cfg->dma_read_buf_tsh_asrt_emer & |
---|
819 | DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT; |
---|
820 | tmp_reg |= cfg->dma_write_buf_tsh_asrt_emer & |
---|
821 | DMA_THRESH_WRITE_INT_BUF_MASK; |
---|
822 | |
---|
823 | iowrite32be(tmp_reg, &dma_rg->fmdmtr); |
---|
824 | |
---|
825 | /* configure hysteresis register */ |
---|
826 | tmp_reg = ((u32)cfg->dma_comm_qtsh_clr_emer << |
---|
827 | DMA_THRESH_COMMQ_SHIFT); |
---|
828 | tmp_reg |= (cfg->dma_read_buf_tsh_clr_emer & |
---|
829 | DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT; |
---|
830 | tmp_reg |= cfg->dma_write_buf_tsh_clr_emer & |
---|
831 | DMA_THRESH_WRITE_INT_BUF_MASK; |
---|
832 | |
---|
833 | iowrite32be(tmp_reg, &dma_rg->fmdmhy); |
---|
834 | |
---|
835 | /* configure emergency threshold */ |
---|
836 | iowrite32be(cfg->dma_sos_emergency, &dma_rg->fmdmsetr); |
---|
837 | |
---|
838 | /* configure Watchdog */ |
---|
839 | iowrite32be((cfg->dma_watchdog * cfg->clk_freq), &dma_rg->fmdmwcr); |
---|
840 | |
---|
841 | iowrite32be(cfg->cam_base_addr, &dma_rg->fmdmebcr); |
---|
842 | |
---|
843 | /* Allocate MURAM for CAM */ |
---|
844 | fman->cam_size = |
---|
845 | (u32)(fman->cfg->dma_cam_num_of_entries * DMA_CAM_SIZEOF_ENTRY); |
---|
846 | fman->cam_offset = fman_muram_alloc(fman->muram, fman->cam_size); |
---|
847 | if (IS_ERR_VALUE(fman->cam_offset)) { |
---|
848 | dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n", |
---|
849 | __func__); |
---|
850 | return -ENOMEM; |
---|
851 | } |
---|
852 | |
---|
853 | if (fman->state->rev_info.major == 2) { |
---|
854 | u32 __iomem *cam_base_addr; |
---|
855 | |
---|
856 | fman_muram_free_mem(fman->muram, fman->cam_offset, |
---|
857 | fman->cam_size); |
---|
858 | |
---|
859 | fman->cam_size = fman->cfg->dma_cam_num_of_entries * 72 + 128; |
---|
860 | fman->cam_offset = fman_muram_alloc(fman->muram, |
---|
861 | fman->cam_size); |
---|
862 | if (IS_ERR_VALUE(fman->cam_offset)) { |
---|
863 | dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n", |
---|
864 | __func__); |
---|
865 | return -ENOMEM; |
---|
866 | } |
---|
867 | |
---|
868 | if (fman->cfg->dma_cam_num_of_entries % 8 || |
---|
869 | fman->cfg->dma_cam_num_of_entries > 32) { |
---|
870 | dev_err(fman->dev, "%s: wrong dma_cam_num_of_entries\n", |
---|
871 | __func__); |
---|
872 | return -EINVAL; |
---|
873 | } |
---|
874 | |
---|
875 | cam_base_addr = (u32 __iomem *) |
---|
876 | fman_muram_offset_to_vbase(fman->muram, |
---|
877 | fman->cam_offset); |
---|
878 | iowrite32be(~((1 << |
---|
879 | (32 - fman->cfg->dma_cam_num_of_entries)) - 1), |
---|
880 | cam_base_addr); |
---|
881 | } |
---|
882 | |
---|
883 | fman->cfg->cam_base_addr = fman->cam_offset; |
---|
884 | |
---|
885 | return 0; |
---|
886 | } |
---|
887 | |
---|
888 | static void fpm_init(struct fman_fpm_regs __iomem *fpm_rg, struct fman_cfg *cfg) |
---|
889 | { |
---|
890 | u32 tmp_reg; |
---|
891 | int i; |
---|
892 | |
---|
893 | /* Init FPM Registers */ |
---|
894 | |
---|
895 | tmp_reg = (u32)(cfg->disp_limit_tsh << FPM_DISP_LIMIT_SHIFT); |
---|
896 | iowrite32be(tmp_reg, &fpm_rg->fmfp_mxd); |
---|
897 | |
---|
898 | tmp_reg = (((u32)cfg->prs_disp_tsh << FPM_THR1_PRS_SHIFT) | |
---|
899 | ((u32)cfg->kg_disp_tsh << FPM_THR1_KG_SHIFT) | |
---|
900 | ((u32)cfg->plcr_disp_tsh << FPM_THR1_PLCR_SHIFT) | |
---|
901 | ((u32)cfg->bmi_disp_tsh << FPM_THR1_BMI_SHIFT)); |
---|
902 | iowrite32be(tmp_reg, &fpm_rg->fmfp_dist1); |
---|
903 | |
---|
904 | tmp_reg = |
---|
905 | (((u32)cfg->qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) | |
---|
906 | ((u32)cfg->qmi_deq_disp_tsh << FPM_THR2_QMI_DEQ_SHIFT) | |
---|
907 | ((u32)cfg->fm_ctl1_disp_tsh << FPM_THR2_FM_CTL1_SHIFT) | |
---|
908 | ((u32)cfg->fm_ctl2_disp_tsh << FPM_THR2_FM_CTL2_SHIFT)); |
---|
909 | iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2); |
---|
910 | |
---|
911 | /* define exceptions and error behavior */ |
---|
912 | tmp_reg = 0; |
---|
913 | /* Clear events */ |
---|
914 | tmp_reg |= (FPM_EV_MASK_STALL | FPM_EV_MASK_DOUBLE_ECC | |
---|
915 | FPM_EV_MASK_SINGLE_ECC); |
---|
916 | /* enable interrupts */ |
---|
917 | if (cfg->exceptions & EX_FPM_STALL_ON_TASKS) |
---|
918 | tmp_reg |= FPM_EV_MASK_STALL_EN; |
---|
919 | if (cfg->exceptions & EX_FPM_SINGLE_ECC) |
---|
920 | tmp_reg |= FPM_EV_MASK_SINGLE_ECC_EN; |
---|
921 | if (cfg->exceptions & EX_FPM_DOUBLE_ECC) |
---|
922 | tmp_reg |= FPM_EV_MASK_DOUBLE_ECC_EN; |
---|
923 | tmp_reg |= (cfg->catastrophic_err << FPM_EV_MASK_CAT_ERR_SHIFT); |
---|
924 | tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT); |
---|
925 | /* FMan is not halted upon external halt activation */ |
---|
926 | tmp_reg |= FPM_EV_MASK_EXTERNAL_HALT; |
---|
927 | /* Man is not halted upon Unrecoverable ECC error behavior */ |
---|
928 | tmp_reg |= FPM_EV_MASK_ECC_ERR_HALT; |
---|
929 | iowrite32be(tmp_reg, &fpm_rg->fmfp_ee); |
---|
930 | |
---|
931 | /* clear all fmCtls event registers */ |
---|
932 | for (i = 0; i < FM_NUM_OF_FMAN_CTRL_EVENT_REGS; i++) |
---|
933 | iowrite32be(0xFFFFFFFF, &fpm_rg->fmfp_cev[i]); |
---|
934 | |
---|
935 | /* RAM ECC - enable and clear events */ |
---|
936 | /* first we need to clear all parser memory, |
---|
937 | * as it is uninitialized and may cause ECC errors |
---|
938 | */ |
---|
939 | /* event bits */ |
---|
940 | tmp_reg = (FPM_RAM_MURAM_ECC | FPM_RAM_IRAM_ECC); |
---|
941 | |
---|
942 | iowrite32be(tmp_reg, &fpm_rg->fm_rcr); |
---|
943 | |
---|
944 | tmp_reg = 0; |
---|
945 | if (cfg->exceptions & EX_IRAM_ECC) { |
---|
946 | tmp_reg |= FPM_IRAM_ECC_ERR_EX_EN; |
---|
947 | enable_rams_ecc(fpm_rg); |
---|
948 | } |
---|
949 | if (cfg->exceptions & EX_MURAM_ECC) { |
---|
950 | tmp_reg |= FPM_MURAM_ECC_ERR_EX_EN; |
---|
951 | enable_rams_ecc(fpm_rg); |
---|
952 | } |
---|
953 | iowrite32be(tmp_reg, &fpm_rg->fm_rie); |
---|
954 | } |
---|
955 | |
---|
956 | static void bmi_init(struct fman_bmi_regs __iomem *bmi_rg, |
---|
957 | struct fman_cfg *cfg) |
---|
958 | { |
---|
959 | u32 tmp_reg; |
---|
960 | |
---|
961 | /* Init BMI Registers */ |
---|
962 | |
---|
963 | /* define common resources */ |
---|
964 | tmp_reg = cfg->fifo_base_addr; |
---|
965 | tmp_reg = tmp_reg / BMI_FIFO_ALIGN; |
---|
966 | |
---|
967 | tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) << |
---|
968 | BMI_CFG1_FIFO_SIZE_SHIFT); |
---|
969 | iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1); |
---|
970 | |
---|
971 | tmp_reg = ((cfg->total_num_of_tasks - 1) & BMI_CFG2_TASKS_MASK) << |
---|
972 | BMI_CFG2_TASKS_SHIFT; |
---|
973 | /* num of DMA's will be dynamically updated when each port is set */ |
---|
974 | iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2); |
---|
975 | |
---|
976 | /* define unmaskable exceptions, enable and clear events */ |
---|
977 | tmp_reg = 0; |
---|
978 | iowrite32be(BMI_ERR_INTR_EN_LIST_RAM_ECC | |
---|
979 | BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC | |
---|
980 | BMI_ERR_INTR_EN_STATISTICS_RAM_ECC | |
---|
981 | BMI_ERR_INTR_EN_DISPATCH_RAM_ECC, &bmi_rg->fmbm_ievr); |
---|
982 | |
---|
983 | if (cfg->exceptions & EX_BMI_LIST_RAM_ECC) |
---|
984 | tmp_reg |= BMI_ERR_INTR_EN_LIST_RAM_ECC; |
---|
985 | if (cfg->exceptions & EX_BMI_STORAGE_PROFILE_ECC) |
---|
986 | tmp_reg |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC; |
---|
987 | if (cfg->exceptions & EX_BMI_STATISTICS_RAM_ECC) |
---|
988 | tmp_reg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC; |
---|
989 | if (cfg->exceptions & EX_BMI_DISPATCH_RAM_ECC) |
---|
990 | tmp_reg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC; |
---|
991 | iowrite32be(tmp_reg, &bmi_rg->fmbm_ier); |
---|
992 | } |
---|
993 | |
---|
994 | static void qmi_init(struct fman_qmi_regs __iomem *qmi_rg, |
---|
995 | struct fman_cfg *cfg) |
---|
996 | { |
---|
997 | u32 tmp_reg; |
---|
998 | |
---|
999 | /* Init QMI Registers */ |
---|
1000 | |
---|
1001 | /* Clear error interrupt events */ |
---|
1002 | |
---|
1003 | iowrite32be(QMI_ERR_INTR_EN_DOUBLE_ECC | QMI_ERR_INTR_EN_DEQ_FROM_DEF, |
---|
1004 | &qmi_rg->fmqm_eie); |
---|
1005 | tmp_reg = 0; |
---|
1006 | if (cfg->exceptions & EX_QMI_DEQ_FROM_UNKNOWN_PORTID) |
---|
1007 | tmp_reg |= QMI_ERR_INTR_EN_DEQ_FROM_DEF; |
---|
1008 | if (cfg->exceptions & EX_QMI_DOUBLE_ECC) |
---|
1009 | tmp_reg |= QMI_ERR_INTR_EN_DOUBLE_ECC; |
---|
1010 | /* enable events */ |
---|
1011 | iowrite32be(tmp_reg, &qmi_rg->fmqm_eien); |
---|
1012 | |
---|
1013 | tmp_reg = 0; |
---|
1014 | /* Clear interrupt events */ |
---|
1015 | iowrite32be(QMI_INTR_EN_SINGLE_ECC, &qmi_rg->fmqm_ie); |
---|
1016 | if (cfg->exceptions & EX_QMI_SINGLE_ECC) |
---|
1017 | tmp_reg |= QMI_INTR_EN_SINGLE_ECC; |
---|
1018 | /* enable events */ |
---|
1019 | iowrite32be(tmp_reg, &qmi_rg->fmqm_ien); |
---|
1020 | } |
---|
1021 | |
---|
1022 | static void hwp_init(struct fman_hwp_regs __iomem *hwp_rg) |
---|
1023 | { |
---|
1024 | /* enable HW Parser */ |
---|
1025 | iowrite32be(HWP_RPIMAC_PEN, &hwp_rg->fmprrpimac); |
---|
1026 | } |
---|
1027 | |
---|
1028 | static int enable(struct fman *fman, struct fman_cfg *cfg) |
---|
1029 | { |
---|
1030 | u32 cfg_reg = 0; |
---|
1031 | |
---|
1032 | /* Enable all modules */ |
---|
1033 | |
---|
1034 | /* clear&enable global counters - calculate reg and save for later, |
---|
1035 | * because it's the same reg for QMI enable |
---|
1036 | */ |
---|
1037 | cfg_reg = QMI_CFG_EN_COUNTERS; |
---|
1038 | |
---|
1039 | /* Set enqueue and dequeue thresholds */ |
---|
1040 | cfg_reg |= (cfg->qmi_def_tnums_thresh << 8) | cfg->qmi_def_tnums_thresh; |
---|
1041 | |
---|
1042 | iowrite32be(BMI_INIT_START, &fman->bmi_regs->fmbm_init); |
---|
1043 | iowrite32be(cfg_reg | QMI_CFG_ENQ_EN | QMI_CFG_DEQ_EN, |
---|
1044 | &fman->qmi_regs->fmqm_gc); |
---|
1045 | |
---|
1046 | return 0; |
---|
1047 | } |
---|
1048 | |
---|
1049 | static int set_exception(struct fman *fman, |
---|
1050 | enum fman_exceptions exception, bool enable) |
---|
1051 | { |
---|
1052 | u32 tmp; |
---|
1053 | |
---|
1054 | switch (exception) { |
---|
1055 | case FMAN_EX_DMA_BUS_ERROR: |
---|
1056 | tmp = ioread32be(&fman->dma_regs->fmdmmr); |
---|
1057 | if (enable) |
---|
1058 | tmp |= DMA_MODE_BER; |
---|
1059 | else |
---|
1060 | tmp &= ~DMA_MODE_BER; |
---|
1061 | /* disable bus error */ |
---|
1062 | iowrite32be(tmp, &fman->dma_regs->fmdmmr); |
---|
1063 | break; |
---|
1064 | case FMAN_EX_DMA_READ_ECC: |
---|
1065 | case FMAN_EX_DMA_SYSTEM_WRITE_ECC: |
---|
1066 | case FMAN_EX_DMA_FM_WRITE_ECC: |
---|
1067 | tmp = ioread32be(&fman->dma_regs->fmdmmr); |
---|
1068 | if (enable) |
---|
1069 | tmp |= DMA_MODE_ECC; |
---|
1070 | else |
---|
1071 | tmp &= ~DMA_MODE_ECC; |
---|
1072 | iowrite32be(tmp, &fman->dma_regs->fmdmmr); |
---|
1073 | break; |
---|
1074 | case FMAN_EX_FPM_STALL_ON_TASKS: |
---|
1075 | tmp = ioread32be(&fman->fpm_regs->fmfp_ee); |
---|
1076 | if (enable) |
---|
1077 | tmp |= FPM_EV_MASK_STALL_EN; |
---|
1078 | else |
---|
1079 | tmp &= ~FPM_EV_MASK_STALL_EN; |
---|
1080 | iowrite32be(tmp, &fman->fpm_regs->fmfp_ee); |
---|
1081 | break; |
---|
1082 | case FMAN_EX_FPM_SINGLE_ECC: |
---|
1083 | tmp = ioread32be(&fman->fpm_regs->fmfp_ee); |
---|
1084 | if (enable) |
---|
1085 | tmp |= FPM_EV_MASK_SINGLE_ECC_EN; |
---|
1086 | else |
---|
1087 | tmp &= ~FPM_EV_MASK_SINGLE_ECC_EN; |
---|
1088 | iowrite32be(tmp, &fman->fpm_regs->fmfp_ee); |
---|
1089 | break; |
---|
1090 | case FMAN_EX_FPM_DOUBLE_ECC: |
---|
1091 | tmp = ioread32be(&fman->fpm_regs->fmfp_ee); |
---|
1092 | if (enable) |
---|
1093 | tmp |= FPM_EV_MASK_DOUBLE_ECC_EN; |
---|
1094 | else |
---|
1095 | tmp &= ~FPM_EV_MASK_DOUBLE_ECC_EN; |
---|
1096 | iowrite32be(tmp, &fman->fpm_regs->fmfp_ee); |
---|
1097 | break; |
---|
1098 | case FMAN_EX_QMI_SINGLE_ECC: |
---|
1099 | tmp = ioread32be(&fman->qmi_regs->fmqm_ien); |
---|
1100 | if (enable) |
---|
1101 | tmp |= QMI_INTR_EN_SINGLE_ECC; |
---|
1102 | else |
---|
1103 | tmp &= ~QMI_INTR_EN_SINGLE_ECC; |
---|
1104 | iowrite32be(tmp, &fman->qmi_regs->fmqm_ien); |
---|
1105 | break; |
---|
1106 | case FMAN_EX_QMI_DOUBLE_ECC: |
---|
1107 | tmp = ioread32be(&fman->qmi_regs->fmqm_eien); |
---|
1108 | if (enable) |
---|
1109 | tmp |= QMI_ERR_INTR_EN_DOUBLE_ECC; |
---|
1110 | else |
---|
1111 | tmp &= ~QMI_ERR_INTR_EN_DOUBLE_ECC; |
---|
1112 | iowrite32be(tmp, &fman->qmi_regs->fmqm_eien); |
---|
1113 | break; |
---|
1114 | case FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: |
---|
1115 | tmp = ioread32be(&fman->qmi_regs->fmqm_eien); |
---|
1116 | if (enable) |
---|
1117 | tmp |= QMI_ERR_INTR_EN_DEQ_FROM_DEF; |
---|
1118 | else |
---|
1119 | tmp &= ~QMI_ERR_INTR_EN_DEQ_FROM_DEF; |
---|
1120 | iowrite32be(tmp, &fman->qmi_regs->fmqm_eien); |
---|
1121 | break; |
---|
1122 | case FMAN_EX_BMI_LIST_RAM_ECC: |
---|
1123 | tmp = ioread32be(&fman->bmi_regs->fmbm_ier); |
---|
1124 | if (enable) |
---|
1125 | tmp |= BMI_ERR_INTR_EN_LIST_RAM_ECC; |
---|
1126 | else |
---|
1127 | tmp &= ~BMI_ERR_INTR_EN_LIST_RAM_ECC; |
---|
1128 | iowrite32be(tmp, &fman->bmi_regs->fmbm_ier); |
---|
1129 | break; |
---|
1130 | case FMAN_EX_BMI_STORAGE_PROFILE_ECC: |
---|
1131 | tmp = ioread32be(&fman->bmi_regs->fmbm_ier); |
---|
1132 | if (enable) |
---|
1133 | tmp |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC; |
---|
1134 | else |
---|
1135 | tmp &= ~BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC; |
---|
1136 | iowrite32be(tmp, &fman->bmi_regs->fmbm_ier); |
---|
1137 | break; |
---|
1138 | case FMAN_EX_BMI_STATISTICS_RAM_ECC: |
---|
1139 | tmp = ioread32be(&fman->bmi_regs->fmbm_ier); |
---|
1140 | if (enable) |
---|
1141 | tmp |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC; |
---|
1142 | else |
---|
1143 | tmp &= ~BMI_ERR_INTR_EN_STATISTICS_RAM_ECC; |
---|
1144 | iowrite32be(tmp, &fman->bmi_regs->fmbm_ier); |
---|
1145 | break; |
---|
1146 | case FMAN_EX_BMI_DISPATCH_RAM_ECC: |
---|
1147 | tmp = ioread32be(&fman->bmi_regs->fmbm_ier); |
---|
1148 | if (enable) |
---|
1149 | tmp |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC; |
---|
1150 | else |
---|
1151 | tmp &= ~BMI_ERR_INTR_EN_DISPATCH_RAM_ECC; |
---|
1152 | iowrite32be(tmp, &fman->bmi_regs->fmbm_ier); |
---|
1153 | break; |
---|
1154 | case FMAN_EX_IRAM_ECC: |
---|
1155 | tmp = ioread32be(&fman->fpm_regs->fm_rie); |
---|
1156 | if (enable) { |
---|
1157 | /* enable ECC if not enabled */ |
---|
1158 | enable_rams_ecc(fman->fpm_regs); |
---|
1159 | /* enable ECC interrupts */ |
---|
1160 | tmp |= FPM_IRAM_ECC_ERR_EX_EN; |
---|
1161 | } else { |
---|
1162 | /* ECC mechanism may be disabled, |
---|
1163 | * depending on driver status |
---|
1164 | */ |
---|
1165 | disable_rams_ecc(fman->fpm_regs); |
---|
1166 | tmp &= ~FPM_IRAM_ECC_ERR_EX_EN; |
---|
1167 | } |
---|
1168 | iowrite32be(tmp, &fman->fpm_regs->fm_rie); |
---|
1169 | break; |
---|
1170 | case FMAN_EX_MURAM_ECC: |
---|
1171 | tmp = ioread32be(&fman->fpm_regs->fm_rie); |
---|
1172 | if (enable) { |
---|
1173 | /* enable ECC if not enabled */ |
---|
1174 | enable_rams_ecc(fman->fpm_regs); |
---|
1175 | /* enable ECC interrupts */ |
---|
1176 | tmp |= FPM_MURAM_ECC_ERR_EX_EN; |
---|
1177 | } else { |
---|
1178 | /* ECC mechanism may be disabled, |
---|
1179 | * depending on driver status |
---|
1180 | */ |
---|
1181 | disable_rams_ecc(fman->fpm_regs); |
---|
1182 | tmp &= ~FPM_MURAM_ECC_ERR_EX_EN; |
---|
1183 | } |
---|
1184 | iowrite32be(tmp, &fman->fpm_regs->fm_rie); |
---|
1185 | break; |
---|
1186 | default: |
---|
1187 | return -EINVAL; |
---|
1188 | } |
---|
1189 | return 0; |
---|
1190 | } |
---|
1191 | |
---|
1192 | static void resume(struct fman_fpm_regs __iomem *fpm_rg) |
---|
1193 | { |
---|
1194 | u32 tmp; |
---|
1195 | |
---|
1196 | tmp = ioread32be(&fpm_rg->fmfp_ee); |
---|
1197 | /* clear tmp_reg event bits in order not to clear standing events */ |
---|
1198 | tmp &= ~(FPM_EV_MASK_DOUBLE_ECC | |
---|
1199 | FPM_EV_MASK_STALL | FPM_EV_MASK_SINGLE_ECC); |
---|
1200 | tmp |= FPM_EV_MASK_RELEASE_FM; |
---|
1201 | |
---|
1202 | iowrite32be(tmp, &fpm_rg->fmfp_ee); |
---|
1203 | } |
---|
1204 | |
---|
1205 | static int fill_soc_specific_params(struct fman_state_struct *state) |
---|
1206 | { |
---|
1207 | u8 minor = state->rev_info.minor; |
---|
1208 | /* P4080 - Major 2 |
---|
1209 | * P2041/P3041/P5020/P5040 - Major 3 |
---|
1210 | * Tx/Bx - Major 6 |
---|
1211 | */ |
---|
1212 | switch (state->rev_info.major) { |
---|
1213 | case 3: |
---|
1214 | state->bmi_max_fifo_size = 160 * 1024; |
---|
1215 | state->fm_iram_size = 64 * 1024; |
---|
1216 | state->dma_thresh_max_commq = 31; |
---|
1217 | state->dma_thresh_max_buf = 127; |
---|
1218 | state->qmi_max_num_of_tnums = 64; |
---|
1219 | state->qmi_def_tnums_thresh = 48; |
---|
1220 | state->bmi_max_num_of_tasks = 128; |
---|
1221 | state->max_num_of_open_dmas = 32; |
---|
1222 | state->fm_port_num_of_cg = 256; |
---|
1223 | state->num_of_rx_ports = 6; |
---|
1224 | state->total_fifo_size = 136 * 1024; |
---|
1225 | break; |
---|
1226 | |
---|
1227 | case 2: |
---|
1228 | state->bmi_max_fifo_size = 160 * 1024; |
---|
1229 | state->fm_iram_size = 64 * 1024; |
---|
1230 | state->dma_thresh_max_commq = 31; |
---|
1231 | state->dma_thresh_max_buf = 127; |
---|
1232 | state->qmi_max_num_of_tnums = 64; |
---|
1233 | state->qmi_def_tnums_thresh = 48; |
---|
1234 | state->bmi_max_num_of_tasks = 128; |
---|
1235 | state->max_num_of_open_dmas = 32; |
---|
1236 | state->fm_port_num_of_cg = 256; |
---|
1237 | state->num_of_rx_ports = 5; |
---|
1238 | state->total_fifo_size = 100 * 1024; |
---|
1239 | break; |
---|
1240 | |
---|
1241 | case 6: |
---|
1242 | state->dma_thresh_max_commq = 83; |
---|
1243 | state->dma_thresh_max_buf = 127; |
---|
1244 | state->qmi_max_num_of_tnums = 64; |
---|
1245 | state->qmi_def_tnums_thresh = 32; |
---|
1246 | state->fm_port_num_of_cg = 256; |
---|
1247 | |
---|
1248 | /* FManV3L */ |
---|
1249 | if (minor == 1 || minor == 4) { |
---|
1250 | state->bmi_max_fifo_size = 192 * 1024; |
---|
1251 | state->bmi_max_num_of_tasks = 64; |
---|
1252 | state->max_num_of_open_dmas = 32; |
---|
1253 | state->num_of_rx_ports = 5; |
---|
1254 | if (minor == 1) |
---|
1255 | state->fm_iram_size = 32 * 1024; |
---|
1256 | else |
---|
1257 | state->fm_iram_size = 64 * 1024; |
---|
1258 | state->total_fifo_size = 156 * 1024; |
---|
1259 | } |
---|
1260 | /* FManV3H */ |
---|
1261 | else if (minor == 0 || minor == 2 || minor == 3) { |
---|
1262 | state->bmi_max_fifo_size = 384 * 1024; |
---|
1263 | state->fm_iram_size = 64 * 1024; |
---|
1264 | state->bmi_max_num_of_tasks = 128; |
---|
1265 | state->max_num_of_open_dmas = 84; |
---|
1266 | state->num_of_rx_ports = 8; |
---|
1267 | state->total_fifo_size = 295 * 1024; |
---|
1268 | } else { |
---|
1269 | pr_err("Unsupported FManv3 version\n"); |
---|
1270 | return -EINVAL; |
---|
1271 | } |
---|
1272 | |
---|
1273 | break; |
---|
1274 | default: |
---|
1275 | pr_err("Unsupported FMan version\n"); |
---|
1276 | return -EINVAL; |
---|
1277 | } |
---|
1278 | |
---|
1279 | return 0; |
---|
1280 | } |
---|
1281 | |
---|
1282 | static bool is_init_done(struct fman_cfg *cfg) |
---|
1283 | { |
---|
1284 | /* Checks if FMan driver parameters were initialized */ |
---|
1285 | if (!cfg) |
---|
1286 | return true; |
---|
1287 | |
---|
1288 | return false; |
---|
1289 | } |
---|
1290 | |
---|
1291 | static void free_init_resources(struct fman *fman) |
---|
1292 | { |
---|
1293 | if (fman->cam_offset) |
---|
1294 | fman_muram_free_mem(fman->muram, fman->cam_offset, |
---|
1295 | fman->cam_size); |
---|
1296 | if (fman->fifo_offset) |
---|
1297 | fman_muram_free_mem(fman->muram, fman->fifo_offset, |
---|
1298 | fman->fifo_size); |
---|
1299 | } |
---|
1300 | |
---|
1301 | static irqreturn_t bmi_err_event(struct fman *fman) |
---|
1302 | { |
---|
1303 | u32 event, mask, force; |
---|
1304 | struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs; |
---|
1305 | irqreturn_t ret = IRQ_NONE; |
---|
1306 | |
---|
1307 | event = ioread32be(&bmi_rg->fmbm_ievr); |
---|
1308 | mask = ioread32be(&bmi_rg->fmbm_ier); |
---|
1309 | event &= mask; |
---|
1310 | /* clear the forced events */ |
---|
1311 | force = ioread32be(&bmi_rg->fmbm_ifr); |
---|
1312 | if (force & event) |
---|
1313 | iowrite32be(force & ~event, &bmi_rg->fmbm_ifr); |
---|
1314 | /* clear the acknowledged events */ |
---|
1315 | iowrite32be(event, &bmi_rg->fmbm_ievr); |
---|
1316 | |
---|
1317 | if (event & BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC) |
---|
1318 | ret = fman->exception_cb(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC); |
---|
1319 | if (event & BMI_ERR_INTR_EN_LIST_RAM_ECC) |
---|
1320 | ret = fman->exception_cb(fman, FMAN_EX_BMI_LIST_RAM_ECC); |
---|
1321 | if (event & BMI_ERR_INTR_EN_STATISTICS_RAM_ECC) |
---|
1322 | ret = fman->exception_cb(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC); |
---|
1323 | if (event & BMI_ERR_INTR_EN_DISPATCH_RAM_ECC) |
---|
1324 | ret = fman->exception_cb(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC); |
---|
1325 | |
---|
1326 | return ret; |
---|
1327 | } |
---|
1328 | |
---|
1329 | static irqreturn_t qmi_err_event(struct fman *fman) |
---|
1330 | { |
---|
1331 | u32 event, mask, force; |
---|
1332 | struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs; |
---|
1333 | irqreturn_t ret = IRQ_NONE; |
---|
1334 | |
---|
1335 | event = ioread32be(&qmi_rg->fmqm_eie); |
---|
1336 | mask = ioread32be(&qmi_rg->fmqm_eien); |
---|
1337 | event &= mask; |
---|
1338 | |
---|
1339 | /* clear the forced events */ |
---|
1340 | force = ioread32be(&qmi_rg->fmqm_eif); |
---|
1341 | if (force & event) |
---|
1342 | iowrite32be(force & ~event, &qmi_rg->fmqm_eif); |
---|
1343 | /* clear the acknowledged events */ |
---|
1344 | iowrite32be(event, &qmi_rg->fmqm_eie); |
---|
1345 | |
---|
1346 | if (event & QMI_ERR_INTR_EN_DOUBLE_ECC) |
---|
1347 | ret = fman->exception_cb(fman, FMAN_EX_QMI_DOUBLE_ECC); |
---|
1348 | if (event & QMI_ERR_INTR_EN_DEQ_FROM_DEF) |
---|
1349 | ret = fman->exception_cb(fman, |
---|
1350 | FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID); |
---|
1351 | |
---|
1352 | return ret; |
---|
1353 | } |
---|
1354 | |
---|
1355 | static irqreturn_t dma_err_event(struct fman *fman) |
---|
1356 | { |
---|
1357 | u32 status, mask, com_id; |
---|
1358 | u8 tnum, port_id, relative_port_id; |
---|
1359 | u16 liodn; |
---|
1360 | struct fman_dma_regs __iomem *dma_rg = fman->dma_regs; |
---|
1361 | irqreturn_t ret = IRQ_NONE; |
---|
1362 | |
---|
1363 | status = ioread32be(&dma_rg->fmdmsr); |
---|
1364 | mask = ioread32be(&dma_rg->fmdmmr); |
---|
1365 | |
---|
1366 | /* clear DMA_STATUS_BUS_ERR if mask has no DMA_MODE_BER */ |
---|
1367 | if ((mask & DMA_MODE_BER) != DMA_MODE_BER) |
---|
1368 | status &= ~DMA_STATUS_BUS_ERR; |
---|
1369 | |
---|
1370 | /* clear relevant bits if mask has no DMA_MODE_ECC */ |
---|
1371 | if ((mask & DMA_MODE_ECC) != DMA_MODE_ECC) |
---|
1372 | status &= ~(DMA_STATUS_FM_SPDAT_ECC | |
---|
1373 | DMA_STATUS_READ_ECC | |
---|
1374 | DMA_STATUS_SYSTEM_WRITE_ECC | |
---|
1375 | DMA_STATUS_FM_WRITE_ECC); |
---|
1376 | |
---|
1377 | /* clear set events */ |
---|
1378 | iowrite32be(status, &dma_rg->fmdmsr); |
---|
1379 | |
---|
1380 | if (status & DMA_STATUS_BUS_ERR) { |
---|
1381 | u64 addr; |
---|
1382 | |
---|
1383 | addr = (u64)ioread32be(&dma_rg->fmdmtal); |
---|
1384 | addr |= ((u64)(ioread32be(&dma_rg->fmdmtah)) << 32); |
---|
1385 | |
---|
1386 | com_id = ioread32be(&dma_rg->fmdmtcid); |
---|
1387 | port_id = (u8)(((com_id & DMA_TRANSFER_PORTID_MASK) >> |
---|
1388 | DMA_TRANSFER_PORTID_SHIFT)); |
---|
1389 | relative_port_id = |
---|
1390 | hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id); |
---|
1391 | tnum = (u8)((com_id & DMA_TRANSFER_TNUM_MASK) >> |
---|
1392 | DMA_TRANSFER_TNUM_SHIFT); |
---|
1393 | liodn = (u16)(com_id & DMA_TRANSFER_LIODN_MASK); |
---|
1394 | ret = fman->bus_error_cb(fman, relative_port_id, addr, tnum, |
---|
1395 | liodn); |
---|
1396 | } |
---|
1397 | if (status & DMA_STATUS_FM_SPDAT_ECC) |
---|
1398 | ret = fman->exception_cb(fman, FMAN_EX_DMA_SINGLE_PORT_ECC); |
---|
1399 | if (status & DMA_STATUS_READ_ECC) |
---|
1400 | ret = fman->exception_cb(fman, FMAN_EX_DMA_READ_ECC); |
---|
1401 | if (status & DMA_STATUS_SYSTEM_WRITE_ECC) |
---|
1402 | ret = fman->exception_cb(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC); |
---|
1403 | if (status & DMA_STATUS_FM_WRITE_ECC) |
---|
1404 | ret = fman->exception_cb(fman, FMAN_EX_DMA_FM_WRITE_ECC); |
---|
1405 | |
---|
1406 | return ret; |
---|
1407 | } |
---|
1408 | |
---|
1409 | static irqreturn_t fpm_err_event(struct fman *fman) |
---|
1410 | { |
---|
1411 | u32 event; |
---|
1412 | struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs; |
---|
1413 | irqreturn_t ret = IRQ_NONE; |
---|
1414 | |
---|
1415 | event = ioread32be(&fpm_rg->fmfp_ee); |
---|
1416 | /* clear the all occurred events */ |
---|
1417 | iowrite32be(event, &fpm_rg->fmfp_ee); |
---|
1418 | |
---|
1419 | if ((event & FPM_EV_MASK_DOUBLE_ECC) && |
---|
1420 | (event & FPM_EV_MASK_DOUBLE_ECC_EN)) |
---|
1421 | ret = fman->exception_cb(fman, FMAN_EX_FPM_DOUBLE_ECC); |
---|
1422 | if ((event & FPM_EV_MASK_STALL) && (event & FPM_EV_MASK_STALL_EN)) |
---|
1423 | ret = fman->exception_cb(fman, FMAN_EX_FPM_STALL_ON_TASKS); |
---|
1424 | if ((event & FPM_EV_MASK_SINGLE_ECC) && |
---|
1425 | (event & FPM_EV_MASK_SINGLE_ECC_EN)) |
---|
1426 | ret = fman->exception_cb(fman, FMAN_EX_FPM_SINGLE_ECC); |
---|
1427 | |
---|
1428 | return ret; |
---|
1429 | } |
---|
1430 | |
---|
1431 | static irqreturn_t muram_err_intr(struct fman *fman) |
---|
1432 | { |
---|
1433 | u32 event, mask; |
---|
1434 | struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs; |
---|
1435 | irqreturn_t ret = IRQ_NONE; |
---|
1436 | |
---|
1437 | event = ioread32be(&fpm_rg->fm_rcr); |
---|
1438 | mask = ioread32be(&fpm_rg->fm_rie); |
---|
1439 | |
---|
1440 | /* clear MURAM event bit (do not clear IRAM event) */ |
---|
1441 | iowrite32be(event & ~FPM_RAM_IRAM_ECC, &fpm_rg->fm_rcr); |
---|
1442 | |
---|
1443 | if ((mask & FPM_MURAM_ECC_ERR_EX_EN) && (event & FPM_RAM_MURAM_ECC)) |
---|
1444 | ret = fman->exception_cb(fman, FMAN_EX_MURAM_ECC); |
---|
1445 | |
---|
1446 | return ret; |
---|
1447 | } |
---|
1448 | |
---|
1449 | static irqreturn_t qmi_event(struct fman *fman) |
---|
1450 | { |
---|
1451 | u32 event, mask, force; |
---|
1452 | struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs; |
---|
1453 | irqreturn_t ret = IRQ_NONE; |
---|
1454 | |
---|
1455 | event = ioread32be(&qmi_rg->fmqm_ie); |
---|
1456 | mask = ioread32be(&qmi_rg->fmqm_ien); |
---|
1457 | event &= mask; |
---|
1458 | /* clear the forced events */ |
---|
1459 | force = ioread32be(&qmi_rg->fmqm_if); |
---|
1460 | if (force & event) |
---|
1461 | iowrite32be(force & ~event, &qmi_rg->fmqm_if); |
---|
1462 | /* clear the acknowledged events */ |
---|
1463 | iowrite32be(event, &qmi_rg->fmqm_ie); |
---|
1464 | |
---|
1465 | if (event & QMI_INTR_EN_SINGLE_ECC) |
---|
1466 | ret = fman->exception_cb(fman, FMAN_EX_QMI_SINGLE_ECC); |
---|
1467 | |
---|
1468 | return ret; |
---|
1469 | } |
---|
1470 | |
---|
1471 | static void enable_time_stamp(struct fman *fman) |
---|
1472 | { |
---|
1473 | struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs; |
---|
1474 | u16 fm_clk_freq = fman->state->fm_clk_freq; |
---|
1475 | u32 tmp, intgr, ts_freq; |
---|
1476 | u64 frac; |
---|
1477 | |
---|
1478 | ts_freq = (u32)(1 << fman->state->count1_micro_bit); |
---|
1479 | /* configure timestamp so that bit 8 will count 1 microsecond |
---|
1480 | * Find effective count rate at TIMESTAMP least significant bits: |
---|
1481 | * Effective_Count_Rate = 1MHz x 2^8 = 256MHz |
---|
1482 | * Find frequency ratio between effective count rate and the clock: |
---|
1483 | * Effective_Count_Rate / CLK e.g. for 600 MHz clock: |
---|
1484 | * 256/600 = 0.4266666... |
---|
1485 | */ |
---|
1486 | |
---|
1487 | intgr = ts_freq / fm_clk_freq; |
---|
1488 | /* we multiply by 2^16 to keep the fraction of the division |
---|
1489 | * we do not div back, since we write this value as a fraction |
---|
1490 | * see spec |
---|
1491 | */ |
---|
1492 | |
---|
1493 | frac = ((ts_freq << 16) - (intgr << 16) * fm_clk_freq) / fm_clk_freq; |
---|
1494 | /* we check remainder of the division in order to round up if not int */ |
---|
1495 | if (((ts_freq << 16) - (intgr << 16) * fm_clk_freq) % fm_clk_freq) |
---|
1496 | frac++; |
---|
1497 | |
---|
1498 | tmp = (intgr << FPM_TS_INT_SHIFT) | (u16)frac; |
---|
1499 | iowrite32be(tmp, &fpm_rg->fmfp_tsc2); |
---|
1500 | |
---|
1501 | /* enable timestamp with original clock */ |
---|
1502 | iowrite32be(FPM_TS_CTL_EN, &fpm_rg->fmfp_tsc1); |
---|
1503 | fman->state->enabled_time_stamp = true; |
---|
1504 | } |
---|
1505 | |
---|
1506 | static int clear_iram(struct fman *fman) |
---|
1507 | { |
---|
1508 | struct fman_iram_regs __iomem *iram; |
---|
1509 | int i, count; |
---|
1510 | |
---|
1511 | iram = fman->base_addr + IMEM_OFFSET; |
---|
1512 | |
---|
1513 | /* Enable the auto-increment */ |
---|
1514 | iowrite32be(IRAM_IADD_AIE, &iram->iadd); |
---|
1515 | count = 100; |
---|
1516 | do { |
---|
1517 | udelay(1); |
---|
1518 | } while ((ioread32be(&iram->iadd) != IRAM_IADD_AIE) && --count); |
---|
1519 | if (count == 0) |
---|
1520 | return -EBUSY; |
---|
1521 | |
---|
1522 | for (i = 0; i < (fman->state->fm_iram_size / 4); i++) |
---|
1523 | iowrite32be(0xffffffff, &iram->idata); |
---|
1524 | |
---|
1525 | iowrite32be(fman->state->fm_iram_size - 4, &iram->iadd); |
---|
1526 | count = 100; |
---|
1527 | do { |
---|
1528 | udelay(1); |
---|
1529 | } while ((ioread32be(&iram->idata) != 0xffffffff) && --count); |
---|
1530 | if (count == 0) |
---|
1531 | return -EBUSY; |
---|
1532 | |
---|
1533 | return 0; |
---|
1534 | } |
---|
1535 | |
---|
1536 | static u32 get_exception_flag(enum fman_exceptions exception) |
---|
1537 | { |
---|
1538 | u32 bit_mask; |
---|
1539 | |
---|
1540 | switch (exception) { |
---|
1541 | case FMAN_EX_DMA_BUS_ERROR: |
---|
1542 | bit_mask = EX_DMA_BUS_ERROR; |
---|
1543 | break; |
---|
1544 | case FMAN_EX_DMA_SINGLE_PORT_ECC: |
---|
1545 | bit_mask = EX_DMA_SINGLE_PORT_ECC; |
---|
1546 | break; |
---|
1547 | case FMAN_EX_DMA_READ_ECC: |
---|
1548 | bit_mask = EX_DMA_READ_ECC; |
---|
1549 | break; |
---|
1550 | case FMAN_EX_DMA_SYSTEM_WRITE_ECC: |
---|
1551 | bit_mask = EX_DMA_SYSTEM_WRITE_ECC; |
---|
1552 | break; |
---|
1553 | case FMAN_EX_DMA_FM_WRITE_ECC: |
---|
1554 | bit_mask = EX_DMA_FM_WRITE_ECC; |
---|
1555 | break; |
---|
1556 | case FMAN_EX_FPM_STALL_ON_TASKS: |
---|
1557 | bit_mask = EX_FPM_STALL_ON_TASKS; |
---|
1558 | break; |
---|
1559 | case FMAN_EX_FPM_SINGLE_ECC: |
---|
1560 | bit_mask = EX_FPM_SINGLE_ECC; |
---|
1561 | break; |
---|
1562 | case FMAN_EX_FPM_DOUBLE_ECC: |
---|
1563 | bit_mask = EX_FPM_DOUBLE_ECC; |
---|
1564 | break; |
---|
1565 | case FMAN_EX_QMI_SINGLE_ECC: |
---|
1566 | bit_mask = EX_QMI_SINGLE_ECC; |
---|
1567 | break; |
---|
1568 | case FMAN_EX_QMI_DOUBLE_ECC: |
---|
1569 | bit_mask = EX_QMI_DOUBLE_ECC; |
---|
1570 | break; |
---|
1571 | case FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: |
---|
1572 | bit_mask = EX_QMI_DEQ_FROM_UNKNOWN_PORTID; |
---|
1573 | break; |
---|
1574 | case FMAN_EX_BMI_LIST_RAM_ECC: |
---|
1575 | bit_mask = EX_BMI_LIST_RAM_ECC; |
---|
1576 | break; |
---|
1577 | case FMAN_EX_BMI_STORAGE_PROFILE_ECC: |
---|
1578 | bit_mask = EX_BMI_STORAGE_PROFILE_ECC; |
---|
1579 | break; |
---|
1580 | case FMAN_EX_BMI_STATISTICS_RAM_ECC: |
---|
1581 | bit_mask = EX_BMI_STATISTICS_RAM_ECC; |
---|
1582 | break; |
---|
1583 | case FMAN_EX_BMI_DISPATCH_RAM_ECC: |
---|
1584 | bit_mask = EX_BMI_DISPATCH_RAM_ECC; |
---|
1585 | break; |
---|
1586 | case FMAN_EX_MURAM_ECC: |
---|
1587 | bit_mask = EX_MURAM_ECC; |
---|
1588 | break; |
---|
1589 | default: |
---|
1590 | bit_mask = 0; |
---|
1591 | break; |
---|
1592 | } |
---|
1593 | |
---|
1594 | return bit_mask; |
---|
1595 | } |
---|
1596 | |
---|
1597 | static int get_module_event(enum fman_event_modules module, u8 mod_id, |
---|
1598 | enum fman_intr_type intr_type) |
---|
1599 | { |
---|
1600 | int event; |
---|
1601 | |
---|
1602 | switch (module) { |
---|
1603 | case FMAN_MOD_MAC: |
---|
1604 | if (intr_type == FMAN_INTR_TYPE_ERR) |
---|
1605 | event = FMAN_EV_ERR_MAC0 + mod_id; |
---|
1606 | else |
---|
1607 | event = FMAN_EV_MAC0 + mod_id; |
---|
1608 | break; |
---|
1609 | case FMAN_MOD_FMAN_CTRL: |
---|
1610 | if (intr_type == FMAN_INTR_TYPE_ERR) |
---|
1611 | event = FMAN_EV_CNT; |
---|
1612 | else |
---|
1613 | event = (FMAN_EV_FMAN_CTRL_0 + mod_id); |
---|
1614 | break; |
---|
1615 | case FMAN_MOD_DUMMY_LAST: |
---|
1616 | event = FMAN_EV_CNT; |
---|
1617 | break; |
---|
1618 | default: |
---|
1619 | event = FMAN_EV_CNT; |
---|
1620 | break; |
---|
1621 | } |
---|
1622 | |
---|
1623 | return event; |
---|
1624 | } |
---|
1625 | |
---|
1626 | static int set_size_of_fifo(struct fman *fman, u8 port_id, u32 *size_of_fifo, |
---|
1627 | u32 *extra_size_of_fifo) |
---|
1628 | { |
---|
1629 | struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs; |
---|
1630 | u32 fifo = *size_of_fifo; |
---|
1631 | u32 extra_fifo = *extra_size_of_fifo; |
---|
1632 | u32 tmp; |
---|
1633 | |
---|
1634 | /* if this is the first time a port requires extra_fifo_pool_size, |
---|
1635 | * the total extra_fifo_pool_size must be initialized to 1 buffer per |
---|
1636 | * port |
---|
1637 | */ |
---|
1638 | if (extra_fifo && !fman->state->extra_fifo_pool_size) |
---|
1639 | fman->state->extra_fifo_pool_size = |
---|
1640 | fman->state->num_of_rx_ports * FMAN_BMI_FIFO_UNITS; |
---|
1641 | |
---|
1642 | fman->state->extra_fifo_pool_size = |
---|
1643 | max(fman->state->extra_fifo_pool_size, extra_fifo); |
---|
1644 | |
---|
1645 | /* check that there are enough uncommitted fifo size */ |
---|
1646 | if ((fman->state->accumulated_fifo_size + fifo) > |
---|
1647 | (fman->state->total_fifo_size - |
---|
1648 | fman->state->extra_fifo_pool_size)) { |
---|
1649 | dev_err(fman->dev, "%s: Requested fifo size and extra size exceed total FIFO size.\n", |
---|
1650 | __func__); |
---|
1651 | return -EAGAIN; |
---|
1652 | } |
---|
1653 | |
---|
1654 | /* Read, modify and write to HW */ |
---|
1655 | tmp = (fifo / FMAN_BMI_FIFO_UNITS - 1) | |
---|
1656 | ((extra_fifo / FMAN_BMI_FIFO_UNITS) << |
---|
1657 | BMI_EXTRA_FIFO_SIZE_SHIFT); |
---|
1658 | iowrite32be(tmp, &bmi_rg->fmbm_pfs[port_id - 1]); |
---|
1659 | |
---|
1660 | /* update accumulated */ |
---|
1661 | fman->state->accumulated_fifo_size += fifo; |
---|
1662 | |
---|
1663 | return 0; |
---|
1664 | } |
---|
1665 | |
---|
1666 | static int set_num_of_tasks(struct fman *fman, u8 port_id, u8 *num_of_tasks, |
---|
1667 | u8 *num_of_extra_tasks) |
---|
1668 | { |
---|
1669 | struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs; |
---|
1670 | u8 tasks = *num_of_tasks; |
---|
1671 | u8 extra_tasks = *num_of_extra_tasks; |
---|
1672 | u32 tmp; |
---|
1673 | |
---|
1674 | if (extra_tasks) |
---|
1675 | fman->state->extra_tasks_pool_size = |
---|
1676 | max(fman->state->extra_tasks_pool_size, extra_tasks); |
---|
1677 | |
---|
1678 | /* check that there are enough uncommitted tasks */ |
---|
1679 | if ((fman->state->accumulated_num_of_tasks + tasks) > |
---|
1680 | (fman->state->total_num_of_tasks - |
---|
1681 | fman->state->extra_tasks_pool_size)) { |
---|
1682 | dev_err(fman->dev, "%s: Requested num_of_tasks and extra tasks pool for fm%d exceed total num_of_tasks.\n", |
---|
1683 | __func__, fman->state->fm_id); |
---|
1684 | return -EAGAIN; |
---|
1685 | } |
---|
1686 | /* update accumulated */ |
---|
1687 | fman->state->accumulated_num_of_tasks += tasks; |
---|
1688 | |
---|
1689 | /* Write to HW */ |
---|
1690 | tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) & |
---|
1691 | ~(BMI_NUM_OF_TASKS_MASK | BMI_NUM_OF_EXTRA_TASKS_MASK); |
---|
1692 | tmp |= ((u32)((tasks - 1) << BMI_NUM_OF_TASKS_SHIFT) | |
---|
1693 | (u32)(extra_tasks << BMI_EXTRA_NUM_OF_TASKS_SHIFT)); |
---|
1694 | iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]); |
---|
1695 | |
---|
1696 | return 0; |
---|
1697 | } |
---|
1698 | |
---|
1699 | static int set_num_of_open_dmas(struct fman *fman, u8 port_id, |
---|
1700 | u8 *num_of_open_dmas, |
---|
1701 | u8 *num_of_extra_open_dmas) |
---|
1702 | { |
---|
1703 | struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs; |
---|
1704 | u8 open_dmas = *num_of_open_dmas; |
---|
1705 | u8 extra_open_dmas = *num_of_extra_open_dmas; |
---|
1706 | u8 total_num_dmas = 0, current_val = 0, current_extra_val = 0; |
---|
1707 | u32 tmp; |
---|
1708 | |
---|
1709 | if (!open_dmas) { |
---|
1710 | /* Configuration according to values in the HW. |
---|
1711 | * read the current number of open Dma's |
---|
1712 | */ |
---|
1713 | tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]); |
---|
1714 | current_extra_val = (u8)((tmp & BMI_NUM_OF_EXTRA_DMAS_MASK) >> |
---|
1715 | BMI_EXTRA_NUM_OF_DMAS_SHIFT); |
---|
1716 | |
---|
1717 | tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]); |
---|
1718 | current_val = (u8)(((tmp & BMI_NUM_OF_DMAS_MASK) >> |
---|
1719 | BMI_NUM_OF_DMAS_SHIFT) + 1); |
---|
1720 | |
---|
1721 | /* This is the first configuration and user did not |
---|
1722 | * specify value (!open_dmas), reset values will be used |
---|
1723 | * and we just save these values for resource management |
---|
1724 | */ |
---|
1725 | fman->state->extra_open_dmas_pool_size = |
---|
1726 | (u8)max(fman->state->extra_open_dmas_pool_size, |
---|
1727 | current_extra_val); |
---|
1728 | fman->state->accumulated_num_of_open_dmas += current_val; |
---|
1729 | *num_of_open_dmas = current_val; |
---|
1730 | *num_of_extra_open_dmas = current_extra_val; |
---|
1731 | return 0; |
---|
1732 | } |
---|
1733 | |
---|
1734 | if (extra_open_dmas > current_extra_val) |
---|
1735 | fman->state->extra_open_dmas_pool_size = |
---|
1736 | (u8)max(fman->state->extra_open_dmas_pool_size, |
---|
1737 | extra_open_dmas); |
---|
1738 | |
---|
1739 | if ((fman->state->rev_info.major < 6) && |
---|
1740 | (fman->state->accumulated_num_of_open_dmas - current_val + |
---|
1741 | open_dmas > fman->state->max_num_of_open_dmas)) { |
---|
1742 | dev_err(fman->dev, "%s: Requested num_of_open_dmas for fm%d exceeds total num_of_open_dmas.\n", |
---|
1743 | __func__, fman->state->fm_id); |
---|
1744 | return -EAGAIN; |
---|
1745 | } else if ((fman->state->rev_info.major >= 6) && |
---|
1746 | !((fman->state->rev_info.major == 6) && |
---|
1747 | (fman->state->rev_info.minor == 0)) && |
---|
1748 | (fman->state->accumulated_num_of_open_dmas - |
---|
1749 | current_val + open_dmas > |
---|
1750 | fman->state->dma_thresh_max_commq + 1)) { |
---|
1751 | dev_err(fman->dev, "%s: Requested num_of_open_dmas for fm%d exceeds DMA Command queue (%d)\n", |
---|
1752 | __func__, fman->state->fm_id, |
---|
1753 | fman->state->dma_thresh_max_commq + 1); |
---|
1754 | return -EAGAIN; |
---|
1755 | } |
---|
1756 | |
---|
1757 | WARN_ON(fman->state->accumulated_num_of_open_dmas < current_val); |
---|
1758 | /* update acummulated */ |
---|
1759 | fman->state->accumulated_num_of_open_dmas -= current_val; |
---|
1760 | fman->state->accumulated_num_of_open_dmas += open_dmas; |
---|
1761 | |
---|
1762 | if (fman->state->rev_info.major < 6) |
---|
1763 | total_num_dmas = |
---|
1764 | (u8)(fman->state->accumulated_num_of_open_dmas + |
---|
1765 | fman->state->extra_open_dmas_pool_size); |
---|
1766 | |
---|
1767 | /* calculate reg */ |
---|
1768 | tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) & |
---|
1769 | ~(BMI_NUM_OF_DMAS_MASK | BMI_NUM_OF_EXTRA_DMAS_MASK); |
---|
1770 | tmp |= (u32)(((open_dmas - 1) << BMI_NUM_OF_DMAS_SHIFT) | |
---|
1771 | (extra_open_dmas << BMI_EXTRA_NUM_OF_DMAS_SHIFT)); |
---|
1772 | iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]); |
---|
1773 | |
---|
1774 | /* update total num of DMA's with committed number of open DMAS, |
---|
1775 | * and max uncommitted pool. |
---|
1776 | */ |
---|
1777 | if (total_num_dmas) { |
---|
1778 | tmp = ioread32be(&bmi_rg->fmbm_cfg2) & ~BMI_CFG2_DMAS_MASK; |
---|
1779 | tmp |= (u32)(total_num_dmas - 1) << BMI_CFG2_DMAS_SHIFT; |
---|
1780 | iowrite32be(tmp, &bmi_rg->fmbm_cfg2); |
---|
1781 | } |
---|
1782 | |
---|
1783 | return 0; |
---|
1784 | } |
---|
1785 | |
---|
1786 | static int fman_config(struct fman *fman) |
---|
1787 | { |
---|
1788 | void __iomem *base_addr; |
---|
1789 | int err; |
---|
1790 | |
---|
1791 | base_addr = fman->dts_params.base_addr; |
---|
1792 | |
---|
1793 | fman->state = kzalloc(sizeof(*fman->state), GFP_KERNEL); |
---|
1794 | if (!fman->state) |
---|
1795 | goto err_fm_state; |
---|
1796 | |
---|
1797 | /* Allocate the FM driver's parameters structure */ |
---|
1798 | fman->cfg = kzalloc(sizeof(*fman->cfg), GFP_KERNEL); |
---|
1799 | if (!fman->cfg) |
---|
1800 | goto err_fm_drv; |
---|
1801 | |
---|
1802 | /* Initialize MURAM block */ |
---|
1803 | fman->muram = |
---|
1804 | fman_muram_init(fman->dts_params.muram_res.start, |
---|
1805 | resource_size(&fman->dts_params.muram_res)); |
---|
1806 | if (!fman->muram) |
---|
1807 | goto err_fm_soc_specific; |
---|
1808 | |
---|
1809 | /* Initialize FM parameters which will be kept by the driver */ |
---|
1810 | fman->state->fm_id = fman->dts_params.id; |
---|
1811 | fman->state->fm_clk_freq = fman->dts_params.clk_freq; |
---|
1812 | fman->state->qman_channel_base = fman->dts_params.qman_channel_base; |
---|
1813 | fman->state->num_of_qman_channels = |
---|
1814 | fman->dts_params.num_of_qman_channels; |
---|
1815 | #ifndef __rtems__ |
---|
1816 | fman->state->res = fman->dts_params.res; |
---|
1817 | #endif /* __rtems__ */ |
---|
1818 | fman->exception_cb = fman_exceptions; |
---|
1819 | fman->bus_error_cb = fman_bus_error; |
---|
1820 | fman->fpm_regs = base_addr + FPM_OFFSET; |
---|
1821 | fman->bmi_regs = base_addr + BMI_OFFSET; |
---|
1822 | fman->qmi_regs = base_addr + QMI_OFFSET; |
---|
1823 | fman->dma_regs = base_addr + DMA_OFFSET; |
---|
1824 | fman->hwp_regs = base_addr + HWP_OFFSET; |
---|
1825 | fman->base_addr = base_addr; |
---|
1826 | |
---|
1827 | spin_lock_init(&fman->spinlock); |
---|
1828 | fman_defconfig(fman->cfg); |
---|
1829 | |
---|
1830 | fman->state->extra_fifo_pool_size = 0; |
---|
1831 | fman->state->exceptions = (EX_DMA_BUS_ERROR | |
---|
1832 | EX_DMA_READ_ECC | |
---|
1833 | EX_DMA_SYSTEM_WRITE_ECC | |
---|
1834 | EX_DMA_FM_WRITE_ECC | |
---|
1835 | EX_FPM_STALL_ON_TASKS | |
---|
1836 | EX_FPM_SINGLE_ECC | |
---|
1837 | EX_FPM_DOUBLE_ECC | |
---|
1838 | EX_QMI_DEQ_FROM_UNKNOWN_PORTID | |
---|
1839 | EX_BMI_LIST_RAM_ECC | |
---|
1840 | EX_BMI_STORAGE_PROFILE_ECC | |
---|
1841 | EX_BMI_STATISTICS_RAM_ECC | |
---|
1842 | EX_MURAM_ECC | |
---|
1843 | EX_BMI_DISPATCH_RAM_ECC | |
---|
1844 | EX_QMI_DOUBLE_ECC | |
---|
1845 | EX_QMI_SINGLE_ECC); |
---|
1846 | |
---|
1847 | /* Read FMan revision for future use*/ |
---|
1848 | fman_get_revision(fman, &fman->state->rev_info); |
---|
1849 | |
---|
1850 | err = fill_soc_specific_params(fman->state); |
---|
1851 | if (err) |
---|
1852 | goto err_fm_soc_specific; |
---|
1853 | |
---|
1854 | /* FM_AID_MODE_NO_TNUM_SW005 Errata workaround */ |
---|
1855 | if (fman->state->rev_info.major >= 6) |
---|
1856 | fman->cfg->dma_aid_mode = FMAN_DMA_AID_OUT_PORT_ID; |
---|
1857 | |
---|
1858 | fman->cfg->qmi_def_tnums_thresh = fman->state->qmi_def_tnums_thresh; |
---|
1859 | |
---|
1860 | fman->state->total_num_of_tasks = |
---|
1861 | (u8)DFLT_TOTAL_NUM_OF_TASKS(fman->state->rev_info.major, |
---|
1862 | fman->state->rev_info.minor, |
---|
1863 | fman->state->bmi_max_num_of_tasks); |
---|
1864 | |
---|
1865 | if (fman->state->rev_info.major < 6) { |
---|
1866 | fman->cfg->dma_comm_qtsh_clr_emer = |
---|
1867 | (u8)DFLT_DMA_COMM_Q_LOW(fman->state->rev_info.major, |
---|
1868 | fman->state->dma_thresh_max_commq); |
---|
1869 | |
---|
1870 | fman->cfg->dma_comm_qtsh_asrt_emer = |
---|
1871 | (u8)DFLT_DMA_COMM_Q_HIGH(fman->state->rev_info.major, |
---|
1872 | fman->state->dma_thresh_max_commq); |
---|
1873 | |
---|
1874 | fman->cfg->dma_cam_num_of_entries = |
---|
1875 | DFLT_DMA_CAM_NUM_OF_ENTRIES(fman->state->rev_info.major); |
---|
1876 | |
---|
1877 | fman->cfg->dma_read_buf_tsh_clr_emer = |
---|
1878 | DFLT_DMA_READ_INT_BUF_LOW(fman->state->dma_thresh_max_buf); |
---|
1879 | |
---|
1880 | fman->cfg->dma_read_buf_tsh_asrt_emer = |
---|
1881 | DFLT_DMA_READ_INT_BUF_HIGH(fman->state->dma_thresh_max_buf); |
---|
1882 | |
---|
1883 | fman->cfg->dma_write_buf_tsh_clr_emer = |
---|
1884 | DFLT_DMA_WRITE_INT_BUF_LOW(fman->state->dma_thresh_max_buf); |
---|
1885 | |
---|
1886 | fman->cfg->dma_write_buf_tsh_asrt_emer = |
---|
1887 | DFLT_DMA_WRITE_INT_BUF_HIGH(fman->state->dma_thresh_max_buf); |
---|
1888 | |
---|
1889 | fman->cfg->dma_axi_dbg_num_of_beats = |
---|
1890 | DFLT_AXI_DBG_NUM_OF_BEATS; |
---|
1891 | } |
---|
1892 | |
---|
1893 | return 0; |
---|
1894 | |
---|
1895 | err_fm_soc_specific: |
---|
1896 | kfree(fman->cfg); |
---|
1897 | err_fm_drv: |
---|
1898 | kfree(fman->state); |
---|
1899 | err_fm_state: |
---|
1900 | kfree(fman); |
---|
1901 | return -EINVAL; |
---|
1902 | } |
---|
1903 | |
---|
1904 | #ifndef __rtems__ |
---|
1905 | static int fman_reset(struct fman *fman) |
---|
1906 | { |
---|
1907 | u32 count; |
---|
1908 | int err = 0; |
---|
1909 | |
---|
1910 | if (fman->state->rev_info.major < 6) { |
---|
1911 | iowrite32be(FPM_RSTC_FM_RESET, &fman->fpm_regs->fm_rstc); |
---|
1912 | /* Wait for reset completion */ |
---|
1913 | count = 100; |
---|
1914 | do { |
---|
1915 | udelay(1); |
---|
1916 | } while (((ioread32be(&fman->fpm_regs->fm_rstc)) & |
---|
1917 | FPM_RSTC_FM_RESET) && --count); |
---|
1918 | if (count == 0) |
---|
1919 | err = -EBUSY; |
---|
1920 | |
---|
1921 | goto _return; |
---|
1922 | } else { |
---|
1923 | #ifdef CONFIG_PPC |
---|
1924 | struct device_node *guts_node; |
---|
1925 | struct ccsr_guts __iomem *guts_regs; |
---|
1926 | u32 devdisr2, reg; |
---|
1927 | |
---|
1928 | /* Errata A007273 */ |
---|
1929 | guts_node = |
---|
1930 | of_find_compatible_node(NULL, NULL, |
---|
1931 | "fsl,qoriq-device-config-2.0"); |
---|
1932 | if (!guts_node) { |
---|
1933 | dev_err(fman->dev, "%s: Couldn't find guts node\n", |
---|
1934 | __func__); |
---|
1935 | goto guts_node; |
---|
1936 | } |
---|
1937 | |
---|
1938 | guts_regs = of_iomap(guts_node, 0); |
---|
1939 | if (!guts_regs) { |
---|
1940 | dev_err(fman->dev, "%s: Couldn't map %s regs\n", |
---|
1941 | __func__, guts_node->full_name); |
---|
1942 | goto guts_regs; |
---|
1943 | } |
---|
1944 | #define FMAN1_ALL_MACS_MASK 0xFCC00000 |
---|
1945 | #define FMAN2_ALL_MACS_MASK 0x000FCC00 |
---|
1946 | /* Read current state */ |
---|
1947 | devdisr2 = ioread32be(&guts_regs->devdisr2); |
---|
1948 | if (fman->dts_params.id == 0) |
---|
1949 | reg = devdisr2 & ~FMAN1_ALL_MACS_MASK; |
---|
1950 | else |
---|
1951 | reg = devdisr2 & ~FMAN2_ALL_MACS_MASK; |
---|
1952 | |
---|
1953 | /* Enable all MACs */ |
---|
1954 | iowrite32be(reg, &guts_regs->devdisr2); |
---|
1955 | #endif |
---|
1956 | |
---|
1957 | /* Perform FMan reset */ |
---|
1958 | iowrite32be(FPM_RSTC_FM_RESET, &fman->fpm_regs->fm_rstc); |
---|
1959 | |
---|
1960 | /* Wait for reset completion */ |
---|
1961 | count = 100; |
---|
1962 | do { |
---|
1963 | udelay(1); |
---|
1964 | } while (((ioread32be(&fman->fpm_regs->fm_rstc)) & |
---|
1965 | FPM_RSTC_FM_RESET) && --count); |
---|
1966 | if (count == 0) { |
---|
1967 | #ifdef CONFIG_PPC |
---|
1968 | iounmap(guts_regs); |
---|
1969 | of_node_put(guts_node); |
---|
1970 | #endif |
---|
1971 | err = -EBUSY; |
---|
1972 | goto _return; |
---|
1973 | } |
---|
1974 | #ifdef CONFIG_PPC |
---|
1975 | |
---|
1976 | /* Restore devdisr2 value */ |
---|
1977 | iowrite32be(devdisr2, &guts_regs->devdisr2); |
---|
1978 | |
---|
1979 | iounmap(guts_regs); |
---|
1980 | of_node_put(guts_node); |
---|
1981 | #endif |
---|
1982 | |
---|
1983 | goto _return; |
---|
1984 | |
---|
1985 | #ifdef CONFIG_PPC |
---|
1986 | guts_regs: |
---|
1987 | of_node_put(guts_node); |
---|
1988 | guts_node: |
---|
1989 | dev_dbg(fman->dev, "%s: Didn't perform FManV3 reset due to Errata A007273!\n", |
---|
1990 | __func__); |
---|
1991 | #endif |
---|
1992 | } |
---|
1993 | _return: |
---|
1994 | return err; |
---|
1995 | } |
---|
1996 | #endif /* __rtems__ */ |
---|
1997 | |
---|
1998 | static int fman_init(struct fman *fman) |
---|
1999 | { |
---|
2000 | struct fman_cfg *cfg = NULL; |
---|
2001 | int err = 0, i, count; |
---|
2002 | |
---|
2003 | if (is_init_done(fman->cfg)) |
---|
2004 | return -EINVAL; |
---|
2005 | |
---|
2006 | fman->state->count1_micro_bit = FM_TIMESTAMP_1_USEC_BIT; |
---|
2007 | |
---|
2008 | cfg = fman->cfg; |
---|
2009 | |
---|
2010 | /* clear revision-dependent non existing exception */ |
---|
2011 | if (fman->state->rev_info.major < 6) |
---|
2012 | fman->state->exceptions &= ~FMAN_EX_BMI_DISPATCH_RAM_ECC; |
---|
2013 | |
---|
2014 | if (fman->state->rev_info.major >= 6) |
---|
2015 | fman->state->exceptions &= ~FMAN_EX_QMI_SINGLE_ECC; |
---|
2016 | |
---|
2017 | /* clear CPG */ |
---|
2018 | memset_io((void __iomem *)(fman->base_addr + CGP_OFFSET), 0, |
---|
2019 | fman->state->fm_port_num_of_cg); |
---|
2020 | |
---|
2021 | /* Save LIODN info before FMan reset |
---|
2022 | * Skipping non-existent port 0 (i = 1) |
---|
2023 | */ |
---|
2024 | for (i = 1; i < FMAN_LIODN_TBL; i++) { |
---|
2025 | u32 liodn_base; |
---|
2026 | |
---|
2027 | fman->liodn_offset[i] = |
---|
2028 | ioread32be(&fman->bmi_regs->fmbm_spliodn[i - 1]); |
---|
2029 | liodn_base = ioread32be(&fman->dma_regs->fmdmplr[i / 2]); |
---|
2030 | if (i % 2) { |
---|
2031 | /* FMDM_PLR LSB holds LIODN base for odd ports */ |
---|
2032 | liodn_base &= DMA_LIODN_BASE_MASK; |
---|
2033 | } else { |
---|
2034 | /* FMDM_PLR MSB holds LIODN base for even ports */ |
---|
2035 | liodn_base >>= DMA_LIODN_SHIFT; |
---|
2036 | liodn_base &= DMA_LIODN_BASE_MASK; |
---|
2037 | } |
---|
2038 | fman->liodn_base[i] = liodn_base; |
---|
2039 | } |
---|
2040 | |
---|
2041 | err = fman_reset(fman); |
---|
2042 | if (err) |
---|
2043 | return err; |
---|
2044 | |
---|
2045 | if (ioread32be(&fman->qmi_regs->fmqm_gs) & QMI_GS_HALT_NOT_BUSY) { |
---|
2046 | resume(fman->fpm_regs); |
---|
2047 | /* Wait until QMI is not in halt not busy state */ |
---|
2048 | count = 100; |
---|
2049 | do { |
---|
2050 | udelay(1); |
---|
2051 | } while (((ioread32be(&fman->qmi_regs->fmqm_gs)) & |
---|
2052 | QMI_GS_HALT_NOT_BUSY) && --count); |
---|
2053 | if (count == 0) |
---|
2054 | dev_warn(fman->dev, "%s: QMI is in halt not busy state\n", |
---|
2055 | __func__); |
---|
2056 | } |
---|
2057 | |
---|
2058 | if (clear_iram(fman) != 0) |
---|
2059 | return -EINVAL; |
---|
2060 | |
---|
2061 | cfg->exceptions = fman->state->exceptions; |
---|
2062 | |
---|
2063 | /* Init DMA Registers */ |
---|
2064 | |
---|
2065 | err = dma_init(fman); |
---|
2066 | if (err != 0) { |
---|
2067 | free_init_resources(fman); |
---|
2068 | return err; |
---|
2069 | } |
---|
2070 | |
---|
2071 | /* Init FPM Registers */ |
---|
2072 | fpm_init(fman->fpm_regs, fman->cfg); |
---|
2073 | |
---|
2074 | /* define common resources */ |
---|
2075 | /* allocate MURAM for FIFO according to total size */ |
---|
2076 | fman->fifo_offset = fman_muram_alloc(fman->muram, |
---|
2077 | fman->state->total_fifo_size); |
---|
2078 | if (IS_ERR_VALUE(fman->fifo_offset)) { |
---|
2079 | free_init_resources(fman); |
---|
2080 | dev_err(fman->dev, "%s: MURAM alloc for BMI FIFO failed\n", |
---|
2081 | __func__); |
---|
2082 | return -ENOMEM; |
---|
2083 | } |
---|
2084 | |
---|
2085 | cfg->fifo_base_addr = fman->fifo_offset; |
---|
2086 | cfg->total_fifo_size = fman->state->total_fifo_size; |
---|
2087 | cfg->total_num_of_tasks = fman->state->total_num_of_tasks; |
---|
2088 | cfg->clk_freq = fman->state->fm_clk_freq; |
---|
2089 | |
---|
2090 | /* Init BMI Registers */ |
---|
2091 | bmi_init(fman->bmi_regs, fman->cfg); |
---|
2092 | |
---|
2093 | /* Init QMI Registers */ |
---|
2094 | qmi_init(fman->qmi_regs, fman->cfg); |
---|
2095 | |
---|
2096 | /* Init HW Parser */ |
---|
2097 | hwp_init(fman->hwp_regs); |
---|
2098 | |
---|
2099 | err = enable(fman, cfg); |
---|
2100 | if (err != 0) |
---|
2101 | return err; |
---|
2102 | |
---|
2103 | enable_time_stamp(fman); |
---|
2104 | |
---|
2105 | kfree(fman->cfg); |
---|
2106 | fman->cfg = NULL; |
---|
2107 | |
---|
2108 | return 0; |
---|
2109 | } |
---|
2110 | |
---|
2111 | static int fman_set_exception(struct fman *fman, |
---|
2112 | enum fman_exceptions exception, bool enable) |
---|
2113 | { |
---|
2114 | u32 bit_mask = 0; |
---|
2115 | |
---|
2116 | if (!is_init_done(fman->cfg)) |
---|
2117 | return -EINVAL; |
---|
2118 | |
---|
2119 | bit_mask = get_exception_flag(exception); |
---|
2120 | if (bit_mask) { |
---|
2121 | if (enable) |
---|
2122 | fman->state->exceptions |= bit_mask; |
---|
2123 | else |
---|
2124 | fman->state->exceptions &= ~bit_mask; |
---|
2125 | } else { |
---|
2126 | dev_err(fman->dev, "%s: Undefined exception (%d)\n", |
---|
2127 | __func__, exception); |
---|
2128 | return -EINVAL; |
---|
2129 | } |
---|
2130 | |
---|
2131 | return set_exception(fman, exception, enable); |
---|
2132 | } |
---|
2133 | |
---|
2134 | /** |
---|
2135 | * fman_register_intr |
---|
2136 | * @fman: A Pointer to FMan device |
---|
2137 | * @mod: Calling module |
---|
2138 | * @mod_id: Module id (if more than 1 exists, '0' if not) |
---|
2139 | * @intr_type: Interrupt type (error/normal) selection. |
---|
2140 | * @f_isr: The interrupt service routine. |
---|
2141 | * @h_src_arg: Argument to be passed to f_isr. |
---|
2142 | * |
---|
2143 | * Used to register an event handler to be processed by FMan |
---|
2144 | * |
---|
2145 | * Return: 0 on success; Error code otherwise. |
---|
2146 | */ |
---|
2147 | void fman_register_intr(struct fman *fman, enum fman_event_modules module, |
---|
2148 | u8 mod_id, enum fman_intr_type intr_type, |
---|
2149 | void (*isr_cb)(void *src_arg), void *src_arg) |
---|
2150 | { |
---|
2151 | int event = 0; |
---|
2152 | |
---|
2153 | event = get_module_event(module, mod_id, intr_type); |
---|
2154 | WARN_ON(event >= FMAN_EV_CNT); |
---|
2155 | |
---|
2156 | /* register in local FM structure */ |
---|
2157 | fman->intr_mng[event].isr_cb = isr_cb; |
---|
2158 | fman->intr_mng[event].src_handle = src_arg; |
---|
2159 | } |
---|
2160 | EXPORT_SYMBOL(fman_register_intr); |
---|
2161 | |
---|
2162 | /** |
---|
2163 | * fman_unregister_intr |
---|
2164 | * @fman: A Pointer to FMan device |
---|
2165 | * @mod: Calling module |
---|
2166 | * @mod_id: Module id (if more than 1 exists, '0' if not) |
---|
2167 | * @intr_type: Interrupt type (error/normal) selection. |
---|
2168 | * |
---|
2169 | * Used to unregister an event handler to be processed by FMan |
---|
2170 | * |
---|
2171 | * Return: 0 on success; Error code otherwise. |
---|
2172 | */ |
---|
2173 | void fman_unregister_intr(struct fman *fman, enum fman_event_modules module, |
---|
2174 | u8 mod_id, enum fman_intr_type intr_type) |
---|
2175 | { |
---|
2176 | int event = 0; |
---|
2177 | |
---|
2178 | event = get_module_event(module, mod_id, intr_type); |
---|
2179 | WARN_ON(event >= FMAN_EV_CNT); |
---|
2180 | |
---|
2181 | fman->intr_mng[event].isr_cb = NULL; |
---|
2182 | fman->intr_mng[event].src_handle = NULL; |
---|
2183 | } |
---|
2184 | EXPORT_SYMBOL(fman_unregister_intr); |
---|
2185 | |
---|
2186 | /** |
---|
2187 | * fman_set_port_params |
---|
2188 | * @fman: A Pointer to FMan device |
---|
2189 | * @port_params: Port parameters |
---|
2190 | * |
---|
2191 | * Used by FMan Port to pass parameters to the FMan |
---|
2192 | * |
---|
2193 | * Return: 0 on success; Error code otherwise. |
---|
2194 | */ |
---|
2195 | int fman_set_port_params(struct fman *fman, |
---|
2196 | struct fman_port_init_params *port_params) |
---|
2197 | { |
---|
2198 | int err; |
---|
2199 | unsigned long flags; |
---|
2200 | u8 port_id = port_params->port_id, mac_id; |
---|
2201 | |
---|
2202 | spin_lock_irqsave(&fman->spinlock, flags); |
---|
2203 | |
---|
2204 | err = set_num_of_tasks(fman, port_params->port_id, |
---|
2205 | &port_params->num_of_tasks, |
---|
2206 | &port_params->num_of_extra_tasks); |
---|
2207 | if (err) |
---|
2208 | goto return_err; |
---|
2209 | |
---|
2210 | /* TX Ports */ |
---|
2211 | if (port_params->port_type != FMAN_PORT_TYPE_RX) { |
---|
2212 | u32 enq_th, deq_th, reg; |
---|
2213 | |
---|
2214 | /* update qmi ENQ/DEQ threshold */ |
---|
2215 | fman->state->accumulated_num_of_deq_tnums += |
---|
2216 | port_params->deq_pipeline_depth; |
---|
2217 | enq_th = (ioread32be(&fman->qmi_regs->fmqm_gc) & |
---|
2218 | QMI_CFG_ENQ_MASK) >> QMI_CFG_ENQ_SHIFT; |
---|
2219 | /* if enq_th is too big, we reduce it to the max value |
---|
2220 | * that is still 0 |
---|
2221 | */ |
---|
2222 | if (enq_th >= (fman->state->qmi_max_num_of_tnums - |
---|
2223 | fman->state->accumulated_num_of_deq_tnums)) { |
---|
2224 | enq_th = |
---|
2225 | fman->state->qmi_max_num_of_tnums - |
---|
2226 | fman->state->accumulated_num_of_deq_tnums - 1; |
---|
2227 | |
---|
2228 | reg = ioread32be(&fman->qmi_regs->fmqm_gc); |
---|
2229 | reg &= ~QMI_CFG_ENQ_MASK; |
---|
2230 | reg |= (enq_th << QMI_CFG_ENQ_SHIFT); |
---|
2231 | iowrite32be(reg, &fman->qmi_regs->fmqm_gc); |
---|
2232 | } |
---|
2233 | |
---|
2234 | deq_th = ioread32be(&fman->qmi_regs->fmqm_gc) & |
---|
2235 | QMI_CFG_DEQ_MASK; |
---|
2236 | /* if deq_th is too small, we enlarge it to the min |
---|
2237 | * value that is still 0. |
---|
2238 | * depTh may not be larger than 63 |
---|
2239 | * (fman->state->qmi_max_num_of_tnums-1). |
---|
2240 | */ |
---|
2241 | if ((deq_th <= fman->state->accumulated_num_of_deq_tnums) && |
---|
2242 | (deq_th < fman->state->qmi_max_num_of_tnums - 1)) { |
---|
2243 | deq_th = fman->state->accumulated_num_of_deq_tnums + 1; |
---|
2244 | reg = ioread32be(&fman->qmi_regs->fmqm_gc); |
---|
2245 | reg &= ~QMI_CFG_DEQ_MASK; |
---|
2246 | reg |= deq_th; |
---|
2247 | iowrite32be(reg, &fman->qmi_regs->fmqm_gc); |
---|
2248 | } |
---|
2249 | } |
---|
2250 | |
---|
2251 | err = set_size_of_fifo(fman, port_params->port_id, |
---|
2252 | &port_params->size_of_fifo, |
---|
2253 | &port_params->extra_size_of_fifo); |
---|
2254 | if (err) |
---|
2255 | goto return_err; |
---|
2256 | |
---|
2257 | err = set_num_of_open_dmas(fman, port_params->port_id, |
---|
2258 | &port_params->num_of_open_dmas, |
---|
2259 | &port_params->num_of_extra_open_dmas); |
---|
2260 | if (err) |
---|
2261 | goto return_err; |
---|
2262 | |
---|
2263 | set_port_liodn(fman, port_id, fman->liodn_base[port_id], |
---|
2264 | fman->liodn_offset[port_id]); |
---|
2265 | |
---|
2266 | if (fman->state->rev_info.major < 6) |
---|
2267 | set_port_order_restoration(fman->fpm_regs, port_id); |
---|
2268 | |
---|
2269 | mac_id = hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id); |
---|
2270 | |
---|
2271 | if (port_params->max_frame_length >= fman->state->mac_mfl[mac_id]) { |
---|
2272 | fman->state->port_mfl[mac_id] = port_params->max_frame_length; |
---|
2273 | } else { |
---|
2274 | dev_warn(fman->dev, "%s: Port (%d) max_frame_length is smaller than MAC (%d) current MTU\n", |
---|
2275 | __func__, port_id, mac_id); |
---|
2276 | err = -EINVAL; |
---|
2277 | goto return_err; |
---|
2278 | } |
---|
2279 | |
---|
2280 | spin_unlock_irqrestore(&fman->spinlock, flags); |
---|
2281 | |
---|
2282 | return 0; |
---|
2283 | |
---|
2284 | return_err: |
---|
2285 | spin_unlock_irqrestore(&fman->spinlock, flags); |
---|
2286 | return err; |
---|
2287 | } |
---|
2288 | EXPORT_SYMBOL(fman_set_port_params); |
---|
2289 | |
---|
2290 | /** |
---|
2291 | * fman_reset_mac |
---|
2292 | * @fman: A Pointer to FMan device |
---|
2293 | * @mac_id: MAC id to be reset |
---|
2294 | * |
---|
2295 | * Reset a specific MAC |
---|
2296 | * |
---|
2297 | * Return: 0 on success; Error code otherwise. |
---|
2298 | */ |
---|
2299 | int fman_reset_mac(struct fman *fman, u8 mac_id) |
---|
2300 | { |
---|
2301 | struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs; |
---|
2302 | u32 msk, timeout = 100; |
---|
2303 | |
---|
2304 | if (fman->state->rev_info.major >= 6) { |
---|
2305 | dev_err(fman->dev, "%s: FMan MAC reset no available for FMan V3!\n", |
---|
2306 | __func__); |
---|
2307 | return -EINVAL; |
---|
2308 | } |
---|
2309 | |
---|
2310 | /* Get the relevant bit mask */ |
---|
2311 | switch (mac_id) { |
---|
2312 | case 0: |
---|
2313 | msk = FPM_RSTC_MAC0_RESET; |
---|
2314 | break; |
---|
2315 | case 1: |
---|
2316 | msk = FPM_RSTC_MAC1_RESET; |
---|
2317 | break; |
---|
2318 | case 2: |
---|
2319 | msk = FPM_RSTC_MAC2_RESET; |
---|
2320 | break; |
---|
2321 | case 3: |
---|
2322 | msk = FPM_RSTC_MAC3_RESET; |
---|
2323 | break; |
---|
2324 | case 4: |
---|
2325 | msk = FPM_RSTC_MAC4_RESET; |
---|
2326 | break; |
---|
2327 | case 5: |
---|
2328 | msk = FPM_RSTC_MAC5_RESET; |
---|
2329 | break; |
---|
2330 | case 6: |
---|
2331 | msk = FPM_RSTC_MAC6_RESET; |
---|
2332 | break; |
---|
2333 | case 7: |
---|
2334 | msk = FPM_RSTC_MAC7_RESET; |
---|
2335 | break; |
---|
2336 | case 8: |
---|
2337 | msk = FPM_RSTC_MAC8_RESET; |
---|
2338 | break; |
---|
2339 | case 9: |
---|
2340 | msk = FPM_RSTC_MAC9_RESET; |
---|
2341 | break; |
---|
2342 | default: |
---|
2343 | dev_warn(fman->dev, "%s: Illegal MAC Id [%d]\n", |
---|
2344 | __func__, mac_id); |
---|
2345 | return -EINVAL; |
---|
2346 | } |
---|
2347 | |
---|
2348 | /* reset */ |
---|
2349 | iowrite32be(msk, &fpm_rg->fm_rstc); |
---|
2350 | while ((ioread32be(&fpm_rg->fm_rstc) & msk) && --timeout) |
---|
2351 | udelay(10); |
---|
2352 | |
---|
2353 | if (!timeout) |
---|
2354 | return -EIO; |
---|
2355 | |
---|
2356 | return 0; |
---|
2357 | } |
---|
2358 | EXPORT_SYMBOL(fman_reset_mac); |
---|
2359 | |
---|
2360 | /** |
---|
2361 | * fman_set_mac_max_frame |
---|
2362 | * @fman: A Pointer to FMan device |
---|
2363 | * @mac_id: MAC id |
---|
2364 | * @mfl: Maximum frame length |
---|
2365 | * |
---|
2366 | * Set maximum frame length of specific MAC in FMan driver |
---|
2367 | * |
---|
2368 | * Return: 0 on success; Error code otherwise. |
---|
2369 | */ |
---|
2370 | int fman_set_mac_max_frame(struct fman *fman, u8 mac_id, u16 mfl) |
---|
2371 | { |
---|
2372 | /* if port is already initialized, check that MaxFrameLength is smaller |
---|
2373 | * or equal to the port's max |
---|
2374 | */ |
---|
2375 | if ((!fman->state->port_mfl[mac_id]) || |
---|
2376 | (mfl <= fman->state->port_mfl[mac_id])) { |
---|
2377 | fman->state->mac_mfl[mac_id] = mfl; |
---|
2378 | } else { |
---|
2379 | dev_warn(fman->dev, "%s: MAC max_frame_length is larger than Port max_frame_length\n", |
---|
2380 | __func__); |
---|
2381 | return -EINVAL; |
---|
2382 | } |
---|
2383 | return 0; |
---|
2384 | } |
---|
2385 | EXPORT_SYMBOL(fman_set_mac_max_frame); |
---|
2386 | |
---|
2387 | /** |
---|
2388 | * fman_get_clock_freq |
---|
2389 | * @fman: A Pointer to FMan device |
---|
2390 | * |
---|
2391 | * Get FMan clock frequency |
---|
2392 | * |
---|
2393 | * Return: FMan clock frequency |
---|
2394 | */ |
---|
2395 | u16 fman_get_clock_freq(struct fman *fman) |
---|
2396 | { |
---|
2397 | return fman->state->fm_clk_freq; |
---|
2398 | } |
---|
2399 | |
---|
2400 | /** |
---|
2401 | * fman_get_bmi_max_fifo_size |
---|
2402 | * @fman: A Pointer to FMan device |
---|
2403 | * |
---|
2404 | * Get FMan maximum FIFO size |
---|
2405 | * |
---|
2406 | * Return: FMan Maximum FIFO size |
---|
2407 | */ |
---|
2408 | u32 fman_get_bmi_max_fifo_size(struct fman *fman) |
---|
2409 | { |
---|
2410 | return fman->state->bmi_max_fifo_size; |
---|
2411 | } |
---|
2412 | EXPORT_SYMBOL(fman_get_bmi_max_fifo_size); |
---|
2413 | |
---|
2414 | /** |
---|
2415 | * fman_get_revision |
---|
2416 | * @fman - Pointer to the FMan module |
---|
2417 | * @rev_info - A structure of revision information parameters. |
---|
2418 | * |
---|
2419 | * Returns the FM revision |
---|
2420 | * |
---|
2421 | * Allowed only following fman_init(). |
---|
2422 | * |
---|
2423 | * Return: 0 on success; Error code otherwise. |
---|
2424 | */ |
---|
2425 | void fman_get_revision(struct fman *fman, struct fman_rev_info *rev_info) |
---|
2426 | { |
---|
2427 | u32 tmp; |
---|
2428 | |
---|
2429 | tmp = ioread32be(&fman->fpm_regs->fm_ip_rev_1); |
---|
2430 | rev_info->major = (u8)((tmp & FPM_REV1_MAJOR_MASK) >> |
---|
2431 | FPM_REV1_MAJOR_SHIFT); |
---|
2432 | rev_info->minor = tmp & FPM_REV1_MINOR_MASK; |
---|
2433 | } |
---|
2434 | EXPORT_SYMBOL(fman_get_revision); |
---|
2435 | |
---|
2436 | /** |
---|
2437 | * fman_get_qman_channel_id |
---|
2438 | * @fman: A Pointer to FMan device |
---|
2439 | * @port_id: Port id |
---|
2440 | * |
---|
2441 | * Get QMan channel ID associated to the Port id |
---|
2442 | * |
---|
2443 | * Return: QMan channel ID |
---|
2444 | */ |
---|
2445 | u32 fman_get_qman_channel_id(struct fman *fman, u32 port_id) |
---|
2446 | { |
---|
2447 | int i; |
---|
2448 | |
---|
2449 | if (fman->state->rev_info.major >= 6) { |
---|
2450 | u32 port_ids[] = {0x30, 0x31, 0x28, 0x29, 0x2a, 0x2b, |
---|
2451 | 0x2c, 0x2d, 0x2, 0x3, 0x4, 0x5, 0x7, 0x7}; |
---|
2452 | for (i = 0; i < fman->state->num_of_qman_channels; i++) { |
---|
2453 | if (port_ids[i] == port_id) |
---|
2454 | break; |
---|
2455 | } |
---|
2456 | } else { |
---|
2457 | u32 port_ids[] = {0x30, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x1, |
---|
2458 | 0x2, 0x3, 0x4, 0x5, 0x7, 0x7}; |
---|
2459 | for (i = 0; i < fman->state->num_of_qman_channels; i++) { |
---|
2460 | if (port_ids[i] == port_id) |
---|
2461 | break; |
---|
2462 | } |
---|
2463 | } |
---|
2464 | |
---|
2465 | if (i == fman->state->num_of_qman_channels) |
---|
2466 | return 0; |
---|
2467 | |
---|
2468 | return fman->state->qman_channel_base + i; |
---|
2469 | } |
---|
2470 | EXPORT_SYMBOL(fman_get_qman_channel_id); |
---|
2471 | |
---|
2472 | /** |
---|
2473 | * fman_get_mem_region |
---|
2474 | * @fman: A Pointer to FMan device |
---|
2475 | * |
---|
2476 | * Get FMan memory region |
---|
2477 | * |
---|
2478 | * Return: A structure with FMan memory region information |
---|
2479 | */ |
---|
2480 | struct resource *fman_get_mem_region(struct fman *fman) |
---|
2481 | { |
---|
2482 | return fman->state->res; |
---|
2483 | } |
---|
2484 | EXPORT_SYMBOL(fman_get_mem_region); |
---|
2485 | |
---|
2486 | /* Bootargs defines */ |
---|
2487 | /* Extra headroom for RX buffers - Default, min and max */ |
---|
2488 | #define FSL_FM_RX_EXTRA_HEADROOM 64 |
---|
2489 | #define FSL_FM_RX_EXTRA_HEADROOM_MIN 16 |
---|
2490 | #define FSL_FM_RX_EXTRA_HEADROOM_MAX 384 |
---|
2491 | |
---|
2492 | /* Maximum frame length */ |
---|
2493 | #define FSL_FM_MAX_FRAME_SIZE 1522 |
---|
2494 | #define FSL_FM_MAX_POSSIBLE_FRAME_SIZE 9600 |
---|
2495 | #define FSL_FM_MIN_POSSIBLE_FRAME_SIZE 64 |
---|
2496 | |
---|
2497 | /* Extra headroom for Rx buffers. |
---|
2498 | * FMan is instructed to allocate, on the Rx path, this amount of |
---|
2499 | * space at the beginning of a data buffer, beside the DPA private |
---|
2500 | * data area and the IC fields. |
---|
2501 | * Does not impact Tx buffer layout. |
---|
2502 | * Configurable from bootargs. 64 by default, it's needed on |
---|
2503 | * particular forwarding scenarios that add extra headers to the |
---|
2504 | * forwarded frame. |
---|
2505 | */ |
---|
2506 | static int fsl_fm_rx_extra_headroom = FSL_FM_RX_EXTRA_HEADROOM; |
---|
2507 | module_param(fsl_fm_rx_extra_headroom, int, 0); |
---|
2508 | MODULE_PARM_DESC(fsl_fm_rx_extra_headroom, "Extra headroom for Rx buffers"); |
---|
2509 | |
---|
2510 | /* Max frame size, across all interfaces. |
---|
2511 | * Configurable from bootargs, to avoid allocating oversized (socket) |
---|
2512 | * buffers when not using jumbo frames. |
---|
2513 | * Must be large enough to accommodate the network MTU, but small enough |
---|
2514 | * to avoid wasting skb memory. |
---|
2515 | * |
---|
2516 | * Could be overridden once, at boot-time, via the |
---|
2517 | * fm_set_max_frm() callback. |
---|
2518 | */ |
---|
2519 | #ifndef __rtems__ |
---|
2520 | static int fsl_fm_max_frm = FSL_FM_MAX_FRAME_SIZE; |
---|
2521 | #else /* __rtems__ */ |
---|
2522 | static int fsl_fm_max_frm = FSL_FM_MAX_POSSIBLE_FRAME_SIZE; |
---|
2523 | #endif /* __rtems__ */ |
---|
2524 | module_param(fsl_fm_max_frm, int, 0); |
---|
2525 | MODULE_PARM_DESC(fsl_fm_max_frm, "Maximum frame size, across all interfaces"); |
---|
2526 | |
---|
2527 | /** |
---|
2528 | * fman_get_max_frm |
---|
2529 | * |
---|
2530 | * Return: Max frame length configured in the FM driver |
---|
2531 | */ |
---|
2532 | u16 fman_get_max_frm(void) |
---|
2533 | { |
---|
2534 | static bool fm_check_mfl; |
---|
2535 | |
---|
2536 | if (!fm_check_mfl) { |
---|
2537 | if (fsl_fm_max_frm > FSL_FM_MAX_POSSIBLE_FRAME_SIZE || |
---|
2538 | fsl_fm_max_frm < FSL_FM_MIN_POSSIBLE_FRAME_SIZE) { |
---|
2539 | pr_warn("Invalid fsl_fm_max_frm value (%d) in bootargs, valid range is %d-%d. Falling back to the default (%d)\n", |
---|
2540 | fsl_fm_max_frm, |
---|
2541 | FSL_FM_MIN_POSSIBLE_FRAME_SIZE, |
---|
2542 | FSL_FM_MAX_POSSIBLE_FRAME_SIZE, |
---|
2543 | FSL_FM_MAX_FRAME_SIZE); |
---|
2544 | fsl_fm_max_frm = FSL_FM_MAX_FRAME_SIZE; |
---|
2545 | } |
---|
2546 | fm_check_mfl = true; |
---|
2547 | } |
---|
2548 | |
---|
2549 | return fsl_fm_max_frm; |
---|
2550 | } |
---|
2551 | EXPORT_SYMBOL(fman_get_max_frm); |
---|
2552 | |
---|
2553 | /** |
---|
2554 | * fman_get_rx_extra_headroom |
---|
2555 | * |
---|
2556 | * Return: Extra headroom size configured in the FM driver |
---|
2557 | */ |
---|
2558 | int fman_get_rx_extra_headroom(void) |
---|
2559 | { |
---|
2560 | static bool fm_check_rx_extra_headroom; |
---|
2561 | |
---|
2562 | if (!fm_check_rx_extra_headroom) { |
---|
2563 | if (fsl_fm_rx_extra_headroom > FSL_FM_RX_EXTRA_HEADROOM_MAX || |
---|
2564 | fsl_fm_rx_extra_headroom < FSL_FM_RX_EXTRA_HEADROOM_MIN) { |
---|
2565 | pr_warn("Invalid fsl_fm_rx_extra_headroom value (%d) in bootargs, valid range is %d-%d. Falling back to the default (%d)\n", |
---|
2566 | fsl_fm_rx_extra_headroom, |
---|
2567 | FSL_FM_RX_EXTRA_HEADROOM_MIN, |
---|
2568 | FSL_FM_RX_EXTRA_HEADROOM_MAX, |
---|
2569 | FSL_FM_RX_EXTRA_HEADROOM); |
---|
2570 | fsl_fm_rx_extra_headroom = FSL_FM_RX_EXTRA_HEADROOM; |
---|
2571 | } |
---|
2572 | |
---|
2573 | fm_check_rx_extra_headroom = true; |
---|
2574 | fsl_fm_rx_extra_headroom = ALIGN(fsl_fm_rx_extra_headroom, 16); |
---|
2575 | } |
---|
2576 | |
---|
2577 | return fsl_fm_rx_extra_headroom; |
---|
2578 | } |
---|
2579 | EXPORT_SYMBOL(fman_get_rx_extra_headroom); |
---|
2580 | |
---|
2581 | /** |
---|
2582 | * fman_bind |
---|
2583 | * @dev: FMan OF device pointer |
---|
2584 | * |
---|
2585 | * Bind to a specific FMan device. |
---|
2586 | * |
---|
2587 | * Allowed only after the port was created. |
---|
2588 | * |
---|
2589 | * Return: A pointer to the FMan device |
---|
2590 | */ |
---|
2591 | struct fman *fman_bind(struct device *fm_dev) |
---|
2592 | { |
---|
2593 | return (struct fman *)(dev_get_drvdata(get_device(fm_dev))); |
---|
2594 | } |
---|
2595 | EXPORT_SYMBOL(fman_bind); |
---|
2596 | |
---|
2597 | static irqreturn_t fman_err_irq(int irq, void *handle) |
---|
2598 | { |
---|
2599 | struct fman *fman = (struct fman *)handle; |
---|
2600 | u32 pending; |
---|
2601 | struct fman_fpm_regs __iomem *fpm_rg; |
---|
2602 | irqreturn_t single_ret, ret = IRQ_NONE; |
---|
2603 | |
---|
2604 | if (!is_init_done(fman->cfg)) |
---|
2605 | return IRQ_NONE; |
---|
2606 | |
---|
2607 | fpm_rg = fman->fpm_regs; |
---|
2608 | |
---|
2609 | /* error interrupts */ |
---|
2610 | pending = ioread32be(&fpm_rg->fm_epi); |
---|
2611 | if (!pending) |
---|
2612 | return IRQ_NONE; |
---|
2613 | |
---|
2614 | if (pending & ERR_INTR_EN_BMI) { |
---|
2615 | single_ret = bmi_err_event(fman); |
---|
2616 | if (single_ret == IRQ_HANDLED) |
---|
2617 | ret = IRQ_HANDLED; |
---|
2618 | } |
---|
2619 | if (pending & ERR_INTR_EN_QMI) { |
---|
2620 | single_ret = qmi_err_event(fman); |
---|
2621 | if (single_ret == IRQ_HANDLED) |
---|
2622 | ret = IRQ_HANDLED; |
---|
2623 | } |
---|
2624 | if (pending & ERR_INTR_EN_FPM) { |
---|
2625 | single_ret = fpm_err_event(fman); |
---|
2626 | if (single_ret == IRQ_HANDLED) |
---|
2627 | ret = IRQ_HANDLED; |
---|
2628 | } |
---|
2629 | if (pending & ERR_INTR_EN_DMA) { |
---|
2630 | single_ret = dma_err_event(fman); |
---|
2631 | if (single_ret == IRQ_HANDLED) |
---|
2632 | ret = IRQ_HANDLED; |
---|
2633 | } |
---|
2634 | if (pending & ERR_INTR_EN_MURAM) { |
---|
2635 | single_ret = muram_err_intr(fman); |
---|
2636 | if (single_ret == IRQ_HANDLED) |
---|
2637 | ret = IRQ_HANDLED; |
---|
2638 | } |
---|
2639 | |
---|
2640 | /* MAC error interrupts */ |
---|
2641 | if (pending & ERR_INTR_EN_MAC0) { |
---|
2642 | single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 0); |
---|
2643 | if (single_ret == IRQ_HANDLED) |
---|
2644 | ret = IRQ_HANDLED; |
---|
2645 | } |
---|
2646 | if (pending & ERR_INTR_EN_MAC1) { |
---|
2647 | single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 1); |
---|
2648 | if (single_ret == IRQ_HANDLED) |
---|
2649 | ret = IRQ_HANDLED; |
---|
2650 | } |
---|
2651 | if (pending & ERR_INTR_EN_MAC2) { |
---|
2652 | single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 2); |
---|
2653 | if (single_ret == IRQ_HANDLED) |
---|
2654 | ret = IRQ_HANDLED; |
---|
2655 | } |
---|
2656 | if (pending & ERR_INTR_EN_MAC3) { |
---|
2657 | single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 3); |
---|
2658 | if (single_ret == IRQ_HANDLED) |
---|
2659 | ret = IRQ_HANDLED; |
---|
2660 | } |
---|
2661 | if (pending & ERR_INTR_EN_MAC4) { |
---|
2662 | single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 4); |
---|
2663 | if (single_ret == IRQ_HANDLED) |
---|
2664 | ret = IRQ_HANDLED; |
---|
2665 | } |
---|
2666 | if (pending & ERR_INTR_EN_MAC5) { |
---|
2667 | single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 5); |
---|
2668 | if (single_ret == IRQ_HANDLED) |
---|
2669 | ret = IRQ_HANDLED; |
---|
2670 | } |
---|
2671 | if (pending & ERR_INTR_EN_MAC6) { |
---|
2672 | single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 6); |
---|
2673 | if (single_ret == IRQ_HANDLED) |
---|
2674 | ret = IRQ_HANDLED; |
---|
2675 | } |
---|
2676 | if (pending & ERR_INTR_EN_MAC7) { |
---|
2677 | single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 7); |
---|
2678 | if (single_ret == IRQ_HANDLED) |
---|
2679 | ret = IRQ_HANDLED; |
---|
2680 | } |
---|
2681 | if (pending & ERR_INTR_EN_MAC8) { |
---|
2682 | single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 8); |
---|
2683 | if (single_ret == IRQ_HANDLED) |
---|
2684 | ret = IRQ_HANDLED; |
---|
2685 | } |
---|
2686 | if (pending & ERR_INTR_EN_MAC9) { |
---|
2687 | single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 9); |
---|
2688 | if (single_ret == IRQ_HANDLED) |
---|
2689 | ret = IRQ_HANDLED; |
---|
2690 | } |
---|
2691 | |
---|
2692 | return ret; |
---|
2693 | } |
---|
2694 | |
---|
2695 | static irqreturn_t fman_irq(int irq, void *handle) |
---|
2696 | { |
---|
2697 | struct fman *fman = (struct fman *)handle; |
---|
2698 | u32 pending; |
---|
2699 | struct fman_fpm_regs __iomem *fpm_rg; |
---|
2700 | irqreturn_t single_ret, ret = IRQ_NONE; |
---|
2701 | |
---|
2702 | if (!is_init_done(fman->cfg)) |
---|
2703 | return IRQ_NONE; |
---|
2704 | |
---|
2705 | fpm_rg = fman->fpm_regs; |
---|
2706 | |
---|
2707 | /* normal interrupts */ |
---|
2708 | pending = ioread32be(&fpm_rg->fm_npi); |
---|
2709 | if (!pending) |
---|
2710 | return IRQ_NONE; |
---|
2711 | |
---|
2712 | if (pending & INTR_EN_QMI) { |
---|
2713 | single_ret = qmi_event(fman); |
---|
2714 | if (single_ret == IRQ_HANDLED) |
---|
2715 | ret = IRQ_HANDLED; |
---|
2716 | } |
---|
2717 | |
---|
2718 | /* MAC interrupts */ |
---|
2719 | if (pending & INTR_EN_MAC0) { |
---|
2720 | single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 0); |
---|
2721 | if (single_ret == IRQ_HANDLED) |
---|
2722 | ret = IRQ_HANDLED; |
---|
2723 | } |
---|
2724 | if (pending & INTR_EN_MAC1) { |
---|
2725 | single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 1); |
---|
2726 | if (single_ret == IRQ_HANDLED) |
---|
2727 | ret = IRQ_HANDLED; |
---|
2728 | } |
---|
2729 | if (pending & INTR_EN_MAC2) { |
---|
2730 | single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 2); |
---|
2731 | if (single_ret == IRQ_HANDLED) |
---|
2732 | ret = IRQ_HANDLED; |
---|
2733 | } |
---|
2734 | if (pending & INTR_EN_MAC3) { |
---|
2735 | single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 3); |
---|
2736 | if (single_ret == IRQ_HANDLED) |
---|
2737 | ret = IRQ_HANDLED; |
---|
2738 | } |
---|
2739 | if (pending & INTR_EN_MAC4) { |
---|
2740 | single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 4); |
---|
2741 | if (single_ret == IRQ_HANDLED) |
---|
2742 | ret = IRQ_HANDLED; |
---|
2743 | } |
---|
2744 | if (pending & INTR_EN_MAC5) { |
---|
2745 | single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 5); |
---|
2746 | if (single_ret == IRQ_HANDLED) |
---|
2747 | ret = IRQ_HANDLED; |
---|
2748 | } |
---|
2749 | if (pending & INTR_EN_MAC6) { |
---|
2750 | single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 6); |
---|
2751 | if (single_ret == IRQ_HANDLED) |
---|
2752 | ret = IRQ_HANDLED; |
---|
2753 | } |
---|
2754 | if (pending & INTR_EN_MAC7) { |
---|
2755 | single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 7); |
---|
2756 | if (single_ret == IRQ_HANDLED) |
---|
2757 | ret = IRQ_HANDLED; |
---|
2758 | } |
---|
2759 | if (pending & INTR_EN_MAC8) { |
---|
2760 | single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 8); |
---|
2761 | if (single_ret == IRQ_HANDLED) |
---|
2762 | ret = IRQ_HANDLED; |
---|
2763 | } |
---|
2764 | if (pending & INTR_EN_MAC9) { |
---|
2765 | single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 9); |
---|
2766 | if (single_ret == IRQ_HANDLED) |
---|
2767 | ret = IRQ_HANDLED; |
---|
2768 | } |
---|
2769 | |
---|
2770 | return ret; |
---|
2771 | } |
---|
2772 | |
---|
2773 | #ifndef __rtems__ |
---|
2774 | static const struct of_device_id fman_muram_match[] = { |
---|
2775 | { |
---|
2776 | .compatible = "fsl,fman-muram"}, |
---|
2777 | {} |
---|
2778 | }; |
---|
2779 | MODULE_DEVICE_TABLE(of, fman_muram_match); |
---|
2780 | #endif /* __rtems__ */ |
---|
2781 | |
---|
2782 | static struct fman *read_dts_node(struct platform_device *of_dev) |
---|
2783 | { |
---|
2784 | struct fman *fman; |
---|
2785 | #ifndef __rtems__ |
---|
2786 | struct device_node *fm_node, *muram_node; |
---|
2787 | struct resource *res; |
---|
2788 | #else /* __rtems__ */ |
---|
2789 | const char *fdt = bsp_fdt_get(); |
---|
2790 | struct device_node *fm_node; |
---|
2791 | #endif /* __rtems__ */ |
---|
2792 | u32 val, range[2]; |
---|
2793 | int err, irq; |
---|
2794 | #ifndef __rtems__ |
---|
2795 | struct clk *clk; |
---|
2796 | u32 clk_rate; |
---|
2797 | #endif /* __rtems__ */ |
---|
2798 | phys_addr_t phys_base_addr; |
---|
2799 | #ifndef __rtems__ |
---|
2800 | resource_size_t mem_size; |
---|
2801 | #endif /* __rtems__ */ |
---|
2802 | |
---|
2803 | fman = kzalloc(sizeof(*fman), GFP_KERNEL); |
---|
2804 | if (!fman) |
---|
2805 | return NULL; |
---|
2806 | |
---|
2807 | fm_node = of_node_get(of_dev->dev.of_node); |
---|
2808 | |
---|
2809 | err = of_property_read_u32(fm_node, "cell-index", &val); |
---|
2810 | if (err) { |
---|
2811 | dev_err(&of_dev->dev, "%s: failed to read cell-index for %s\n", |
---|
2812 | __func__, fm_node->full_name); |
---|
2813 | goto fman_node_put; |
---|
2814 | } |
---|
2815 | fman->dts_params.id = (u8)val; |
---|
2816 | |
---|
2817 | #ifndef __rtems__ |
---|
2818 | /* Get the FM interrupt */ |
---|
2819 | res = platform_get_resource(of_dev, IORESOURCE_IRQ, 0); |
---|
2820 | if (!res) { |
---|
2821 | dev_err(&of_dev->dev, "%s: Can't get FMan IRQ resource\n", |
---|
2822 | __func__); |
---|
2823 | goto fman_node_put; |
---|
2824 | } |
---|
2825 | irq = res->start; |
---|
2826 | |
---|
2827 | /* Get the FM error interrupt */ |
---|
2828 | res = platform_get_resource(of_dev, IORESOURCE_IRQ, 1); |
---|
2829 | if (!res) { |
---|
2830 | dev_err(&of_dev->dev, "%s: Can't get FMan Error IRQ resource\n", |
---|
2831 | __func__); |
---|
2832 | goto fman_node_put; |
---|
2833 | } |
---|
2834 | fman->dts_params.err_irq = res->start; |
---|
2835 | |
---|
2836 | /* Get the FM address */ |
---|
2837 | res = platform_get_resource(of_dev, IORESOURCE_MEM, 0); |
---|
2838 | if (!res) { |
---|
2839 | dev_err(&of_dev->dev, "%s: Can't get FMan memory resource\n", |
---|
2840 | __func__); |
---|
2841 | goto fman_node_put; |
---|
2842 | } |
---|
2843 | |
---|
2844 | phys_base_addr = res->start; |
---|
2845 | mem_size = resource_size(res); |
---|
2846 | |
---|
2847 | #else /* __rtems__ */ |
---|
2848 | irq = of_irq_to_resource(fm_node, 0, NULL); |
---|
2849 | fman->dts_params.err_irq = of_irq_to_resource(fm_node, 1, NULL); |
---|
2850 | phys_base_addr = of_dev->dev.base; |
---|
2851 | fman->dts_params.base_addr = (void *)(uintptr_t)phys_base_addr; |
---|
2852 | #endif /* __rtems__ */ |
---|
2853 | |
---|
2854 | #ifndef __rtems__ |
---|
2855 | clk = of_clk_get(fm_node, 0); |
---|
2856 | if (IS_ERR(clk)) { |
---|
2857 | dev_err(&of_dev->dev, "%s: Failed to get FM%d clock structure\n", |
---|
2858 | __func__, fman->dts_params.id); |
---|
2859 | goto fman_node_put; |
---|
2860 | } |
---|
2861 | |
---|
2862 | clk_rate = clk_get_rate(clk); |
---|
2863 | if (!clk_rate) { |
---|
2864 | dev_err(&of_dev->dev, "%s: Failed to determine FM%d clock rate\n", |
---|
2865 | __func__, fman->dts_params.id); |
---|
2866 | goto fman_node_put; |
---|
2867 | } |
---|
2868 | /* Rounding to MHz */ |
---|
2869 | fman->dts_params.clk_freq = DIV_ROUND_UP(clk_rate, 1000000); |
---|
2870 | #else /* __rtems__ */ |
---|
2871 | /* FIXME */ |
---|
2872 | fman->dts_params.clk_freq = 733; |
---|
2873 | #endif /* __rtems__ */ |
---|
2874 | |
---|
2875 | err = of_property_read_u32_array(fm_node, "fsl,qman-channel-range", |
---|
2876 | &range[0], 2); |
---|
2877 | if (err) { |
---|
2878 | dev_err(&of_dev->dev, "%s: failed to read fsl,qman-channel-range for %s\n", |
---|
2879 | __func__, fm_node->full_name); |
---|
2880 | goto fman_node_put; |
---|
2881 | } |
---|
2882 | fman->dts_params.qman_channel_base = range[0]; |
---|
2883 | fman->dts_params.num_of_qman_channels = range[1]; |
---|
2884 | |
---|
2885 | /* Get the MURAM base address and size */ |
---|
2886 | #ifndef __rtems__ |
---|
2887 | /* FIXME */ |
---|
2888 | muram_node = of_find_matching_node(fm_node, fman_muram_match); |
---|
2889 | if (!muram_node) { |
---|
2890 | dev_err(&of_dev->dev, "%s: could not find MURAM node\n", |
---|
2891 | __func__); |
---|
2892 | goto fman_node_put; |
---|
2893 | } |
---|
2894 | |
---|
2895 | err = of_address_to_resource(muram_node, 0, |
---|
2896 | &fman->dts_params.muram_res); |
---|
2897 | if (err) { |
---|
2898 | of_node_put(muram_node); |
---|
2899 | dev_err(&of_dev->dev, "%s: of_address_to_resource() = %d\n", |
---|
2900 | __func__, err); |
---|
2901 | goto fman_node_put; |
---|
2902 | } |
---|
2903 | #else /* __rtems__ */ |
---|
2904 | { |
---|
2905 | int node = fdt_node_offset_by_compatible(fdt, |
---|
2906 | fm_node->offset, "fsl,fman-muram"); |
---|
2907 | struct device_node muram_node = { |
---|
2908 | .offset = node |
---|
2909 | }; |
---|
2910 | struct resource res; |
---|
2911 | |
---|
2912 | err = of_address_to_resource(&muram_node, 0, &res); |
---|
2913 | if (err != 0) { |
---|
2914 | pr_err("could not find MURAM node\n"); |
---|
2915 | goto fman_node_put; |
---|
2916 | } |
---|
2917 | fman->dts_params.muram_res.start = phys_base_addr + res.start; |
---|
2918 | fman->dts_params.muram_res.end = phys_base_addr + res.end - 1; |
---|
2919 | } |
---|
2920 | #endif /* __rtems__ */ |
---|
2921 | #ifndef __rtems__ |
---|
2922 | of_node_put(muram_node); |
---|
2923 | #endif /* __rtems__ */ |
---|
2924 | |
---|
2925 | err = devm_request_irq(&of_dev->dev, irq, fman_irq, 0, "fman", fman); |
---|
2926 | if (err < 0) { |
---|
2927 | dev_err(&of_dev->dev, "%s: irq %d allocation failed (error = %d)\n", |
---|
2928 | __func__, irq, err); |
---|
2929 | goto fman_free; |
---|
2930 | } |
---|
2931 | |
---|
2932 | if (fman->dts_params.err_irq != 0) { |
---|
2933 | err = devm_request_irq(&of_dev->dev, fman->dts_params.err_irq, |
---|
2934 | fman_err_irq, IRQF_SHARED, |
---|
2935 | "fman-err", fman); |
---|
2936 | if (err < 0) { |
---|
2937 | dev_err(&of_dev->dev, "%s: irq %d allocation failed (error = %d)\n", |
---|
2938 | __func__, fman->dts_params.err_irq, err); |
---|
2939 | goto fman_free; |
---|
2940 | } |
---|
2941 | } |
---|
2942 | |
---|
2943 | #ifndef __rtems__ |
---|
2944 | fman->dts_params.res = |
---|
2945 | devm_request_mem_region(&of_dev->dev, phys_base_addr, |
---|
2946 | mem_size, "fman"); |
---|
2947 | if (!fman->dts_params.res) { |
---|
2948 | dev_err(&of_dev->dev, "%s: request_mem_region() failed\n", |
---|
2949 | __func__); |
---|
2950 | goto fman_free; |
---|
2951 | } |
---|
2952 | |
---|
2953 | fman->dts_params.base_addr = |
---|
2954 | devm_ioremap(&of_dev->dev, phys_base_addr, mem_size); |
---|
2955 | if (!fman->dts_params.base_addr) { |
---|
2956 | dev_err(&of_dev->dev, "%s: devm_ioremap() failed\n", __func__); |
---|
2957 | goto fman_free; |
---|
2958 | } |
---|
2959 | |
---|
2960 | fman->dev = &of_dev->dev; |
---|
2961 | |
---|
2962 | err = of_platform_populate(fm_node, NULL, NULL, &of_dev->dev); |
---|
2963 | if (err) { |
---|
2964 | dev_err(&of_dev->dev, "%s: of_platform_populate() failed\n", |
---|
2965 | __func__); |
---|
2966 | goto fman_free; |
---|
2967 | } |
---|
2968 | #endif /* __rtems__ */ |
---|
2969 | |
---|
2970 | return fman; |
---|
2971 | |
---|
2972 | fman_node_put: |
---|
2973 | of_node_put(fm_node); |
---|
2974 | fman_free: |
---|
2975 | kfree(fman); |
---|
2976 | return NULL; |
---|
2977 | } |
---|
2978 | |
---|
2979 | static int fman_probe(struct platform_device *of_dev) |
---|
2980 | { |
---|
2981 | struct fman *fman; |
---|
2982 | struct device *dev; |
---|
2983 | int err; |
---|
2984 | |
---|
2985 | dev = &of_dev->dev; |
---|
2986 | |
---|
2987 | fman = read_dts_node(of_dev); |
---|
2988 | if (!fman) |
---|
2989 | return -EIO; |
---|
2990 | |
---|
2991 | err = fman_config(fman); |
---|
2992 | if (err) { |
---|
2993 | dev_err(dev, "%s: FMan config failed\n", __func__); |
---|
2994 | return -EINVAL; |
---|
2995 | } |
---|
2996 | |
---|
2997 | if (fman_init(fman) != 0) { |
---|
2998 | dev_err(dev, "%s: FMan init failed\n", __func__); |
---|
2999 | return -EINVAL; |
---|
3000 | } |
---|
3001 | |
---|
3002 | if (fman->dts_params.err_irq == 0) { |
---|
3003 | fman_set_exception(fman, FMAN_EX_DMA_BUS_ERROR, false); |
---|
3004 | fman_set_exception(fman, FMAN_EX_DMA_READ_ECC, false); |
---|
3005 | fman_set_exception(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC, false); |
---|
3006 | fman_set_exception(fman, FMAN_EX_DMA_FM_WRITE_ECC, false); |
---|
3007 | fman_set_exception(fman, FMAN_EX_DMA_SINGLE_PORT_ECC, false); |
---|
3008 | fman_set_exception(fman, FMAN_EX_FPM_STALL_ON_TASKS, false); |
---|
3009 | fman_set_exception(fman, FMAN_EX_FPM_SINGLE_ECC, false); |
---|
3010 | fman_set_exception(fman, FMAN_EX_FPM_DOUBLE_ECC, false); |
---|
3011 | fman_set_exception(fman, FMAN_EX_QMI_SINGLE_ECC, false); |
---|
3012 | fman_set_exception(fman, FMAN_EX_QMI_DOUBLE_ECC, false); |
---|
3013 | fman_set_exception(fman, |
---|
3014 | FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID, false); |
---|
3015 | fman_set_exception(fman, FMAN_EX_BMI_LIST_RAM_ECC, false); |
---|
3016 | fman_set_exception(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC, |
---|
3017 | false); |
---|
3018 | fman_set_exception(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC, false); |
---|
3019 | fman_set_exception(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC, false); |
---|
3020 | } |
---|
3021 | |
---|
3022 | dev_set_drvdata(dev, fman); |
---|
3023 | |
---|
3024 | dev_dbg(dev, "FMan%d probed\n", fman->dts_params.id); |
---|
3025 | |
---|
3026 | return 0; |
---|
3027 | } |
---|
3028 | |
---|
3029 | #ifndef __rtems__ |
---|
3030 | static const struct of_device_id fman_match[] = { |
---|
3031 | { |
---|
3032 | .compatible = "fsl,fman"}, |
---|
3033 | {} |
---|
3034 | }; |
---|
3035 | |
---|
3036 | MODULE_DEVICE_TABLE(of, fman_match); |
---|
3037 | |
---|
3038 | static struct platform_driver fman_driver = { |
---|
3039 | .driver = { |
---|
3040 | .name = "fsl-fman", |
---|
3041 | .of_match_table = fman_match, |
---|
3042 | }, |
---|
3043 | .probe = fman_probe, |
---|
3044 | }; |
---|
3045 | |
---|
3046 | static int __init fman_load(void) |
---|
3047 | { |
---|
3048 | int err; |
---|
3049 | |
---|
3050 | pr_debug("FSL DPAA FMan driver\n"); |
---|
3051 | |
---|
3052 | err = platform_driver_register(&fman_driver); |
---|
3053 | if (err < 0) |
---|
3054 | pr_err("Error, platform_driver_register() = %d\n", err); |
---|
3055 | |
---|
3056 | return err; |
---|
3057 | } |
---|
3058 | module_init(fman_load); |
---|
3059 | |
---|
3060 | static void __exit fman_unload(void) |
---|
3061 | { |
---|
3062 | platform_driver_unregister(&fman_driver); |
---|
3063 | } |
---|
3064 | module_exit(fman_unload); |
---|
3065 | |
---|
3066 | MODULE_LICENSE("Dual BSD/GPL"); |
---|
3067 | MODULE_DESCRIPTION("Freescale DPAA Frame Manager driver"); |
---|
3068 | #else /* __rtems__ */ |
---|
3069 | #include <sys/cdefs.h> |
---|
3070 | #include <sys/param.h> |
---|
3071 | #include <sys/systm.h> |
---|
3072 | #include <sys/bus.h> |
---|
3073 | #include <sys/kernel.h> |
---|
3074 | |
---|
3075 | int |
---|
3076 | fman_reset(struct fman *fman) |
---|
3077 | { |
---|
3078 | |
---|
3079 | /* |
---|
3080 | * Ignore errata A007273, since we do not disable the Ethernet MAC |
---|
3081 | * clocks. |
---|
3082 | */ |
---|
3083 | |
---|
3084 | out_be32(&fman->fpm_regs->fm_rstc, FPM_RSTC_FM_RESET); |
---|
3085 | /* Memory barrier */ |
---|
3086 | mb(); |
---|
3087 | usleep_range(100, 300); |
---|
3088 | |
---|
3089 | if (!!(ioread32be(&fman->qmi_regs->fmqm_gs) & |
---|
3090 | QMI_GS_HALT_NOT_BUSY)) { |
---|
3091 | usleep_range(100, 300); |
---|
3092 | } |
---|
3093 | |
---|
3094 | return (0); |
---|
3095 | } |
---|
3096 | |
---|
3097 | struct fman_softc { |
---|
3098 | struct platform_device of_dev; |
---|
3099 | struct device_node dn; |
---|
3100 | }; |
---|
3101 | |
---|
3102 | static int |
---|
3103 | fman_dev_probe_fdt(struct fman_softc *sc, int unit) |
---|
3104 | { |
---|
3105 | const char *fdt = bsp_fdt_get(); |
---|
3106 | const char *name = "fsl,fman"; |
---|
3107 | int node = 0; |
---|
3108 | |
---|
3109 | while (1) { |
---|
3110 | node = fdt_node_offset_by_compatible(fdt, node, name); |
---|
3111 | if (node >= 0) { |
---|
3112 | int len; |
---|
3113 | const fdt32_t *p = fdt_getprop(fdt, node, "cell-index", &len); |
---|
3114 | |
---|
3115 | if (p != NULL && len == sizeof(*p)) { |
---|
3116 | if (fdt32_to_cpu(*p) == (uint32_t)unit) { |
---|
3117 | sc->dn.offset = node; |
---|
3118 | sc->dn.full_name = name; |
---|
3119 | sc->of_dev.dev.of_node = &sc->dn; |
---|
3120 | #if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) |
---|
3121 | sc->of_dev.dev.base = (uintptr_t)&qoriq.fman[unit]; |
---|
3122 | #endif |
---|
3123 | return (BUS_PROBE_DEFAULT); |
---|
3124 | } |
---|
3125 | } else { |
---|
3126 | return (ENXIO); |
---|
3127 | } |
---|
3128 | } else { |
---|
3129 | return (ENXIO); |
---|
3130 | } |
---|
3131 | } |
---|
3132 | } |
---|
3133 | |
---|
3134 | static int |
---|
3135 | fman_dev_probe(device_t dev) |
---|
3136 | { |
---|
3137 | struct fman_softc *sc = device_get_softc(dev); |
---|
3138 | |
---|
3139 | device_set_desc(dev, "FMan"); |
---|
3140 | |
---|
3141 | return (fman_dev_probe_fdt(sc, device_get_unit(dev))); |
---|
3142 | } |
---|
3143 | |
---|
3144 | static int |
---|
3145 | fman_dev_attach(device_t dev) |
---|
3146 | { |
---|
3147 | const char *fdt = bsp_fdt_get(); |
---|
3148 | struct fman_softc *sc = device_get_softc(dev); |
---|
3149 | int node; |
---|
3150 | int err; |
---|
3151 | |
---|
3152 | err = fman_probe(&sc->of_dev); |
---|
3153 | if (err != 0) { |
---|
3154 | return (ENXIO); |
---|
3155 | } |
---|
3156 | |
---|
3157 | node = fdt_first_subnode(fdt, sc->dn.offset); |
---|
3158 | while (node >= 0) { |
---|
3159 | struct fman_ivars *ivars = |
---|
3160 | kzalloc(sizeof(*ivars), GFP_KERNEL); |
---|
3161 | device_t child; |
---|
3162 | |
---|
3163 | if (ivars == NULL) { |
---|
3164 | return (ENOMEM); |
---|
3165 | } |
---|
3166 | |
---|
3167 | ivars->dn.offset = node; |
---|
3168 | ivars->of_dev.dev.of_node = &ivars->dn; |
---|
3169 | ivars->of_dev.dev.base = sc->of_dev.dev.base; |
---|
3170 | ivars->fman = dev_get_drvdata(&sc->of_dev.dev); |
---|
3171 | |
---|
3172 | child = device_add_child(dev, NULL, -1); |
---|
3173 | if (child == NULL) { |
---|
3174 | kfree(ivars); |
---|
3175 | return (ENOMEM); |
---|
3176 | } |
---|
3177 | |
---|
3178 | device_set_ivars(child, ivars); |
---|
3179 | |
---|
3180 | err = device_probe_and_attach(child); |
---|
3181 | if (err != 0) { |
---|
3182 | kfree(ivars); |
---|
3183 | } |
---|
3184 | |
---|
3185 | node = fdt_next_subnode(fdt, node); |
---|
3186 | } |
---|
3187 | |
---|
3188 | return (0); |
---|
3189 | } |
---|
3190 | |
---|
3191 | static int |
---|
3192 | fman_dev_detach(device_t dev) |
---|
3193 | { |
---|
3194 | struct fman_softc *sc = device_get_softc(dev); |
---|
3195 | int err; |
---|
3196 | |
---|
3197 | err = bus_generic_detach(dev); |
---|
3198 | if (err == 0) { |
---|
3199 | fman_reset(dev_get_drvdata(&sc->of_dev.dev)); |
---|
3200 | } |
---|
3201 | |
---|
3202 | return (err); |
---|
3203 | } |
---|
3204 | |
---|
3205 | static device_method_t fman_methods[] = { |
---|
3206 | /* Device interface */ |
---|
3207 | DEVMETHOD(device_probe, fman_dev_probe), |
---|
3208 | DEVMETHOD(device_attach, fman_dev_attach), |
---|
3209 | DEVMETHOD(device_detach, fman_dev_detach), |
---|
3210 | DEVMETHOD(device_suspend, bus_generic_suspend), |
---|
3211 | DEVMETHOD(device_resume, bus_generic_resume), |
---|
3212 | DEVMETHOD(device_shutdown, bus_generic_shutdown), |
---|
3213 | |
---|
3214 | DEVMETHOD_END |
---|
3215 | }; |
---|
3216 | |
---|
3217 | driver_t fman_driver = { |
---|
3218 | .name = "fman", |
---|
3219 | .methods = fman_methods, |
---|
3220 | .size = sizeof(struct fman_softc), |
---|
3221 | }; |
---|
3222 | |
---|
3223 | static devclass_t fman_devclass; |
---|
3224 | |
---|
3225 | DRIVER_MODULE(fman, nexus, fman_driver, fman_devclass, 0, 0); |
---|
3226 | #endif /* __rtems__ */ |
---|