1 | #include <machine/rtems-bsd-kernel-space.h> |
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2 | |
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3 | #include <rtems/bsd/local/opt_dpaa.h> |
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4 | |
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5 | /* |
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6 | * Copyright 2008-2015 Freescale Semiconductor Inc. |
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7 | * |
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8 | * Redistribution and use in source and binary forms, with or without |
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9 | * modification, are permitted provided that the following conditions are met: |
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10 | * * Redistributions of source code must retain the above copyright |
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11 | * notice, this list of conditions and the following disclaimer. |
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12 | * * Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * * Neither the name of Freescale Semiconductor nor the |
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16 | * names of its contributors may be used to endorse or promote products |
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17 | * derived from this software without specific prior written permission. |
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18 | * |
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19 | // * |
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20 | * ALTERNATIVELY, this software may be distributed under the terms of the |
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21 | * GNU General Public License ("GPL") as published by the Free Software |
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22 | * Foundation, either version 2 of that License or (at your option) any |
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23 | * later version. |
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24 | * |
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25 | * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
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26 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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27 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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28 | * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
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29 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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30 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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31 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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32 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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33 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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34 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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35 | */ |
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36 | |
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37 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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38 | |
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39 | #include "fman.h" |
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40 | #include "fman_muram.h" |
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41 | #include <asm/mpc85xx.h> |
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42 | |
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43 | #include <linux/slab.h> |
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44 | #include <linux/delay.h> |
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45 | #include <linux/module.h> |
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46 | #include <linux/of_platform.h> |
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47 | #include <linux/clk.h> |
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48 | #include <linux/of_address.h> |
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49 | #include <linux/of_irq.h> |
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50 | #include <linux/interrupt.h> |
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51 | #ifdef __rtems__ |
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52 | #include <bsp/fdt.h> |
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53 | #include <bsp/qoriq.h> |
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54 | #endif /* __rtems__ */ |
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55 | |
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56 | |
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57 | /* General defines */ |
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58 | #define FMAN_LIODN_TBL 64 /* size of LIODN table */ |
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59 | #define MAX_NUM_OF_MACS 10 |
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60 | #define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4 |
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61 | #define BASE_RX_PORTID 0x08 |
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62 | #define BASE_TX_PORTID 0x28 |
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63 | |
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64 | /* Modules registers offsets */ |
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65 | #define BMI_OFFSET 0x00080000 |
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66 | #define QMI_OFFSET 0x00080400 |
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67 | #define DMA_OFFSET 0x000C2000 |
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68 | #define FPM_OFFSET 0x000C3000 |
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69 | #define IMEM_OFFSET 0x000C4000 |
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70 | #define CGP_OFFSET 0x000DB000 |
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71 | |
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72 | /* Exceptions bit map */ |
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73 | #define EX_DMA_BUS_ERROR 0x80000000 |
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74 | #define EX_DMA_READ_ECC 0x40000000 |
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75 | #define EX_DMA_SYSTEM_WRITE_ECC 0x20000000 |
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76 | #define EX_DMA_FM_WRITE_ECC 0x10000000 |
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77 | #define EX_FPM_STALL_ON_TASKS 0x08000000 |
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78 | #define EX_FPM_SINGLE_ECC 0x04000000 |
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79 | #define EX_FPM_DOUBLE_ECC 0x02000000 |
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80 | #define EX_QMI_SINGLE_ECC 0x01000000 |
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81 | #define EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000 |
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82 | #define EX_QMI_DOUBLE_ECC 0x00400000 |
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83 | #define EX_BMI_LIST_RAM_ECC 0x00200000 |
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84 | #define EX_BMI_STORAGE_PROFILE_ECC 0x00100000 |
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85 | #define EX_BMI_STATISTICS_RAM_ECC 0x00080000 |
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86 | #define EX_IRAM_ECC 0x00040000 |
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87 | #define EX_MURAM_ECC 0x00020000 |
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88 | #define EX_BMI_DISPATCH_RAM_ECC 0x00010000 |
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89 | #define EX_DMA_SINGLE_PORT_ECC 0x00008000 |
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90 | |
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91 | #define DFLT_EXCEPTIONS \ |
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92 | ((EX_DMA_BUS_ERROR) | \ |
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93 | (EX_DMA_READ_ECC) | \ |
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94 | (EX_DMA_SYSTEM_WRITE_ECC) | \ |
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95 | (EX_DMA_FM_WRITE_ECC) | \ |
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96 | (EX_FPM_STALL_ON_TASKS) | \ |
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97 | (EX_FPM_SINGLE_ECC) | \ |
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98 | (EX_FPM_DOUBLE_ECC) | \ |
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99 | (EX_QMI_DEQ_FROM_UNKNOWN_PORTID) | \ |
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100 | (EX_BMI_LIST_RAM_ECC) | \ |
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101 | (EX_BMI_STORAGE_PROFILE_ECC) | \ |
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102 | (EX_BMI_STATISTICS_RAM_ECC) | \ |
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103 | (EX_MURAM_ECC) | \ |
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104 | (EX_BMI_DISPATCH_RAM_ECC) | \ |
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105 | (EX_QMI_DOUBLE_ECC) | \ |
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106 | (EX_QMI_SINGLE_ECC)) |
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107 | |
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108 | /* DMA defines */ |
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109 | /* masks */ |
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110 | #define DMA_MODE_AID_OR 0x20000000 |
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111 | #define DMA_MODE_SBER 0x10000000 |
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112 | #define DMA_MODE_BER 0x00200000 |
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113 | #define DMA_MODE_ECC 0x00000020 |
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114 | #define DMA_MODE_SECURE_PROT 0x00000800 |
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115 | #define DMA_MODE_EMER_READ 0x00080000 |
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116 | #define DMA_MODE_AXI_DBG_MASK 0x0F000000 |
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117 | |
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118 | #define DMA_TRANSFER_PORTID_MASK 0xFF000000 |
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119 | #define DMA_TRANSFER_TNUM_MASK 0x00FF0000 |
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120 | #define DMA_TRANSFER_LIODN_MASK 0x00000FFF |
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121 | |
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122 | #define DMA_STATUS_BUS_ERR 0x08000000 |
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123 | #define DMA_STATUS_READ_ECC 0x04000000 |
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124 | #define DMA_STATUS_SYSTEM_WRITE_ECC 0x02000000 |
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125 | #define DMA_STATUS_FM_WRITE_ECC 0x01000000 |
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126 | #define DMA_STATUS_FM_SPDAT_ECC 0x00080000 |
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127 | |
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128 | #define DMA_MODE_CACHE_OR_SHIFT 30 |
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129 | #define DMA_MODE_AXI_DBG_SHIFT 24 |
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130 | #define DMA_MODE_CEN_SHIFT 13 |
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131 | #define DMA_MODE_CEN_MASK 0x00000007 |
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132 | #define DMA_MODE_DBG_SHIFT 7 |
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133 | #define DMA_MODE_EMER_LVL_SHIFT 6 |
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134 | #define DMA_MODE_AID_MODE_SHIFT 4 |
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135 | |
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136 | #define DMA_THRESH_COMMQ_SHIFT 24 |
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137 | #define DMA_THRESH_READ_INT_BUF_SHIFT 16 |
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138 | #define DMA_THRESH_READ_INT_BUF_MASK 0x0000003f |
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139 | #define DMA_THRESH_WRITE_INT_BUF_MASK 0x0000003f |
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140 | |
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141 | #define DMA_TRANSFER_PORTID_SHIFT 24 |
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142 | #define DMA_TRANSFER_TNUM_SHIFT 16 |
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143 | |
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144 | #define DMA_CAM_SIZEOF_ENTRY 0x40 |
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145 | #define DMA_CAM_UNITS 8 |
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146 | |
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147 | #define DMA_LIODN_SHIFT 16 |
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148 | #define DMA_LIODN_BASE_MASK 0x00000FFF |
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149 | |
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150 | /* FPM defines */ |
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151 | #define FPM_EV_MASK_DOUBLE_ECC 0x80000000 |
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152 | #define FPM_EV_MASK_STALL 0x40000000 |
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153 | #define FPM_EV_MASK_SINGLE_ECC 0x20000000 |
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154 | #define FPM_EV_MASK_RELEASE_FM 0x00010000 |
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155 | #define FPM_EV_MASK_DOUBLE_ECC_EN 0x00008000 |
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156 | #define FPM_EV_MASK_STALL_EN 0x00004000 |
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157 | #define FPM_EV_MASK_SINGLE_ECC_EN 0x00002000 |
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158 | #define FPM_EV_MASK_EXTERNAL_HALT 0x00000008 |
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159 | #define FPM_EV_MASK_ECC_ERR_HALT 0x00000004 |
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160 | |
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161 | #define FPM_RAM_MURAM_ECC 0x00008000 |
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162 | #define FPM_RAM_IRAM_ECC 0x00004000 |
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163 | #define FPM_RAM_MURAM_TEST_ECC 0x20000000 |
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164 | #define FPM_RAM_IRAM_TEST_ECC 0x10000000 |
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165 | #define FPM_IRAM_ECC_ERR_EX_EN 0x00020000 |
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166 | #define FPM_MURAM_ECC_ERR_EX_EN 0x00040000 |
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167 | #define FPM_RAM_IRAM_ECC_EN 0x40000000 |
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168 | #define FPM_RAM_RAMS_ECC_EN 0x80000000 |
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169 | #define FPM_RAM_RAMS_ECC_EN_SRC_SEL 0x08000000 |
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170 | |
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171 | #define FPM_REV1_MAJOR_MASK 0x0000FF00 |
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172 | #define FPM_REV1_MINOR_MASK 0x000000FF |
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173 | |
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174 | #define FPM_DISP_LIMIT_SHIFT 24 |
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175 | |
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176 | #define FPM_PRT_FM_CTL1 0x00000001 |
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177 | #define FPM_PRT_FM_CTL2 0x00000002 |
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178 | #define FPM_PORT_FM_CTL_PORTID_SHIFT 24 |
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179 | #define FPM_PRC_ORA_FM_CTL_SEL_SHIFT 16 |
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180 | |
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181 | #define FPM_THR1_PRS_SHIFT 24 |
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182 | #define FPM_THR1_KG_SHIFT 16 |
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183 | #define FPM_THR1_PLCR_SHIFT 8 |
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184 | #define FPM_THR1_BMI_SHIFT 0 |
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185 | |
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186 | #define FPM_THR2_QMI_ENQ_SHIFT 24 |
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187 | #define FPM_THR2_QMI_DEQ_SHIFT 0 |
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188 | #define FPM_THR2_FM_CTL1_SHIFT 16 |
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189 | #define FPM_THR2_FM_CTL2_SHIFT 8 |
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190 | |
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191 | #define FPM_EV_MASK_CAT_ERR_SHIFT 1 |
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192 | #define FPM_EV_MASK_DMA_ERR_SHIFT 0 |
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193 | |
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194 | #define FPM_REV1_MAJOR_SHIFT 8 |
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195 | |
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196 | #define FPM_RSTC_FM_RESET 0x80000000 |
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197 | #define FPM_RSTC_MAC0_RESET 0x40000000 |
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198 | #define FPM_RSTC_MAC1_RESET 0x20000000 |
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199 | #define FPM_RSTC_MAC2_RESET 0x10000000 |
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200 | #define FPM_RSTC_MAC3_RESET 0x08000000 |
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201 | #define FPM_RSTC_MAC8_RESET 0x04000000 |
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202 | #define FPM_RSTC_MAC4_RESET 0x02000000 |
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203 | #define FPM_RSTC_MAC5_RESET 0x01000000 |
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204 | #define FPM_RSTC_MAC6_RESET 0x00800000 |
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205 | #define FPM_RSTC_MAC7_RESET 0x00400000 |
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206 | #define FPM_RSTC_MAC9_RESET 0x00200000 |
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207 | |
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208 | #define FPM_TS_INT_SHIFT 16 |
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209 | #define FPM_TS_CTL_EN 0x80000000 |
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210 | |
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211 | /* BMI defines */ |
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212 | #define BMI_INIT_START 0x80000000 |
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213 | #define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC 0x80000000 |
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214 | #define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000 |
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215 | #define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000 |
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216 | #define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000 |
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217 | #define BMI_NUM_OF_TASKS_MASK 0x3F000000 |
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218 | #define BMI_NUM_OF_EXTRA_TASKS_MASK 0x000F0000 |
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219 | #define BMI_NUM_OF_DMAS_MASK 0x00000F00 |
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220 | #define BMI_NUM_OF_EXTRA_DMAS_MASK 0x0000000F |
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221 | #define BMI_FIFO_SIZE_MASK 0x000003FF |
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222 | #define BMI_EXTRA_FIFO_SIZE_MASK 0x03FF0000 |
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223 | #define BMI_CFG2_DMAS_MASK 0x0000003F |
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224 | #define BMI_CFG2_TASKS_MASK 0x0000003F |
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225 | |
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226 | #define BMI_CFG2_TASKS_SHIFT 16 |
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227 | #define BMI_CFG2_DMAS_SHIFT 0 |
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228 | #define BMI_CFG1_FIFO_SIZE_SHIFT 16 |
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229 | #define BMI_NUM_OF_TASKS_SHIFT 24 |
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230 | #define BMI_EXTRA_NUM_OF_TASKS_SHIFT 16 |
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231 | #define BMI_NUM_OF_DMAS_SHIFT 8 |
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232 | #define BMI_EXTRA_NUM_OF_DMAS_SHIFT 0 |
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233 | |
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234 | #define BMI_FIFO_ALIGN 0x100 |
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235 | |
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236 | #define BMI_EXTRA_FIFO_SIZE_SHIFT 16 |
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237 | |
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238 | /* QMI defines */ |
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239 | #define QMI_CFG_ENQ_EN 0x80000000 |
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240 | #define QMI_CFG_DEQ_EN 0x40000000 |
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241 | #define QMI_CFG_EN_COUNTERS 0x10000000 |
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242 | #define QMI_CFG_DEQ_MASK 0x0000003F |
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243 | #define QMI_CFG_ENQ_MASK 0x00003F00 |
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244 | #define QMI_CFG_ENQ_SHIFT 8 |
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245 | |
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246 | #define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000 |
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247 | #define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000 |
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248 | #define QMI_INTR_EN_SINGLE_ECC 0x80000000 |
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249 | |
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250 | #define QMI_TAPC_TAP 22 |
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251 | |
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252 | #define QMI_GS_HALT_NOT_BUSY 0x00000002 |
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253 | |
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254 | /* IRAM defines */ |
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255 | #define IRAM_IADD_AIE 0x80000000 |
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256 | #define IRAM_READY 0x80000000 |
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257 | |
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258 | /* Default values */ |
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259 | #define DEFAULT_CATASTROPHIC_ERR 0 |
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260 | #define DEFAULT_DMA_ERR 0 |
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261 | #define DEFAULT_AID_MODE FMAN_DMA_AID_OUT_TNUM |
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262 | #define DEFAULT_DMA_COMM_Q_LOW 0x2A |
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263 | #define DEFAULT_DMA_COMM_Q_HIGH 0x3F |
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264 | #define DEFAULT_CACHE_OVERRIDE 0 |
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265 | #define DEFAULT_DMA_CAM_NUM_OF_ENTRIES 64 |
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266 | #define DEFAULT_DMA_DBG_CNT_MODE 0 |
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267 | #define DEFAULT_DMA_SOS_EMERGENCY 0 |
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268 | #define DEFAULT_DMA_WATCHDOG 0 |
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269 | #define DEFAULT_DMA_EMERGENCY_SWITCH_COUNTER 0 |
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270 | #define DEFAULT_DISP_LIMIT 0 |
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271 | #define DEFAULT_PRS_DISP_TH 16 |
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272 | #define DEFAULT_PLCR_DISP_TH 16 |
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273 | #define DEFAULT_KG_DISP_TH 16 |
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274 | #define DEFAULT_BMI_DISP_TH 16 |
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275 | #define DEFAULT_QMI_ENQ_DISP_TH 16 |
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276 | #define DEFAULT_QMI_DEQ_DISP_TH 16 |
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277 | #define DEFAULT_FM_CTL1_DISP_TH 16 |
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278 | #define DEFAULT_FM_CTL2_DISP_TH 16 |
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279 | |
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280 | #define DFLT_AXI_DBG_NUM_OF_BEATS 1 |
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281 | |
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282 | #define DFLT_DMA_READ_INT_BUF_LOW(dma_thresh_max_buf) \ |
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283 | ((dma_thresh_max_buf + 1) / 2) |
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284 | #define DFLT_DMA_READ_INT_BUF_HIGH(dma_thresh_max_buf) \ |
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285 | ((dma_thresh_max_buf + 1) * 3 / 4) |
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286 | #define DFLT_DMA_WRITE_INT_BUF_LOW(dma_thresh_max_buf) \ |
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287 | ((dma_thresh_max_buf + 1) / 2) |
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288 | #define DFLT_DMA_WRITE_INT_BUF_HIGH(dma_thresh_max_buf)\ |
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289 | ((dma_thresh_max_buf + 1) * 3 / 4) |
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290 | |
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291 | #define DMA_COMM_Q_LOW_FMAN_V3 0x2A |
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292 | #define DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq) \ |
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293 | ((dma_thresh_max_commq + 1) / 2) |
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294 | #define DFLT_DMA_COMM_Q_LOW(major, dma_thresh_max_commq) \ |
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295 | ((major == 6) ? DMA_COMM_Q_LOW_FMAN_V3 : \ |
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296 | DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq)) |
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297 | |
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298 | #define DMA_COMM_Q_HIGH_FMAN_V3 0x3f |
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299 | #define DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq) \ |
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300 | ((dma_thresh_max_commq + 1) * 3 / 4) |
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301 | #define DFLT_DMA_COMM_Q_HIGH(major, dma_thresh_max_commq) \ |
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302 | ((major == 6) ? DMA_COMM_Q_HIGH_FMAN_V3 : \ |
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303 | DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq)) |
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304 | |
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305 | #define TOTAL_NUM_OF_TASKS_FMAN_V3L 59 |
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306 | #define TOTAL_NUM_OF_TASKS_FMAN_V3H 124 |
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307 | #define DFLT_TOTAL_NUM_OF_TASKS(major, minor, bmi_max_num_of_tasks) \ |
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308 | ((major == 6) ? ((minor == 1 || minor == 4) ? \ |
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309 | TOTAL_NUM_OF_TASKS_FMAN_V3L : TOTAL_NUM_OF_TASKS_FMAN_V3H) : \ |
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310 | bmi_max_num_of_tasks) |
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311 | |
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312 | #define DMA_CAM_NUM_OF_ENTRIES_FMAN_V3 64 |
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313 | #define DMA_CAM_NUM_OF_ENTRIES_FMAN_V2 32 |
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314 | #define DFLT_DMA_CAM_NUM_OF_ENTRIES(major) \ |
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315 | (major == 6 ? DMA_CAM_NUM_OF_ENTRIES_FMAN_V3 : \ |
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316 | DMA_CAM_NUM_OF_ENTRIES_FMAN_V2) |
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317 | |
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318 | #define FM_TIMESTAMP_1_USEC_BIT 8 |
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319 | |
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320 | /* Defines used for enabling/disabling FMan interrupts */ |
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321 | #define ERR_INTR_EN_DMA 0x00010000 |
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322 | #define ERR_INTR_EN_FPM 0x80000000 |
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323 | #define ERR_INTR_EN_BMI 0x00800000 |
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324 | #define ERR_INTR_EN_QMI 0x00400000 |
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325 | #define ERR_INTR_EN_MURAM 0x00040000 |
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326 | #define ERR_INTR_EN_MAC0 0x00004000 |
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327 | #define ERR_INTR_EN_MAC1 0x00002000 |
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328 | #define ERR_INTR_EN_MAC2 0x00001000 |
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329 | #define ERR_INTR_EN_MAC3 0x00000800 |
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330 | #define ERR_INTR_EN_MAC4 0x00000400 |
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331 | #define ERR_INTR_EN_MAC5 0x00000200 |
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332 | #define ERR_INTR_EN_MAC6 0x00000100 |
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333 | #define ERR_INTR_EN_MAC7 0x00000080 |
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334 | #define ERR_INTR_EN_MAC8 0x00008000 |
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335 | #define ERR_INTR_EN_MAC9 0x00000040 |
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336 | |
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337 | #define INTR_EN_QMI 0x40000000 |
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338 | #define INTR_EN_MAC0 0x00080000 |
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339 | #define INTR_EN_MAC1 0x00040000 |
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340 | #define INTR_EN_MAC2 0x00020000 |
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341 | #define INTR_EN_MAC3 0x00010000 |
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342 | #define INTR_EN_MAC4 0x00000040 |
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343 | #define INTR_EN_MAC5 0x00000020 |
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344 | #define INTR_EN_MAC6 0x00000008 |
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345 | #define INTR_EN_MAC7 0x00000002 |
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346 | #define INTR_EN_MAC8 0x00200000 |
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347 | #define INTR_EN_MAC9 0x00100000 |
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348 | #define INTR_EN_REV0 0x00008000 |
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349 | #define INTR_EN_REV1 0x00004000 |
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350 | #define INTR_EN_REV2 0x00002000 |
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351 | #define INTR_EN_REV3 0x00001000 |
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352 | #define INTR_EN_TMR 0x01000000 |
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353 | |
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354 | enum fman_dma_aid_mode { |
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355 | FMAN_DMA_AID_OUT_PORT_ID = 0, /* 4 LSB of PORT_ID */ |
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356 | FMAN_DMA_AID_OUT_TNUM /* 4 LSB of TNUM */ |
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357 | }; |
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358 | |
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359 | struct fman_iram_regs { |
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360 | u32 iadd; /* FM IRAM instruction address register */ |
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361 | u32 idata; /* FM IRAM instruction data register */ |
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362 | u32 itcfg; /* FM IRAM timing config register */ |
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363 | u32 iready; /* FM IRAM ready register */ |
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364 | }; |
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365 | |
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366 | struct fman_fpm_regs { |
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367 | u32 fmfp_tnc; /* FPM TNUM Control 0x00 */ |
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368 | u32 fmfp_prc; /* FPM Port_ID FmCtl Association 0x04 */ |
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369 | u32 fmfp_brkc; /* FPM Breakpoint Control 0x08 */ |
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370 | u32 fmfp_mxd; /* FPM Flush Control 0x0c */ |
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371 | u32 fmfp_dist1; /* FPM Dispatch Thresholds1 0x10 */ |
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372 | u32 fmfp_dist2; /* FPM Dispatch Thresholds2 0x14 */ |
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373 | u32 fm_epi; /* FM Error Pending Interrupts 0x18 */ |
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374 | u32 fm_rie; /* FM Error Interrupt Enable 0x1c */ |
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375 | u32 fmfp_fcev[4]; /* FPM FMan-Controller Event 1-4 0x20-0x2f */ |
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376 | u32 res0030[4]; /* res 0x30 - 0x3f */ |
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377 | u32 fmfp_cee[4]; /* PM FMan-Controller Event 1-4 0x40-0x4f */ |
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378 | u32 res0050[4]; /* res 0x50-0x5f */ |
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379 | u32 fmfp_tsc1; /* FPM TimeStamp Control1 0x60 */ |
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380 | u32 fmfp_tsc2; /* FPM TimeStamp Control2 0x64 */ |
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381 | u32 fmfp_tsp; /* FPM Time Stamp 0x68 */ |
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382 | u32 fmfp_tsf; /* FPM Time Stamp Fraction 0x6c */ |
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383 | u32 fm_rcr; /* FM Rams Control 0x70 */ |
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384 | u32 fmfp_extc; /* FPM External Requests Control 0x74 */ |
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385 | u32 fmfp_ext1; /* FPM External Requests Config1 0x78 */ |
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386 | u32 fmfp_ext2; /* FPM External Requests Config2 0x7c */ |
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387 | u32 fmfp_drd[16]; /* FPM Data_Ram Data 0-15 0x80 - 0xbf */ |
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388 | u32 fmfp_dra; /* FPM Data Ram Access 0xc0 */ |
---|
389 | u32 fm_ip_rev_1; /* FM IP Block Revision 1 0xc4 */ |
---|
390 | u32 fm_ip_rev_2; /* FM IP Block Revision 2 0xc8 */ |
---|
391 | u32 fm_rstc; /* FM Reset Command 0xcc */ |
---|
392 | u32 fm_cld; /* FM Classifier Debug 0xd0 */ |
---|
393 | u32 fm_npi; /* FM Normal Pending Interrupts 0xd4 */ |
---|
394 | u32 fmfp_exte; /* FPM External Requests Enable 0xd8 */ |
---|
395 | u32 fmfp_ee; /* FPM Event&Mask 0xdc */ |
---|
396 | u32 fmfp_cev[4]; /* FPM CPU Event 1-4 0xe0-0xef */ |
---|
397 | u32 res00f0[4]; /* res 0xf0-0xff */ |
---|
398 | u32 fmfp_ps[50]; /* FPM Port Status 0x100-0x1c7 */ |
---|
399 | u32 res01c8[14]; /* res 0x1c8-0x1ff */ |
---|
400 | u32 fmfp_clfabc; /* FPM CLFABC 0x200 */ |
---|
401 | u32 fmfp_clfcc; /* FPM CLFCC 0x204 */ |
---|
402 | u32 fmfp_clfaval; /* FPM CLFAVAL 0x208 */ |
---|
403 | u32 fmfp_clfbval; /* FPM CLFBVAL 0x20c */ |
---|
404 | u32 fmfp_clfcval; /* FPM CLFCVAL 0x210 */ |
---|
405 | u32 fmfp_clfamsk; /* FPM CLFAMSK 0x214 */ |
---|
406 | u32 fmfp_clfbmsk; /* FPM CLFBMSK 0x218 */ |
---|
407 | u32 fmfp_clfcmsk; /* FPM CLFCMSK 0x21c */ |
---|
408 | u32 fmfp_clfamc; /* FPM CLFAMC 0x220 */ |
---|
409 | u32 fmfp_clfbmc; /* FPM CLFBMC 0x224 */ |
---|
410 | u32 fmfp_clfcmc; /* FPM CLFCMC 0x228 */ |
---|
411 | u32 fmfp_decceh; /* FPM DECCEH 0x22c */ |
---|
412 | u32 res0230[116]; /* res 0x230 - 0x3ff */ |
---|
413 | u32 fmfp_ts[128]; /* 0x400: FPM Task Status 0x400 - 0x5ff */ |
---|
414 | u32 res0600[0x400 - 384]; |
---|
415 | }; |
---|
416 | |
---|
417 | struct fman_bmi_regs { |
---|
418 | u32 fmbm_init; /* BMI Initialization 0x00 */ |
---|
419 | u32 fmbm_cfg1; /* BMI Configuration 1 0x04 */ |
---|
420 | u32 fmbm_cfg2; /* BMI Configuration 2 0x08 */ |
---|
421 | u32 res000c[5]; /* 0x0c - 0x1f */ |
---|
422 | u32 fmbm_ievr; /* Interrupt Event Register 0x20 */ |
---|
423 | u32 fmbm_ier; /* Interrupt Enable Register 0x24 */ |
---|
424 | u32 fmbm_ifr; /* Interrupt Force Register 0x28 */ |
---|
425 | u32 res002c[5]; /* 0x2c - 0x3f */ |
---|
426 | u32 fmbm_arb[8]; /* BMI Arbitration 0x40 - 0x5f */ |
---|
427 | u32 res0060[12]; /* 0x60 - 0x8f */ |
---|
428 | u32 fmbm_dtc[3]; /* Debug Trap Counter 0x90 - 0x9b */ |
---|
429 | u32 res009c; /* 0x9c */ |
---|
430 | u32 fmbm_dcv[3][4]; /* Debug Compare val 0xa0-0xcf */ |
---|
431 | u32 fmbm_dcm[3][4]; /* Debug Compare Mask 0xd0-0xff */ |
---|
432 | u32 fmbm_gde; /* BMI Global Debug Enable 0x100 */ |
---|
433 | u32 fmbm_pp[63]; /* BMI Port Parameters 0x104 - 0x1ff */ |
---|
434 | u32 res0200; /* 0x200 */ |
---|
435 | u32 fmbm_pfs[63]; /* BMI Port FIFO Size 0x204 - 0x2ff */ |
---|
436 | u32 res0300; /* 0x300 */ |
---|
437 | u32 fmbm_spliodn[63]; /* Port Partition ID 0x304 - 0x3ff */ |
---|
438 | }; |
---|
439 | |
---|
440 | struct fman_qmi_regs { |
---|
441 | u32 fmqm_gc; /* General Configuration Register 0x00 */ |
---|
442 | u32 res0004; /* 0x04 */ |
---|
443 | u32 fmqm_eie; /* Error Interrupt Event Register 0x08 */ |
---|
444 | u32 fmqm_eien; /* Error Interrupt Enable Register 0x0c */ |
---|
445 | u32 fmqm_eif; /* Error Interrupt Force Register 0x10 */ |
---|
446 | u32 fmqm_ie; /* Interrupt Event Register 0x14 */ |
---|
447 | u32 fmqm_ien; /* Interrupt Enable Register 0x18 */ |
---|
448 | u32 fmqm_if; /* Interrupt Force Register 0x1c */ |
---|
449 | u32 fmqm_gs; /* Global Status Register 0x20 */ |
---|
450 | u32 fmqm_ts; /* Task Status Register 0x24 */ |
---|
451 | u32 fmqm_etfc; /* Enqueue Total Frame Counter 0x28 */ |
---|
452 | u32 fmqm_dtfc; /* Dequeue Total Frame Counter 0x2c */ |
---|
453 | u32 fmqm_dc0; /* Dequeue Counter 0 0x30 */ |
---|
454 | u32 fmqm_dc1; /* Dequeue Counter 1 0x34 */ |
---|
455 | u32 fmqm_dc2; /* Dequeue Counter 2 0x38 */ |
---|
456 | u32 fmqm_dc3; /* Dequeue Counter 3 0x3c */ |
---|
457 | u32 fmqm_dfdc; /* Dequeue FQID from Default Counter 0x40 */ |
---|
458 | u32 fmqm_dfcc; /* Dequeue FQID from Context Counter 0x44 */ |
---|
459 | u32 fmqm_dffc; /* Dequeue FQID from FD Counter 0x48 */ |
---|
460 | u32 fmqm_dcc; /* Dequeue Confirm Counter 0x4c */ |
---|
461 | u32 res0050[7]; /* 0x50 - 0x6b */ |
---|
462 | u32 fmqm_tapc; /* Tnum Aging Period Control 0x6c */ |
---|
463 | u32 fmqm_dmcvc; /* Dequeue MAC Command Valid Counter 0x70 */ |
---|
464 | u32 fmqm_difdcc; /* Dequeue Invalid FD Command Counter 0x74 */ |
---|
465 | u32 fmqm_da1v; /* Dequeue A1 Valid Counter 0x78 */ |
---|
466 | u32 res007c; /* 0x7c */ |
---|
467 | u32 fmqm_dtc; /* 0x80 Debug Trap Counter 0x80 */ |
---|
468 | u32 fmqm_efddd; /* 0x84 Enqueue Frame desc Dynamic dbg 0x84 */ |
---|
469 | u32 res0088[2]; /* 0x88 - 0x8f */ |
---|
470 | struct { |
---|
471 | u32 fmqm_dtcfg1; /* 0x90 dbg trap cfg 1 Register 0x00 */ |
---|
472 | u32 fmqm_dtval1; /* Debug Trap Value 1 Register 0x04 */ |
---|
473 | u32 fmqm_dtm1; /* Debug Trap Mask 1 Register 0x08 */ |
---|
474 | u32 fmqm_dtc1; /* Debug Trap Counter 1 Register 0x0c */ |
---|
475 | u32 fmqm_dtcfg2; /* dbg Trap cfg 2 Register 0x10 */ |
---|
476 | u32 fmqm_dtval2; /* Debug Trap Value 2 Register 0x14 */ |
---|
477 | u32 fmqm_dtm2; /* Debug Trap Mask 2 Register 0x18 */ |
---|
478 | u32 res001c; /* 0x1c */ |
---|
479 | } dbg_traps[3]; /* 0x90 - 0xef */ |
---|
480 | u8 res00f0[0x400 - 0xf0]; /* 0xf0 - 0x3ff */ |
---|
481 | }; |
---|
482 | |
---|
483 | struct fman_dma_regs { |
---|
484 | u32 fmdmsr; /* FM DMA status register 0x00 */ |
---|
485 | u32 fmdmmr; /* FM DMA mode register 0x04 */ |
---|
486 | u32 fmdmtr; /* FM DMA bus threshold register 0x08 */ |
---|
487 | u32 fmdmhy; /* FM DMA bus hysteresis register 0x0c */ |
---|
488 | u32 fmdmsetr; /* FM DMA SOS emergency Threshold Register 0x10 */ |
---|
489 | u32 fmdmtah; /* FM DMA transfer bus address high reg 0x14 */ |
---|
490 | u32 fmdmtal; /* FM DMA transfer bus address low reg 0x18 */ |
---|
491 | u32 fmdmtcid; /* FM DMA transfer bus communication ID reg 0x1c */ |
---|
492 | u32 fmdmra; /* FM DMA bus internal ram address register 0x20 */ |
---|
493 | u32 fmdmrd; /* FM DMA bus internal ram data register 0x24 */ |
---|
494 | u32 fmdmwcr; /* FM DMA CAM watchdog counter value 0x28 */ |
---|
495 | u32 fmdmebcr; /* FM DMA CAM base in MURAM register 0x2c */ |
---|
496 | u32 fmdmccqdr; /* FM DMA CAM and CMD Queue Debug reg 0x30 */ |
---|
497 | u32 fmdmccqvr1; /* FM DMA CAM and CMD Queue Value reg #1 0x34 */ |
---|
498 | u32 fmdmccqvr2; /* FM DMA CAM and CMD Queue Value reg #2 0x38 */ |
---|
499 | u32 fmdmcqvr3; /* FM DMA CMD Queue Value register #3 0x3c */ |
---|
500 | u32 fmdmcqvr4; /* FM DMA CMD Queue Value register #4 0x40 */ |
---|
501 | u32 fmdmcqvr5; /* FM DMA CMD Queue Value register #5 0x44 */ |
---|
502 | u32 fmdmsefrc; /* FM DMA Semaphore Entry Full Reject Cntr 0x48 */ |
---|
503 | u32 fmdmsqfrc; /* FM DMA Semaphore Queue Full Reject Cntr 0x4c */ |
---|
504 | u32 fmdmssrc; /* FM DMA Semaphore SYNC Reject Counter 0x50 */ |
---|
505 | u32 fmdmdcr; /* FM DMA Debug Counter 0x54 */ |
---|
506 | u32 fmdmemsr; /* FM DMA Emergency Smoother Register 0x58 */ |
---|
507 | u32 res005c; /* 0x5c */ |
---|
508 | u32 fmdmplr[FMAN_LIODN_TBL / 2]; /* DMA LIODN regs 0x60-0xdf */ |
---|
509 | u32 res00e0[0x400 - 56]; |
---|
510 | }; |
---|
511 | |
---|
512 | struct fman_rg { |
---|
513 | struct fman_fpm_regs __iomem *fpm_rg; |
---|
514 | struct fman_dma_regs __iomem *dma_rg; |
---|
515 | struct fman_bmi_regs __iomem *bmi_rg; |
---|
516 | struct fman_qmi_regs __iomem *qmi_rg; |
---|
517 | }; |
---|
518 | |
---|
519 | struct fman_state_struct { |
---|
520 | u8 fm_id; |
---|
521 | u16 fm_clk_freq; |
---|
522 | struct fman_rev_info rev_info; |
---|
523 | bool enabled_time_stamp; |
---|
524 | u8 count1_micro_bit; |
---|
525 | u8 total_num_of_tasks; |
---|
526 | u8 accumulated_num_of_tasks; |
---|
527 | u32 accumulated_fifo_size; |
---|
528 | u8 accumulated_num_of_open_dmas; |
---|
529 | u8 accumulated_num_of_deq_tnums; |
---|
530 | bool low_end_restriction; |
---|
531 | u32 exceptions; |
---|
532 | u32 extra_fifo_pool_size; |
---|
533 | u8 extra_tasks_pool_size; |
---|
534 | u8 extra_open_dmas_pool_size; |
---|
535 | u16 port_mfl[MAX_NUM_OF_MACS]; |
---|
536 | u16 mac_mfl[MAX_NUM_OF_MACS]; |
---|
537 | |
---|
538 | /* SOC specific */ |
---|
539 | u32 fm_iram_size; |
---|
540 | /* DMA */ |
---|
541 | u32 dma_thresh_max_commq; |
---|
542 | u32 dma_thresh_max_buf; |
---|
543 | u32 max_num_of_open_dmas; |
---|
544 | /* QMI */ |
---|
545 | u32 qmi_max_num_of_tnums; |
---|
546 | u32 qmi_def_tnums_thresh; |
---|
547 | /* BMI */ |
---|
548 | u32 bmi_max_num_of_tasks; |
---|
549 | u32 bmi_max_fifo_size; |
---|
550 | /* General */ |
---|
551 | u32 fm_port_num_of_cg; |
---|
552 | u32 num_of_rx_ports; |
---|
553 | u32 total_fifo_size; |
---|
554 | |
---|
555 | u32 qman_channel_base; |
---|
556 | u32 num_of_qman_channels; |
---|
557 | |
---|
558 | struct resource *res; |
---|
559 | }; |
---|
560 | |
---|
561 | struct fman_cfg { |
---|
562 | u8 disp_limit_tsh; |
---|
563 | u8 prs_disp_tsh; |
---|
564 | u8 plcr_disp_tsh; |
---|
565 | u8 kg_disp_tsh; |
---|
566 | u8 bmi_disp_tsh; |
---|
567 | u8 qmi_enq_disp_tsh; |
---|
568 | u8 qmi_deq_disp_tsh; |
---|
569 | u8 fm_ctl1_disp_tsh; |
---|
570 | u8 fm_ctl2_disp_tsh; |
---|
571 | int dma_cache_override; |
---|
572 | enum fman_dma_aid_mode dma_aid_mode; |
---|
573 | bool dma_aid_override; |
---|
574 | u32 dma_axi_dbg_num_of_beats; |
---|
575 | u32 dma_cam_num_of_entries; |
---|
576 | u32 dma_watchdog; |
---|
577 | u8 dma_comm_qtsh_asrt_emer; |
---|
578 | u32 dma_write_buf_tsh_asrt_emer; |
---|
579 | u32 dma_read_buf_tsh_asrt_emer; |
---|
580 | u8 dma_comm_qtsh_clr_emer; |
---|
581 | u32 dma_write_buf_tsh_clr_emer; |
---|
582 | u32 dma_read_buf_tsh_clr_emer; |
---|
583 | u32 dma_sos_emergency; |
---|
584 | int dma_dbg_cnt_mode; |
---|
585 | bool dma_stop_on_bus_error; |
---|
586 | bool dma_en_emergency; |
---|
587 | u32 dma_emergency_bus_select; |
---|
588 | int dma_emergency_level; |
---|
589 | bool dma_en_emergency_smoother; |
---|
590 | u32 dma_emergency_switch_counter; |
---|
591 | bool halt_on_external_activ; |
---|
592 | bool halt_on_unrecov_ecc_err; |
---|
593 | int catastrophic_err; |
---|
594 | int dma_err; |
---|
595 | bool en_muram_test_mode; |
---|
596 | bool en_iram_test_mode; |
---|
597 | bool external_ecc_rams_enable; |
---|
598 | u16 tnum_aging_period; |
---|
599 | u32 exceptions; |
---|
600 | u16 clk_freq; |
---|
601 | bool pedantic_dma; |
---|
602 | u32 cam_base_addr; |
---|
603 | u32 fifo_base_addr; |
---|
604 | u32 total_fifo_size; |
---|
605 | u32 total_num_of_tasks; |
---|
606 | bool qmi_deq_option_support; |
---|
607 | u32 qmi_def_tnums_thresh; |
---|
608 | }; |
---|
609 | |
---|
610 | struct fman_dts_params { |
---|
611 | void __iomem *base_addr; /* FMan virtual address */ |
---|
612 | #ifndef __rtems__ |
---|
613 | struct resource *res; /* FMan memory resource */ |
---|
614 | #endif /* __rtems__ */ |
---|
615 | u8 id; /* FMan ID */ |
---|
616 | |
---|
617 | int err_irq; /* FMan Error IRQ */ |
---|
618 | |
---|
619 | u16 clk_freq; /* FMan clock freq (In Mhz) */ |
---|
620 | |
---|
621 | u32 qman_channel_base; /* QMan channels base */ |
---|
622 | u32 num_of_qman_channels; /* Number of QMan channels */ |
---|
623 | |
---|
624 | phys_addr_t muram_phy_base_addr; /* MURAM physical address */ |
---|
625 | resource_size_t muram_size; /* MURAM size */ |
---|
626 | }; |
---|
627 | |
---|
628 | struct fman { |
---|
629 | struct device *dev; |
---|
630 | void __iomem *base_addr; |
---|
631 | struct fman_intr_src intr_mng[FMAN_EV_CNT]; |
---|
632 | |
---|
633 | struct fman_fpm_regs __iomem *fpm_regs; |
---|
634 | struct fman_bmi_regs __iomem *bmi_regs; |
---|
635 | struct fman_qmi_regs __iomem *qmi_regs; |
---|
636 | struct fman_dma_regs __iomem *dma_regs; |
---|
637 | fman_exceptions_cb *exception_cb; |
---|
638 | fman_bus_error_cb *bus_error_cb; |
---|
639 | /* Spinlock for FMan use */ |
---|
640 | spinlock_t spinlock; |
---|
641 | struct fman_state_struct *state; |
---|
642 | |
---|
643 | struct fman_cfg *cfg; |
---|
644 | struct muram_info *muram; |
---|
645 | /* cam section in muram */ |
---|
646 | int cam_offset; |
---|
647 | size_t cam_size; |
---|
648 | /* Fifo in MURAM */ |
---|
649 | int fifo_offset; |
---|
650 | size_t fifo_size; |
---|
651 | bool reset_on_init; |
---|
652 | |
---|
653 | u32 liodn_base[64]; |
---|
654 | u32 liodn_offset[64]; |
---|
655 | |
---|
656 | struct fman_dts_params dts_params; |
---|
657 | }; |
---|
658 | |
---|
659 | static void fman_exceptions(struct fman *fman, enum fman_exceptions exception) |
---|
660 | { |
---|
661 | pr_debug("FMan[%d] exception %d\n", |
---|
662 | fman->state->fm_id, exception); |
---|
663 | } |
---|
664 | |
---|
665 | static void fman_bus_error(struct fman *fman, u8 __maybe_unused port_id, |
---|
666 | u64 __maybe_unused addr, u8 __maybe_unused tnum, |
---|
667 | u16 __maybe_unused liodn) |
---|
668 | { |
---|
669 | pr_debug("FMan[%d] bus error: port_id[%d]\n", |
---|
670 | fman->state->fm_id, port_id); |
---|
671 | } |
---|
672 | |
---|
673 | static inline void call_mac_isr(struct fman *fman, u8 id) |
---|
674 | { |
---|
675 | if (fman->intr_mng[id].isr_cb) |
---|
676 | fman->intr_mng[id].isr_cb(fman->intr_mng[id].src_handle); |
---|
677 | } |
---|
678 | |
---|
679 | static inline u8 hw_port_id_to_sw_port_id(u8 major, u8 hw_port_id) |
---|
680 | { |
---|
681 | u8 sw_port_id = 0; |
---|
682 | |
---|
683 | if (hw_port_id >= BASE_TX_PORTID) { |
---|
684 | sw_port_id = hw_port_id - BASE_TX_PORTID; |
---|
685 | } else if (hw_port_id >= BASE_RX_PORTID) { |
---|
686 | sw_port_id = hw_port_id - BASE_RX_PORTID; |
---|
687 | } else { |
---|
688 | sw_port_id = 0; |
---|
689 | WARN_ON(false); |
---|
690 | } |
---|
691 | |
---|
692 | return sw_port_id; |
---|
693 | } |
---|
694 | |
---|
695 | static void set_port_order_restoration(struct fman_fpm_regs __iomem *fpm_rg, |
---|
696 | u8 port_id) |
---|
697 | { |
---|
698 | u32 tmp = 0; |
---|
699 | |
---|
700 | tmp = (u32)(port_id << FPM_PORT_FM_CTL_PORTID_SHIFT); |
---|
701 | |
---|
702 | tmp |= (FPM_PRT_FM_CTL2 | FPM_PRT_FM_CTL1); |
---|
703 | |
---|
704 | /* order restoration */ |
---|
705 | if (port_id % 2) |
---|
706 | tmp |= (FPM_PRT_FM_CTL1 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT); |
---|
707 | else |
---|
708 | tmp |= (FPM_PRT_FM_CTL2 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT); |
---|
709 | |
---|
710 | iowrite32be(tmp, &fpm_rg->fmfp_prc); |
---|
711 | } |
---|
712 | |
---|
713 | static void set_port_liodn(struct fman_rg *fman_rg, u8 port_id, |
---|
714 | u32 liodn_base, u32 liodn_ofst) |
---|
715 | { |
---|
716 | u32 tmp; |
---|
717 | |
---|
718 | /* set LIODN base for this port */ |
---|
719 | tmp = ioread32be(&fman_rg->dma_rg->fmdmplr[port_id / 2]); |
---|
720 | if (port_id % 2) { |
---|
721 | tmp &= ~DMA_LIODN_BASE_MASK; |
---|
722 | tmp |= liodn_base; |
---|
723 | } else { |
---|
724 | tmp &= ~(DMA_LIODN_BASE_MASK << DMA_LIODN_SHIFT); |
---|
725 | tmp |= liodn_base << DMA_LIODN_SHIFT; |
---|
726 | } |
---|
727 | iowrite32be(tmp, &fman_rg->dma_rg->fmdmplr[port_id / 2]); |
---|
728 | iowrite32be(liodn_ofst, &fman_rg->bmi_rg->fmbm_spliodn[port_id - 1]); |
---|
729 | } |
---|
730 | |
---|
731 | static void enable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg) |
---|
732 | { |
---|
733 | u32 tmp; |
---|
734 | |
---|
735 | tmp = ioread32be(&fpm_rg->fm_rcr); |
---|
736 | if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL) |
---|
737 | iowrite32be(tmp | FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr); |
---|
738 | else |
---|
739 | iowrite32be(tmp | FPM_RAM_RAMS_ECC_EN | |
---|
740 | FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr); |
---|
741 | } |
---|
742 | |
---|
743 | static void disable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg) |
---|
744 | { |
---|
745 | u32 tmp; |
---|
746 | |
---|
747 | tmp = ioread32be(&fpm_rg->fm_rcr); |
---|
748 | if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL) |
---|
749 | iowrite32be(tmp & ~FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr); |
---|
750 | else |
---|
751 | iowrite32be(tmp & ~(FPM_RAM_RAMS_ECC_EN | FPM_RAM_IRAM_ECC_EN), |
---|
752 | &fpm_rg->fm_rcr); |
---|
753 | } |
---|
754 | |
---|
755 | static void fman_defconfig(struct fman_cfg *cfg) |
---|
756 | { |
---|
757 | memset(cfg, 0, sizeof(struct fman_cfg)); |
---|
758 | |
---|
759 | cfg->catastrophic_err = DEFAULT_CATASTROPHIC_ERR; |
---|
760 | cfg->dma_err = DEFAULT_DMA_ERR; |
---|
761 | cfg->halt_on_external_activ = false; |
---|
762 | cfg->halt_on_unrecov_ecc_err = false; |
---|
763 | cfg->en_iram_test_mode = false; |
---|
764 | cfg->en_muram_test_mode = false; |
---|
765 | cfg->external_ecc_rams_enable = false; |
---|
766 | cfg->dma_aid_override = false; |
---|
767 | cfg->dma_aid_mode = DEFAULT_AID_MODE; |
---|
768 | cfg->dma_comm_qtsh_clr_emer = DEFAULT_DMA_COMM_Q_LOW; |
---|
769 | cfg->dma_comm_qtsh_asrt_emer = DEFAULT_DMA_COMM_Q_HIGH; |
---|
770 | cfg->dma_cache_override = DEFAULT_CACHE_OVERRIDE; |
---|
771 | cfg->dma_cam_num_of_entries = DEFAULT_DMA_CAM_NUM_OF_ENTRIES; |
---|
772 | cfg->dma_dbg_cnt_mode = DEFAULT_DMA_DBG_CNT_MODE; |
---|
773 | cfg->dma_en_emergency = false; |
---|
774 | cfg->dma_sos_emergency = DEFAULT_DMA_SOS_EMERGENCY; |
---|
775 | cfg->dma_watchdog = DEFAULT_DMA_WATCHDOG; |
---|
776 | cfg->dma_en_emergency_smoother = false; |
---|
777 | cfg->dma_emergency_switch_counter = |
---|
778 | DEFAULT_DMA_EMERGENCY_SWITCH_COUNTER; |
---|
779 | cfg->disp_limit_tsh = DEFAULT_DISP_LIMIT; |
---|
780 | cfg->prs_disp_tsh = DEFAULT_PRS_DISP_TH; |
---|
781 | cfg->plcr_disp_tsh = DEFAULT_PLCR_DISP_TH; |
---|
782 | cfg->kg_disp_tsh = DEFAULT_KG_DISP_TH; |
---|
783 | cfg->bmi_disp_tsh = DEFAULT_BMI_DISP_TH; |
---|
784 | cfg->qmi_enq_disp_tsh = DEFAULT_QMI_ENQ_DISP_TH; |
---|
785 | cfg->qmi_deq_disp_tsh = DEFAULT_QMI_DEQ_DISP_TH; |
---|
786 | cfg->fm_ctl1_disp_tsh = DEFAULT_FM_CTL1_DISP_TH; |
---|
787 | cfg->fm_ctl2_disp_tsh = DEFAULT_FM_CTL2_DISP_TH; |
---|
788 | |
---|
789 | cfg->pedantic_dma = false; |
---|
790 | cfg->tnum_aging_period = 0; |
---|
791 | cfg->dma_stop_on_bus_error = false; |
---|
792 | cfg->qmi_deq_option_support = false; |
---|
793 | } |
---|
794 | |
---|
795 | static int dma_init(struct fman *fman) |
---|
796 | { |
---|
797 | struct fman_dma_regs __iomem *dma_rg = fman->dma_regs; |
---|
798 | struct fman_cfg *cfg = fman->cfg; |
---|
799 | u32 tmp_reg; |
---|
800 | |
---|
801 | /* Init DMA Registers */ |
---|
802 | |
---|
803 | /* clear status reg events */ |
---|
804 | tmp_reg = (DMA_STATUS_BUS_ERR | DMA_STATUS_READ_ECC | |
---|
805 | DMA_STATUS_SYSTEM_WRITE_ECC | DMA_STATUS_FM_WRITE_ECC); |
---|
806 | iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg, &dma_rg->fmdmsr); |
---|
807 | |
---|
808 | /* configure mode register */ |
---|
809 | tmp_reg = 0; |
---|
810 | tmp_reg |= cfg->dma_cache_override << DMA_MODE_CACHE_OR_SHIFT; |
---|
811 | if (cfg->dma_aid_override) |
---|
812 | tmp_reg |= DMA_MODE_AID_OR; |
---|
813 | if (cfg->exceptions & EX_DMA_BUS_ERROR) |
---|
814 | tmp_reg |= DMA_MODE_BER; |
---|
815 | if ((cfg->exceptions & EX_DMA_SYSTEM_WRITE_ECC) | |
---|
816 | (cfg->exceptions & EX_DMA_READ_ECC) | |
---|
817 | (cfg->exceptions & EX_DMA_FM_WRITE_ECC)) |
---|
818 | tmp_reg |= DMA_MODE_ECC; |
---|
819 | if (cfg->dma_stop_on_bus_error) |
---|
820 | tmp_reg |= DMA_MODE_SBER; |
---|
821 | if (cfg->dma_axi_dbg_num_of_beats) |
---|
822 | tmp_reg |= (DMA_MODE_AXI_DBG_MASK & |
---|
823 | ((cfg->dma_axi_dbg_num_of_beats - 1) |
---|
824 | << DMA_MODE_AXI_DBG_SHIFT)); |
---|
825 | |
---|
826 | if (cfg->dma_en_emergency) { |
---|
827 | tmp_reg |= cfg->dma_emergency_bus_select; |
---|
828 | tmp_reg |= cfg->dma_emergency_level << DMA_MODE_EMER_LVL_SHIFT; |
---|
829 | if (cfg->dma_en_emergency_smoother) |
---|
830 | iowrite32be(cfg->dma_emergency_switch_counter, |
---|
831 | &dma_rg->fmdmemsr); |
---|
832 | } |
---|
833 | tmp_reg |= (((cfg->dma_cam_num_of_entries / DMA_CAM_UNITS) - 1) & |
---|
834 | DMA_MODE_CEN_MASK) << DMA_MODE_CEN_SHIFT; |
---|
835 | tmp_reg |= DMA_MODE_SECURE_PROT; |
---|
836 | tmp_reg |= cfg->dma_dbg_cnt_mode << DMA_MODE_DBG_SHIFT; |
---|
837 | tmp_reg |= cfg->dma_aid_mode << DMA_MODE_AID_MODE_SHIFT; |
---|
838 | |
---|
839 | if (cfg->pedantic_dma) |
---|
840 | tmp_reg |= DMA_MODE_EMER_READ; |
---|
841 | |
---|
842 | iowrite32be(tmp_reg, &dma_rg->fmdmmr); |
---|
843 | |
---|
844 | /* configure thresholds register */ |
---|
845 | tmp_reg = ((u32)cfg->dma_comm_qtsh_asrt_emer << |
---|
846 | DMA_THRESH_COMMQ_SHIFT); |
---|
847 | tmp_reg |= (cfg->dma_read_buf_tsh_asrt_emer & |
---|
848 | DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT; |
---|
849 | tmp_reg |= cfg->dma_write_buf_tsh_asrt_emer & |
---|
850 | DMA_THRESH_WRITE_INT_BUF_MASK; |
---|
851 | |
---|
852 | iowrite32be(tmp_reg, &dma_rg->fmdmtr); |
---|
853 | |
---|
854 | /* configure hysteresis register */ |
---|
855 | tmp_reg = ((u32)cfg->dma_comm_qtsh_clr_emer << |
---|
856 | DMA_THRESH_COMMQ_SHIFT); |
---|
857 | tmp_reg |= (cfg->dma_read_buf_tsh_clr_emer & |
---|
858 | DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT; |
---|
859 | tmp_reg |= cfg->dma_write_buf_tsh_clr_emer & |
---|
860 | DMA_THRESH_WRITE_INT_BUF_MASK; |
---|
861 | |
---|
862 | iowrite32be(tmp_reg, &dma_rg->fmdmhy); |
---|
863 | |
---|
864 | /* configure emergency threshold */ |
---|
865 | iowrite32be(cfg->dma_sos_emergency, &dma_rg->fmdmsetr); |
---|
866 | |
---|
867 | /* configure Watchdog */ |
---|
868 | iowrite32be((cfg->dma_watchdog * cfg->clk_freq), &dma_rg->fmdmwcr); |
---|
869 | |
---|
870 | iowrite32be(cfg->cam_base_addr, &dma_rg->fmdmebcr); |
---|
871 | |
---|
872 | /* Allocate MURAM for CAM */ |
---|
873 | fman->cam_size = |
---|
874 | (u32)(fman->cfg->dma_cam_num_of_entries * DMA_CAM_SIZEOF_ENTRY); |
---|
875 | fman->cam_offset = fman_muram_alloc(fman->muram, fman->cam_size); |
---|
876 | if (IS_ERR_VALUE(fman->cam_offset)) { |
---|
877 | pr_err("MURAM alloc for DMA CAM failed\n"); |
---|
878 | return -ENOMEM; |
---|
879 | } |
---|
880 | |
---|
881 | if (fman->state->rev_info.major == 2) { |
---|
882 | u32 __iomem *cam_base_addr; |
---|
883 | |
---|
884 | fman_muram_free_mem(fman->muram, fman->cam_offset, |
---|
885 | fman->cam_size); |
---|
886 | |
---|
887 | fman->cam_size = fman->cfg->dma_cam_num_of_entries * 72 + 128; |
---|
888 | fman->cam_offset = fman_muram_alloc(fman->muram, |
---|
889 | fman->cam_size); |
---|
890 | if (IS_ERR_VALUE(fman->cam_offset)) { |
---|
891 | pr_err("MURAM alloc for DMA CAM failed\n"); |
---|
892 | return -ENOMEM; |
---|
893 | } |
---|
894 | |
---|
895 | if (fman->cfg->dma_cam_num_of_entries % 8 || |
---|
896 | fman->cfg->dma_cam_num_of_entries > 32) { |
---|
897 | pr_err("wrong dma_cam_num_of_entries\n"); |
---|
898 | return -EINVAL; |
---|
899 | } |
---|
900 | |
---|
901 | cam_base_addr = (u32 __iomem *) |
---|
902 | fman_muram_offset_to_vbase(fman->muram, |
---|
903 | fman->cam_offset); |
---|
904 | out_be32(cam_base_addr, |
---|
905 | ~((1 << (32 - fman->cfg->dma_cam_num_of_entries)) - |
---|
906 | 1)); |
---|
907 | } |
---|
908 | |
---|
909 | fman->cfg->cam_base_addr = fman->cam_offset; |
---|
910 | |
---|
911 | return 0; |
---|
912 | } |
---|
913 | |
---|
914 | static void fpm_init(struct fman_fpm_regs __iomem *fpm_rg, struct fman_cfg *cfg) |
---|
915 | { |
---|
916 | u32 tmp_reg; |
---|
917 | int i; |
---|
918 | |
---|
919 | /* Init FPM Registers */ |
---|
920 | |
---|
921 | tmp_reg = (u32)(cfg->disp_limit_tsh << FPM_DISP_LIMIT_SHIFT); |
---|
922 | iowrite32be(tmp_reg, &fpm_rg->fmfp_mxd); |
---|
923 | |
---|
924 | tmp_reg = (((u32)cfg->prs_disp_tsh << FPM_THR1_PRS_SHIFT) | |
---|
925 | ((u32)cfg->kg_disp_tsh << FPM_THR1_KG_SHIFT) | |
---|
926 | ((u32)cfg->plcr_disp_tsh << FPM_THR1_PLCR_SHIFT) | |
---|
927 | ((u32)cfg->bmi_disp_tsh << FPM_THR1_BMI_SHIFT)); |
---|
928 | iowrite32be(tmp_reg, &fpm_rg->fmfp_dist1); |
---|
929 | |
---|
930 | tmp_reg = |
---|
931 | (((u32)cfg->qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) | |
---|
932 | ((u32)cfg->qmi_deq_disp_tsh << FPM_THR2_QMI_DEQ_SHIFT) | |
---|
933 | ((u32)cfg->fm_ctl1_disp_tsh << FPM_THR2_FM_CTL1_SHIFT) | |
---|
934 | ((u32)cfg->fm_ctl2_disp_tsh << FPM_THR2_FM_CTL2_SHIFT)); |
---|
935 | iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2); |
---|
936 | |
---|
937 | /* define exceptions and error behavior */ |
---|
938 | tmp_reg = 0; |
---|
939 | /* Clear events */ |
---|
940 | tmp_reg |= (FPM_EV_MASK_STALL | FPM_EV_MASK_DOUBLE_ECC | |
---|
941 | FPM_EV_MASK_SINGLE_ECC); |
---|
942 | /* enable interrupts */ |
---|
943 | if (cfg->exceptions & EX_FPM_STALL_ON_TASKS) |
---|
944 | tmp_reg |= FPM_EV_MASK_STALL_EN; |
---|
945 | if (cfg->exceptions & EX_FPM_SINGLE_ECC) |
---|
946 | tmp_reg |= FPM_EV_MASK_SINGLE_ECC_EN; |
---|
947 | if (cfg->exceptions & EX_FPM_DOUBLE_ECC) |
---|
948 | tmp_reg |= FPM_EV_MASK_DOUBLE_ECC_EN; |
---|
949 | tmp_reg |= (cfg->catastrophic_err << FPM_EV_MASK_CAT_ERR_SHIFT); |
---|
950 | tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT); |
---|
951 | if (!cfg->halt_on_external_activ) |
---|
952 | tmp_reg |= FPM_EV_MASK_EXTERNAL_HALT; |
---|
953 | if (!cfg->halt_on_unrecov_ecc_err) |
---|
954 | tmp_reg |= FPM_EV_MASK_ECC_ERR_HALT; |
---|
955 | iowrite32be(tmp_reg, &fpm_rg->fmfp_ee); |
---|
956 | |
---|
957 | /* clear all fmCtls event registers */ |
---|
958 | for (i = 0; i < FM_NUM_OF_FMAN_CTRL_EVENT_REGS; i++) |
---|
959 | iowrite32be(0xFFFFFFFF, &fpm_rg->fmfp_cev[i]); |
---|
960 | |
---|
961 | /* RAM ECC - enable and clear events */ |
---|
962 | /* first we need to clear all parser memory, |
---|
963 | * as it is uninitialized and may cause ECC errors |
---|
964 | */ |
---|
965 | /* event bits */ |
---|
966 | tmp_reg = (FPM_RAM_MURAM_ECC | FPM_RAM_IRAM_ECC); |
---|
967 | /* Rams enable not effected by RCR bit, |
---|
968 | * but by a COP configuration |
---|
969 | */ |
---|
970 | if (cfg->external_ecc_rams_enable) |
---|
971 | tmp_reg |= FPM_RAM_RAMS_ECC_EN_SRC_SEL; |
---|
972 | |
---|
973 | /* enable test mode */ |
---|
974 | if (cfg->en_muram_test_mode) |
---|
975 | tmp_reg |= FPM_RAM_MURAM_TEST_ECC; |
---|
976 | if (cfg->en_iram_test_mode) |
---|
977 | tmp_reg |= FPM_RAM_IRAM_TEST_ECC; |
---|
978 | iowrite32be(tmp_reg, &fpm_rg->fm_rcr); |
---|
979 | |
---|
980 | tmp_reg = 0; |
---|
981 | if (cfg->exceptions & EX_IRAM_ECC) { |
---|
982 | tmp_reg |= FPM_IRAM_ECC_ERR_EX_EN; |
---|
983 | enable_rams_ecc(fpm_rg); |
---|
984 | } |
---|
985 | if (cfg->exceptions & EX_MURAM_ECC) { |
---|
986 | tmp_reg |= FPM_MURAM_ECC_ERR_EX_EN; |
---|
987 | enable_rams_ecc(fpm_rg); |
---|
988 | } |
---|
989 | iowrite32be(tmp_reg, &fpm_rg->fm_rie); |
---|
990 | } |
---|
991 | |
---|
992 | static void bmi_init(struct fman_bmi_regs __iomem *bmi_rg, |
---|
993 | struct fman_cfg *cfg) |
---|
994 | { |
---|
995 | u32 tmp_reg; |
---|
996 | |
---|
997 | /* Init BMI Registers */ |
---|
998 | |
---|
999 | /* define common resources */ |
---|
1000 | tmp_reg = cfg->fifo_base_addr; |
---|
1001 | tmp_reg = tmp_reg / BMI_FIFO_ALIGN; |
---|
1002 | |
---|
1003 | tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) << |
---|
1004 | BMI_CFG1_FIFO_SIZE_SHIFT); |
---|
1005 | iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1); |
---|
1006 | |
---|
1007 | tmp_reg = ((cfg->total_num_of_tasks - 1) & BMI_CFG2_TASKS_MASK) << |
---|
1008 | BMI_CFG2_TASKS_SHIFT; |
---|
1009 | /* num of DMA's will be dynamically updated when each port is set */ |
---|
1010 | iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2); |
---|
1011 | |
---|
1012 | /* define unmaskable exceptions, enable and clear events */ |
---|
1013 | tmp_reg = 0; |
---|
1014 | iowrite32be(BMI_ERR_INTR_EN_LIST_RAM_ECC | |
---|
1015 | BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC | |
---|
1016 | BMI_ERR_INTR_EN_STATISTICS_RAM_ECC | |
---|
1017 | BMI_ERR_INTR_EN_DISPATCH_RAM_ECC, &bmi_rg->fmbm_ievr); |
---|
1018 | |
---|
1019 | if (cfg->exceptions & EX_BMI_LIST_RAM_ECC) |
---|
1020 | tmp_reg |= BMI_ERR_INTR_EN_LIST_RAM_ECC; |
---|
1021 | if (cfg->exceptions & EX_BMI_STORAGE_PROFILE_ECC) |
---|
1022 | tmp_reg |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC; |
---|
1023 | if (cfg->exceptions & EX_BMI_STATISTICS_RAM_ECC) |
---|
1024 | tmp_reg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC; |
---|
1025 | if (cfg->exceptions & EX_BMI_DISPATCH_RAM_ECC) |
---|
1026 | tmp_reg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC; |
---|
1027 | iowrite32be(tmp_reg, &bmi_rg->fmbm_ier); |
---|
1028 | } |
---|
1029 | |
---|
1030 | static void qmi_init(struct fman_qmi_regs __iomem *qmi_rg, |
---|
1031 | struct fman_cfg *cfg) |
---|
1032 | { |
---|
1033 | u32 tmp_reg; |
---|
1034 | u16 period_in_fm_clocks; |
---|
1035 | u8 remainder; |
---|
1036 | |
---|
1037 | /* Init QMI Registers */ |
---|
1038 | |
---|
1039 | /* Clear error interrupt events */ |
---|
1040 | |
---|
1041 | iowrite32be(QMI_ERR_INTR_EN_DOUBLE_ECC | QMI_ERR_INTR_EN_DEQ_FROM_DEF, |
---|
1042 | &qmi_rg->fmqm_eie); |
---|
1043 | tmp_reg = 0; |
---|
1044 | if (cfg->exceptions & EX_QMI_DEQ_FROM_UNKNOWN_PORTID) |
---|
1045 | tmp_reg |= QMI_ERR_INTR_EN_DEQ_FROM_DEF; |
---|
1046 | if (cfg->exceptions & EX_QMI_DOUBLE_ECC) |
---|
1047 | tmp_reg |= QMI_ERR_INTR_EN_DOUBLE_ECC; |
---|
1048 | /* enable events */ |
---|
1049 | iowrite32be(tmp_reg, &qmi_rg->fmqm_eien); |
---|
1050 | |
---|
1051 | if (cfg->tnum_aging_period) { |
---|
1052 | /* tnum_aging_period is in units of usec, clk_freq in Mhz */ |
---|
1053 | period_in_fm_clocks = (u16) |
---|
1054 | (cfg->tnum_aging_period * cfg->clk_freq); |
---|
1055 | /* period_in_fm_clocks must be a 64 multiple */ |
---|
1056 | remainder = (u8)(period_in_fm_clocks % 64); |
---|
1057 | if (remainder) { |
---|
1058 | tmp_reg = (u32)((period_in_fm_clocks / 64) + 1); |
---|
1059 | } else { |
---|
1060 | tmp_reg = (u32)(period_in_fm_clocks / 64); |
---|
1061 | if (!tmp_reg) |
---|
1062 | tmp_reg = 1; |
---|
1063 | } |
---|
1064 | tmp_reg <<= QMI_TAPC_TAP; |
---|
1065 | iowrite32be(tmp_reg, &qmi_rg->fmqm_tapc); |
---|
1066 | } |
---|
1067 | tmp_reg = 0; |
---|
1068 | /* Clear interrupt events */ |
---|
1069 | iowrite32be(QMI_INTR_EN_SINGLE_ECC, &qmi_rg->fmqm_ie); |
---|
1070 | if (cfg->exceptions & EX_QMI_SINGLE_ECC) |
---|
1071 | tmp_reg |= QMI_INTR_EN_SINGLE_ECC; |
---|
1072 | /* enable events */ |
---|
1073 | iowrite32be(tmp_reg, &qmi_rg->fmqm_ien); |
---|
1074 | } |
---|
1075 | |
---|
1076 | static int enable(struct fman_rg *fman_rg, struct fman_cfg *cfg) |
---|
1077 | { |
---|
1078 | u32 cfg_reg = 0; |
---|
1079 | |
---|
1080 | /* Enable all modules */ |
---|
1081 | |
---|
1082 | /* clear&enable global counters - calculate reg and save for later, |
---|
1083 | * because it's the same reg for QMI enable |
---|
1084 | */ |
---|
1085 | cfg_reg = QMI_CFG_EN_COUNTERS; |
---|
1086 | if (cfg->qmi_deq_option_support) |
---|
1087 | cfg_reg |= (u32)(((cfg->qmi_def_tnums_thresh) << 8) | |
---|
1088 | cfg->qmi_def_tnums_thresh); |
---|
1089 | |
---|
1090 | iowrite32be(BMI_INIT_START, &fman_rg->bmi_rg->fmbm_init); |
---|
1091 | iowrite32be(cfg_reg | QMI_CFG_ENQ_EN | QMI_CFG_DEQ_EN, |
---|
1092 | &fman_rg->qmi_rg->fmqm_gc); |
---|
1093 | |
---|
1094 | return 0; |
---|
1095 | } |
---|
1096 | |
---|
1097 | static int set_exception(struct fman_rg *fman_rg, |
---|
1098 | enum fman_exceptions exception, bool enable) |
---|
1099 | { |
---|
1100 | u32 tmp; |
---|
1101 | |
---|
1102 | switch (exception) { |
---|
1103 | case FMAN_EX_DMA_BUS_ERROR: |
---|
1104 | tmp = ioread32be(&fman_rg->dma_rg->fmdmmr); |
---|
1105 | if (enable) |
---|
1106 | tmp |= DMA_MODE_BER; |
---|
1107 | else |
---|
1108 | tmp &= ~DMA_MODE_BER; |
---|
1109 | /* disable bus error */ |
---|
1110 | iowrite32be(tmp, &fman_rg->dma_rg->fmdmmr); |
---|
1111 | break; |
---|
1112 | case FMAN_EX_DMA_READ_ECC: |
---|
1113 | case FMAN_EX_DMA_SYSTEM_WRITE_ECC: |
---|
1114 | case FMAN_EX_DMA_FM_WRITE_ECC: |
---|
1115 | tmp = ioread32be(&fman_rg->dma_rg->fmdmmr); |
---|
1116 | if (enable) |
---|
1117 | tmp |= DMA_MODE_ECC; |
---|
1118 | else |
---|
1119 | tmp &= ~DMA_MODE_ECC; |
---|
1120 | iowrite32be(tmp, &fman_rg->dma_rg->fmdmmr); |
---|
1121 | break; |
---|
1122 | case FMAN_EX_FPM_STALL_ON_TASKS: |
---|
1123 | tmp = ioread32be(&fman_rg->fpm_rg->fmfp_ee); |
---|
1124 | if (enable) |
---|
1125 | tmp |= FPM_EV_MASK_STALL_EN; |
---|
1126 | else |
---|
1127 | tmp &= ~FPM_EV_MASK_STALL_EN; |
---|
1128 | iowrite32be(tmp, &fman_rg->fpm_rg->fmfp_ee); |
---|
1129 | break; |
---|
1130 | case FMAN_EX_FPM_SINGLE_ECC: |
---|
1131 | tmp = ioread32be(&fman_rg->fpm_rg->fmfp_ee); |
---|
1132 | if (enable) |
---|
1133 | tmp |= FPM_EV_MASK_SINGLE_ECC_EN; |
---|
1134 | else |
---|
1135 | tmp &= ~FPM_EV_MASK_SINGLE_ECC_EN; |
---|
1136 | iowrite32be(tmp, &fman_rg->fpm_rg->fmfp_ee); |
---|
1137 | break; |
---|
1138 | case FMAN_EX_FPM_DOUBLE_ECC: |
---|
1139 | tmp = ioread32be(&fman_rg->fpm_rg->fmfp_ee); |
---|
1140 | if (enable) |
---|
1141 | tmp |= FPM_EV_MASK_DOUBLE_ECC_EN; |
---|
1142 | else |
---|
1143 | tmp &= ~FPM_EV_MASK_DOUBLE_ECC_EN; |
---|
1144 | iowrite32be(tmp, &fman_rg->fpm_rg->fmfp_ee); |
---|
1145 | break; |
---|
1146 | case FMAN_EX_QMI_SINGLE_ECC: |
---|
1147 | tmp = ioread32be(&fman_rg->qmi_rg->fmqm_ien); |
---|
1148 | if (enable) |
---|
1149 | tmp |= QMI_INTR_EN_SINGLE_ECC; |
---|
1150 | else |
---|
1151 | tmp &= ~QMI_INTR_EN_SINGLE_ECC; |
---|
1152 | iowrite32be(tmp, &fman_rg->qmi_rg->fmqm_ien); |
---|
1153 | break; |
---|
1154 | case FMAN_EX_QMI_DOUBLE_ECC: |
---|
1155 | tmp = ioread32be(&fman_rg->qmi_rg->fmqm_eien); |
---|
1156 | if (enable) |
---|
1157 | tmp |= QMI_ERR_INTR_EN_DOUBLE_ECC; |
---|
1158 | else |
---|
1159 | tmp &= ~QMI_ERR_INTR_EN_DOUBLE_ECC; |
---|
1160 | iowrite32be(tmp, &fman_rg->qmi_rg->fmqm_eien); |
---|
1161 | break; |
---|
1162 | case FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: |
---|
1163 | tmp = ioread32be(&fman_rg->qmi_rg->fmqm_eien); |
---|
1164 | if (enable) |
---|
1165 | tmp |= QMI_ERR_INTR_EN_DEQ_FROM_DEF; |
---|
1166 | else |
---|
1167 | tmp &= ~QMI_ERR_INTR_EN_DEQ_FROM_DEF; |
---|
1168 | iowrite32be(tmp, &fman_rg->qmi_rg->fmqm_eien); |
---|
1169 | break; |
---|
1170 | case FMAN_EX_BMI_LIST_RAM_ECC: |
---|
1171 | tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier); |
---|
1172 | if (enable) |
---|
1173 | tmp |= BMI_ERR_INTR_EN_LIST_RAM_ECC; |
---|
1174 | else |
---|
1175 | tmp &= ~BMI_ERR_INTR_EN_LIST_RAM_ECC; |
---|
1176 | iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier); |
---|
1177 | break; |
---|
1178 | case FMAN_EX_BMI_STORAGE_PROFILE_ECC: |
---|
1179 | tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier); |
---|
1180 | if (enable) |
---|
1181 | tmp |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC; |
---|
1182 | else |
---|
1183 | tmp &= ~BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC; |
---|
1184 | iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier); |
---|
1185 | break; |
---|
1186 | case FMAN_EX_BMI_STATISTICS_RAM_ECC: |
---|
1187 | tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier); |
---|
1188 | if (enable) |
---|
1189 | tmp |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC; |
---|
1190 | else |
---|
1191 | tmp &= ~BMI_ERR_INTR_EN_STATISTICS_RAM_ECC; |
---|
1192 | iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier); |
---|
1193 | break; |
---|
1194 | case FMAN_EX_BMI_DISPATCH_RAM_ECC: |
---|
1195 | tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier); |
---|
1196 | if (enable) |
---|
1197 | tmp |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC; |
---|
1198 | else |
---|
1199 | tmp &= ~BMI_ERR_INTR_EN_DISPATCH_RAM_ECC; |
---|
1200 | iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier); |
---|
1201 | break; |
---|
1202 | case FMAN_EX_IRAM_ECC: |
---|
1203 | tmp = ioread32be(&fman_rg->fpm_rg->fm_rie); |
---|
1204 | if (enable) { |
---|
1205 | /* enable ECC if not enabled */ |
---|
1206 | enable_rams_ecc(fman_rg->fpm_rg); |
---|
1207 | /* enable ECC interrupts */ |
---|
1208 | tmp |= FPM_IRAM_ECC_ERR_EX_EN; |
---|
1209 | } else { |
---|
1210 | /* ECC mechanism may be disabled, |
---|
1211 | * depending on driver status |
---|
1212 | */ |
---|
1213 | disable_rams_ecc(fman_rg->fpm_rg); |
---|
1214 | tmp &= ~FPM_IRAM_ECC_ERR_EX_EN; |
---|
1215 | } |
---|
1216 | iowrite32be(tmp, &fman_rg->fpm_rg->fm_rie); |
---|
1217 | break; |
---|
1218 | case FMAN_EX_MURAM_ECC: |
---|
1219 | tmp = ioread32be(&fman_rg->fpm_rg->fm_rie); |
---|
1220 | if (enable) { |
---|
1221 | /* enable ECC if not enabled */ |
---|
1222 | enable_rams_ecc(fman_rg->fpm_rg); |
---|
1223 | /* enable ECC interrupts */ |
---|
1224 | tmp |= FPM_MURAM_ECC_ERR_EX_EN; |
---|
1225 | } else { |
---|
1226 | /* ECC mechanism may be disabled, |
---|
1227 | * depending on driver status |
---|
1228 | */ |
---|
1229 | disable_rams_ecc(fman_rg->fpm_rg); |
---|
1230 | tmp &= ~FPM_MURAM_ECC_ERR_EX_EN; |
---|
1231 | } |
---|
1232 | iowrite32be(tmp, &fman_rg->fpm_rg->fm_rie); |
---|
1233 | break; |
---|
1234 | default: |
---|
1235 | return -EINVAL; |
---|
1236 | } |
---|
1237 | return 0; |
---|
1238 | } |
---|
1239 | |
---|
1240 | static void resume(struct fman_fpm_regs __iomem *fpm_rg) |
---|
1241 | { |
---|
1242 | u32 tmp; |
---|
1243 | |
---|
1244 | tmp = ioread32be(&fpm_rg->fmfp_ee); |
---|
1245 | /* clear tmp_reg event bits in order not to clear standing events */ |
---|
1246 | tmp &= ~(FPM_EV_MASK_DOUBLE_ECC | |
---|
1247 | FPM_EV_MASK_STALL | FPM_EV_MASK_SINGLE_ECC); |
---|
1248 | tmp |= FPM_EV_MASK_RELEASE_FM; |
---|
1249 | |
---|
1250 | iowrite32be(tmp, &fpm_rg->fmfp_ee); |
---|
1251 | } |
---|
1252 | |
---|
1253 | static int fill_soc_specific_params(struct fman_state_struct *state) |
---|
1254 | { |
---|
1255 | u8 minor = state->rev_info.minor; |
---|
1256 | /* P4080 - Major 2 |
---|
1257 | * P2041/P3041/P5020/P5040 - Major 3 |
---|
1258 | * Tx/Bx - Major 6 |
---|
1259 | */ |
---|
1260 | switch (state->rev_info.major) { |
---|
1261 | case 3: |
---|
1262 | state->bmi_max_fifo_size = 160 * 1024; |
---|
1263 | state->fm_iram_size = 64 * 1024; |
---|
1264 | state->dma_thresh_max_commq = 31; |
---|
1265 | state->dma_thresh_max_buf = 127; |
---|
1266 | state->qmi_max_num_of_tnums = 64; |
---|
1267 | state->qmi_def_tnums_thresh = 48; |
---|
1268 | state->bmi_max_num_of_tasks = 128; |
---|
1269 | state->max_num_of_open_dmas = 32; |
---|
1270 | state->fm_port_num_of_cg = 256; |
---|
1271 | state->num_of_rx_ports = 6; |
---|
1272 | state->total_fifo_size = 122 * 1024; |
---|
1273 | break; |
---|
1274 | |
---|
1275 | case 2: |
---|
1276 | state->bmi_max_fifo_size = 160 * 1024; |
---|
1277 | state->fm_iram_size = 64 * 1024; |
---|
1278 | state->dma_thresh_max_commq = 31; |
---|
1279 | state->dma_thresh_max_buf = 127; |
---|
1280 | state->qmi_max_num_of_tnums = 64; |
---|
1281 | state->qmi_def_tnums_thresh = 48; |
---|
1282 | state->bmi_max_num_of_tasks = 128; |
---|
1283 | state->max_num_of_open_dmas = 32; |
---|
1284 | state->fm_port_num_of_cg = 256; |
---|
1285 | state->num_of_rx_ports = 5; |
---|
1286 | state->total_fifo_size = 100 * 1024; |
---|
1287 | break; |
---|
1288 | |
---|
1289 | case 6: |
---|
1290 | state->dma_thresh_max_commq = 83; |
---|
1291 | state->dma_thresh_max_buf = 127; |
---|
1292 | state->qmi_max_num_of_tnums = 64; |
---|
1293 | state->qmi_def_tnums_thresh = 32; |
---|
1294 | state->fm_port_num_of_cg = 256; |
---|
1295 | |
---|
1296 | /* FManV3L */ |
---|
1297 | if (minor == 1 || minor == 4) { |
---|
1298 | state->bmi_max_fifo_size = 192 * 1024; |
---|
1299 | state->bmi_max_num_of_tasks = 64; |
---|
1300 | state->max_num_of_open_dmas = 32; |
---|
1301 | state->num_of_rx_ports = 5; |
---|
1302 | if (minor == 1) |
---|
1303 | state->fm_iram_size = 32 * 1024; |
---|
1304 | else |
---|
1305 | state->fm_iram_size = 64 * 1024; |
---|
1306 | state->total_fifo_size = 156 * 1024; |
---|
1307 | } |
---|
1308 | /* FManV3H */ |
---|
1309 | else if (minor == 0 || minor == 2 || minor == 3) { |
---|
1310 | state->bmi_max_fifo_size = 384 * 1024; |
---|
1311 | state->fm_iram_size = 64 * 1024; |
---|
1312 | state->bmi_max_num_of_tasks = 128; |
---|
1313 | state->max_num_of_open_dmas = 84; |
---|
1314 | state->num_of_rx_ports = 8; |
---|
1315 | state->total_fifo_size = 295 * 1024; |
---|
1316 | } else { |
---|
1317 | pr_err("Unsupported FManv3 version\n"); |
---|
1318 | return -EINVAL; |
---|
1319 | } |
---|
1320 | |
---|
1321 | break; |
---|
1322 | default: |
---|
1323 | pr_err("Unsupported FMan version\n"); |
---|
1324 | return -EINVAL; |
---|
1325 | } |
---|
1326 | |
---|
1327 | return 0; |
---|
1328 | } |
---|
1329 | |
---|
1330 | static bool is_init_done(struct fman_cfg *cfg) |
---|
1331 | { |
---|
1332 | /* Checks if FMan driver parameters were initialized */ |
---|
1333 | if (!cfg) |
---|
1334 | return true; |
---|
1335 | |
---|
1336 | return false; |
---|
1337 | } |
---|
1338 | |
---|
1339 | static void free_init_resources(struct fman *fman) |
---|
1340 | { |
---|
1341 | if (fman->cam_offset) |
---|
1342 | fman_muram_free_mem(fman->muram, fman->cam_offset, |
---|
1343 | fman->cam_size); |
---|
1344 | if (fman->fifo_offset) |
---|
1345 | fman_muram_free_mem(fman->muram, fman->fifo_offset, |
---|
1346 | fman->fifo_size); |
---|
1347 | } |
---|
1348 | |
---|
1349 | static void bmi_err_event(struct fman *fman) |
---|
1350 | { |
---|
1351 | u32 event, mask, force; |
---|
1352 | struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs; |
---|
1353 | |
---|
1354 | event = ioread32be(&bmi_rg->fmbm_ievr); |
---|
1355 | mask = ioread32be(&bmi_rg->fmbm_ier); |
---|
1356 | event &= mask; |
---|
1357 | /* clear the forced events */ |
---|
1358 | force = ioread32be(&bmi_rg->fmbm_ifr); |
---|
1359 | if (force & event) |
---|
1360 | iowrite32be(force & ~event, &bmi_rg->fmbm_ifr); |
---|
1361 | /* clear the acknowledged events */ |
---|
1362 | iowrite32be(event, &bmi_rg->fmbm_ievr); |
---|
1363 | |
---|
1364 | if (event & BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC) |
---|
1365 | fman->exception_cb(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC); |
---|
1366 | if (event & BMI_ERR_INTR_EN_LIST_RAM_ECC) |
---|
1367 | fman->exception_cb(fman, FMAN_EX_BMI_LIST_RAM_ECC); |
---|
1368 | if (event & BMI_ERR_INTR_EN_STATISTICS_RAM_ECC) |
---|
1369 | fman->exception_cb(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC); |
---|
1370 | if (event & BMI_ERR_INTR_EN_DISPATCH_RAM_ECC) |
---|
1371 | fman->exception_cb(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC); |
---|
1372 | } |
---|
1373 | |
---|
1374 | static void qmi_err_event(struct fman *fman) |
---|
1375 | { |
---|
1376 | u32 event, mask, force; |
---|
1377 | struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs; |
---|
1378 | |
---|
1379 | event = ioread32be(&qmi_rg->fmqm_eie); |
---|
1380 | mask = ioread32be(&qmi_rg->fmqm_eien); |
---|
1381 | event &= mask; |
---|
1382 | |
---|
1383 | /* clear the forced events */ |
---|
1384 | force = ioread32be(&qmi_rg->fmqm_eif); |
---|
1385 | if (force & event) |
---|
1386 | iowrite32be(force & ~event, &qmi_rg->fmqm_eif); |
---|
1387 | /* clear the acknowledged events */ |
---|
1388 | iowrite32be(event, &qmi_rg->fmqm_eie); |
---|
1389 | |
---|
1390 | if (event & QMI_ERR_INTR_EN_DOUBLE_ECC) |
---|
1391 | fman->exception_cb(fman, FMAN_EX_QMI_DOUBLE_ECC); |
---|
1392 | if (event & QMI_ERR_INTR_EN_DEQ_FROM_DEF) |
---|
1393 | fman->exception_cb(fman, FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID); |
---|
1394 | } |
---|
1395 | |
---|
1396 | static void dma_err_event(struct fman *fman) |
---|
1397 | { |
---|
1398 | u32 status, mask, com_id; |
---|
1399 | u8 tnum, port_id, relative_port_id; |
---|
1400 | u16 liodn; |
---|
1401 | struct fman_dma_regs __iomem *dma_rg = fman->dma_regs; |
---|
1402 | |
---|
1403 | status = ioread32be(&dma_rg->fmdmsr); |
---|
1404 | mask = ioread32be(&dma_rg->fmdmmr); |
---|
1405 | |
---|
1406 | /* clear DMA_STATUS_BUS_ERR if mask has no DMA_MODE_BER */ |
---|
1407 | if ((mask & DMA_MODE_BER) != DMA_MODE_BER) |
---|
1408 | status &= ~DMA_STATUS_BUS_ERR; |
---|
1409 | |
---|
1410 | /* clear relevant bits if mask has no DMA_MODE_ECC */ |
---|
1411 | if ((mask & DMA_MODE_ECC) != DMA_MODE_ECC) |
---|
1412 | status &= ~(DMA_STATUS_FM_SPDAT_ECC | |
---|
1413 | DMA_STATUS_READ_ECC | |
---|
1414 | DMA_STATUS_SYSTEM_WRITE_ECC | |
---|
1415 | DMA_STATUS_FM_WRITE_ECC); |
---|
1416 | |
---|
1417 | /* clear set events */ |
---|
1418 | iowrite32be(status, &dma_rg->fmdmsr); |
---|
1419 | |
---|
1420 | if (status & DMA_STATUS_BUS_ERR) { |
---|
1421 | u64 addr; |
---|
1422 | |
---|
1423 | addr = (u64)ioread32be(&dma_rg->fmdmtal); |
---|
1424 | addr |= ((u64)(ioread32be(&dma_rg->fmdmtah)) << 32); |
---|
1425 | |
---|
1426 | com_id = ioread32be(&dma_rg->fmdmtcid); |
---|
1427 | port_id = (u8)(((com_id & DMA_TRANSFER_PORTID_MASK) >> |
---|
1428 | DMA_TRANSFER_PORTID_SHIFT)); |
---|
1429 | relative_port_id = |
---|
1430 | hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id); |
---|
1431 | tnum = (u8)((com_id & DMA_TRANSFER_TNUM_MASK) >> |
---|
1432 | DMA_TRANSFER_TNUM_SHIFT); |
---|
1433 | liodn = (u16)(com_id & DMA_TRANSFER_LIODN_MASK); |
---|
1434 | fman->bus_error_cb(fman, relative_port_id, addr, tnum, liodn); |
---|
1435 | } |
---|
1436 | if (status & DMA_STATUS_FM_SPDAT_ECC) |
---|
1437 | fman->exception_cb(fman, FMAN_EX_DMA_SINGLE_PORT_ECC); |
---|
1438 | if (status & DMA_STATUS_READ_ECC) |
---|
1439 | fman->exception_cb(fman, FMAN_EX_DMA_READ_ECC); |
---|
1440 | if (status & DMA_STATUS_SYSTEM_WRITE_ECC) |
---|
1441 | fman->exception_cb(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC); |
---|
1442 | if (status & DMA_STATUS_FM_WRITE_ECC) |
---|
1443 | fman->exception_cb(fman, FMAN_EX_DMA_FM_WRITE_ECC); |
---|
1444 | } |
---|
1445 | |
---|
1446 | static void fpm_err_event(struct fman *fman) |
---|
1447 | { |
---|
1448 | u32 event; |
---|
1449 | struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs; |
---|
1450 | |
---|
1451 | event = ioread32be(&fpm_rg->fmfp_ee); |
---|
1452 | /* clear the all occurred events */ |
---|
1453 | iowrite32be(event, &fpm_rg->fmfp_ee); |
---|
1454 | |
---|
1455 | if ((event & FPM_EV_MASK_DOUBLE_ECC) && |
---|
1456 | (event & FPM_EV_MASK_DOUBLE_ECC_EN)) |
---|
1457 | fman->exception_cb(fman, FMAN_EX_FPM_DOUBLE_ECC); |
---|
1458 | if ((event & FPM_EV_MASK_STALL) && (event & FPM_EV_MASK_STALL_EN)) |
---|
1459 | fman->exception_cb(fman, FMAN_EX_FPM_STALL_ON_TASKS); |
---|
1460 | if ((event & FPM_EV_MASK_SINGLE_ECC) && |
---|
1461 | (event & FPM_EV_MASK_SINGLE_ECC_EN)) |
---|
1462 | fman->exception_cb(fman, FMAN_EX_FPM_SINGLE_ECC); |
---|
1463 | } |
---|
1464 | |
---|
1465 | static void muram_err_intr(struct fman *fman) |
---|
1466 | { |
---|
1467 | u32 event, mask; |
---|
1468 | struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs; |
---|
1469 | |
---|
1470 | event = ioread32be(&fpm_rg->fm_rcr); |
---|
1471 | mask = ioread32be(&fpm_rg->fm_rie); |
---|
1472 | |
---|
1473 | /* clear MURAM event bit (do not clear IRAM event) */ |
---|
1474 | iowrite32be(event & ~FPM_RAM_IRAM_ECC, &fpm_rg->fm_rcr); |
---|
1475 | |
---|
1476 | if ((mask & FPM_MURAM_ECC_ERR_EX_EN) && (event & FPM_RAM_MURAM_ECC)) |
---|
1477 | fman->exception_cb(fman, FMAN_EX_MURAM_ECC); |
---|
1478 | } |
---|
1479 | |
---|
1480 | static void qmi_event(struct fman *fman) |
---|
1481 | { |
---|
1482 | u32 event, mask, force; |
---|
1483 | struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs; |
---|
1484 | |
---|
1485 | event = ioread32be(&qmi_rg->fmqm_ie); |
---|
1486 | mask = ioread32be(&qmi_rg->fmqm_ien); |
---|
1487 | event &= mask; |
---|
1488 | /* clear the forced events */ |
---|
1489 | force = ioread32be(&qmi_rg->fmqm_if); |
---|
1490 | if (force & event) |
---|
1491 | iowrite32be(force & ~event, &qmi_rg->fmqm_if); |
---|
1492 | /* clear the acknowledged events */ |
---|
1493 | iowrite32be(event, &qmi_rg->fmqm_ie); |
---|
1494 | |
---|
1495 | if (event & QMI_INTR_EN_SINGLE_ECC) |
---|
1496 | fman->exception_cb(fman, FMAN_EX_QMI_SINGLE_ECC); |
---|
1497 | } |
---|
1498 | |
---|
1499 | static void enable_time_stamp(struct fman *fman) |
---|
1500 | { |
---|
1501 | struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs; |
---|
1502 | u16 fm_clk_freq = fman->state->fm_clk_freq; |
---|
1503 | u32 tmp, intgr, ts_freq; |
---|
1504 | u64 frac; |
---|
1505 | |
---|
1506 | ts_freq = (u32)(1 << fman->state->count1_micro_bit); |
---|
1507 | /* configure timestamp so that bit 8 will count 1 microsecond |
---|
1508 | * Find effective count rate at TIMESTAMP least significant bits: |
---|
1509 | * Effective_Count_Rate = 1MHz x 2^8 = 256MHz |
---|
1510 | * Find frequency ratio between effective count rate and the clock: |
---|
1511 | * Effective_Count_Rate / CLK e.g. for 600 MHz clock: |
---|
1512 | * 256/600 = 0.4266666... |
---|
1513 | */ |
---|
1514 | |
---|
1515 | intgr = ts_freq / fm_clk_freq; |
---|
1516 | /* we multiply by 2^16 to keep the fraction of the division |
---|
1517 | * we do not div back, since we write this value as a fraction |
---|
1518 | * see spec |
---|
1519 | */ |
---|
1520 | |
---|
1521 | frac = ((ts_freq << 16) - (intgr << 16) * fm_clk_freq) / fm_clk_freq; |
---|
1522 | /* we check remainder of the division in order to round up if not int */ |
---|
1523 | if (((ts_freq << 16) - (intgr << 16) * fm_clk_freq) % fm_clk_freq) |
---|
1524 | frac++; |
---|
1525 | |
---|
1526 | tmp = (intgr << FPM_TS_INT_SHIFT) | (u16)frac; |
---|
1527 | iowrite32be(tmp, &fpm_rg->fmfp_tsc2); |
---|
1528 | |
---|
1529 | /* enable timestamp with original clock */ |
---|
1530 | iowrite32be(FPM_TS_CTL_EN, &fpm_rg->fmfp_tsc1); |
---|
1531 | fman->state->enabled_time_stamp = true; |
---|
1532 | } |
---|
1533 | |
---|
1534 | static int clear_iram(struct fman *fman) |
---|
1535 | { |
---|
1536 | struct fman_iram_regs __iomem *iram; |
---|
1537 | int i; |
---|
1538 | |
---|
1539 | iram = (struct fman_iram_regs __iomem *)(fman->base_addr + IMEM_OFFSET); |
---|
1540 | |
---|
1541 | /* Enable the auto-increment */ |
---|
1542 | out_be32(&iram->iadd, IRAM_IADD_AIE); |
---|
1543 | while (in_be32(&iram->iadd) != IRAM_IADD_AIE) |
---|
1544 | ; |
---|
1545 | |
---|
1546 | for (i = 0; i < (fman->state->fm_iram_size / 4); i++) |
---|
1547 | out_be32(&iram->idata, 0xffffffff); |
---|
1548 | |
---|
1549 | out_be32(&iram->iadd, fman->state->fm_iram_size - 4); |
---|
1550 | /* Memory barrier */ |
---|
1551 | mb(); |
---|
1552 | while (in_be32(&iram->idata) != 0xffffffff) |
---|
1553 | ; |
---|
1554 | |
---|
1555 | return 0; |
---|
1556 | } |
---|
1557 | |
---|
1558 | static u32 get_exception_flag(enum fman_exceptions exception) |
---|
1559 | { |
---|
1560 | u32 bit_mask; |
---|
1561 | |
---|
1562 | switch (exception) { |
---|
1563 | case FMAN_EX_DMA_BUS_ERROR: |
---|
1564 | bit_mask = EX_DMA_BUS_ERROR; |
---|
1565 | break; |
---|
1566 | case FMAN_EX_DMA_SINGLE_PORT_ECC: |
---|
1567 | bit_mask = EX_DMA_SINGLE_PORT_ECC; |
---|
1568 | break; |
---|
1569 | case FMAN_EX_DMA_READ_ECC: |
---|
1570 | bit_mask = EX_DMA_READ_ECC; |
---|
1571 | break; |
---|
1572 | case FMAN_EX_DMA_SYSTEM_WRITE_ECC: |
---|
1573 | bit_mask = EX_DMA_SYSTEM_WRITE_ECC; |
---|
1574 | break; |
---|
1575 | case FMAN_EX_DMA_FM_WRITE_ECC: |
---|
1576 | bit_mask = EX_DMA_FM_WRITE_ECC; |
---|
1577 | break; |
---|
1578 | case FMAN_EX_FPM_STALL_ON_TASKS: |
---|
1579 | bit_mask = EX_FPM_STALL_ON_TASKS; |
---|
1580 | break; |
---|
1581 | case FMAN_EX_FPM_SINGLE_ECC: |
---|
1582 | bit_mask = EX_FPM_SINGLE_ECC; |
---|
1583 | break; |
---|
1584 | case FMAN_EX_FPM_DOUBLE_ECC: |
---|
1585 | bit_mask = EX_FPM_DOUBLE_ECC; |
---|
1586 | break; |
---|
1587 | case FMAN_EX_QMI_SINGLE_ECC: |
---|
1588 | bit_mask = EX_QMI_SINGLE_ECC; |
---|
1589 | break; |
---|
1590 | case FMAN_EX_QMI_DOUBLE_ECC: |
---|
1591 | bit_mask = EX_QMI_DOUBLE_ECC; |
---|
1592 | break; |
---|
1593 | case FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: |
---|
1594 | bit_mask = EX_QMI_DEQ_FROM_UNKNOWN_PORTID; |
---|
1595 | break; |
---|
1596 | case FMAN_EX_BMI_LIST_RAM_ECC: |
---|
1597 | bit_mask = EX_BMI_LIST_RAM_ECC; |
---|
1598 | break; |
---|
1599 | case FMAN_EX_BMI_STORAGE_PROFILE_ECC: |
---|
1600 | bit_mask = EX_BMI_STORAGE_PROFILE_ECC; |
---|
1601 | break; |
---|
1602 | case FMAN_EX_BMI_STATISTICS_RAM_ECC: |
---|
1603 | bit_mask = EX_BMI_STATISTICS_RAM_ECC; |
---|
1604 | break; |
---|
1605 | case FMAN_EX_BMI_DISPATCH_RAM_ECC: |
---|
1606 | bit_mask = EX_BMI_DISPATCH_RAM_ECC; |
---|
1607 | break; |
---|
1608 | case FMAN_EX_MURAM_ECC: |
---|
1609 | bit_mask = EX_MURAM_ECC; |
---|
1610 | break; |
---|
1611 | default: |
---|
1612 | bit_mask = 0; |
---|
1613 | break; |
---|
1614 | } |
---|
1615 | |
---|
1616 | return bit_mask; |
---|
1617 | } |
---|
1618 | |
---|
1619 | static int get_module_event(enum fman_event_modules module, u8 mod_id, |
---|
1620 | enum fman_intr_type intr_type) |
---|
1621 | { |
---|
1622 | int event; |
---|
1623 | |
---|
1624 | switch (module) { |
---|
1625 | case FMAN_MOD_MAC: |
---|
1626 | event = (intr_type == FMAN_INTR_TYPE_ERR) ? |
---|
1627 | (FMAN_EV_ERR_MAC0 + mod_id) : |
---|
1628 | (FMAN_EV_MAC0 + mod_id); |
---|
1629 | break; |
---|
1630 | case FMAN_MOD_FMAN_CTRL: |
---|
1631 | if (intr_type == FMAN_INTR_TYPE_ERR) |
---|
1632 | event = FMAN_EV_CNT; |
---|
1633 | else |
---|
1634 | event = (FMAN_EV_FMAN_CTRL_0 + mod_id); |
---|
1635 | break; |
---|
1636 | case FMAN_MOD_DUMMY_LAST: |
---|
1637 | event = FMAN_EV_CNT; |
---|
1638 | break; |
---|
1639 | default: |
---|
1640 | event = FMAN_EV_CNT; |
---|
1641 | break; |
---|
1642 | } |
---|
1643 | |
---|
1644 | return event; |
---|
1645 | } |
---|
1646 | |
---|
1647 | static int set_size_of_fifo(struct fman *fman, u8 port_id, u32 *size_of_fifo, |
---|
1648 | u32 *extra_size_of_fifo) |
---|
1649 | { |
---|
1650 | struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs; |
---|
1651 | u32 fifo = *size_of_fifo; |
---|
1652 | u32 extra_fifo = *extra_size_of_fifo; |
---|
1653 | u32 tmp; |
---|
1654 | |
---|
1655 | /* if this is the first time a port requires extra_fifo_pool_size, |
---|
1656 | * the total extra_fifo_pool_size must be initialized to 1 buffer per |
---|
1657 | * port |
---|
1658 | */ |
---|
1659 | if (extra_fifo && !fman->state->extra_fifo_pool_size) |
---|
1660 | fman->state->extra_fifo_pool_size = |
---|
1661 | fman->state->num_of_rx_ports * FMAN_BMI_FIFO_UNITS; |
---|
1662 | |
---|
1663 | fman->state->extra_fifo_pool_size = |
---|
1664 | max(fman->state->extra_fifo_pool_size, extra_fifo); |
---|
1665 | |
---|
1666 | /* check that there are enough uncommitted fifo size */ |
---|
1667 | if ((fman->state->accumulated_fifo_size + fifo) > |
---|
1668 | (fman->state->total_fifo_size - |
---|
1669 | fman->state->extra_fifo_pool_size)) { |
---|
1670 | pr_err("Requested fifo size and extra size exceed total FIFO size.\n"); |
---|
1671 | return -EAGAIN; |
---|
1672 | } |
---|
1673 | |
---|
1674 | /* Read, modify and write to HW */ |
---|
1675 | tmp = (u32)((fifo / FMAN_BMI_FIFO_UNITS - 1) | |
---|
1676 | ((extra_fifo / FMAN_BMI_FIFO_UNITS) << |
---|
1677 | BMI_EXTRA_FIFO_SIZE_SHIFT)); |
---|
1678 | iowrite32be(tmp, &bmi_rg->fmbm_pfs[port_id - 1]); |
---|
1679 | |
---|
1680 | /* update accumulated */ |
---|
1681 | fman->state->accumulated_fifo_size += fifo; |
---|
1682 | |
---|
1683 | return 0; |
---|
1684 | } |
---|
1685 | |
---|
1686 | static int set_num_of_tasks(struct fman *fman, u8 port_id, u8 *num_of_tasks, |
---|
1687 | u8 *num_of_extra_tasks) |
---|
1688 | { |
---|
1689 | struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs; |
---|
1690 | u8 tasks = *num_of_tasks; |
---|
1691 | u8 extra_tasks = *num_of_extra_tasks; |
---|
1692 | u32 tmp; |
---|
1693 | |
---|
1694 | if (extra_tasks) |
---|
1695 | fman->state->extra_tasks_pool_size = |
---|
1696 | (u8)max(fman->state->extra_tasks_pool_size, extra_tasks); |
---|
1697 | |
---|
1698 | /* check that there are enough uncommitted tasks */ |
---|
1699 | if ((fman->state->accumulated_num_of_tasks + tasks) > |
---|
1700 | (fman->state->total_num_of_tasks - |
---|
1701 | fman->state->extra_tasks_pool_size)) { |
---|
1702 | pr_err("Requested num_of_tasks and extra tasks pool for fm%d exceed total num_of_tasks.\n", |
---|
1703 | fman->state->fm_id); |
---|
1704 | return -EAGAIN; |
---|
1705 | } |
---|
1706 | /* update accumulated */ |
---|
1707 | fman->state->accumulated_num_of_tasks += tasks; |
---|
1708 | |
---|
1709 | /* Write to HW */ |
---|
1710 | tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) & |
---|
1711 | ~(BMI_NUM_OF_TASKS_MASK | BMI_NUM_OF_EXTRA_TASKS_MASK); |
---|
1712 | tmp |= ((u32)((tasks - 1) << BMI_NUM_OF_TASKS_SHIFT) | |
---|
1713 | (u32)(extra_tasks << BMI_EXTRA_NUM_OF_TASKS_SHIFT)); |
---|
1714 | iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]); |
---|
1715 | |
---|
1716 | return 0; |
---|
1717 | } |
---|
1718 | |
---|
1719 | static int set_num_of_open_dmas(struct fman *fman, u8 port_id, |
---|
1720 | u8 *num_of_open_dmas, |
---|
1721 | u8 *num_of_extra_open_dmas) |
---|
1722 | { |
---|
1723 | struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs; |
---|
1724 | u8 open_dmas = *num_of_open_dmas; |
---|
1725 | u8 extra_open_dmas = *num_of_extra_open_dmas; |
---|
1726 | u8 total_num_dmas = 0, current_val = 0, current_extra_val = 0; |
---|
1727 | u32 tmp; |
---|
1728 | |
---|
1729 | if (!open_dmas) { |
---|
1730 | /* Configuration according to values in the HW. |
---|
1731 | * read the current number of open Dma's |
---|
1732 | */ |
---|
1733 | tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]); |
---|
1734 | current_extra_val = (u8)((tmp & BMI_NUM_OF_EXTRA_DMAS_MASK) >> |
---|
1735 | BMI_EXTRA_NUM_OF_DMAS_SHIFT); |
---|
1736 | |
---|
1737 | tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]); |
---|
1738 | current_val = (u8)(((tmp & BMI_NUM_OF_DMAS_MASK) >> |
---|
1739 | BMI_NUM_OF_DMAS_SHIFT) + 1); |
---|
1740 | |
---|
1741 | /* This is the first configuration and user did not |
---|
1742 | * specify value (!open_dmas), reset values will be used |
---|
1743 | * and we just save these values for resource management |
---|
1744 | */ |
---|
1745 | fman->state->extra_open_dmas_pool_size = |
---|
1746 | (u8)max(fman->state->extra_open_dmas_pool_size, |
---|
1747 | current_extra_val); |
---|
1748 | fman->state->accumulated_num_of_open_dmas += current_val; |
---|
1749 | *num_of_open_dmas = current_val; |
---|
1750 | *num_of_extra_open_dmas = current_extra_val; |
---|
1751 | return 0; |
---|
1752 | } |
---|
1753 | |
---|
1754 | if (extra_open_dmas > current_extra_val) |
---|
1755 | fman->state->extra_open_dmas_pool_size = |
---|
1756 | (u8)max(fman->state->extra_open_dmas_pool_size, |
---|
1757 | extra_open_dmas); |
---|
1758 | |
---|
1759 | if ((fman->state->rev_info.major < 6) && |
---|
1760 | (fman->state->accumulated_num_of_open_dmas - current_val + |
---|
1761 | open_dmas > fman->state->max_num_of_open_dmas)) { |
---|
1762 | pr_err("Requested num_of_open_dmas for fm%d exceeds total num_of_open_dmas.\n", |
---|
1763 | fman->state->fm_id); |
---|
1764 | return -EAGAIN; |
---|
1765 | } else if ((fman->state->rev_info.major >= 6) && |
---|
1766 | !((fman->state->rev_info.major == 6) && |
---|
1767 | (fman->state->rev_info.minor == 0)) && |
---|
1768 | (fman->state->accumulated_num_of_open_dmas - |
---|
1769 | current_val + open_dmas > |
---|
1770 | fman->state->dma_thresh_max_commq + 1)) { |
---|
1771 | pr_err("Requested num_of_open_dmas for fm%d exceeds DMA Command queue (%d)\n", |
---|
1772 | fman->state->fm_id, |
---|
1773 | fman->state->dma_thresh_max_commq + 1); |
---|
1774 | return -EAGAIN; |
---|
1775 | } |
---|
1776 | |
---|
1777 | WARN_ON(fman->state->accumulated_num_of_open_dmas < current_val); |
---|
1778 | /* update acummulated */ |
---|
1779 | fman->state->accumulated_num_of_open_dmas -= current_val; |
---|
1780 | fman->state->accumulated_num_of_open_dmas += open_dmas; |
---|
1781 | |
---|
1782 | if (fman->state->rev_info.major < 6) |
---|
1783 | total_num_dmas = |
---|
1784 | (u8)(fman->state->accumulated_num_of_open_dmas + |
---|
1785 | fman->state->extra_open_dmas_pool_size); |
---|
1786 | |
---|
1787 | /* calculate reg */ |
---|
1788 | tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) & |
---|
1789 | ~(BMI_NUM_OF_DMAS_MASK | BMI_NUM_OF_EXTRA_DMAS_MASK); |
---|
1790 | tmp |= (u32)(((open_dmas - 1) << BMI_NUM_OF_DMAS_SHIFT) | |
---|
1791 | (extra_open_dmas << BMI_EXTRA_NUM_OF_DMAS_SHIFT)); |
---|
1792 | iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]); |
---|
1793 | |
---|
1794 | /* update total num of DMA's with committed number of open DMAS, |
---|
1795 | * and max uncommitted pool. |
---|
1796 | */ |
---|
1797 | if (total_num_dmas) { |
---|
1798 | tmp = ioread32be(&bmi_rg->fmbm_cfg2) & ~BMI_CFG2_DMAS_MASK; |
---|
1799 | tmp |= (u32)(total_num_dmas - 1) << BMI_CFG2_DMAS_SHIFT; |
---|
1800 | iowrite32be(tmp, &bmi_rg->fmbm_cfg2); |
---|
1801 | } |
---|
1802 | |
---|
1803 | return 0; |
---|
1804 | } |
---|
1805 | |
---|
1806 | static int fman_config(struct fman *fman) |
---|
1807 | { |
---|
1808 | void __iomem *base_addr; |
---|
1809 | int err; |
---|
1810 | |
---|
1811 | base_addr = fman->dts_params.base_addr; |
---|
1812 | |
---|
1813 | fman->state = kzalloc(sizeof(*fman->state), GFP_KERNEL); |
---|
1814 | if (!fman->state) |
---|
1815 | goto err_fm_state; |
---|
1816 | |
---|
1817 | /* Allocate the FM driver's parameters structure */ |
---|
1818 | fman->cfg = kzalloc(sizeof(*fman->cfg), GFP_KERNEL); |
---|
1819 | if (!fman->cfg) |
---|
1820 | goto err_fm_drv; |
---|
1821 | |
---|
1822 | /* Initialize MURAM block */ |
---|
1823 | fman->muram = fman_muram_init(fman->dts_params.muram_phy_base_addr, |
---|
1824 | fman->dts_params.muram_size); |
---|
1825 | if (!fman->muram) |
---|
1826 | goto err_fm_soc_specific; |
---|
1827 | |
---|
1828 | /* Initialize FM parameters which will be kept by the driver */ |
---|
1829 | fman->state->fm_id = fman->dts_params.id; |
---|
1830 | fman->state->fm_clk_freq = fman->dts_params.clk_freq; |
---|
1831 | fman->state->qman_channel_base = fman->dts_params.qman_channel_base; |
---|
1832 | fman->state->num_of_qman_channels = |
---|
1833 | fman->dts_params.num_of_qman_channels; |
---|
1834 | #ifndef __rtems__ |
---|
1835 | fman->state->res = fman->dts_params.res; |
---|
1836 | #endif /* __rtems__ */ |
---|
1837 | fman->exception_cb = fman_exceptions; |
---|
1838 | fman->bus_error_cb = fman_bus_error; |
---|
1839 | fman->fpm_regs = |
---|
1840 | (struct fman_fpm_regs __iomem *)(base_addr + FPM_OFFSET); |
---|
1841 | fman->bmi_regs = |
---|
1842 | (struct fman_bmi_regs __iomem *)(base_addr + BMI_OFFSET); |
---|
1843 | fman->qmi_regs = |
---|
1844 | (struct fman_qmi_regs __iomem *)(base_addr + QMI_OFFSET); |
---|
1845 | fman->dma_regs = |
---|
1846 | (struct fman_dma_regs __iomem *)(base_addr + DMA_OFFSET); |
---|
1847 | fman->base_addr = base_addr; |
---|
1848 | |
---|
1849 | spin_lock_init(&fman->spinlock); |
---|
1850 | fman_defconfig(fman->cfg); |
---|
1851 | |
---|
1852 | fman->cfg->qmi_deq_option_support = true; |
---|
1853 | |
---|
1854 | fman->state->extra_fifo_pool_size = 0; |
---|
1855 | fman->state->exceptions = DFLT_EXCEPTIONS; |
---|
1856 | fman->reset_on_init = true; |
---|
1857 | |
---|
1858 | /* Read FMan revision for future use*/ |
---|
1859 | fman_get_revision(fman, &fman->state->rev_info); |
---|
1860 | |
---|
1861 | err = fill_soc_specific_params(fman->state); |
---|
1862 | if (err) |
---|
1863 | goto err_fm_soc_specific; |
---|
1864 | |
---|
1865 | /* FM_AID_MODE_NO_TNUM_SW005 Errata workaround */ |
---|
1866 | if (fman->state->rev_info.major >= 6) |
---|
1867 | fman->cfg->dma_aid_mode = FMAN_DMA_AID_OUT_PORT_ID; |
---|
1868 | |
---|
1869 | fman->cfg->qmi_def_tnums_thresh = fman->state->qmi_def_tnums_thresh; |
---|
1870 | |
---|
1871 | fman->state->total_num_of_tasks = |
---|
1872 | (u8)DFLT_TOTAL_NUM_OF_TASKS(fman->state->rev_info.major, |
---|
1873 | fman->state->rev_info.minor, |
---|
1874 | fman->state->bmi_max_num_of_tasks); |
---|
1875 | |
---|
1876 | if (fman->state->rev_info.major < 6) { |
---|
1877 | fman->cfg->dma_comm_qtsh_clr_emer = |
---|
1878 | (u8)DFLT_DMA_COMM_Q_LOW(fman->state->rev_info.major, |
---|
1879 | fman->state->dma_thresh_max_commq); |
---|
1880 | |
---|
1881 | fman->cfg->dma_comm_qtsh_asrt_emer = |
---|
1882 | (u8)DFLT_DMA_COMM_Q_HIGH(fman->state->rev_info.major, |
---|
1883 | fman->state->dma_thresh_max_commq); |
---|
1884 | |
---|
1885 | fman->cfg->dma_cam_num_of_entries = |
---|
1886 | DFLT_DMA_CAM_NUM_OF_ENTRIES(fman->state->rev_info.major); |
---|
1887 | |
---|
1888 | fman->cfg->dma_read_buf_tsh_clr_emer = |
---|
1889 | DFLT_DMA_READ_INT_BUF_LOW(fman->state->dma_thresh_max_buf); |
---|
1890 | |
---|
1891 | fman->cfg->dma_read_buf_tsh_asrt_emer = |
---|
1892 | DFLT_DMA_READ_INT_BUF_HIGH(fman->state->dma_thresh_max_buf); |
---|
1893 | |
---|
1894 | fman->cfg->dma_write_buf_tsh_clr_emer = |
---|
1895 | DFLT_DMA_WRITE_INT_BUF_LOW(fman->state->dma_thresh_max_buf); |
---|
1896 | |
---|
1897 | fman->cfg->dma_write_buf_tsh_asrt_emer = |
---|
1898 | DFLT_DMA_WRITE_INT_BUF_HIGH(fman->state->dma_thresh_max_buf); |
---|
1899 | |
---|
1900 | fman->cfg->dma_axi_dbg_num_of_beats = |
---|
1901 | DFLT_AXI_DBG_NUM_OF_BEATS; |
---|
1902 | } |
---|
1903 | |
---|
1904 | return 0; |
---|
1905 | |
---|
1906 | err_fm_soc_specific: |
---|
1907 | kfree(fman->cfg); |
---|
1908 | err_fm_drv: |
---|
1909 | kfree(fman->state); |
---|
1910 | err_fm_state: |
---|
1911 | kfree(fman); |
---|
1912 | return -EINVAL; |
---|
1913 | } |
---|
1914 | |
---|
1915 | static int fman_init(struct fman *fman) |
---|
1916 | { |
---|
1917 | struct fman_cfg *cfg = NULL; |
---|
1918 | struct fman_rg fman_rg; |
---|
1919 | int err = 0, i; |
---|
1920 | |
---|
1921 | if (is_init_done(fman->cfg)) |
---|
1922 | return -EINVAL; |
---|
1923 | |
---|
1924 | fman_rg.bmi_rg = fman->bmi_regs; |
---|
1925 | fman_rg.qmi_rg = fman->qmi_regs; |
---|
1926 | fman_rg.fpm_rg = fman->fpm_regs; |
---|
1927 | fman_rg.dma_rg = fman->dma_regs; |
---|
1928 | |
---|
1929 | fman->state->count1_micro_bit = FM_TIMESTAMP_1_USEC_BIT; |
---|
1930 | |
---|
1931 | cfg = fman->cfg; |
---|
1932 | |
---|
1933 | /* clear revision-dependent non existing exception */ |
---|
1934 | if (fman->state->rev_info.major < 6) |
---|
1935 | fman->state->exceptions &= ~FMAN_EX_BMI_DISPATCH_RAM_ECC; |
---|
1936 | |
---|
1937 | if (fman->state->rev_info.major >= 6) |
---|
1938 | fman->state->exceptions &= ~FMAN_EX_QMI_SINGLE_ECC; |
---|
1939 | |
---|
1940 | /* clear CPG */ |
---|
1941 | memset_io((void __iomem *)(fman->base_addr + CGP_OFFSET), 0, |
---|
1942 | fman->state->fm_port_num_of_cg); |
---|
1943 | |
---|
1944 | /* Save LIODN info before FMan reset |
---|
1945 | * Skipping non-existent port 0 (i = 1) |
---|
1946 | */ |
---|
1947 | for (i = 1; i < FMAN_LIODN_TBL; i++) { |
---|
1948 | u32 liodn_base; |
---|
1949 | |
---|
1950 | fman->liodn_offset[i] = |
---|
1951 | ioread32be(&fman_rg.bmi_rg->fmbm_spliodn[i - 1]); |
---|
1952 | liodn_base = ioread32be(&fman_rg.dma_rg->fmdmplr[i / 2]); |
---|
1953 | if (i % 2) { |
---|
1954 | /* FMDM_PLR LSB holds LIODN base for odd ports */ |
---|
1955 | liodn_base &= DMA_LIODN_BASE_MASK; |
---|
1956 | } else { |
---|
1957 | /* FMDM_PLR MSB holds LIODN base for even ports */ |
---|
1958 | liodn_base >>= DMA_LIODN_SHIFT; |
---|
1959 | liodn_base &= DMA_LIODN_BASE_MASK; |
---|
1960 | } |
---|
1961 | fman->liodn_base[i] = liodn_base; |
---|
1962 | } |
---|
1963 | |
---|
1964 | /* Reset the FM if required. */ |
---|
1965 | if (fman->reset_on_init) { |
---|
1966 | if (fman->state->rev_info.major >= 6) { |
---|
1967 | /* Errata A007273 */ |
---|
1968 | pr_debug("FManV3 reset is not supported!\n"); |
---|
1969 | } else { |
---|
1970 | out_be32(&fman->fpm_regs->fm_rstc, FPM_RSTC_FM_RESET); |
---|
1971 | /* Memory barrier */ |
---|
1972 | mb(); |
---|
1973 | usleep_range(100, 300); |
---|
1974 | } |
---|
1975 | |
---|
1976 | if (!!(ioread32be(&fman_rg.qmi_rg->fmqm_gs) & |
---|
1977 | QMI_GS_HALT_NOT_BUSY)) { |
---|
1978 | resume(fman->fpm_regs); |
---|
1979 | usleep_range(100, 300); |
---|
1980 | } |
---|
1981 | } |
---|
1982 | |
---|
1983 | if (clear_iram(fman) != 0) |
---|
1984 | return -EINVAL; |
---|
1985 | |
---|
1986 | cfg->exceptions = fman->state->exceptions; |
---|
1987 | |
---|
1988 | /* Init DMA Registers */ |
---|
1989 | |
---|
1990 | err = dma_init(fman); |
---|
1991 | if (err != 0) { |
---|
1992 | free_init_resources(fman); |
---|
1993 | return err; |
---|
1994 | } |
---|
1995 | |
---|
1996 | /* Init FPM Registers */ |
---|
1997 | fpm_init(fman->fpm_regs, fman->cfg); |
---|
1998 | |
---|
1999 | /* define common resources */ |
---|
2000 | /* allocate MURAM for FIFO according to total size */ |
---|
2001 | fman->fifo_offset = fman_muram_alloc(fman->muram, |
---|
2002 | fman->state->total_fifo_size); |
---|
2003 | if (IS_ERR_VALUE(fman->cam_offset)) { |
---|
2004 | free_init_resources(fman); |
---|
2005 | pr_err("MURAM alloc for BMI FIFO failed\n"); |
---|
2006 | return -ENOMEM; |
---|
2007 | } |
---|
2008 | |
---|
2009 | cfg->fifo_base_addr = fman->fifo_offset; |
---|
2010 | cfg->total_fifo_size = fman->state->total_fifo_size; |
---|
2011 | cfg->total_num_of_tasks = fman->state->total_num_of_tasks; |
---|
2012 | cfg->clk_freq = fman->state->fm_clk_freq; |
---|
2013 | |
---|
2014 | /* Init BMI Registers */ |
---|
2015 | bmi_init(fman->bmi_regs, fman->cfg); |
---|
2016 | |
---|
2017 | /* Init QMI Registers */ |
---|
2018 | qmi_init(fman->qmi_regs, fman->cfg); |
---|
2019 | |
---|
2020 | err = enable(&fman_rg, cfg); |
---|
2021 | if (err != 0) |
---|
2022 | return err; |
---|
2023 | |
---|
2024 | enable_time_stamp(fman); |
---|
2025 | |
---|
2026 | kfree(fman->cfg); |
---|
2027 | fman->cfg = NULL; |
---|
2028 | |
---|
2029 | return 0; |
---|
2030 | } |
---|
2031 | |
---|
2032 | static int fman_set_exception(struct fman *fman, |
---|
2033 | enum fman_exceptions exception, bool enable) |
---|
2034 | { |
---|
2035 | u32 bit_mask = 0; |
---|
2036 | struct fman_rg fman_rg; |
---|
2037 | |
---|
2038 | if (!is_init_done(fman->cfg)) |
---|
2039 | return -EINVAL; |
---|
2040 | |
---|
2041 | fman_rg.bmi_rg = fman->bmi_regs; |
---|
2042 | fman_rg.qmi_rg = fman->qmi_regs; |
---|
2043 | fman_rg.fpm_rg = fman->fpm_regs; |
---|
2044 | fman_rg.dma_rg = fman->dma_regs; |
---|
2045 | |
---|
2046 | bit_mask = get_exception_flag(exception); |
---|
2047 | if (bit_mask) { |
---|
2048 | if (enable) |
---|
2049 | fman->state->exceptions |= bit_mask; |
---|
2050 | else |
---|
2051 | fman->state->exceptions &= ~bit_mask; |
---|
2052 | } else { |
---|
2053 | pr_err("Undefined exception\n"); |
---|
2054 | return -EINVAL; |
---|
2055 | } |
---|
2056 | |
---|
2057 | return set_exception(&fman_rg, exception, enable); |
---|
2058 | } |
---|
2059 | |
---|
2060 | void fman_register_intr(struct fman *fman, enum fman_event_modules module, |
---|
2061 | u8 mod_id, enum fman_intr_type intr_type, |
---|
2062 | void (*isr_cb)(void *src_arg), void *src_arg) |
---|
2063 | { |
---|
2064 | int event = 0; |
---|
2065 | |
---|
2066 | event = get_module_event(module, mod_id, intr_type); |
---|
2067 | WARN_ON(!(event < FMAN_EV_CNT)); |
---|
2068 | |
---|
2069 | /* register in local FM structure */ |
---|
2070 | fman->intr_mng[event].isr_cb = isr_cb; |
---|
2071 | fman->intr_mng[event].src_handle = src_arg; |
---|
2072 | } |
---|
2073 | |
---|
2074 | void fman_unregister_intr(struct fman *fman, enum fman_event_modules module, |
---|
2075 | u8 mod_id, enum fman_intr_type intr_type) |
---|
2076 | { |
---|
2077 | int event = 0; |
---|
2078 | |
---|
2079 | event = get_module_event(module, mod_id, intr_type); |
---|
2080 | WARN_ON(!(event < FMAN_EV_CNT)); |
---|
2081 | |
---|
2082 | fman->intr_mng[event].isr_cb = NULL; |
---|
2083 | fman->intr_mng[event].src_handle = NULL; |
---|
2084 | } |
---|
2085 | |
---|
2086 | int fman_set_port_params(struct fman *fman, |
---|
2087 | struct fman_port_init_params *port_params) |
---|
2088 | { |
---|
2089 | int err; |
---|
2090 | unsigned long int_flags; |
---|
2091 | u8 port_id = port_params->port_id, mac_id; |
---|
2092 | struct fman_rg fman_rg; |
---|
2093 | |
---|
2094 | fman_rg.bmi_rg = fman->bmi_regs; |
---|
2095 | fman_rg.qmi_rg = fman->qmi_regs; |
---|
2096 | fman_rg.fpm_rg = fman->fpm_regs; |
---|
2097 | fman_rg.dma_rg = fman->dma_regs; |
---|
2098 | |
---|
2099 | spin_lock_irqsave(&fman->spinlock, int_flags); |
---|
2100 | |
---|
2101 | err = set_num_of_tasks(fman, port_params->port_id, |
---|
2102 | &port_params->num_of_tasks, |
---|
2103 | &port_params->num_of_extra_tasks); |
---|
2104 | if (err) { |
---|
2105 | spin_unlock_irqrestore(&fman->spinlock, int_flags); |
---|
2106 | return err; |
---|
2107 | } |
---|
2108 | |
---|
2109 | /* TX Ports */ |
---|
2110 | if (port_params->port_type != FMAN_PORT_TYPE_RX) { |
---|
2111 | u32 enq_th, deq_th, reg; |
---|
2112 | |
---|
2113 | /* update qmi ENQ/DEQ threshold */ |
---|
2114 | fman->state->accumulated_num_of_deq_tnums += |
---|
2115 | port_params->deq_pipeline_depth; |
---|
2116 | enq_th = (ioread32be(&fman_rg.qmi_rg->fmqm_gc) & |
---|
2117 | QMI_CFG_ENQ_MASK) >> QMI_CFG_ENQ_SHIFT; |
---|
2118 | /* if enq_th is too big, we reduce it to the max value |
---|
2119 | * that is still 0 |
---|
2120 | */ |
---|
2121 | if (enq_th >= (fman->state->qmi_max_num_of_tnums - |
---|
2122 | fman->state->accumulated_num_of_deq_tnums)) { |
---|
2123 | enq_th = |
---|
2124 | fman->state->qmi_max_num_of_tnums - |
---|
2125 | fman->state->accumulated_num_of_deq_tnums - 1; |
---|
2126 | |
---|
2127 | reg = ioread32be(&fman_rg.qmi_rg->fmqm_gc); |
---|
2128 | reg &= ~QMI_CFG_ENQ_MASK; |
---|
2129 | reg |= (enq_th << QMI_CFG_ENQ_SHIFT); |
---|
2130 | iowrite32be(reg, &fman_rg.qmi_rg->fmqm_gc); |
---|
2131 | } |
---|
2132 | |
---|
2133 | deq_th = ioread32be(&fman_rg.qmi_rg->fmqm_gc) & |
---|
2134 | QMI_CFG_DEQ_MASK; |
---|
2135 | /* if deq_th is too small, we enlarge it to the min |
---|
2136 | * value that is still 0. |
---|
2137 | * depTh may not be larger than 63 |
---|
2138 | * (fman->state->qmi_max_num_of_tnums-1). |
---|
2139 | */ |
---|
2140 | if ((deq_th <= fman->state->accumulated_num_of_deq_tnums) && |
---|
2141 | (deq_th < fman->state->qmi_max_num_of_tnums - 1)) { |
---|
2142 | deq_th = |
---|
2143 | fman->state->accumulated_num_of_deq_tnums + 1; |
---|
2144 | reg = ioread32be(&fman_rg.qmi_rg->fmqm_gc); |
---|
2145 | reg &= ~QMI_CFG_DEQ_MASK; |
---|
2146 | reg |= deq_th; |
---|
2147 | iowrite32be(reg, &fman_rg.qmi_rg->fmqm_gc); |
---|
2148 | } |
---|
2149 | } |
---|
2150 | |
---|
2151 | err = set_size_of_fifo(fman, port_params->port_id, |
---|
2152 | &port_params->size_of_fifo, |
---|
2153 | &port_params->extra_size_of_fifo); |
---|
2154 | if (err) { |
---|
2155 | spin_unlock_irqrestore(&fman->spinlock, int_flags); |
---|
2156 | return err; |
---|
2157 | } |
---|
2158 | |
---|
2159 | err = set_num_of_open_dmas(fman, port_params->port_id, |
---|
2160 | &port_params->num_of_open_dmas, |
---|
2161 | &port_params->num_of_extra_open_dmas); |
---|
2162 | if (err) { |
---|
2163 | spin_unlock_irqrestore(&fman->spinlock, int_flags); |
---|
2164 | return err; |
---|
2165 | } |
---|
2166 | |
---|
2167 | set_port_liodn(&fman_rg, port_id, fman->liodn_base[port_id], |
---|
2168 | fman->liodn_offset[port_id]); |
---|
2169 | |
---|
2170 | if (fman->state->rev_info.major < 6) |
---|
2171 | set_port_order_restoration(fman_rg.fpm_rg, port_id); |
---|
2172 | |
---|
2173 | mac_id = hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id); |
---|
2174 | |
---|
2175 | if (port_params->max_frame_length >= fman->state->mac_mfl[mac_id]) { |
---|
2176 | fman->state->port_mfl[mac_id] = port_params->max_frame_length; |
---|
2177 | } else { |
---|
2178 | pr_warn("Port max_frame_length is smaller than MAC current MTU\n"); |
---|
2179 | spin_unlock_irqrestore(&fman->spinlock, int_flags); |
---|
2180 | return -EINVAL; |
---|
2181 | } |
---|
2182 | |
---|
2183 | spin_unlock_irqrestore(&fman->spinlock, int_flags); |
---|
2184 | |
---|
2185 | return 0; |
---|
2186 | } |
---|
2187 | |
---|
2188 | int fman_reset_mac(struct fman *fman, u8 mac_id) |
---|
2189 | { |
---|
2190 | struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs; |
---|
2191 | u32 msk, timeout = 100; |
---|
2192 | |
---|
2193 | if (fman->state->rev_info.major >= 6) { |
---|
2194 | pr_warn("FMan MAC reset no available for FMan V3!\n"); |
---|
2195 | return -EINVAL; |
---|
2196 | } |
---|
2197 | |
---|
2198 | /* Get the relevant bit mask */ |
---|
2199 | switch (mac_id) { |
---|
2200 | case 0: |
---|
2201 | msk = FPM_RSTC_MAC0_RESET; |
---|
2202 | break; |
---|
2203 | case 1: |
---|
2204 | msk = FPM_RSTC_MAC1_RESET; |
---|
2205 | break; |
---|
2206 | case 2: |
---|
2207 | msk = FPM_RSTC_MAC2_RESET; |
---|
2208 | break; |
---|
2209 | case 3: |
---|
2210 | msk = FPM_RSTC_MAC3_RESET; |
---|
2211 | break; |
---|
2212 | case 4: |
---|
2213 | msk = FPM_RSTC_MAC4_RESET; |
---|
2214 | break; |
---|
2215 | case 5: |
---|
2216 | msk = FPM_RSTC_MAC5_RESET; |
---|
2217 | break; |
---|
2218 | case 6: |
---|
2219 | msk = FPM_RSTC_MAC6_RESET; |
---|
2220 | break; |
---|
2221 | case 7: |
---|
2222 | msk = FPM_RSTC_MAC7_RESET; |
---|
2223 | break; |
---|
2224 | case 8: |
---|
2225 | msk = FPM_RSTC_MAC8_RESET; |
---|
2226 | break; |
---|
2227 | case 9: |
---|
2228 | msk = FPM_RSTC_MAC9_RESET; |
---|
2229 | break; |
---|
2230 | default: |
---|
2231 | pr_warn("Illegal MAC Id\n"); |
---|
2232 | return -EINVAL; |
---|
2233 | } |
---|
2234 | |
---|
2235 | /* reset */ |
---|
2236 | iowrite32be(msk, &fpm_rg->fm_rstc); |
---|
2237 | while ((ioread32be(&fpm_rg->fm_rstc) & msk) && --timeout) |
---|
2238 | udelay(10); |
---|
2239 | |
---|
2240 | if (!timeout) |
---|
2241 | return -EIO; |
---|
2242 | |
---|
2243 | return 0; |
---|
2244 | } |
---|
2245 | |
---|
2246 | int fman_set_mac_max_frame(struct fman *fman, u8 mac_id, u16 mfl) |
---|
2247 | { |
---|
2248 | /* if port is already initialized, check that MaxFrameLength is smaller |
---|
2249 | * or equal to the port's max |
---|
2250 | */ |
---|
2251 | if ((!fman->state->port_mfl[mac_id]) || |
---|
2252 | (fman->state->port_mfl[mac_id] && |
---|
2253 | (mfl <= fman->state->port_mfl[mac_id]))) { |
---|
2254 | fman->state->mac_mfl[mac_id] = mfl; |
---|
2255 | } else { |
---|
2256 | pr_warn("MAC max_frame_length is larger than Port max_frame_length\n"); |
---|
2257 | return -EINVAL; |
---|
2258 | } |
---|
2259 | return 0; |
---|
2260 | } |
---|
2261 | |
---|
2262 | u16 fman_get_clock_freq(struct fman *fman) |
---|
2263 | { |
---|
2264 | return fman->state->fm_clk_freq; |
---|
2265 | } |
---|
2266 | |
---|
2267 | u32 fman_get_bmi_max_fifo_size(struct fman *fman) |
---|
2268 | { |
---|
2269 | return fman->state->bmi_max_fifo_size; |
---|
2270 | } |
---|
2271 | |
---|
2272 | static void fman_event_isr(struct fman *fman) |
---|
2273 | { |
---|
2274 | u32 pending; |
---|
2275 | struct fman_fpm_regs __iomem *fpm_rg; |
---|
2276 | |
---|
2277 | if (!is_init_done(fman->cfg)) |
---|
2278 | return; |
---|
2279 | |
---|
2280 | fpm_rg = fman->fpm_regs; |
---|
2281 | |
---|
2282 | /* normal interrupts */ |
---|
2283 | pending = ioread32be(&fpm_rg->fm_npi); |
---|
2284 | if (!pending) |
---|
2285 | return; |
---|
2286 | |
---|
2287 | if (pending & INTR_EN_QMI) |
---|
2288 | qmi_event(fman); |
---|
2289 | |
---|
2290 | /* MAC interrupts */ |
---|
2291 | if (pending & INTR_EN_MAC0) |
---|
2292 | call_mac_isr(fman, FMAN_EV_MAC0 + 0); |
---|
2293 | if (pending & INTR_EN_MAC1) |
---|
2294 | call_mac_isr(fman, FMAN_EV_MAC0 + 1); |
---|
2295 | if (pending & INTR_EN_MAC2) |
---|
2296 | call_mac_isr(fman, FMAN_EV_MAC0 + 2); |
---|
2297 | if (pending & INTR_EN_MAC3) |
---|
2298 | call_mac_isr(fman, FMAN_EV_MAC0 + 3); |
---|
2299 | if (pending & INTR_EN_MAC4) |
---|
2300 | call_mac_isr(fman, FMAN_EV_MAC0 + 4); |
---|
2301 | if (pending & INTR_EN_MAC5) |
---|
2302 | call_mac_isr(fman, FMAN_EV_MAC0 + 5); |
---|
2303 | if (pending & INTR_EN_MAC6) |
---|
2304 | call_mac_isr(fman, FMAN_EV_MAC0 + 6); |
---|
2305 | if (pending & INTR_EN_MAC7) |
---|
2306 | call_mac_isr(fman, FMAN_EV_MAC0 + 7); |
---|
2307 | if (pending & INTR_EN_MAC8) |
---|
2308 | call_mac_isr(fman, FMAN_EV_MAC0 + 8); |
---|
2309 | if (pending & INTR_EN_MAC9) |
---|
2310 | call_mac_isr(fman, FMAN_EV_MAC0 + 9); |
---|
2311 | } |
---|
2312 | |
---|
2313 | static int fman_error_isr(struct fman *fman) |
---|
2314 | { |
---|
2315 | u32 pending; |
---|
2316 | struct fman_fpm_regs __iomem *fpm_rg; |
---|
2317 | |
---|
2318 | if (!is_init_done(fman->cfg)) |
---|
2319 | return -EINVAL; |
---|
2320 | |
---|
2321 | fpm_rg = fman->fpm_regs; |
---|
2322 | |
---|
2323 | /* error interrupts */ |
---|
2324 | pending = ioread32be(&fpm_rg->fm_epi); |
---|
2325 | if (!pending) |
---|
2326 | return -EINVAL; |
---|
2327 | |
---|
2328 | if (pending & ERR_INTR_EN_BMI) |
---|
2329 | bmi_err_event(fman); |
---|
2330 | if (pending & ERR_INTR_EN_QMI) |
---|
2331 | qmi_err_event(fman); |
---|
2332 | if (pending & ERR_INTR_EN_FPM) |
---|
2333 | fpm_err_event(fman); |
---|
2334 | if (pending & ERR_INTR_EN_DMA) |
---|
2335 | dma_err_event(fman); |
---|
2336 | if (pending & ERR_INTR_EN_MURAM) |
---|
2337 | muram_err_intr(fman); |
---|
2338 | |
---|
2339 | /* MAC error interrupts */ |
---|
2340 | if (pending & ERR_INTR_EN_MAC0) |
---|
2341 | call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 0); |
---|
2342 | if (pending & ERR_INTR_EN_MAC1) |
---|
2343 | call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 1); |
---|
2344 | if (pending & ERR_INTR_EN_MAC2) |
---|
2345 | call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 2); |
---|
2346 | if (pending & ERR_INTR_EN_MAC3) |
---|
2347 | call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 3); |
---|
2348 | if (pending & ERR_INTR_EN_MAC4) |
---|
2349 | call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 4); |
---|
2350 | if (pending & ERR_INTR_EN_MAC5) |
---|
2351 | call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 5); |
---|
2352 | if (pending & ERR_INTR_EN_MAC6) |
---|
2353 | call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 6); |
---|
2354 | if (pending & ERR_INTR_EN_MAC7) |
---|
2355 | call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 7); |
---|
2356 | if (pending & ERR_INTR_EN_MAC8) |
---|
2357 | call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 8); |
---|
2358 | if (pending & ERR_INTR_EN_MAC9) |
---|
2359 | call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 9); |
---|
2360 | |
---|
2361 | return 0; |
---|
2362 | } |
---|
2363 | |
---|
2364 | void fman_get_revision(struct fman *fman, struct fman_rev_info *rev_info) |
---|
2365 | { |
---|
2366 | u32 tmp; |
---|
2367 | |
---|
2368 | tmp = ioread32be(&fman->fpm_regs->fm_ip_rev_1); |
---|
2369 | rev_info->major = (u8)((tmp & FPM_REV1_MAJOR_MASK) >> |
---|
2370 | FPM_REV1_MAJOR_SHIFT); |
---|
2371 | rev_info->minor = tmp & FPM_REV1_MINOR_MASK; |
---|
2372 | } |
---|
2373 | |
---|
2374 | u32 fman_get_qman_channel_id(struct fman *fman, u32 port_id) |
---|
2375 | { |
---|
2376 | int i; |
---|
2377 | |
---|
2378 | if (fman->state->rev_info.major >= 6) { |
---|
2379 | u32 port_ids[] = {0x30, 0x31, 0x28, 0x29, 0x2a, 0x2b, |
---|
2380 | 0x2c, 0x2d, 0x2, 0x3, 0x4, 0x5, 0x7, 0x7}; |
---|
2381 | for (i = 0; i < fman->state->num_of_qman_channels; i++) { |
---|
2382 | if (port_ids[i] == port_id) |
---|
2383 | break; |
---|
2384 | } |
---|
2385 | } else { |
---|
2386 | u32 port_ids[] = {0x30, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x1, |
---|
2387 | 0x2, 0x3, 0x4, 0x5, 0x7, 0x7}; |
---|
2388 | for (i = 0; i < fman->state->num_of_qman_channels; i++) { |
---|
2389 | if (port_ids[i] == port_id) |
---|
2390 | break; |
---|
2391 | } |
---|
2392 | } |
---|
2393 | |
---|
2394 | if (i == fman->state->num_of_qman_channels) |
---|
2395 | return 0; |
---|
2396 | |
---|
2397 | return fman->state->qman_channel_base + i; |
---|
2398 | } |
---|
2399 | |
---|
2400 | struct resource *fman_get_mem_region(struct fman *fman) |
---|
2401 | { |
---|
2402 | return fman->state->res; |
---|
2403 | } |
---|
2404 | |
---|
2405 | /* Bootargs defines */ |
---|
2406 | /* Extra headroom for RX buffers - Default, min and max */ |
---|
2407 | #define FSL_FM_RX_EXTRA_HEADROOM 64 |
---|
2408 | #define FSL_FM_RX_EXTRA_HEADROOM_MIN 16 |
---|
2409 | #define FSL_FM_RX_EXTRA_HEADROOM_MAX 384 |
---|
2410 | |
---|
2411 | /* Maximum frame length */ |
---|
2412 | #define FSL_FM_MAX_FRAME_SIZE 1522 |
---|
2413 | #define FSL_FM_MAX_POSSIBLE_FRAME_SIZE 9600 |
---|
2414 | #define FSL_FM_MIN_POSSIBLE_FRAME_SIZE 64 |
---|
2415 | |
---|
2416 | /* Extra headroom for Rx buffers. |
---|
2417 | * FMan is instructed to allocate, on the Rx path, this amount of |
---|
2418 | * space at the beginning of a data buffer, beside the DPA private |
---|
2419 | * data area and the IC fields. |
---|
2420 | * Does not impact Tx buffer layout. |
---|
2421 | * Configurable from bootargs. 64 by default, it's needed on |
---|
2422 | * particular forwarding scenarios that add extra headers to the |
---|
2423 | * forwarded frame. |
---|
2424 | */ |
---|
2425 | int fsl_fm_rx_extra_headroom = FSL_FM_RX_EXTRA_HEADROOM; |
---|
2426 | module_param(fsl_fm_rx_extra_headroom, int, 0); |
---|
2427 | MODULE_PARM_DESC(fsl_fm_rx_extra_headroom, "Extra headroom for Rx buffers"); |
---|
2428 | |
---|
2429 | /* Max frame size, across all interfaces. |
---|
2430 | * Configurable from bootargs, to avoid allocating oversized (socket) |
---|
2431 | * buffers when not using jumbo frames. |
---|
2432 | * Must be large enough to accommodate the network MTU, but small enough |
---|
2433 | * to avoid wasting skb memory. |
---|
2434 | * |
---|
2435 | * Could be overridden once, at boot-time, via the |
---|
2436 | * fm_set_max_frm() callback. |
---|
2437 | */ |
---|
2438 | #ifndef __rtems__ |
---|
2439 | int fsl_fm_max_frm = FSL_FM_MAX_FRAME_SIZE; |
---|
2440 | #else /* __rtems__ */ |
---|
2441 | int fsl_fm_max_frm = FSL_FM_MAX_POSSIBLE_FRAME_SIZE; |
---|
2442 | #endif /* __rtems__ */ |
---|
2443 | module_param(fsl_fm_max_frm, int, 0); |
---|
2444 | MODULE_PARM_DESC(fsl_fm_max_frm, "Maximum frame size, across all interfaces"); |
---|
2445 | |
---|
2446 | u16 fman_get_max_frm(void) |
---|
2447 | { |
---|
2448 | static bool fm_check_mfl; |
---|
2449 | |
---|
2450 | if (!fm_check_mfl) { |
---|
2451 | if (fsl_fm_max_frm > FSL_FM_MAX_POSSIBLE_FRAME_SIZE || |
---|
2452 | fsl_fm_max_frm < FSL_FM_MIN_POSSIBLE_FRAME_SIZE) { |
---|
2453 | pr_warn("Invalid fsl_fm_max_frm value (%d) in bootargs, valid range is %d-%d. Falling back to the default (%d)\n", |
---|
2454 | fsl_fm_max_frm, |
---|
2455 | FSL_FM_MIN_POSSIBLE_FRAME_SIZE, |
---|
2456 | FSL_FM_MAX_POSSIBLE_FRAME_SIZE, |
---|
2457 | FSL_FM_MAX_FRAME_SIZE); |
---|
2458 | fsl_fm_max_frm = FSL_FM_MAX_FRAME_SIZE; |
---|
2459 | } |
---|
2460 | fm_check_mfl = true; |
---|
2461 | } |
---|
2462 | |
---|
2463 | return fsl_fm_max_frm; |
---|
2464 | } |
---|
2465 | EXPORT_SYMBOL(fman_get_max_frm); |
---|
2466 | |
---|
2467 | int fman_get_rx_extra_headroom(void) |
---|
2468 | { |
---|
2469 | static bool fm_check_rx_extra_headroom; |
---|
2470 | |
---|
2471 | if (!fm_check_rx_extra_headroom) { |
---|
2472 | if (fsl_fm_rx_extra_headroom > FSL_FM_RX_EXTRA_HEADROOM_MAX || |
---|
2473 | fsl_fm_rx_extra_headroom < FSL_FM_RX_EXTRA_HEADROOM_MIN) { |
---|
2474 | pr_warn("Invalid fsl_fm_rx_extra_headroom value (%d) in bootargs, valid range is %d-%d. Falling back to the default (%d)\n", |
---|
2475 | fsl_fm_rx_extra_headroom, |
---|
2476 | FSL_FM_RX_EXTRA_HEADROOM_MIN, |
---|
2477 | FSL_FM_RX_EXTRA_HEADROOM_MAX, |
---|
2478 | FSL_FM_RX_EXTRA_HEADROOM); |
---|
2479 | fsl_fm_rx_extra_headroom = FSL_FM_RX_EXTRA_HEADROOM; |
---|
2480 | } |
---|
2481 | |
---|
2482 | fsl_fm_rx_extra_headroom = true; |
---|
2483 | fsl_fm_rx_extra_headroom = ALIGN(fsl_fm_rx_extra_headroom, 16); |
---|
2484 | } |
---|
2485 | |
---|
2486 | return fsl_fm_rx_extra_headroom; |
---|
2487 | } |
---|
2488 | EXPORT_SYMBOL(fman_get_rx_extra_headroom); |
---|
2489 | |
---|
2490 | struct fman *fman_bind(struct device *fm_dev) |
---|
2491 | { |
---|
2492 | return (struct fman *)(dev_get_drvdata(get_device(fm_dev))); |
---|
2493 | } |
---|
2494 | |
---|
2495 | void fman_unbind(struct fman *fman) |
---|
2496 | { |
---|
2497 | put_device(fman->dev); |
---|
2498 | } |
---|
2499 | |
---|
2500 | struct device *fman_get_device(struct fman *fman) |
---|
2501 | { |
---|
2502 | return fman->dev; |
---|
2503 | } |
---|
2504 | |
---|
2505 | static irqreturn_t fman_irq(int irq, void *fman) |
---|
2506 | { |
---|
2507 | fman_event_isr(fman); |
---|
2508 | |
---|
2509 | return IRQ_HANDLED; |
---|
2510 | } |
---|
2511 | |
---|
2512 | #ifndef __rtems__ |
---|
2513 | static const struct of_device_id fman_muram_match[] = { |
---|
2514 | { |
---|
2515 | .compatible = "fsl,fman-muram"}, |
---|
2516 | {} |
---|
2517 | }; |
---|
2518 | MODULE_DEVICE_TABLE(of, fman_muram_match); |
---|
2519 | #endif /* __rtems__ */ |
---|
2520 | |
---|
2521 | static struct fman *read_dts_node(struct platform_device *of_dev) |
---|
2522 | { |
---|
2523 | struct fman *fman; |
---|
2524 | #ifndef __rtems__ |
---|
2525 | struct device_node *fm_node, *muram_node; |
---|
2526 | struct resource *res; |
---|
2527 | #else /* __rtems__ */ |
---|
2528 | const char *fdt = bsp_fdt_get(); |
---|
2529 | struct device_node *fm_node; |
---|
2530 | #endif /* __rtems__ */ |
---|
2531 | const u32 *u32_prop; |
---|
2532 | int lenp, err, irq; |
---|
2533 | #ifndef __rtems__ |
---|
2534 | struct clk *clk; |
---|
2535 | u32 clk_rate; |
---|
2536 | #endif /* __rtems__ */ |
---|
2537 | phys_addr_t phys_base_addr; |
---|
2538 | #ifndef __rtems__ |
---|
2539 | resource_size_t mem_size; |
---|
2540 | #endif /* __rtems__ */ |
---|
2541 | |
---|
2542 | fman = kzalloc(sizeof(*fman), GFP_KERNEL); |
---|
2543 | if (!fman) |
---|
2544 | return NULL; |
---|
2545 | |
---|
2546 | fm_node = of_node_get(of_dev->dev.of_node); |
---|
2547 | |
---|
2548 | u32_prop = (const u32 *)of_get_property(fm_node, "cell-index", &lenp); |
---|
2549 | if (!u32_prop) { |
---|
2550 | pr_err("of_get_property(%s, cell-index) failed\n", |
---|
2551 | fm_node->full_name); |
---|
2552 | goto fman_node_put; |
---|
2553 | } |
---|
2554 | if (WARN_ON(lenp != sizeof(u32))) |
---|
2555 | goto fman_node_put; |
---|
2556 | |
---|
2557 | fman->dts_params.id = (u8)*u32_prop; |
---|
2558 | |
---|
2559 | #ifndef __rtems__ |
---|
2560 | /* Get the FM interrupt */ |
---|
2561 | res = platform_get_resource(of_dev, IORESOURCE_IRQ, 0); |
---|
2562 | if (!res) { |
---|
2563 | pr_err("Can't get FMan IRQ resource\n"); |
---|
2564 | goto fman_node_put; |
---|
2565 | } |
---|
2566 | irq = res->start; |
---|
2567 | |
---|
2568 | /* Get the FM error interrupt */ |
---|
2569 | res = platform_get_resource(of_dev, IORESOURCE_IRQ, 1); |
---|
2570 | if (!res) { |
---|
2571 | pr_err("Can't get FMan Error IRQ resource\n"); |
---|
2572 | goto fman_node_put; |
---|
2573 | } |
---|
2574 | fman->dts_params.err_irq = res->start; |
---|
2575 | |
---|
2576 | /* Get the FM address */ |
---|
2577 | res = platform_get_resource(of_dev, IORESOURCE_MEM, 0); |
---|
2578 | if (!res) { |
---|
2579 | pr_err("Can't get FMan memory resouce\n"); |
---|
2580 | goto fman_node_put; |
---|
2581 | } |
---|
2582 | |
---|
2583 | phys_base_addr = res->start; |
---|
2584 | mem_size = res->end + 1 - res->start; |
---|
2585 | #else /* __rtems__ */ |
---|
2586 | irq = of_irq_to_resource(fm_node, 0, NULL); |
---|
2587 | fman->dts_params.err_irq = of_irq_to_resource(fm_node, 1, NULL); |
---|
2588 | phys_base_addr = of_dev->dev.base; |
---|
2589 | fman->dts_params.base_addr = (void *)(uintptr_t)phys_base_addr; |
---|
2590 | #endif /* __rtems__ */ |
---|
2591 | |
---|
2592 | #ifndef __rtems__ |
---|
2593 | clk = of_clk_get_by_name(fm_node, NULL); |
---|
2594 | if (IS_ERR(clk)) { |
---|
2595 | pr_err("Failed to get FM%d clock structure\n", |
---|
2596 | fman->dts_params.id); |
---|
2597 | goto fman_node_put; |
---|
2598 | } |
---|
2599 | |
---|
2600 | clk_rate = clk_get_rate(clk); |
---|
2601 | if (!clk_rate) { |
---|
2602 | pr_err("Failed to determine FM%d clock rate\n", |
---|
2603 | fman->dts_params.id); |
---|
2604 | goto fman_node_put; |
---|
2605 | } |
---|
2606 | /* Rounding to MHz */ |
---|
2607 | fman->dts_params.clk_freq = (u16)((clk_rate + 500000) / 1000000); |
---|
2608 | #else /* __rtems__ */ |
---|
2609 | /* FIXME */ |
---|
2610 | fman->dts_params.clk_freq = 733; |
---|
2611 | #endif /* __rtems__ */ |
---|
2612 | |
---|
2613 | u32_prop = (const u32 *)of_get_property(fm_node, |
---|
2614 | "fsl,qman-channel-range", |
---|
2615 | &lenp); |
---|
2616 | if (!u32_prop) { |
---|
2617 | pr_err("of_get_property(%s, fsl,qman-channel-range) failed\n", |
---|
2618 | fm_node->full_name); |
---|
2619 | goto fman_node_put; |
---|
2620 | } |
---|
2621 | if (WARN_ON(lenp != sizeof(u32) * 2)) |
---|
2622 | goto fman_node_put; |
---|
2623 | fman->dts_params.qman_channel_base = u32_prop[0]; |
---|
2624 | fman->dts_params.num_of_qman_channels = u32_prop[1]; |
---|
2625 | |
---|
2626 | /* Get the MURAM base address and size */ |
---|
2627 | #ifndef __rtems__ |
---|
2628 | /* FIXME */ |
---|
2629 | muram_node = of_find_matching_node(fm_node, fman_muram_match); |
---|
2630 | if (!muram_node) { |
---|
2631 | pr_err("could not find MURAM node\n"); |
---|
2632 | goto fman_node_put; |
---|
2633 | } |
---|
2634 | |
---|
2635 | err = of_address_to_resource(muram_node, 0, res); |
---|
2636 | if (err) { |
---|
2637 | of_node_put(muram_node); |
---|
2638 | pr_err("of_address_to_resource() = %d\n", err); |
---|
2639 | goto fman_node_put; |
---|
2640 | } |
---|
2641 | |
---|
2642 | fman->dts_params.muram_phy_base_addr = res->start; |
---|
2643 | fman->dts_params.muram_size = res->end + 1 - res->start; |
---|
2644 | #else /* __rtems__ */ |
---|
2645 | { |
---|
2646 | int node = fdt_node_offset_by_compatible(fdt, |
---|
2647 | fm_node->offset, "fsl,fman-muram"); |
---|
2648 | struct device_node muram_node = { |
---|
2649 | .offset = node |
---|
2650 | }; |
---|
2651 | struct resource res; |
---|
2652 | |
---|
2653 | err = of_address_to_resource(&muram_node, 0, &res); |
---|
2654 | if (err != 0) { |
---|
2655 | pr_err("could not find MURAM node\n"); |
---|
2656 | goto fman_node_put; |
---|
2657 | } |
---|
2658 | fman->dts_params.muram_phy_base_addr = phys_base_addr + |
---|
2659 | res.start; |
---|
2660 | fman->dts_params.muram_size = res.end - res.start; |
---|
2661 | } |
---|
2662 | #endif /* __rtems__ */ |
---|
2663 | { |
---|
2664 | /* In B4 rev 2.0 (and above) the MURAM size is 512KB. |
---|
2665 | * Check the SVR and update MURAM size if required. |
---|
2666 | */ |
---|
2667 | u32 svr; |
---|
2668 | |
---|
2669 | svr = mfspr(SPRN_SVR); |
---|
2670 | |
---|
2671 | if ((SVR_SOC_VER(svr) == SVR_B4860) && (SVR_MAJ(svr) >= 2)) |
---|
2672 | fman->dts_params.muram_size = 0x80000; |
---|
2673 | } |
---|
2674 | |
---|
2675 | #ifndef __rtems__ |
---|
2676 | of_node_put(muram_node); |
---|
2677 | #endif /* __rtems__ */ |
---|
2678 | of_node_put(fm_node); |
---|
2679 | |
---|
2680 | err = devm_request_irq(&of_dev->dev, irq, fman_irq, |
---|
2681 | IRQF_NO_SUSPEND, "fman", fman); |
---|
2682 | if (err < 0) { |
---|
2683 | pr_err("Error: allocating irq %d (error = %d)\n", irq, err); |
---|
2684 | goto fman_free; |
---|
2685 | } |
---|
2686 | |
---|
2687 | #ifndef __rtems__ |
---|
2688 | fman->dts_params.res = |
---|
2689 | devm_request_mem_region(&of_dev->dev, phys_base_addr, |
---|
2690 | mem_size, "fman"); |
---|
2691 | if (!fman->dts_params.res) { |
---|
2692 | pr_err("request_mem_region() failed\n"); |
---|
2693 | goto fman_free; |
---|
2694 | } |
---|
2695 | |
---|
2696 | fman->dts_params.base_addr = |
---|
2697 | devm_ioremap(&of_dev->dev, phys_base_addr, mem_size); |
---|
2698 | if (fman->dts_params.base_addr == 0) { |
---|
2699 | pr_err("devm_ioremap() failed\n"); |
---|
2700 | goto fman_free; |
---|
2701 | } |
---|
2702 | #endif /* __rtems__ */ |
---|
2703 | |
---|
2704 | return fman; |
---|
2705 | |
---|
2706 | fman_node_put: |
---|
2707 | of_node_put(fm_node); |
---|
2708 | fman_free: |
---|
2709 | kfree(fman); |
---|
2710 | return NULL; |
---|
2711 | } |
---|
2712 | |
---|
2713 | static irqreturn_t fman_err_irq(int irq, void *fman) |
---|
2714 | { |
---|
2715 | if (fman_error_isr(fman) == 0) |
---|
2716 | return IRQ_HANDLED; |
---|
2717 | |
---|
2718 | return IRQ_NONE; |
---|
2719 | } |
---|
2720 | |
---|
2721 | static int fman_probe(struct platform_device *of_dev) |
---|
2722 | { |
---|
2723 | struct fman *fman; |
---|
2724 | struct device *dev; |
---|
2725 | int err; |
---|
2726 | |
---|
2727 | dev = &of_dev->dev; |
---|
2728 | |
---|
2729 | fman = read_dts_node(of_dev); |
---|
2730 | if (!fman) |
---|
2731 | return -EIO; |
---|
2732 | |
---|
2733 | if (fman->dts_params.err_irq != 0) { |
---|
2734 | err = devm_request_irq(dev, fman->dts_params.err_irq, |
---|
2735 | fman_err_irq, |
---|
2736 | IRQF_SHARED | IRQF_NO_SUSPEND, |
---|
2737 | "fman-err", fman); |
---|
2738 | if (err < 0) { |
---|
2739 | pr_err("Error: allocating irq %d (error = %d)\n", |
---|
2740 | fman->dts_params.err_irq, err); |
---|
2741 | return -EINVAL; |
---|
2742 | } |
---|
2743 | } |
---|
2744 | |
---|
2745 | err = fman_config(fman); |
---|
2746 | if (err) { |
---|
2747 | pr_err("FMan config failed\n"); |
---|
2748 | return -EINVAL; |
---|
2749 | } |
---|
2750 | |
---|
2751 | if (fman_init(fman) != 0) { |
---|
2752 | pr_err("FMan init failed\n"); |
---|
2753 | return -EINVAL; |
---|
2754 | } |
---|
2755 | |
---|
2756 | if (fman->dts_params.err_irq == 0) { |
---|
2757 | fman_set_exception(fman, FMAN_EX_DMA_BUS_ERROR, false); |
---|
2758 | fman_set_exception(fman, FMAN_EX_DMA_READ_ECC, false); |
---|
2759 | fman_set_exception(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC, false); |
---|
2760 | fman_set_exception(fman, FMAN_EX_DMA_FM_WRITE_ECC, false); |
---|
2761 | fman_set_exception(fman, FMAN_EX_DMA_SINGLE_PORT_ECC, false); |
---|
2762 | fman_set_exception(fman, FMAN_EX_FPM_STALL_ON_TASKS, false); |
---|
2763 | fman_set_exception(fman, FMAN_EX_FPM_SINGLE_ECC, false); |
---|
2764 | fman_set_exception(fman, FMAN_EX_FPM_DOUBLE_ECC, false); |
---|
2765 | fman_set_exception(fman, FMAN_EX_QMI_SINGLE_ECC, false); |
---|
2766 | fman_set_exception(fman, FMAN_EX_QMI_DOUBLE_ECC, false); |
---|
2767 | fman_set_exception(fman, |
---|
2768 | FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID, false); |
---|
2769 | fman_set_exception(fman, FMAN_EX_BMI_LIST_RAM_ECC, false); |
---|
2770 | fman_set_exception(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC, |
---|
2771 | false); |
---|
2772 | fman_set_exception(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC, false); |
---|
2773 | fman_set_exception(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC, false); |
---|
2774 | } |
---|
2775 | |
---|
2776 | dev_set_drvdata(dev, fman); |
---|
2777 | |
---|
2778 | fman->dev = dev; |
---|
2779 | |
---|
2780 | pr_debug("FM%d probed\n", fman->dts_params.id); |
---|
2781 | |
---|
2782 | return 0; |
---|
2783 | } |
---|
2784 | |
---|
2785 | #ifndef __rtems__ |
---|
2786 | static const struct of_device_id fman_match[] = { |
---|
2787 | { |
---|
2788 | .compatible = "fsl,fman"}, |
---|
2789 | {} |
---|
2790 | }; |
---|
2791 | |
---|
2792 | MODULE_DEVICE_TABLE(of, fm_match); |
---|
2793 | |
---|
2794 | static struct platform_driver fman_driver = { |
---|
2795 | .driver = { |
---|
2796 | .name = "fsl-fman", |
---|
2797 | .of_match_table = fman_match, |
---|
2798 | }, |
---|
2799 | .probe = fman_probe, |
---|
2800 | }; |
---|
2801 | |
---|
2802 | builtin_platform_driver(fman_driver); |
---|
2803 | #else /* __rtems__ */ |
---|
2804 | #include <sys/cdefs.h> |
---|
2805 | #include <sys/param.h> |
---|
2806 | #include <sys/systm.h> |
---|
2807 | #include <sys/bus.h> |
---|
2808 | #include <sys/kernel.h> |
---|
2809 | |
---|
2810 | void |
---|
2811 | fman_reset(struct fman *fman) |
---|
2812 | { |
---|
2813 | |
---|
2814 | /* |
---|
2815 | * Ignore errata A007273, since we do not disable the Ethernet MAC |
---|
2816 | * clocks. |
---|
2817 | */ |
---|
2818 | |
---|
2819 | out_be32(&fman->fpm_regs->fm_rstc, FPM_RSTC_FM_RESET); |
---|
2820 | /* Memory barrier */ |
---|
2821 | mb(); |
---|
2822 | usleep_range(100, 300); |
---|
2823 | |
---|
2824 | if (!!(ioread32be(&fman->qmi_regs->fmqm_gs) & |
---|
2825 | QMI_GS_HALT_NOT_BUSY)) { |
---|
2826 | usleep_range(100, 300); |
---|
2827 | } |
---|
2828 | } |
---|
2829 | |
---|
2830 | struct fman_softc { |
---|
2831 | struct platform_device of_dev; |
---|
2832 | struct device_node dn; |
---|
2833 | }; |
---|
2834 | |
---|
2835 | static int |
---|
2836 | fman_dev_probe_fdt(struct fman_softc *sc, int unit) |
---|
2837 | { |
---|
2838 | const char *fdt = bsp_fdt_get(); |
---|
2839 | const char *name = "fsl,fman"; |
---|
2840 | int node = 0; |
---|
2841 | |
---|
2842 | while (1) { |
---|
2843 | node = fdt_node_offset_by_compatible(fdt, node, name); |
---|
2844 | if (node >= 0) { |
---|
2845 | int len; |
---|
2846 | const fdt32_t *p = fdt_getprop(fdt, node, "cell-index", &len); |
---|
2847 | |
---|
2848 | if (p != NULL && len == sizeof(*p)) { |
---|
2849 | if (fdt32_to_cpu(*p) == (uint32_t)unit) { |
---|
2850 | sc->dn.offset = node; |
---|
2851 | sc->dn.full_name = name; |
---|
2852 | sc->of_dev.dev.of_node = &sc->dn; |
---|
2853 | sc->of_dev.dev.base = (uintptr_t)&qoriq.fman[unit]; |
---|
2854 | return (BUS_PROBE_DEFAULT); |
---|
2855 | } |
---|
2856 | } else { |
---|
2857 | return (ENXIO); |
---|
2858 | } |
---|
2859 | } else { |
---|
2860 | return (ENXIO); |
---|
2861 | } |
---|
2862 | } |
---|
2863 | } |
---|
2864 | |
---|
2865 | static int |
---|
2866 | fman_dev_probe(device_t dev) |
---|
2867 | { |
---|
2868 | struct fman_softc *sc = device_get_softc(dev); |
---|
2869 | |
---|
2870 | device_set_desc(dev, "FMan"); |
---|
2871 | |
---|
2872 | return (fman_dev_probe_fdt(sc, device_get_unit(dev))); |
---|
2873 | } |
---|
2874 | |
---|
2875 | static int |
---|
2876 | fman_dev_attach(device_t dev) |
---|
2877 | { |
---|
2878 | const char *fdt = bsp_fdt_get(); |
---|
2879 | struct fman_softc *sc = device_get_softc(dev); |
---|
2880 | int node; |
---|
2881 | int err; |
---|
2882 | |
---|
2883 | err = fman_probe(&sc->of_dev); |
---|
2884 | if (err != 0) { |
---|
2885 | return (ENXIO); |
---|
2886 | } |
---|
2887 | |
---|
2888 | node = fdt_first_subnode(fdt, sc->dn.offset); |
---|
2889 | while (node >= 0) { |
---|
2890 | struct fman_ivars *ivars = |
---|
2891 | kzalloc(sizeof(*ivars), GFP_KERNEL); |
---|
2892 | device_t child; |
---|
2893 | |
---|
2894 | if (ivars == NULL) { |
---|
2895 | return (ENOMEM); |
---|
2896 | } |
---|
2897 | |
---|
2898 | ivars->dn.offset = node; |
---|
2899 | ivars->of_dev.dev.of_node = &ivars->dn; |
---|
2900 | ivars->of_dev.dev.base = sc->of_dev.dev.base; |
---|
2901 | ivars->fman = dev_get_drvdata(&sc->of_dev.dev); |
---|
2902 | |
---|
2903 | child = device_add_child(dev, NULL, -1); |
---|
2904 | if (child == NULL) { |
---|
2905 | kfree(ivars); |
---|
2906 | return (ENOMEM); |
---|
2907 | } |
---|
2908 | |
---|
2909 | device_set_ivars(child, ivars); |
---|
2910 | |
---|
2911 | err = device_probe_and_attach(child); |
---|
2912 | if (err != 0) { |
---|
2913 | kfree(ivars); |
---|
2914 | } |
---|
2915 | |
---|
2916 | node = fdt_next_subnode(fdt, node); |
---|
2917 | } |
---|
2918 | |
---|
2919 | return (0); |
---|
2920 | } |
---|
2921 | |
---|
2922 | static int |
---|
2923 | fman_dev_detach(device_t dev) |
---|
2924 | { |
---|
2925 | struct fman_softc *sc = device_get_softc(dev); |
---|
2926 | int err; |
---|
2927 | |
---|
2928 | err = bus_generic_detach(dev); |
---|
2929 | if (err == 0) { |
---|
2930 | fman_reset(dev_get_drvdata(&sc->of_dev.dev)); |
---|
2931 | } |
---|
2932 | |
---|
2933 | return (err); |
---|
2934 | } |
---|
2935 | |
---|
2936 | static device_method_t fman_methods[] = { |
---|
2937 | /* Device interface */ |
---|
2938 | DEVMETHOD(device_probe, fman_dev_probe), |
---|
2939 | DEVMETHOD(device_attach, fman_dev_attach), |
---|
2940 | DEVMETHOD(device_detach, fman_dev_detach), |
---|
2941 | DEVMETHOD(device_suspend, bus_generic_suspend), |
---|
2942 | DEVMETHOD(device_resume, bus_generic_resume), |
---|
2943 | DEVMETHOD(device_shutdown, bus_generic_shutdown), |
---|
2944 | |
---|
2945 | DEVMETHOD_END |
---|
2946 | }; |
---|
2947 | |
---|
2948 | driver_t fman_driver = { |
---|
2949 | .name = "fman", |
---|
2950 | .methods = fman_methods, |
---|
2951 | .size = sizeof(struct fman_softc), |
---|
2952 | }; |
---|
2953 | |
---|
2954 | static devclass_t fman_devclass; |
---|
2955 | |
---|
2956 | DRIVER_MODULE(fman, nexus, fman_driver, fman_devclass, 0, 0); |
---|
2957 | #endif /* __rtems__ */ |
---|