Context Navigation

dpaa_eth.c @ cf40770

55-freebsd-126-freebsd-12

Last change on this file since cf40770 was cf40770, checked in by Sebastian Huber <sebastian.huber@…>, on 05/18/17 at 05:27:33

Linux update to 4.12-rc1+

Linux baseline b23afd384801711ab6dbccd259cc14cb09a1dcaf.

Property mode set to 100644

File size: 83.8 KB

Line
1	#include <machine/rtems-bsd-kernel-space.h>
2
3	#include <rtems/bsd/local/opt_dpaa.h>
4
5	/* Copyright 2008 - 2016 Freescale Semiconductor Inc.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	* * Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.
11	* * Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.
14	* * Neither the name of Freescale Semiconductor nor the
15	* names of its contributors may be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* ALTERNATIVELY, this software may be distributed under the terms of the
19	* GNU General Public License ("GPL") as published by the Free Software
20	* Foundation, either version 2 of that License or (at your option) any
21	* later version.
22	*
23	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33	*/
34
35	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37	#include <linux/init.h>
38	#include <linux/module.h>
39	#include <linux/of_platform.h>
40	#include <linux/of_mdio.h>
41	#include <linux/of_net.h>
42	#include <linux/io.h>
43	#ifndef __rtems__
44	#include <linux/if_arp.h>
45	#include <linux/if_vlan.h>
46	#include <linux/icmp.h>
47	#include <linux/ip.h>
48	#include <linux/ipv6.h>
49	#include <linux/udp.h>
50	#include <linux/tcp.h>
51	#include <linux/net.h>
52	#include <linux/skbuff.h>
53	#include <linux/etherdevice.h>
54	#include <linux/if_ether.h>
55	#include <linux/highmem.h>
56	#include <linux/percpu.h>
57	#include <linux/dma-mapping.h>
58	#include <linux/sort.h>
59	#endif /* __rtems__ */
60	#include <soc/fsl/bman.h>
61	#include <soc/fsl/qman.h>
62
63	#include "fman.h"
64	#include "fman_port.h"
65	#include "mac.h"
66	#include "dpaa_eth.h"
67
68	/* CREATE_TRACE_POINTS only needs to be defined once. Other dpaa files
69	* using trace events only need to #include <trace/events/sched.h>
70	*/
71	#define CREATE_TRACE_POINTS
72	#include "dpaa_eth_trace.h"
73
74	static int debug = -1;
75	module_param(debug, int, 0444);
76	MODULE_PARM_DESC(debug, "Module/Driver verbosity level (0=none,...,16=all)");
77
78	static u16 tx_timeout = 1000;
79	module_param(tx_timeout, ushort, 0444);
80	MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms");
81
82	#define FM_FD_STAT_RX_ERRORS \
83	(FM_FD_ERR_DMA \| FM_FD_ERR_PHYSICAL \| \
84	FM_FD_ERR_SIZE \| FM_FD_ERR_CLS_DISCARD \| \
85	FM_FD_ERR_EXTRACTION \| FM_FD_ERR_NO_SCHEME \| \
86	FM_FD_ERR_PRS_TIMEOUT \| FM_FD_ERR_PRS_ILL_INSTRUCT \| \
87	FM_FD_ERR_PRS_HDR_ERR)
88
89	#define FM_FD_STAT_TX_ERRORS \
90	(FM_FD_ERR_UNSUPPORTED_FORMAT \| \
91	FM_FD_ERR_LENGTH \| FM_FD_ERR_DMA)
92
93	#define DPAA_MSG_DEFAULT (NETIF_MSG_DRV \| NETIF_MSG_PROBE \| \
94	NETIF_MSG_LINK \| NETIF_MSG_IFUP \| \
95	NETIF_MSG_IFDOWN)
96
97	#define DPAA_INGRESS_CS_THRESHOLD 0x10000000
98	/* Ingress congestion threshold on FMan ports
99	* The size in bytes of the ingress tail-drop threshold on FMan ports.
100	* Traffic piling up above this value will be rejected by QMan and discarded
101	* by FMan.
102	*/
103
104	/* Size in bytes of the FQ taildrop threshold */
105	#define DPAA_FQ_TD 0x200000
106
107	#define DPAA_CS_THRESHOLD_1G 0x06000000
108	/* Egress congestion threshold on 1G ports, range 0x1000 .. 0x10000000
109	* The size in bytes of the egress Congestion State notification threshold on
110	* 1G ports. The 1G dTSECs can quite easily be flooded by cores doing Tx in a
111	* tight loop (e.g. by sending UDP datagrams at "while(1) speed"),
112	* and the larger the frame size, the more acute the problem.
113	* So we have to find a balance between these factors:
114	* - avoiding the device staying congested for a prolonged time (risking
115	* the netdev watchdog to fire - see also the tx_timeout module param);
116	* - affecting performance of protocols such as TCP, which otherwise
117	* behave well under the congestion notification mechanism;
118	* - preventing the Tx cores from tightly-looping (as if the congestion
119	* threshold was too low to be effective);
120	* - running out of memory if the CS threshold is set too high.
121	*/
122
123	#define DPAA_CS_THRESHOLD_10G 0x10000000
124	/* The size in bytes of the egress Congestion State notification threshold on
125	* 10G ports, range 0x1000 .. 0x10000000
126	*/
127
128	/* Largest value that the FQD's OAL field can hold */
129	#define FSL_QMAN_MAX_OAL 127
130
131	/* Default alignment for start of data in an Rx FD */
132	#define DPAA_FD_DATA_ALIGNMENT 16
133
134	/* Values for the L3R field of the FM Parse Results
135	*/
136	/* L3 Type field: First IP Present IPv4 */
137	#define FM_L3_PARSE_RESULT_IPV4 0x8000
138	/* L3 Type field: First IP Present IPv6 */
139	#define FM_L3_PARSE_RESULT_IPV6 0x4000
140	/* Values for the L4R field of the FM Parse Results */
141	/* L4 Type field: UDP */
142	#define FM_L4_PARSE_RESULT_UDP 0x40
143	/* L4 Type field: TCP */
144	#define FM_L4_PARSE_RESULT_TCP 0x20
145
146	/* FD status field indicating whether the FM Parser has attempted to validate
147	* the L4 csum of the frame.
148	* Note that having this bit set doesn't necessarily imply that the checksum
149	* is valid. One would have to check the parse results to find that out.
150	*/
151	#define FM_FD_STAT_L4CV 0x00000004
152
153	#define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
154	#define DPAA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */
155
156	#define FSL_DPAA_BPID_INV 0xff
157	#define FSL_DPAA_ETH_MAX_BUF_COUNT 128
158	#define FSL_DPAA_ETH_REFILL_THRESHOLD 80
159
160	#define DPAA_TX_PRIV_DATA_SIZE 16
161	#define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result)
162	#define DPAA_TIME_STAMP_SIZE 8
163	#define DPAA_HASH_RESULTS_SIZE 8
164	#define DPAA_RX_PRIV_DATA_SIZE (u16)(DPAA_TX_PRIV_DATA_SIZE + \
165	dpaa_rx_extra_headroom)
166
167	#define DPAA_ETH_RX_QUEUES 128
168
169	#define DPAA_ENQUEUE_RETRIES 100000
170
171	enum port_type {RX, TX};
172
173	struct fm_port_fqs {
174	struct dpaa_fq *tx_defq;
175	struct dpaa_fq *tx_errq;
176	struct dpaa_fq *rx_defq;
177	struct dpaa_fq *rx_errq;
178	};
179
180	/* All the dpa bps in use at any moment */
181	static struct dpaa_bp *dpaa_bp_array[BM_MAX_NUM_OF_POOLS];
182
183	/* The raw buffer size must be cacheline aligned */
184	#ifndef __rtems__
185	#define DPAA_BP_RAW_SIZE 4096
186	#else /* __rtems__ */
187	/*
188	* FIXME: Support multiple buffer pools.
189	*/
190	#define DPAA_BP_RAW_SIZE 2048
191
192	/*
193	* FIXME: 4 bytes would be enough for the mbuf pointer. However, jumbo receive
194	* frames overwrite this area if < 64 bytes.
195	*/
196	#define DPAA_OUT_OF_BAND_SIZE 64
197
198	#define DPAA_MBUF_POINTER_OFFSET (DPAA_BP_RAW_SIZE - DPAA_OUT_OF_BAND_SIZE)
199	#endif /* __rtems__ */
200	/* When using more than one buffer pool, the raw sizes are as follows:
201	* 1 bp: 4KB
202	* 2 bp: 2KB, 4KB
203	* 3 bp: 1KB, 2KB, 4KB
204	* 4 bp: 1KB, 2KB, 4KB, 8KB
205	*/
206	static inline size_t bpool_buffer_raw_size(u8 index, u8 cnt)
207	{
208	size_t res = DPAA_BP_RAW_SIZE / 4;
209	u8 i;
210
211	for (i = (cnt < 3) ? cnt : 3; i < 3 + index; i++)
212	res *= 2;
213	return res;
214	}
215
216	/* FMan-DMA requires 16-byte alignment for Rx buffers, but SKB_DATA_ALIGN is
217	* even stronger (SMP_CACHE_BYTES-aligned), so we just get away with that,
218	* via SKB_WITH_OVERHEAD(). We can't rely on netdev_alloc_frag() giving us
219	* half-page-aligned buffers, so we reserve some more space for start-of-buffer
220	* alignment.
221	*/
222	#ifndef __rtems__
223	#define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD((raw_size) - SMP_CACHE_BYTES)
224	#else /* __rtems__ */
225	#define dpaa_bp_size(raw_size) DPAA_MBUF_POINTER_OFFSET
226	#endif /* __rtems__ */
227
228	#ifndef __rtems__
229	static int dpaa_max_frm;
230	#endif /* __rtems__ */
231
232	#ifndef __rtems__
233	static int dpaa_rx_extra_headroom;
234	#else /* __rtems__ */
235	#define dpaa_rx_extra_headroom fman_get_rx_extra_headroom()
236	#endif /* __rtems__ */
237
238	#define dpaa_get_max_mtu() \
239	(dpaa_max_frm - (VLAN_ETH_HLEN + ETH_FCS_LEN))
240
241	#ifndef __rtems__
242	static int dpaa_netdev_init(struct net_device *net_dev,
243	const struct net_device_ops *dpaa_ops,
244	u16 tx_timeout)
245	{
246	struct dpaa_priv *priv = netdev_priv(net_dev);
247	struct device *dev = net_dev->dev.parent;
248	struct dpaa_percpu_priv *percpu_priv;
249	const u8 *mac_addr;
250	int i, err;
251
252	/* Although we access another CPU's private data here
253	* we do it at initialization so it is safe
254	*/
255	for_each_possible_cpu(i) {
256	percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
257	percpu_priv->net_dev = net_dev;
258	}
259
260	net_dev->netdev_ops = dpaa_ops;
261	mac_addr = priv->mac_dev->addr;
262
263	net_dev->mem_start = priv->mac_dev->res->start;
264	net_dev->mem_end = priv->mac_dev->res->end;
265
266	net_dev->min_mtu = ETH_MIN_MTU;
267	net_dev->max_mtu = dpaa_get_max_mtu();
268
269	net_dev->hw_features \|= (NETIF_F_IP_CSUM \| NETIF_F_IPV6_CSUM \|
270	NETIF_F_LLTX);
271
272	net_dev->hw_features \|= NETIF_F_SG \| NETIF_F_HIGHDMA;
273	/* The kernels enables GSO automatically, if we declare NETIF_F_SG.
274	* For conformity, we'll still declare GSO explicitly.
275	*/
276	net_dev->features \|= NETIF_F_GSO;
277	net_dev->features \|= NETIF_F_RXCSUM;
278
279	net_dev->priv_flags \|= IFF_LIVE_ADDR_CHANGE;
280	/* we do not want shared skbs on TX */
281	net_dev->priv_flags &= ~IFF_TX_SKB_SHARING;
282
283	net_dev->features \|= net_dev->hw_features;
284	net_dev->vlan_features = net_dev->features;
285
286	memcpy(net_dev->perm_addr, mac_addr, net_dev->addr_len);
287	memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len);
288
289	net_dev->ethtool_ops = &dpaa_ethtool_ops;
290
291	net_dev->needed_headroom = priv->tx_headroom;
292	net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
293
294	/* start without the RUNNING flag, phylib controls it later */
295	netif_carrier_off(net_dev);
296
297	err = register_netdev(net_dev);
298	if (err < 0) {
299	dev_err(dev, "register_netdev() = %d\n", err);
300	return err;
301	}
302
303	return 0;
304	}
305	#endif /* __rtems__ */
306
307	static int dpaa_stop(struct net_device *net_dev)
308	{
309	struct mac_device *mac_dev;
310	struct dpaa_priv *priv;
311	int i, err, error;
312
313	priv = netdev_priv(net_dev);
314	mac_dev = priv->mac_dev;
315
316	#ifndef __rtems__
317	netif_tx_stop_all_queues(net_dev);
318	#endif /* __rtems__ */
319	/* Allow the Fman (Tx) port to process in-flight frames before we
320	* try switching it off.
321	*/
322	usleep_range(5000, 10000);
323
324	err = mac_dev->stop(mac_dev);
325	if (err < 0)
326	netif_err(priv, ifdown, net_dev, "mac_dev->stop() = %d\n",
327	err);
328
329	for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
330	error = fman_port_disable(mac_dev->port[i]);
331	if (error)
332	err = error;
333	}
334
335	#ifndef __rtems__
336	if (net_dev->phydev)
337	phy_disconnect(net_dev->phydev);
338	net_dev->phydev = NULL;
339	#endif /* __rtems__ */
340
341	return err;
342	}
343
344	#ifndef __rtems__
345	static void dpaa_tx_timeout(struct net_device *net_dev)
346	{
347	struct dpaa_percpu_priv *percpu_priv;
348	const struct dpaa_priv *priv;
349
350	priv = netdev_priv(net_dev);
351	percpu_priv = this_cpu_ptr(priv->percpu_priv);
352
353	netif_crit(priv, timer, net_dev, "Transmit timeout latency: %u ms\n",
354	jiffies_to_msecs(jiffies - dev_trans_start(net_dev)));
355
356	percpu_priv->stats.tx_errors++;
357	}
358
359	/* Calculates the statistics for the given device by adding the statistics
360	* collected by each CPU.
361	*/
362	static void dpaa_get_stats64(struct net_device *net_dev,
363	struct rtnl_link_stats64 *s)
364	{
365	int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64);
366	struct dpaa_priv *priv = netdev_priv(net_dev);
367	struct dpaa_percpu_priv *percpu_priv;
368	u64 netstats = (u64 )s;
369	u64 *cpustats;
370	int i, j;
371
372	for_each_possible_cpu(i) {
373	percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
374
375	cpustats = (u64 *)&percpu_priv->stats;
376
377	/* add stats from all CPUs */
378	for (j = 0; j < numstats; j++)
379	netstats[j] += cpustats[j];
380	}
381	}
382
383	static int dpaa_setup_tc(struct net_device *net_dev, u32 handle, __be16 proto,
384	struct tc_to_netdev *tc)
385	{
386	struct dpaa_priv *priv = netdev_priv(net_dev);
387	u8 num_tc;
388	int i;
389
390	if (tc->type != TC_SETUP_MQPRIO)
391	return -EINVAL;
392
393	tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
394	num_tc = tc->mqprio->num_tc;
395
396	if (num_tc == priv->num_tc)
397	return 0;
398
399	if (!num_tc) {
400	netdev_reset_tc(net_dev);
401	goto out;
402	}
403
404	if (num_tc > DPAA_TC_NUM) {
405	netdev_err(net_dev, "Too many traffic classes: max %d supported.\n",
406	DPAA_TC_NUM);
407	return -EINVAL;
408	}
409
410	netdev_set_num_tc(net_dev, num_tc);
411
412	for (i = 0; i < num_tc; i++)
413	netdev_set_tc_queue(net_dev, i, DPAA_TC_TXQ_NUM,
414	i * DPAA_TC_TXQ_NUM);
415
416	out:
417	priv->num_tc = num_tc ? : 1;
418	netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM);
419	return 0;
420	}
421
422	static struct mac_device dpaa_mac_dev_get(struct platform_device pdev)
423	{
424	struct platform_device *of_dev;
425	struct dpaa_eth_data *eth_data;
426	struct device dpaa_dev, dev;
427	struct device_node *mac_node;
428	struct mac_device *mac_dev;
429
430	dpaa_dev = &pdev->dev;
431	eth_data = dpaa_dev->platform_data;
432	if (!eth_data)
433	return ERR_PTR(-ENODEV);
434
435	mac_node = eth_data->mac_node;
436
437	of_dev = of_find_device_by_node(mac_node);
438	if (!of_dev) {
439	dev_err(dpaa_dev, "of_find_device_by_node(%s) failed\n",
440	mac_node->full_name);
441	of_node_put(mac_node);
442	return ERR_PTR(-EINVAL);
443	}
444	of_node_put(mac_node);
445
446	dev = &of_dev->dev;
447
448	mac_dev = dev_get_drvdata(dev);
449	if (!mac_dev) {
450	dev_err(dpaa_dev, "dev_get_drvdata(%s) failed\n",
451	dev_name(dev));
452	return ERR_PTR(-EINVAL);
453	}
454
455	return mac_dev;
456	}
457
458	static int dpaa_set_mac_address(struct net_device net_dev, void addr)
459	{
460	const struct dpaa_priv *priv;
461	struct mac_device *mac_dev;
462	struct sockaddr old_addr;
463	int err;
464
465	priv = netdev_priv(net_dev);
466
467	memcpy(old_addr.sa_data, net_dev->dev_addr, ETH_ALEN);
468
469	err = eth_mac_addr(net_dev, addr);
470	if (err < 0) {
471	netif_err(priv, drv, net_dev, "eth_mac_addr() = %d\n", err);
472	return err;
473	}
474
475	mac_dev = priv->mac_dev;
476
477	err = mac_dev->change_addr(mac_dev->fman_mac,
478	(enet_addr_t *)net_dev->dev_addr);
479	if (err < 0) {
480	netif_err(priv, drv, net_dev, "mac_dev->change_addr() = %d\n",
481	err);
482	/* reverting to previous address */
483	eth_mac_addr(net_dev, &old_addr);
484
485	return err;
486	}
487
488	return 0;
489	}
490
491	static void dpaa_set_rx_mode(struct net_device *net_dev)
492	{
493	const struct dpaa_priv *priv;
494	int err;
495
496	priv = netdev_priv(net_dev);
497
498	if (!!(net_dev->flags & IFF_PROMISC) != priv->mac_dev->promisc) {
499	priv->mac_dev->promisc = !priv->mac_dev->promisc;
500	err = priv->mac_dev->set_promisc(priv->mac_dev->fman_mac,
501	priv->mac_dev->promisc);
502	if (err < 0)
503	netif_err(priv, drv, net_dev,
504	"mac_dev->set_promisc() = %d\n",
505	err);
506	}
507
508	err = priv->mac_dev->set_multi(net_dev, priv->mac_dev);
509	if (err < 0)
510	netif_err(priv, drv, net_dev, "mac_dev->set_multi() = %d\n",
511	err);
512	}
513	#endif /* __rtems__ */
514
515	static struct dpaa_bp *dpaa_bpid2pool(int bpid)
516	{
517	if (WARN_ON(bpid < 0 \|\| bpid >= BM_MAX_NUM_OF_POOLS))
518	return NULL;
519
520	return dpaa_bp_array[bpid];
521	}
522
523	/* checks if this bpool is already allocated */
524	static bool dpaa_bpid2pool_use(int bpid)
525	{
526	if (dpaa_bpid2pool(bpid)) {
527	atomic_inc(&dpaa_bp_array[bpid]->refs);
528	return true;
529	}
530
531	return false;
532	}
533
534	/* called only once per bpid by dpaa_bp_alloc_pool() */
535	static void dpaa_bpid2pool_map(int bpid, struct dpaa_bp *dpaa_bp)
536	{
537	dpaa_bp_array[bpid] = dpaa_bp;
538	atomic_set(&dpaa_bp->refs, 1);
539	}
540
541	static int dpaa_bp_alloc_pool(struct dpaa_bp *dpaa_bp)
542	{
543	int err;
544
545	if (dpaa_bp->size == 0 \|\| dpaa_bp->config_count == 0) {
546	pr_err("%s: Buffer pool is not properly initialized! Missing size or initial number of buffers\n",
547	__func__);
548	return -EINVAL;
549	}
550
551	/* If the pool is already specified, we only create one per bpid */
552	if (dpaa_bp->bpid != FSL_DPAA_BPID_INV &&
553	dpaa_bpid2pool_use(dpaa_bp->bpid))
554	return 0;
555
556	if (dpaa_bp->bpid == FSL_DPAA_BPID_INV) {
557	dpaa_bp->pool = bman_new_pool();
558	if (!dpaa_bp->pool) {
559	pr_err("%s: bman_new_pool() failed\n",
560	__func__);
561	return -ENODEV;
562	}
563
564	dpaa_bp->bpid = (u8)bman_get_bpid(dpaa_bp->pool);
565	}
566
567	if (dpaa_bp->seed_cb) {
568	err = dpaa_bp->seed_cb(dpaa_bp);
569	if (err)
570	goto pool_seed_failed;
571	}
572
573	dpaa_bpid2pool_map(dpaa_bp->bpid, dpaa_bp);
574
575	return 0;
576
577	pool_seed_failed:
578	pr_err("%s: pool seeding failed\n", __func__);
579	bman_free_pool(dpaa_bp->pool);
580
581	return err;
582	}
583
584	/* remove and free all the buffers from the given buffer pool */
585	static void dpaa_bp_drain(struct dpaa_bp *bp)
586	{
587	u8 num = 8;
588	int ret;
589
590	do {
591	struct bm_buffer bmb[8];
592	int i;
593
594	ret = bman_acquire(bp->pool, bmb, num);
595	if (ret < 0) {
596	if (num == 8) {
597	/* we have less than 8 buffers left;
598	* drain them one by one
599	*/
600	num = 1;
601	ret = 1;
602	continue;
603	} else {
604	/* Pool is fully drained */
605	break;
606	}
607	}
608
609	if (bp->free_buf_cb)
610	for (i = 0; i < num; i++)
611	bp->free_buf_cb(bp, &bmb[i]);
612	} while (ret > 0);
613	}
614
615	static void dpaa_bp_free(struct dpaa_bp *dpaa_bp)
616	{
617	struct dpaa_bp *bp = dpaa_bpid2pool(dpaa_bp->bpid);
618
619	/* the mapping between bpid and dpaa_bp is done very late in the
620	* allocation procedure; if something failed before the mapping, the bp
621	* was not configured, therefore we don't need the below instructions
622	*/
623	if (!bp)
624	return;
625
626	if (!atomic_dec_and_test(&bp->refs))
627	return;
628
629	if (bp->free_buf_cb)
630	dpaa_bp_drain(bp);
631
632	dpaa_bp_array[bp->bpid] = NULL;
633	bman_free_pool(bp->pool);
634	}
635
636	static void dpaa_bps_free(struct dpaa_priv *priv)
637	{
638	int i;
639
640	for (i = 0; i < DPAA_BPS_NUM; i++)
641	dpaa_bp_free(priv->dpaa_bps[i]);
642	}
643
644	/* Use multiple WQs for FQ assignment:
645	* - Tx Confirmation queues go to WQ1.
646	* - Rx Error and Tx Error queues go to WQ5 (giving them a better chance
647	* to be scheduled, in case there are many more FQs in WQ6).
648	* - Rx Default goes to WQ6.
649	* - Tx queues go to different WQs depending on their priority. Equal
650	* chunks of NR_CPUS queues go to WQ6 (lowest priority), WQ2, WQ1 and
651	* WQ0 (highest priority).
652	* This ensures that Tx-confirmed buffers are timely released. In particular,
653	* it avoids congestion on the Tx Confirm FQs, which can pile up PFDRs if they
654	* are greatly outnumbered by other FQs in the system, while
655	* dequeue scheduling is round-robin.
656	*/
657	static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx)
658	{
659	switch (fq->fq_type) {
660	case FQ_TYPE_TX_CONFIRM:
661	case FQ_TYPE_TX_CONF_MQ:
662	fq->wq = 1;
663	break;
664	case FQ_TYPE_RX_ERROR:
665	case FQ_TYPE_TX_ERROR:
666	fq->wq = 5;
667	break;
668	case FQ_TYPE_RX_DEFAULT:
669	fq->wq = 6;
670	break;
671	case FQ_TYPE_TX:
672	switch (idx / DPAA_TC_TXQ_NUM) {
673	case 0:
674	/* Low priority (best effort) */
675	fq->wq = 6;
676	break;
677	case 1:
678	/* Medium priority */
679	fq->wq = 2;
680	break;
681	case 2:
682	/* High priority */
683	fq->wq = 1;
684	break;
685	case 3:
686	/* Very high priority */
687	fq->wq = 0;
688	break;
689	default:
690	WARN(1, "Too many TX FQs: more than %d!\n",
691	DPAA_ETH_TXQ_NUM);
692	}
693	break;
694	default:
695	WARN(1, "Invalid FQ type %d for FQID %d!\n",
696	fq->fq_type, fq->fqid);
697	}
698	}
699
700	static struct dpaa_fq dpaa_fq_alloc(struct device dev,
701	u32 start, u32 count,
702	struct list_head *list,
703	enum dpaa_fq_type fq_type)
704	{
705	struct dpaa_fq *dpaa_fq;
706	int i;
707
708	dpaa_fq = devm_kzalloc(dev, sizeof(dpaa_fq) count,
709	GFP_KERNEL);
710	if (!dpaa_fq)
711	return NULL;
712
713	for (i = 0; i < count; i++) {
714	dpaa_fq[i].fq_type = fq_type;
715	dpaa_fq[i].fqid = start ? start + i : 0;
716	list_add_tail(&dpaa_fq[i].list, list);
717	}
718
719	for (i = 0; i < count; i++)
720	dpaa_assign_wq(dpaa_fq + i, i);
721
722	return dpaa_fq;
723	}
724
725	static int dpaa_alloc_all_fqs(struct device dev, struct list_head list,
726	struct fm_port_fqs *port_fqs)
727	{
728	struct dpaa_fq *dpaa_fq;
729
730	dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_ERROR);
731	if (!dpaa_fq)
732	goto fq_alloc_failed;
733
734	port_fqs->rx_errq = &dpaa_fq[0];
735
736	dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_DEFAULT);
737	if (!dpaa_fq)
738	goto fq_alloc_failed;
739
740	port_fqs->rx_defq = &dpaa_fq[0];
741
742	if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX_CONF_MQ))
743	goto fq_alloc_failed;
744
745	dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_ERROR);
746	if (!dpaa_fq)
747	goto fq_alloc_failed;
748
749	port_fqs->tx_errq = &dpaa_fq[0];
750
751	dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_CONFIRM);
752	if (!dpaa_fq)
753	goto fq_alloc_failed;
754
755	port_fqs->tx_defq = &dpaa_fq[0];
756
757	if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX))
758	goto fq_alloc_failed;
759
760	return 0;
761
762	fq_alloc_failed:
763	dev_err(dev, "dpaa_fq_alloc() failed\n");
764	return -ENOMEM;
765	}
766
767	static u32 rx_pool_channel;
768	static DEFINE_SPINLOCK(rx_pool_channel_init);
769
770	static int dpaa_get_channel(void)
771	{
772	spin_lock(&rx_pool_channel_init);
773	if (!rx_pool_channel) {
774	u32 pool;
775	int ret;
776
777	ret = qman_alloc_pool(&pool);
778
779	if (!ret)
780	rx_pool_channel = pool;
781	}
782	spin_unlock(&rx_pool_channel_init);
783	if (!rx_pool_channel)
784	return -ENOMEM;
785	return rx_pool_channel;
786	}
787
788	#ifndef __rtems__
789	static void dpaa_release_channel(void)
790	{
791	qman_release_pool(rx_pool_channel);
792	}
793	#endif /* __rtems__ */
794
795	static void dpaa_eth_add_channel(u16 channel)
796	{
797	u32 pool = QM_SDQCR_CHANNELS_POOL_CONV(channel);
798	#ifndef __rtems__
799	const cpumask_t *cpus = qman_affine_cpus();
800	#endif /* __rtems__ */
801	struct qman_portal *portal;
802	int cpu;
803
804	for_each_cpu(cpu, cpus) {
805	portal = qman_get_affine_portal(cpu);
806	qman_p_static_dequeue_add(portal, pool);
807	}
808	}
809
810	/* Congestion group state change notification callback.
811	* Stops the device's egress queues while they are congested and
812	* wakes them upon exiting congested state.
813	* Also updates some CGR-related stats.
814	*/
815	static void dpaa_eth_cgscn(struct qman_portal qm, struct qman_cgr cgr,
816	int congested)
817	{
818	struct dpaa_priv priv = (struct dpaa_priv )container_of(cgr,
819	struct dpaa_priv, cgr_data.cgr);
820
821	if (congested) {
822	priv->cgr_data.congestion_start_jiffies = jiffies;
823	#ifndef __rtems__
824	netif_tx_stop_all_queues(priv->net_dev);
825	#endif /* __rtems__ */
826	priv->cgr_data.cgr_congested_count++;
827	} else {
828	priv->cgr_data.congested_jiffies +=
829	(jiffies - priv->cgr_data.congestion_start_jiffies);
830	#ifndef __rtems__
831	netif_tx_wake_all_queues(priv->net_dev);
832	#endif /* __rtems__ */
833	}
834	}
835
836	static int dpaa_eth_cgr_init(struct dpaa_priv *priv)
837	{
838	struct qm_mcc_initcgr initcgr;
839	u32 cs_th;
840	int err;
841
842	err = qman_alloc_cgrid(&priv->cgr_data.cgr.cgrid);
843	if (err < 0) {
844	if (netif_msg_drv(priv))
845	pr_err("%s: Error %d allocating CGR ID\n",
846	__func__, err);
847	goto out_error;
848	}
849	priv->cgr_data.cgr.cb = dpaa_eth_cgscn;
850
851	/* Enable Congestion State Change Notifications and CS taildrop */
852	memset(&initcgr, 0, sizeof(initcgr));
853	initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN \| QM_CGR_WE_CS_THRES);
854	initcgr.cgr.cscn_en = QM_CGR_EN;
855
856	/* Set different thresholds based on the MAC speed.
857	* This may turn suboptimal if the MAC is reconfigured at a speed
858	* lower than its max, e.g. if a dTSEC later negotiates a 100Mbps link.
859	* In such cases, we ought to reconfigure the threshold, too.
860	*/
861	if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full)
862	cs_th = DPAA_CS_THRESHOLD_10G;
863	else
864	cs_th = DPAA_CS_THRESHOLD_1G;
865	qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
866
867	initcgr.we_mask \|= cpu_to_be16(QM_CGR_WE_CSTD_EN);
868	initcgr.cgr.cstd_en = QM_CGR_EN;
869
870	err = qman_create_cgr(&priv->cgr_data.cgr, QMAN_CGR_FLAG_USE_INIT,
871	&initcgr);
872	if (err < 0) {
873	if (netif_msg_drv(priv))
874	pr_err("%s: Error %d creating CGR with ID %d\n",
875	__func__, err, priv->cgr_data.cgr.cgrid);
876	qman_release_cgrid(priv->cgr_data.cgr.cgrid);
877	goto out_error;
878	}
879	if (netif_msg_drv(priv))
880	pr_debug("Created CGR %d for netdev with hwaddr %pM on QMan channel %d\n",
881	priv->cgr_data.cgr.cgrid, priv->mac_dev->addr,
882	priv->cgr_data.cgr.chan);
883
884	out_error:
885	return err;
886	}
887
888	static inline void dpaa_setup_ingress(const struct dpaa_priv *priv,
889	struct dpaa_fq *fq,
890	const struct qman_fq *template)
891	{
892	fq->fq_base = *template;
893	fq->net_dev = priv->net_dev;
894
895	fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE;
896	fq->channel = priv->channel;
897	}
898
899	static inline void dpaa_setup_egress(const struct dpaa_priv *priv,
900	struct dpaa_fq *fq,
901	struct fman_port *port,
902	const struct qman_fq *template)
903	{
904	fq->fq_base = *template;
905	fq->net_dev = priv->net_dev;
906
907	if (port) {
908	fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL;
909	fq->channel = (u16)fman_port_get_qman_channel_id(port);
910	} else {
911	fq->flags = QMAN_FQ_FLAG_NO_MODIFY;
912	}
913	}
914
915	static void dpaa_fq_setup(struct dpaa_priv *priv,
916	const struct dpaa_fq_cbs *fq_cbs,
917	struct fman_port *tx_port)
918	{
919	#ifndef __rtems__
920	int egress_cnt = 0, conf_cnt = 0, num_portals = 0, cpu;
921	const cpumask_t *affine_cpus = qman_affine_cpus();
922	u16 portals[NR_CPUS];
923	#else /* __rtems__ */
924	int egress_cnt = 0, conf_cnt = 0;
925	#endif /* __rtems__ */
926	struct dpaa_fq *fq;
927
928	#ifndef __rtems__
929	for_each_cpu(cpu, affine_cpus)
930	portals[num_portals++] = qman_affine_channel(cpu);
931	if (num_portals == 0)
932	dev_err(priv->net_dev->dev.parent,
933	"No Qman software (affine) channels found");
934	#endif /* __rtems__ */
935
936	/* Initialize each FQ in the list */
937	list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
938	switch (fq->fq_type) {
939	case FQ_TYPE_RX_DEFAULT:
940	dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
941	break;
942	case FQ_TYPE_RX_ERROR:
943	dpaa_setup_ingress(priv, fq, &fq_cbs->rx_errq);
944	break;
945	case FQ_TYPE_TX:
946	dpaa_setup_egress(priv, fq, tx_port,
947	&fq_cbs->egress_ern);
948	/* If we have more Tx queues than the number of cores,
949	* just ignore the extra ones.
950	*/
951	if (egress_cnt < DPAA_ETH_TXQ_NUM)
952	priv->egress_fqs[egress_cnt++] = &fq->fq_base;
953	break;
954	case FQ_TYPE_TX_CONF_MQ:
955	priv->conf_fqs[conf_cnt++] = &fq->fq_base;
956	/* fall through */
957	case FQ_TYPE_TX_CONFIRM:
958	dpaa_setup_ingress(priv, fq, &fq_cbs->tx_defq);
959	break;
960	case FQ_TYPE_TX_ERROR:
961	dpaa_setup_ingress(priv, fq, &fq_cbs->tx_errq);
962	break;
963	default:
964	#ifndef __rtems__
965	dev_warn(priv->net_dev->dev.parent,
966	"Unknown FQ type detected!\n");
967	#else /* __rtems__ */
968	BSD_ASSERT(0);
969	#endif /* __rtems__ */
970	break;
971	}
972	}
973
974	/* Make sure all CPUs receive a corresponding Tx queue. */
975	while (egress_cnt < DPAA_ETH_TXQ_NUM) {
976	list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
977	if (fq->fq_type != FQ_TYPE_TX)
978	continue;
979	priv->egress_fqs[egress_cnt++] = &fq->fq_base;
980	if (egress_cnt == DPAA_ETH_TXQ_NUM)
981	break;
982	}
983	}
984	}
985
986	static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv,
987	struct qman_fq *tx_fq)
988	{
989	int i;
990
991	for (i = 0; i < DPAA_ETH_TXQ_NUM; i++)
992	if (priv->egress_fqs[i] == tx_fq)
993	return i;
994
995	return -EINVAL;
996	}
997
998	static int dpaa_fq_init(struct dpaa_fq *dpaa_fq, bool td_enable)
999	{
1000	const struct dpaa_priv *priv;
1001	struct qman_fq *confq = NULL;
1002	struct qm_mcc_initfq initfq;
1003	#ifndef __rtems__
1004	struct device *dev;
1005	#endif /* __rtems__ */
1006	struct qman_fq *fq;
1007	int queue_id;
1008	int err;
1009
1010	priv = netdev_priv(dpaa_fq->net_dev);
1011	#ifndef __rtems__
1012	dev = dpaa_fq->net_dev->dev.parent;
1013	#endif /* __rtems__ */
1014
1015	if (dpaa_fq->fqid == 0)
1016	dpaa_fq->flags \|= QMAN_FQ_FLAG_DYNAMIC_FQID;
1017
1018	dpaa_fq->init = !(dpaa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY);
1019
1020	err = qman_create_fq(dpaa_fq->fqid, dpaa_fq->flags, &dpaa_fq->fq_base);
1021	if (err) {
1022	#ifndef __rtems__
1023	dev_err(dev, "qman_create_fq() failed\n");
1024	#else /* __rtems__ */
1025	BSD_ASSERT(0);
1026	#endif /* __rtems__ */
1027	return err;
1028	}
1029	fq = &dpaa_fq->fq_base;
1030
1031	if (dpaa_fq->init) {
1032	memset(&initfq, 0, sizeof(initfq));
1033
1034	initfq.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL);
1035	/* Note: we may get to keep an empty FQ in cache */
1036	initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_PREFERINCACHE);
1037
1038	/* Try to reduce the number of portal interrupts for
1039	* Tx Confirmation FQs.
1040	*/
1041	if (dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM)
1042	initfq.fqd.fq_ctrl \|= cpu_to_be16(QM_FQCTRL_AVOIDBLOCK);
1043
1044	/* FQ placement */
1045	initfq.we_mask \|= cpu_to_be16(QM_INITFQ_WE_DESTWQ);
1046
1047	qm_fqd_set_destwq(&initfq.fqd, dpaa_fq->channel, dpaa_fq->wq);
1048
1049	/* Put all egress queues in a congestion group of their own.
1050	* Sensu stricto, the Tx confirmation queues are Rx FQs,
1051	* rather than Tx - but they nonetheless account for the
1052	* memory footprint on behalf of egress traffic. We therefore
1053	* place them in the netdev's CGR, along with the Tx FQs.
1054	*/
1055	if (dpaa_fq->fq_type == FQ_TYPE_TX \|\|
1056	dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM \|\|
1057	dpaa_fq->fq_type == FQ_TYPE_TX_CONF_MQ) {
1058	initfq.we_mask \|= cpu_to_be16(QM_INITFQ_WE_CGID);
1059	initfq.fqd.fq_ctrl \|= cpu_to_be16(QM_FQCTRL_CGE);
1060	initfq.fqd.cgid = (u8)priv->cgr_data.cgr.cgrid;
1061	/* Set a fixed overhead accounting, in an attempt to
1062	* reduce the impact of fixed-size skb shells and the
1063	* driver's needed headroom on system memory. This is
1064	* especially the case when the egress traffic is
1065	* composed of small datagrams.
1066	* Unfortunately, QMan's OAL value is capped to an
1067	* insufficient value, but even that is better than
1068	* no overhead accounting at all.
1069	*/
1070	initfq.we_mask \|= cpu_to_be16(QM_INITFQ_WE_OAC);
1071	qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1072	qm_fqd_set_oal(&initfq.fqd,
1073	#ifndef __rtems__
1074	min(sizeof(struct sk_buff) +
1075	#else /* __rtems__ */
1076	min(
1077	#endif /* __rtems__ */
1078	priv->tx_headroom,
1079	(size_t)FSL_QMAN_MAX_OAL));
1080	}
1081
1082	if (td_enable) {
1083	initfq.we_mask \|= cpu_to_be16(QM_INITFQ_WE_TDTHRESH);
1084	qm_fqd_set_taildrop(&initfq.fqd, DPAA_FQ_TD, 1);
1085	initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_TDE);
1086	}
1087
1088	if (dpaa_fq->fq_type == FQ_TYPE_TX) {
1089	queue_id = dpaa_tx_fq_to_id(priv, &dpaa_fq->fq_base);
1090	if (queue_id >= 0)
1091	confq = priv->conf_fqs[queue_id];
1092	if (confq) {
1093	initfq.we_mask \|=
1094	cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1095	/* ContextA: OVOM=1(use contextA2 bits instead of ICAD)
1096	* A2V=1 (contextA A2 field is valid)
1097	* A0V=1 (contextA A0 field is valid)
1098	* B0V=1 (contextB field is valid)
1099	* ContextA A2: EBD=1 (deallocate buffers inside FMan)
1100	* ContextB B0(ASPID): 0 (absolute Virtual Storage ID)
1101	*/
1102	qm_fqd_context_a_set64(&initfq.fqd,
1103	0x1e00000080000000ULL);
1104	}
1105	}
1106
1107	/* Put all the ingress queues in our "ingress CGR". */
1108	if (priv->use_ingress_cgr &&
1109	(dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT \|\|
1110	dpaa_fq->fq_type == FQ_TYPE_RX_ERROR)) {
1111	initfq.we_mask \|= cpu_to_be16(QM_INITFQ_WE_CGID);
1112	initfq.fqd.fq_ctrl \|= cpu_to_be16(QM_FQCTRL_CGE);
1113	initfq.fqd.cgid = (u8)priv->ingress_cgr.cgrid;
1114	/* Set a fixed overhead accounting, just like for the
1115	* egress CGR.
1116	*/
1117	initfq.we_mask \|= cpu_to_be16(QM_INITFQ_WE_OAC);
1118	qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1119	qm_fqd_set_oal(&initfq.fqd,
1120	#ifndef __rtems__
1121	min(sizeof(struct sk_buff) +
1122	#else /* __rtems__ */
1123	min(
1124	#endif /* __rtems__ */
1125	priv->tx_headroom,
1126	(size_t)FSL_QMAN_MAX_OAL));
1127	}
1128
1129	/* Initialization common to all ingress queues */
1130	if (dpaa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) {
1131	initfq.we_mask \|= cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1132	initfq.fqd.fq_ctrl \|= cpu_to_be16(QM_FQCTRL_HOLDACTIVE \|
1133	QM_FQCTRL_CTXASTASHING);
1134	initfq.fqd.context_a.stashing.exclusive =
1135	QM_STASHING_EXCL_DATA \| QM_STASHING_EXCL_CTX \|
1136	QM_STASHING_EXCL_ANNOTATION;
1137	qm_fqd_set_stashing(&initfq.fqd, 1, 2,
1138	DIV_ROUND_UP(sizeof(struct qman_fq),
1139	64));
1140	}
1141
1142	err = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq);
1143	if (err < 0) {
1144	#ifndef __rtems__
1145	dev_err(dev, "qman_init_fq(%u) = %d\n",
1146	qman_fq_fqid(fq), err);
1147	#else /* __rtems__ */
1148	BSD_ASSERT(0);
1149	#endif /* __rtems__ */
1150	qman_destroy_fq(fq);
1151	return err;
1152	}
1153	}
1154
1155	dpaa_fq->fqid = qman_fq_fqid(fq);
1156
1157	return 0;
1158	}
1159
1160	#ifndef __rtems__
1161	static int dpaa_fq_free_entry(struct device dev, struct qman_fq fq)
1162	{
1163	#ifndef __rtems__
1164	const struct dpaa_priv *priv;
1165	#endif /* __rtems__ */
1166	struct dpaa_fq *dpaa_fq;
1167	int err, error;
1168
1169	err = 0;
1170
1171	dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
1172	#ifndef __rtems__
1173	priv = netdev_priv(dpaa_fq->net_dev);
1174	#endif /* __rtems__ */
1175
1176	if (dpaa_fq->init) {
1177	err = qman_retire_fq(fq, NULL);
1178	if (err < 0 && netif_msg_drv(priv))
1179	dev_err(dev, "qman_retire_fq(%u) = %d\n",
1180	qman_fq_fqid(fq), err);
1181
1182	error = qman_oos_fq(fq);
1183	if (error < 0 && netif_msg_drv(priv)) {
1184	dev_err(dev, "qman_oos_fq(%u) = %d\n",
1185	qman_fq_fqid(fq), error);
1186	if (err >= 0)
1187	err = error;
1188	}
1189	}
1190
1191	qman_destroy_fq(fq);
1192	list_del(&dpaa_fq->list);
1193
1194	return err;
1195	}
1196
1197	static int dpaa_fq_free(struct device dev, struct list_head list)
1198	{
1199	struct dpaa_fq dpaa_fq, tmp;
1200	int err, error;
1201
1202	err = 0;
1203	list_for_each_entry_safe(dpaa_fq, tmp, list, list) {
1204	error = dpaa_fq_free_entry(dev, (struct qman_fq *)dpaa_fq);
1205	if (error < 0 && err >= 0)
1206	err = error;
1207	}
1208
1209	return err;
1210	}
1211	#endif /* __rtems__ */
1212
1213	static int dpaa_eth_init_tx_port(struct fman_port port, struct dpaa_fq errq,
1214	struct dpaa_fq *defq,
1215	struct dpaa_buffer_layout *buf_layout)
1216	{
1217	struct fman_buffer_prefix_content buf_prefix_content;
1218	struct fman_port_params params;
1219	int err;
1220
1221	memset(&params, 0, sizeof(params));
1222	memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1223
1224	buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1225	buf_prefix_content.pass_prs_result = true;
1226	buf_prefix_content.pass_hash_result = true;
1227	buf_prefix_content.pass_time_stamp = false;
1228	buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
1229
1230	params.specific_params.non_rx_params.err_fqid = errq->fqid;
1231	params.specific_params.non_rx_params.dflt_fqid = defq->fqid;
1232
1233	err = fman_port_config(port, &params);
1234	if (err) {
1235	pr_err("%s: fman_port_config failed\n", __func__);
1236	return err;
1237	}
1238
1239	err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1240	if (err) {
1241	pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1242	__func__);
1243	return err;
1244	}
1245
1246	err = fman_port_init(port);
1247	if (err)
1248	pr_err("%s: fm_port_init failed\n", __func__);
1249
1250	return err;
1251	}
1252
1253	static int dpaa_eth_init_rx_port(struct fman_port port, struct dpaa_bp *bps,
1254	size_t count, struct dpaa_fq *errq,
1255	struct dpaa_fq *defq,
1256	struct dpaa_buffer_layout *buf_layout)
1257	{
1258	struct fman_buffer_prefix_content buf_prefix_content;
1259	struct fman_port_rx_params *rx_p;
1260	struct fman_port_params params;
1261	int i, err;
1262
1263	memset(&params, 0, sizeof(params));
1264	memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1265
1266	buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1267	buf_prefix_content.pass_prs_result = true;
1268	buf_prefix_content.pass_hash_result = true;
1269	buf_prefix_content.pass_time_stamp = false;
1270	buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
1271
1272	rx_p = &params.specific_params.rx_params;
1273	rx_p->err_fqid = errq->fqid;
1274	rx_p->dflt_fqid = defq->fqid;
1275
1276	count = min(ARRAY_SIZE(rx_p->ext_buf_pools.ext_buf_pool), count);
1277	rx_p->ext_buf_pools.num_of_pools_used = (u8)count;
1278	for (i = 0; i < count; i++) {
1279	rx_p->ext_buf_pools.ext_buf_pool[i].id = bps[i]->bpid;
1280	rx_p->ext_buf_pools.ext_buf_pool[i].size = (u16)bps[i]->size;
1281	}
1282
1283	err = fman_port_config(port, &params);
1284	if (err) {
1285	pr_err("%s: fman_port_config failed\n", __func__);
1286	return err;
1287	}
1288
1289	err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1290	if (err) {
1291	pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1292	__func__);
1293	return err;
1294	}
1295
1296	err = fman_port_init(port);
1297	if (err)
1298	pr_err("%s: fm_port_init failed\n", __func__);
1299
1300	return err;
1301	}
1302
1303	static int dpaa_eth_init_ports(struct mac_device *mac_dev,
1304	struct dpaa_bp **bps, size_t count,
1305	struct fm_port_fqs *port_fqs,
1306	struct dpaa_buffer_layout *buf_layout,
1307	struct device *dev)
1308	{
1309	struct fman_port *rxport = mac_dev->port[RX];
1310	struct fman_port *txport = mac_dev->port[TX];
1311	int err;
1312
1313	err = dpaa_eth_init_tx_port(txport, port_fqs->tx_errq,
1314	port_fqs->tx_defq, &buf_layout[TX]);
1315	if (err)
1316	return err;
1317
1318	err = dpaa_eth_init_rx_port(rxport, bps, count, port_fqs->rx_errq,
1319	port_fqs->rx_defq, &buf_layout[RX]);
1320
1321	return err;
1322	}
1323
1324	static int dpaa_bman_release(const struct dpaa_bp *dpaa_bp,
1325	struct bm_buffer *bmb, int cnt)
1326	{
1327	int err;
1328
1329	err = bman_release(dpaa_bp->pool, bmb, cnt);
1330	/* Should never occur, address anyway to avoid leaking the buffers */
1331	if (unlikely(WARN_ON(err)) && dpaa_bp->free_buf_cb)
1332	while (cnt-- > 0)
1333	dpaa_bp->free_buf_cb(dpaa_bp, &bmb[cnt]);
1334
1335	return cnt;
1336	}
1337
1338	static void dpaa_release_sgt_members(struct qm_sg_entry *sgt)
1339	{
1340	struct bm_buffer bmb[DPAA_BUFF_RELEASE_MAX];
1341	struct dpaa_bp *dpaa_bp;
1342	int i = 0, j;
1343
1344	memset(bmb, 0, sizeof(bmb));
1345
1346	do {
1347	dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1348	if (!dpaa_bp)
1349	return;
1350
1351	j = 0;
1352	do {
1353	WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1354
1355	bm_buffer_set64(&bmb[j], qm_sg_entry_get64(&sgt[i]));
1356
1357	j++; i++;
1358	} while (j < ARRAY_SIZE(bmb) &&
1359	!qm_sg_entry_is_final(&sgt[i - 1]) &&
1360	sgt[i - 1].bpid == sgt[i].bpid);
1361
1362	dpaa_bman_release(dpaa_bp, bmb, j);
1363	} while (!qm_sg_entry_is_final(&sgt[i - 1]));
1364	}
1365
1366	static void dpaa_fd_release(const struct net_device *net_dev,
1367	const struct qm_fd *fd)
1368	{
1369	struct qm_sg_entry *sgt;
1370	struct dpaa_bp *dpaa_bp;
1371	struct bm_buffer bmb;
1372	dma_addr_t addr;
1373	void *vaddr;
1374
1375	bmb.data = 0;
1376	bm_buffer_set64(&bmb, qm_fd_addr(fd));
1377
1378	dpaa_bp = dpaa_bpid2pool(fd->bpid);
1379	if (!dpaa_bp)
1380	return;
1381
1382	if (qm_fd_get_format(fd) == qm_fd_sg) {
1383	vaddr = phys_to_virt(qm_fd_addr(fd));
1384	sgt = vaddr + qm_fd_get_offset(fd);
1385
1386	#ifndef __rtems__
1387	dma_unmap_single(dpaa_bp->dev, qm_fd_addr(fd), dpaa_bp->size,
1388	DMA_FROM_DEVICE);
1389	#endif /* __rtems__ */
1390
1391	dpaa_release_sgt_members(sgt);
1392
1393	#ifndef __rtems__
1394	addr = dma_map_single(dpaa_bp->dev, vaddr, dpaa_bp->size,
1395	DMA_FROM_DEVICE);
1396	if (dma_mapping_error(dpaa_bp->dev, addr)) {
1397	dev_err(dpaa_bp->dev, "DMA mapping failed");
1398	return;
1399	}
1400	#else /* __rtems__ */
1401	addr = (dma_addr_t)vaddr;
1402	#endif /* __rtems__ */
1403	bm_buffer_set64(&bmb, addr);
1404	}
1405
1406	dpaa_bman_release(dpaa_bp, &bmb, 1);
1407	}
1408
1409	static void count_ern(struct dpaa_percpu_priv *percpu_priv,
1410	const union qm_mr_entry *msg)
1411	{
1412	switch (msg->ern.rc & QM_MR_RC_MASK) {
1413	case QM_MR_RC_CGR_TAILDROP:
1414	percpu_priv->ern_cnt.cg_tdrop++;
1415	break;
1416	case QM_MR_RC_WRED:
1417	percpu_priv->ern_cnt.wred++;
1418	break;
1419	case QM_MR_RC_ERROR:
1420	percpu_priv->ern_cnt.err_cond++;
1421	break;
1422	case QM_MR_RC_ORPWINDOW_EARLY:
1423	percpu_priv->ern_cnt.early_window++;
1424	break;
1425	case QM_MR_RC_ORPWINDOW_LATE:
1426	percpu_priv->ern_cnt.late_window++;
1427	break;
1428	case QM_MR_RC_FQ_TAILDROP:
1429	percpu_priv->ern_cnt.fq_tdrop++;
1430	break;
1431	case QM_MR_RC_ORPWINDOW_RETIRED:
1432	percpu_priv->ern_cnt.fq_retired++;
1433	break;
1434	case QM_MR_RC_ORP_ZERO:
1435	percpu_priv->ern_cnt.orp_zero++;
1436	break;
1437	}
1438	}
1439
1440	#ifndef __rtems__
1441	/* Turn on HW checksum computation for this outgoing frame.
1442	* If the current protocol is not something we support in this regard
1443	* (or if the stack has already computed the SW checksum), we do nothing.
1444	*
1445	* Returns 0 if all goes well (or HW csum doesn't apply), and a negative value
1446	* otherwise.
1447	*
1448	* Note that this function may modify the fd->cmd field and the skb data buffer
1449	* (the Parse Results area).
1450	*/
1451	static int dpaa_enable_tx_csum(struct dpaa_priv *priv,
1452	struct sk_buff *skb,
1453	struct qm_fd *fd,
1454	char *parse_results)
1455	{
1456	struct fman_prs_result *parse_result;
1457	u16 ethertype = ntohs(skb->protocol);
1458	struct ipv6hdr *ipv6h = NULL;
1459	struct iphdr *iph;
1460	int retval = 0;
1461	u8 l4_proto;
1462
1463	if (skb->ip_summed != CHECKSUM_PARTIAL)
1464	return 0;
1465
1466	/* Note: L3 csum seems to be already computed in sw, but we can't choose
1467	* L4 alone from the FM configuration anyway.
1468	*/
1469
1470	/* Fill in some fields of the Parse Results array, so the FMan
1471	* can find them as if they came from the FMan Parser.
1472	*/
1473	parse_result = (struct fman_prs_result *)parse_results;
1474
1475	/* If we're dealing with VLAN, get the real Ethernet type */
1476	if (ethertype == ETH_P_8021Q) {
1477	/* We can't always assume the MAC header is set correctly
1478	* by the stack, so reset to beginning of skb->data
1479	*/
1480	skb_reset_mac_header(skb);
1481	ethertype = ntohs(vlan_eth_hdr(skb)->h_vlan_encapsulated_proto);
1482	}
1483
1484	/* Fill in the relevant L3 parse result fields
1485	* and read the L4 protocol type
1486	*/
1487	switch (ethertype) {
1488	case ETH_P_IP:
1489	parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV4);
1490	iph = ip_hdr(skb);
1491	WARN_ON(!iph);
1492	l4_proto = iph->protocol;
1493	break;
1494	case ETH_P_IPV6:
1495	parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV6);
1496	ipv6h = ipv6_hdr(skb);
1497	WARN_ON(!ipv6h);
1498	l4_proto = ipv6h->nexthdr;
1499	break;
1500	default:
1501	/* We shouldn't even be here */
1502	if (net_ratelimit())
1503	netif_alert(priv, tx_err, priv->net_dev,
1504	"Can't compute HW csum for L3 proto 0x%x\n",
1505	ntohs(skb->protocol));
1506	retval = -EIO;
1507	goto return_error;
1508	}
1509
1510	/* Fill in the relevant L4 parse result fields */
1511	switch (l4_proto) {
1512	case IPPROTO_UDP:
1513	parse_result->l4r = FM_L4_PARSE_RESULT_UDP;
1514	break;
1515	case IPPROTO_TCP:
1516	parse_result->l4r = FM_L4_PARSE_RESULT_TCP;
1517	break;
1518	default:
1519	if (net_ratelimit())
1520	netif_alert(priv, tx_err, priv->net_dev,
1521	"Can't compute HW csum for L4 proto 0x%x\n",
1522	l4_proto);
1523	retval = -EIO;
1524	goto return_error;
1525	}
1526
1527	/* At index 0 is IPOffset_1 as defined in the Parse Results */
1528	parse_result->ip_off[0] = (u8)skb_network_offset(skb);
1529	parse_result->l4_off = (u8)skb_transport_offset(skb);
1530
1531	/* Enable L3 (and L4, if TCP or UDP) HW checksum. */
1532	fd->cmd \|= cpu_to_be32(FM_FD_CMD_RPD \| FM_FD_CMD_DTC);
1533
1534	/* On P1023 and similar platforms fd->cmd interpretation could
1535	* be disabled by setting CONTEXT_A bit ICMD; currently this bit
1536	* is not set so we do not need to check; in the future, if/when
1537	* using context_a we need to check this bit
1538	*/
1539
1540	return_error:
1541	return retval;
1542	}
1543	#endif /* __rtems__ */
1544
1545	static int dpaa_bp_add_8_bufs(const struct dpaa_bp *dpaa_bp)
1546	{
1547	#ifndef __rtems__
1548	struct device *dev = dpaa_bp->dev;
1549	#endif /* __rtems__ */
1550	struct bm_buffer bmb[8];
1551	dma_addr_t addr;
1552	#ifndef __rtems__
1553	void *new_buf;
1554	#endif /* __rtems__ */
1555	u8 i;
1556
1557	for (i = 0; i < 8; i++) {
1558	#ifndef __rtems__
1559	new_buf = netdev_alloc_frag(dpaa_bp->raw_size);
1560	if (unlikely(!new_buf)) {
1561	dev_err(dev, "netdev_alloc_frag() failed, size %zu\n",
1562	dpaa_bp->raw_size);
1563	goto release_previous_buffs;
1564	}
1565	new_buf = PTR_ALIGN(new_buf, SMP_CACHE_BYTES);
1566
1567	addr = dma_map_single(dev, new_buf,
1568	dpaa_bp->size, DMA_FROM_DEVICE);
1569	if (unlikely(dma_mapping_error(dev, addr))) {
1570	dev_err(dpaa_bp->dev, "DMA map failed");
1571	goto release_previous_buffs;
1572	}
1573	#else /* __rtems__ */
1574	struct mbuf *m;
1575
1576	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1577	if (unlikely(m == NULL)) {
1578	goto release_previous_buffs;
1579	}
1580
1581	RTEMS_STATIC_ASSERT(DPAA_BP_RAW_SIZE == MCLBYTES,
1582	DPAA_BP_RAW_SIZE);
1583	(struct mbuf )(mtod(m, char ) + DPAA_MBUF_POINTER_OFFSET) =
1584	m;
1585	addr = mtod(m, dma_addr_t);
1586	#endif /* __rtems__ */
1587
1588	bmb[i].data = 0;
1589	bm_buffer_set64(&bmb[i], addr);
1590	}
1591
1592	release_bufs:
1593	return dpaa_bman_release(dpaa_bp, bmb, i);
1594
1595	release_previous_buffs:
1596	#ifndef __rtems__
1597	WARN_ONCE(1, "dpaa_eth: failed to add buffers on Rx\n");
1598	#endif /* __rtems__ */
1599
1600	bm_buffer_set64(&bmb[i], 0);
1601	/* Avoid releasing a completely null buffer; bman_release() requires
1602	* at least one buffer.
1603	*/
1604	if (likely(i))
1605	goto release_bufs;
1606
1607	return 0;
1608	}
1609
1610	static int dpaa_bp_seed(struct dpaa_bp *dpaa_bp)
1611	{
1612	int i;
1613
1614	/* Give each CPU an allotment of "config_count" buffers */
1615	for_each_possible_cpu(i) {
1616	int *count_ptr = per_cpu_ptr(dpaa_bp->percpu_count, i);
1617	int j;
1618
1619	/* Although we access another CPU's counters here
1620	* we do it at boot time so it is safe
1621	*/
1622	for (j = 0; j < dpaa_bp->config_count; j += 8)
1623	*count_ptr += dpaa_bp_add_8_bufs(dpaa_bp);
1624	}
1625	return 0;
1626	}
1627
1628	/* Add buffers/(pages) for Rx processing whenever bpool count falls below
1629	* REFILL_THRESHOLD.
1630	*/
1631	static int dpaa_eth_refill_bpool(struct dpaa_bp dpaa_bp, int countptr)
1632	{
1633	int count = *countptr;
1634	int new_bufs;
1635
1636	if (unlikely(count < FSL_DPAA_ETH_REFILL_THRESHOLD)) {
1637	do {
1638	new_bufs = dpaa_bp_add_8_bufs(dpaa_bp);
1639	if (unlikely(!new_bufs)) {
1640	/* Avoid looping forever if we've temporarily
1641	* run out of memory. We'll try again at the
1642	* next NAPI cycle.
1643	*/
1644	break;
1645	}
1646	count += new_bufs;
1647	} while (count < FSL_DPAA_ETH_MAX_BUF_COUNT);
1648
1649	*countptr = count;
1650	if (unlikely(count < FSL_DPAA_ETH_MAX_BUF_COUNT))
1651	return -ENOMEM;
1652	}
1653
1654	return 0;
1655	}
1656
1657	static int dpaa_eth_refill_bpools(struct dpaa_priv *priv)
1658	{
1659	struct dpaa_bp *dpaa_bp;
1660	int *countptr;
1661	int res, i;
1662
1663	for (i = 0; i < DPAA_BPS_NUM; i++) {
1664	dpaa_bp = priv->dpaa_bps[i];
1665	if (!dpaa_bp)
1666	return -EINVAL;
1667	countptr = this_cpu_ptr(dpaa_bp->percpu_count);
1668	res = dpaa_eth_refill_bpool(dpaa_bp, countptr);
1669	if (res)
1670	return res;
1671	}
1672	return 0;
1673	}
1674
1675	#ifndef __rtems__
1676	/* Cleanup function for outgoing frame descriptors that were built on Tx path,
1677	* either contiguous frames or scatter/gather ones.
1678	* Skb freeing is not handled here.
1679	*
1680	* This function may be called on error paths in the Tx function, so guard
1681	* against cases when not all fd relevant fields were filled in.
1682	*
1683	* Return the skb backpointer, since for S/G frames the buffer containing it
1684	* gets freed here.
1685	*/
1686	static struct sk_buff dpaa_cleanup_tx_fd(const struct dpaa_priv priv,
1687	const struct qm_fd *fd)
1688	{
1689	const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1690	struct device *dev = priv->net_dev->dev.parent;
1691	dma_addr_t addr = qm_fd_addr(fd);
1692	const struct qm_sg_entry *sgt;
1693	struct sk_buff *skbh, skb;
1694	int nr_frags, i;
1695
1696	skbh = (struct sk_buff **)phys_to_virt(addr);
1697	skb = *skbh;
1698
1699	if (unlikely(qm_fd_get_format(fd) == qm_fd_sg)) {
1700	nr_frags = skb_shinfo(skb)->nr_frags;
1701	dma_unmap_single(dev, addr, qm_fd_get_offset(fd) +
1702	sizeof(struct qm_sg_entry) * (1 + nr_frags),
1703	dma_dir);
1704
1705	/* The sgt buffer has been allocated with netdev_alloc_frag(),
1706	* it's from lowmem.
1707	*/
1708	sgt = phys_to_virt(addr + qm_fd_get_offset(fd));
1709
1710	/* sgt[0] is from lowmem, was dma_map_single()-ed */
1711	dma_unmap_single(dev, qm_sg_addr(&sgt[0]),
1712	qm_sg_entry_get_len(&sgt[0]), dma_dir);
1713
1714	/* remaining pages were mapped with skb_frag_dma_map() */
1715	for (i = 1; i < nr_frags; i++) {
1716	WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1717
1718	dma_unmap_page(dev, qm_sg_addr(&sgt[i]),
1719	qm_sg_entry_get_len(&sgt[i]), dma_dir);
1720	}
1721
1722	/* Free the page frag that we allocated on Tx */
1723	skb_free_frag(phys_to_virt(addr));
1724	} else {
1725	dma_unmap_single(dev, addr,
1726	skb_tail_pointer(skb) - (u8 *)skbh, dma_dir);
1727	}
1728
1729	return skb;
1730	}
1731
1732	static u8 rx_csum_offload(const struct dpaa_priv priv, const struct qm_fd fd)
1733	{
1734	/* The parser has run and performed L4 checksum validation.
1735	* We know there were no parser errors (and implicitly no
1736	* L4 csum error), otherwise we wouldn't be here.
1737	*/
1738	if ((priv->net_dev->features & NETIF_F_RXCSUM) &&
1739	(be32_to_cpu(fd->status) & FM_FD_STAT_L4CV))
1740	return CHECKSUM_UNNECESSARY;
1741
1742	/* We're here because either the parser didn't run or the L4 checksum
1743	* was not verified. This may include the case of a UDP frame with
1744	* checksum zero or an L4 proto other than TCP/UDP
1745	*/
1746	return CHECKSUM_NONE;
1747	}
1748
1749	/* Build a linear skb around the received buffer.
1750	* We are guaranteed there is enough room at the end of the data buffer to
1751	* accommodate the shared info area of the skb.
1752	*/
1753	static struct sk_buff contig_fd_to_skb(const struct dpaa_priv priv,
1754	const struct qm_fd *fd)
1755	{
1756	ssize_t fd_off = qm_fd_get_offset(fd);
1757	dma_addr_t addr = qm_fd_addr(fd);
1758	struct dpaa_bp *dpaa_bp;
1759	struct sk_buff *skb;
1760	void *vaddr;
1761
1762	vaddr = phys_to_virt(addr);
1763	WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1764
1765	dpaa_bp = dpaa_bpid2pool(fd->bpid);
1766	if (!dpaa_bp)
1767	goto free_buffer;
1768
1769	skb = build_skb(vaddr, dpaa_bp->size +
1770	SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
1771	if (unlikely(!skb)) {
1772	WARN_ONCE(1, "Build skb failure on Rx\n");
1773	goto free_buffer;
1774	}
1775	WARN_ON(fd_off != priv->rx_headroom);
1776	skb_reserve(skb, fd_off);
1777	skb_put(skb, qm_fd_get_length(fd));
1778
1779	skb->ip_summed = rx_csum_offload(priv, fd);
1780
1781	return skb;
1782
1783	free_buffer:
1784	skb_free_frag(vaddr);
1785	return NULL;
1786	}
1787
1788	/* Build an skb with the data of the first S/G entry in the linear portion and
1789	* the rest of the frame as skb fragments.
1790	*
1791	* The page fragment holding the S/G Table is recycled here.
1792	*/
1793	static struct sk_buff sg_fd_to_skb(const struct dpaa_priv priv,
1794	const struct qm_fd *fd)
1795	{
1796	ssize_t fd_off = qm_fd_get_offset(fd);
1797	dma_addr_t addr = qm_fd_addr(fd);
1798	const struct qm_sg_entry *sgt;
1799	struct page page, head_page;
1800	struct dpaa_bp *dpaa_bp;
1801	void vaddr, sg_vaddr;
1802	int frag_off, frag_len;
1803	struct sk_buff *skb;
1804	dma_addr_t sg_addr;
1805	int page_offset;
1806	unsigned int sz;
1807	int *count_ptr;
1808	int i;
1809
1810	vaddr = phys_to_virt(addr);
1811	WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1812
1813	/* Iterate through the SGT entries and add data buffers to the skb */
1814	sgt = vaddr + fd_off;
1815	for (i = 0; i < DPAA_SGT_MAX_ENTRIES; i++) {
1816	/* Extension bit is not supported */
1817	WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1818
1819	sg_addr = qm_sg_addr(&sgt[i]);
1820	sg_vaddr = phys_to_virt(sg_addr);
1821	WARN_ON(!IS_ALIGNED((unsigned long)sg_vaddr,
1822	SMP_CACHE_BYTES));
1823
1824	/* We may use multiple Rx pools */
1825	dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1826	if (!dpaa_bp)
1827	goto free_buffers;
1828
1829	count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1830	dma_unmap_single(dpaa_bp->dev, sg_addr, dpaa_bp->size,
1831	DMA_FROM_DEVICE);
1832	if (i == 0) {
1833	sz = dpaa_bp->size +
1834	SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1835	skb = build_skb(sg_vaddr, sz);
1836	if (WARN_ON(unlikely(!skb)))
1837	goto free_buffers;
1838
1839	skb->ip_summed = rx_csum_offload(priv, fd);
1840
1841	/* Make sure forwarded skbs will have enough space
1842	* on Tx, if extra headers are added.
1843	*/
1844	WARN_ON(fd_off != priv->rx_headroom);
1845	skb_reserve(skb, fd_off);
1846	skb_put(skb, qm_sg_entry_get_len(&sgt[i]));
1847	} else {
1848	/* Not the first S/G entry; all data from buffer will
1849	* be added in an skb fragment; fragment index is offset
1850	* by one since first S/G entry was incorporated in the
1851	* linear part of the skb.
1852	*
1853	* Caution: 'page' may be a tail page.
1854	*/
1855	page = virt_to_page(sg_vaddr);
1856	head_page = virt_to_head_page(sg_vaddr);
1857
1858	/* Compute offset in (possibly tail) page */
1859	page_offset = ((unsigned long)sg_vaddr &
1860	(PAGE_SIZE - 1)) +
1861	(page_address(page) - page_address(head_page));
1862	/* page_offset only refers to the beginning of sgt[i];
1863	* but the buffer itself may have an internal offset.
1864	*/
1865	frag_off = qm_sg_entry_get_off(&sgt[i]) + page_offset;
1866	frag_len = qm_sg_entry_get_len(&sgt[i]);
1867	/* skb_add_rx_frag() does no checking on the page; if
1868	* we pass it a tail page, we'll end up with
1869	* bad page accounting and eventually with segafults.
1870	*/
1871	skb_add_rx_frag(skb, i - 1, head_page, frag_off,
1872	frag_len, dpaa_bp->size);
1873	}
1874	/* Update the pool count for the current {cpu x bpool} */
1875	(*count_ptr)--;
1876
1877	if (qm_sg_entry_is_final(&sgt[i]))
1878	break;
1879	}
1880	WARN_ONCE(i == DPAA_SGT_MAX_ENTRIES, "No final bit on SGT\n");
1881
1882	/* free the SG table buffer */
1883	skb_free_frag(vaddr);
1884
1885	return skb;
1886
1887	free_buffers:
1888	/* compensate sw bpool counter changes */
1889	for (i--; i >= 0; i--) {
1890	dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1891	if (dpaa_bp) {
1892	count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1893	(*count_ptr)++;
1894	}
1895	}
1896	/* free all the SG entries */
1897	for (i = 0; i < DPAA_SGT_MAX_ENTRIES ; i++) {
1898	sg_addr = qm_sg_addr(&sgt[i]);
1899	sg_vaddr = phys_to_virt(sg_addr);
1900	skb_free_frag(sg_vaddr);
1901	dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1902	if (dpaa_bp) {
1903	count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1904	(*count_ptr)--;
1905	}
1906
1907	if (qm_sg_entry_is_final(&sgt[i]))
1908	break;
1909	}
1910	/* free the SGT fragment */
1911	skb_free_frag(vaddr);
1912
1913	return NULL;
1914	}
1915
1916	static int skb_to_contig_fd(struct dpaa_priv *priv,
1917	struct sk_buff skb, struct qm_fd fd,
1918	int *offset)
1919	{
1920	struct net_device *net_dev = priv->net_dev;
1921	struct device *dev = net_dev->dev.parent;
1922	enum dma_data_direction dma_dir;
1923	unsigned char *buffer_start;
1924	struct sk_buff **skbh;
1925	dma_addr_t addr;
1926	int err;
1927
1928	/* We are guaranteed to have at least tx_headroom bytes
1929	* available, so just use that for offset.
1930	*/
1931	fd->bpid = FSL_DPAA_BPID_INV;
1932	buffer_start = skb->data - priv->tx_headroom;
1933	dma_dir = DMA_TO_DEVICE;
1934
1935	skbh = (struct sk_buff **)buffer_start;
1936	*skbh = skb;
1937
1938	/* Enable L3/L4 hardware checksum computation.
1939	*
1940	* We must do this before dma_map_single(DMA_TO_DEVICE), because we may
1941	* need to write into the skb.
1942	*/
1943	err = dpaa_enable_tx_csum(priv, skb, fd,
1944	((char *)skbh) + DPAA_TX_PRIV_DATA_SIZE);
1945	if (unlikely(err < 0)) {
1946	if (net_ratelimit())
1947	netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
1948	err);
1949	return err;
1950	}
1951
1952	/* Fill in the rest of the FD fields */
1953	qm_fd_set_contig(fd, priv->tx_headroom, skb->len);
1954	fd->cmd \|= cpu_to_be32(FM_FD_CMD_FCO);
1955
1956	/* Map the entire buffer size that may be seen by FMan, but no more */
1957	addr = dma_map_single(dev, skbh,
1958	skb_tail_pointer(skb) - buffer_start, dma_dir);
1959	if (unlikely(dma_mapping_error(dev, addr))) {
1960	if (net_ratelimit())
1961	netif_err(priv, tx_err, net_dev, "dma_map_single() failed\n");
1962	return -EINVAL;
1963	}
1964	qm_fd_addr_set64(fd, addr);
1965
1966	return 0;
1967	}
1968
1969	static int skb_to_sg_fd(struct dpaa_priv *priv,
1970	struct sk_buff skb, struct qm_fd fd)
1971	{
1972	const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1973	const int nr_frags = skb_shinfo(skb)->nr_frags;
1974	struct net_device *net_dev = priv->net_dev;
1975	struct device *dev = net_dev->dev.parent;
1976	struct qm_sg_entry *sgt;
1977	struct sk_buff **skbh;
1978	int i, j, err, sz;
1979	void *buffer_start;
1980	skb_frag_t *frag;
1981	dma_addr_t addr;
1982	size_t frag_len;
1983	void *sgt_buf;
1984
1985	/* get a page frag to store the SGTable */
1986	sz = SKB_DATA_ALIGN(priv->tx_headroom +
1987	sizeof(struct qm_sg_entry) * (1 + nr_frags));
1988	sgt_buf = netdev_alloc_frag(sz);
1989	if (unlikely(!sgt_buf)) {
1990	netdev_err(net_dev, "netdev_alloc_frag() failed for size %d\n",
1991	sz);
1992	return -ENOMEM;
1993	}
1994
1995	/* Enable L3/L4 hardware checksum computation.
1996	*
1997	* We must do this before dma_map_single(DMA_TO_DEVICE), because we may
1998	* need to write into the skb.
1999	*/
2000	err = dpaa_enable_tx_csum(priv, skb, fd,
2001	sgt_buf + DPAA_TX_PRIV_DATA_SIZE);
2002	if (unlikely(err < 0)) {
2003	if (net_ratelimit())
2004	netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
2005	err);
2006	goto csum_failed;
2007	}
2008
2009	sgt = (struct qm_sg_entry *)(sgt_buf + priv->tx_headroom);
2010	qm_sg_entry_set_len(&sgt[0], skb_headlen(skb));
2011	sgt[0].bpid = FSL_DPAA_BPID_INV;
2012	sgt[0].offset = 0;
2013	addr = dma_map_single(dev, skb->data,
2014	skb_headlen(skb), dma_dir);
2015	if (unlikely(dma_mapping_error(dev, addr))) {
2016	dev_err(dev, "DMA mapping failed");
2017	err = -EINVAL;
2018	goto sg0_map_failed;
2019	}
2020	qm_sg_entry_set64(&sgt[0], addr);
2021
2022	/* populate the rest of SGT entries */
2023	frag = &skb_shinfo(skb)->frags[0];
2024	frag_len = frag->size;
2025	for (i = 1; i <= nr_frags; i++, frag++) {
2026	WARN_ON(!skb_frag_page(frag));
2027	addr = skb_frag_dma_map(dev, frag, 0,
2028	frag_len, dma_dir);
2029	if (unlikely(dma_mapping_error(dev, addr))) {
2030	dev_err(dev, "DMA mapping failed");
2031	err = -EINVAL;
2032	goto sg_map_failed;
2033	}
2034
2035	qm_sg_entry_set_len(&sgt[i], frag_len);
2036	sgt[i].bpid = FSL_DPAA_BPID_INV;
2037	sgt[i].offset = 0;
2038
2039	/* keep the offset in the address */
2040	qm_sg_entry_set64(&sgt[i], addr);
2041	frag_len = frag->size;
2042	}
2043	qm_sg_entry_set_f(&sgt[i - 1], frag_len);
2044
2045	qm_fd_set_sg(fd, priv->tx_headroom, skb->len);
2046
2047	/* DMA map the SGT page */
2048	buffer_start = (void *)sgt - priv->tx_headroom;
2049	skbh = (struct sk_buff **)buffer_start;
2050	*skbh = skb;
2051
2052	addr = dma_map_single(dev, buffer_start, priv->tx_headroom +
2053	sizeof(struct qm_sg_entry) * (1 + nr_frags),
2054	dma_dir);
2055	if (unlikely(dma_mapping_error(dev, addr))) {
2056	dev_err(dev, "DMA mapping failed");
2057	err = -EINVAL;
2058	goto sgt_map_failed;
2059	}
2060
2061	fd->bpid = FSL_DPAA_BPID_INV;
2062	fd->cmd \|= cpu_to_be32(FM_FD_CMD_FCO);
2063	qm_fd_addr_set64(fd, addr);
2064
2065	return 0;
2066
2067	sgt_map_failed:
2068	sg_map_failed:
2069	for (j = 0; j < i; j++)
2070	dma_unmap_page(dev, qm_sg_addr(&sgt[j]),
2071	qm_sg_entry_get_len(&sgt[j]), dma_dir);
2072	sg0_map_failed:
2073	csum_failed:
2074	skb_free_frag(sgt_buf);
2075
2076	return err;
2077	}
2078
2079	static inline int dpaa_xmit(struct dpaa_priv *priv,
2080	struct rtnl_link_stats64 *percpu_stats,
2081	int queue,
2082	struct qm_fd *fd)
2083	{
2084	struct qman_fq *egress_fq;
2085	int err, i;
2086
2087	egress_fq = priv->egress_fqs[queue];
2088	if (fd->bpid == FSL_DPAA_BPID_INV)
2089	fd->cmd \|= cpu_to_be32(qman_fq_fqid(priv->conf_fqs[queue]));
2090
2091	/* Trace this Tx fd */
2092	trace_dpaa_tx_fd(priv->net_dev, egress_fq, fd);
2093
2094	for (i = 0; i < DPAA_ENQUEUE_RETRIES; i++) {
2095	err = qman_enqueue(egress_fq, fd);
2096	if (err != -EBUSY)
2097	break;
2098	}
2099
2100	if (unlikely(err < 0)) {
2101	percpu_stats->tx_errors++;
2102	percpu_stats->tx_fifo_errors++;
2103	return err;
2104	}
2105
2106	percpu_stats->tx_packets++;
2107	percpu_stats->tx_bytes += qm_fd_get_length(fd);
2108
2109	return 0;
2110	}
2111
2112	static int dpaa_start_xmit(struct sk_buff skb, struct net_device net_dev)
2113	{
2114	const int queue_mapping = skb_get_queue_mapping(skb);
2115	bool nonlinear = skb_is_nonlinear(skb);
2116	struct rtnl_link_stats64 *percpu_stats;
2117	struct dpaa_percpu_priv *percpu_priv;
2118	struct dpaa_priv *priv;
2119	struct qm_fd fd;
2120	int offset = 0;
2121	int err = 0;
2122
2123	priv = netdev_priv(net_dev);
2124	percpu_priv = this_cpu_ptr(priv->percpu_priv);
2125	percpu_stats = &percpu_priv->stats;
2126
2127	qm_fd_clear_fd(&fd);
2128
2129	if (!nonlinear) {
2130	/* We're going to store the skb backpointer at the beginning
2131	* of the data buffer, so we need a privately owned skb
2132	*
2133	* We've made sure skb is not shared in dev->priv_flags,
2134	* we need to verify the skb head is not cloned
2135	*/
2136	if (skb_cow_head(skb, priv->tx_headroom))
2137	goto enomem;
2138
2139	WARN_ON(skb_is_nonlinear(skb));
2140	}
2141
2142	/* MAX_SKB_FRAGS is equal or larger than our dpaa_SGT_MAX_ENTRIES;
2143	* make sure we don't feed FMan with more fragments than it supports.
2144	*/
2145	if (nonlinear &&
2146	likely(skb_shinfo(skb)->nr_frags < DPAA_SGT_MAX_ENTRIES)) {
2147	/* Just create a S/G fd based on the skb */
2148	err = skb_to_sg_fd(priv, skb, &fd);
2149	percpu_priv->tx_frag_skbuffs++;
2150	} else {
2151	/* If the egress skb contains more fragments than we support
2152	* we have no choice but to linearize it ourselves.
2153	*/
2154	if (unlikely(nonlinear) && __skb_linearize(skb))
2155	goto enomem;
2156
2157	/* Finally, create a contig FD from this skb */
2158	err = skb_to_contig_fd(priv, skb, &fd, &offset);
2159	}
2160	if (unlikely(err < 0))
2161	goto skb_to_fd_failed;
2162
2163	if (likely(dpaa_xmit(priv, percpu_stats, queue_mapping, &fd) == 0))
2164	return NETDEV_TX_OK;
2165
2166	dpaa_cleanup_tx_fd(priv, &fd);
2167	skb_to_fd_failed:
2168	enomem:
2169	percpu_stats->tx_errors++;
2170	dev_kfree_skb(skb);
2171	return NETDEV_TX_OK;
2172	}
2173	#endif /* __rtems__ */
2174
2175	static void dpaa_rx_error(struct net_device *net_dev,
2176	const struct dpaa_priv *priv,
2177	struct dpaa_percpu_priv *percpu_priv,
2178	const struct qm_fd *fd,
2179	u32 fqid)
2180	{
2181	#ifndef __rtems__
2182	if (net_ratelimit())
2183	netif_err(priv, hw, net_dev, "Err FD status = 0x%08x\n",
2184	be32_to_cpu(fd->status) & FM_FD_STAT_RX_ERRORS);
2185
2186	percpu_priv->stats.rx_errors++;
2187	#endif /* __rtems__ */
2188
2189	if (be32_to_cpu(fd->status) & FM_FD_ERR_DMA)
2190	percpu_priv->rx_errors.dme++;
2191	if (be32_to_cpu(fd->status) & FM_FD_ERR_PHYSICAL)
2192	percpu_priv->rx_errors.fpe++;
2193	if (be32_to_cpu(fd->status) & FM_FD_ERR_SIZE)
2194	percpu_priv->rx_errors.fse++;
2195	if (be32_to_cpu(fd->status) & FM_FD_ERR_PRS_HDR_ERR)
2196	percpu_priv->rx_errors.phe++;
2197
2198	dpaa_fd_release(net_dev, fd);
2199	}
2200
2201	static void dpaa_tx_error(struct net_device *net_dev,
2202	const struct dpaa_priv *priv,
2203	struct dpaa_percpu_priv *percpu_priv,
2204	const struct qm_fd *fd,
2205	u32 fqid)
2206	{
2207	#ifndef __rtems__
2208	struct sk_buff *skb;
2209
2210	if (net_ratelimit())
2211	netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2212	be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS);
2213
2214	percpu_priv->stats.tx_errors++;
2215	#else /* __rtems__ */
2216	struct ifnet *ifp = net_dev->ifp;
2217
2218	if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2219	#endif /* __rtems__ */
2220
2221	#ifndef __rtems__
2222	skb = dpaa_cleanup_tx_fd(priv, fd);
2223	dev_kfree_skb(skb);
2224	#else /* __rtems__ */
2225	dpaa_cleanup_tx_fd(ifp, fd);
2226	#endif /* __rtems__ */
2227	}
2228
2229	#ifndef __rtems__
2230	static int dpaa_eth_poll(struct napi_struct *napi, int budget)
2231	{
2232	struct dpaa_napi_portal *np =
2233	container_of(napi, struct dpaa_napi_portal, napi);
2234
2235	int cleaned = qman_p_poll_dqrr(np->p, budget);
2236
2237	if (cleaned < budget) {
2238	napi_complete_done(napi, cleaned);
2239	qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2240
2241	} else if (np->down) {
2242	qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2243	}
2244
2245	return cleaned;
2246	}
2247	#endif /* __rtems__ */
2248
2249	static void dpaa_tx_conf(struct net_device *net_dev,
2250	const struct dpaa_priv *priv,
2251	struct dpaa_percpu_priv *percpu_priv,
2252	const struct qm_fd *fd,
2253	u32 fqid)
2254	{
2255	#ifndef __rtems__
2256	struct sk_buff *skb;
2257
2258	if (unlikely(be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS)) {
2259	if (net_ratelimit())
2260	netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2261	be32_to_cpu(fd->status) &
2262	FM_FD_STAT_TX_ERRORS);
2263
2264	percpu_priv->stats.tx_errors++;
2265	}
2266
2267	percpu_priv->tx_confirm++;
2268
2269	skb = dpaa_cleanup_tx_fd(priv, fd);
2270
2271	consume_skb(skb);
2272	#else /* __rtems__ */
2273	struct ifnet *ifp = net_dev->ifp;
2274
2275	if (unlikely(fd->status & FM_FD_STAT_TX_ERRORS) != 0) {
2276	if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2277	}
2278
2279	dpaa_cleanup_tx_fd(ifp, fd);
2280	#endif /* __rtems__ */
2281	}
2282
2283	static inline int dpaa_eth_napi_schedule(struct dpaa_percpu_priv *percpu_priv,
2284	struct qman_portal *portal)
2285	{
2286	#ifndef __rtems__
2287	if (unlikely(in_irq() \|\| !in_serving_softirq())) {
2288	/* Disable QMan IRQ and invoke NAPI */
2289	qman_p_irqsource_remove(portal, QM_PIRQ_DQRI);
2290
2291	percpu_priv->np.p = portal;
2292	napi_schedule(&percpu_priv->np.napi);
2293	percpu_priv->in_interrupt++;
2294	return 1;
2295	}
2296	#endif /* __rtems__ */
2297	return 0;
2298	}
2299
2300	static enum qman_cb_dqrr_result rx_error_dqrr(struct qman_portal *portal,
2301	struct qman_fq *fq,
2302	const struct qm_dqrr_entry *dq)
2303	{
2304	struct dpaa_fq *dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
2305	struct dpaa_percpu_priv *percpu_priv;
2306	struct net_device *net_dev;
2307	struct dpaa_bp *dpaa_bp;
2308	struct dpaa_priv *priv;
2309
2310	net_dev = dpaa_fq->net_dev;
2311	priv = netdev_priv(net_dev);
2312	dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2313	if (!dpaa_bp)
2314	return qman_cb_dqrr_consume;
2315
2316	percpu_priv = this_cpu_ptr(priv->percpu_priv);
2317
2318	if (dpaa_eth_napi_schedule(percpu_priv, portal))
2319	return qman_cb_dqrr_stop;
2320
2321	if (dpaa_eth_refill_bpools(priv))
2322	/* Unable to refill the buffer pool due to insufficient
2323	* system memory. Just release the frame back into the pool,
2324	* otherwise we'll soon end up with an empty buffer pool.
2325	*/
2326	dpaa_fd_release(net_dev, &dq->fd);
2327	else
2328	dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2329
2330	return qman_cb_dqrr_consume;
2331	}
2332
2333	#ifdef __rtems__
2334	static struct mbuf *
2335	dpaa_bp_addr_to_mbuf(dma_addr_t addr)
2336	{
2337	void *vaddr = phys_to_virt(addr);
2338
2339	return ((struct mbuf *)(vaddr + DPAA_MBUF_POINTER_OFFSET));
2340	}
2341
2342	static struct mbuf *
2343	contig_fd_to_mbuf(const struct qm_fd fd, struct ifnet ifp)
2344	{
2345	struct mbuf *m;
2346	ssize_t fd_off = qm_fd_get_offset(fd);
2347	dma_addr_t addr = qm_fd_addr(fd);
2348
2349	m = dpaa_bp_addr_to_mbuf(addr);
2350	m->m_pkthdr.rcvif = ifp;
2351	m->m_pkthdr.len = m->m_len = qm_fd_get_length(fd);
2352	m->m_data = mtod(m, char *) + fd_off;
2353
2354	return (m);
2355	}
2356
2357	static void
2358	dpaa_bp_recycle_frag(struct dpaa_bp dpaa_bp, dma_addr_t addr, int count_ptr)
2359	{
2360	struct bm_buffer bmb;
2361
2362	bm_buffer_set64(&bmb, addr);
2363
2364	while (bman_release(dpaa_bp->pool, &bmb, 1))
2365	cpu_relax();
2366
2367	++(*count_ptr);
2368	}
2369
2370	static struct mbuf *
2371	sg_fd_to_mbuf(struct dpaa_bp dpaa_bp, const struct qm_fd fd,
2372	struct ifnet ifp, int count_ptr)
2373	{
2374	ssize_t fd_off = qm_fd_get_offset(fd);
2375	dma_addr_t addr = qm_fd_addr(fd);
2376	const struct qm_sg_entry *sgt;
2377	int i;
2378	int len;
2379	struct mbuf *m;
2380	struct mbuf *last;
2381
2382	sgt = (const struct qm_sg_entry )((char )phys_to_virt(addr) + fd_off);
2383	len = 0;
2384
2385	for (i = 0; i < DPAA_SGT_MAX_ENTRIES; ++i) {
2386	dma_addr_t sg_addr;
2387	int sg_len;
2388	struct mbuf *n;
2389
2390	BSD_ASSERT(!qm_sg_entry_is_ext(&sgt[i]));
2391	BSD_ASSERT(dpaa_bp == dpaa_bpid2pool(sgt[i].bpid));
2392
2393	sg_addr = qm_sg_addr(&sgt[i]);
2394	n = dpaa_bp_addr_to_mbuf(sg_addr);
2395
2396	sg_len = qm_sg_entry_get_len(&sgt[i]);
2397	len += sg_len;
2398
2399	if (i == 0) {
2400	m = n;
2401	} else {
2402	last->m_next = n;
2403	}
2404
2405	n->m_len = sg_len;
2406	n->m_data = mtod(n, char *) + sgt[i].offset;
2407	last = n;
2408
2409	--(*count_ptr);
2410
2411	if (qm_sg_entry_is_final(&sgt[i])) {
2412	break;
2413	}
2414	}
2415
2416	m->m_pkthdr.rcvif = ifp;
2417	m->m_pkthdr.len = len;
2418
2419	dpaa_bp_recycle_frag(dpaa_bp, addr, count_ptr);
2420
2421	return (m);
2422	}
2423
2424	static void
2425	dpaa_rx(struct net_device net_dev, struct qman_portal portal,
2426	const struct dpaa_priv priv, struct dpaa_percpu_priv percpu_priv,
2427	const struct qm_fd fd, u32 fqid, int count_ptr)
2428	{
2429	struct dpaa_bp *dpaa_bp;
2430	enum qm_fd_format fd_format;
2431	struct mbuf *m;
2432	struct ifnet *ifp;
2433
2434	ifp = net_dev->ifp;
2435
2436	if (unlikely(fd->status & FM_FD_STAT_RX_ERRORS) != 0) {
2437	if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2438	dpaa_fd_release(net_dev, fd);
2439	return;
2440	}
2441
2442	dpaa_bp = dpaa_bpid2pool(fd->bpid);
2443	fd_format = qm_fd_get_format(fd);
2444
2445	if (likely(fd_format == qm_fd_contig)) {
2446	m = contig_fd_to_mbuf(fd, ifp);
2447	} else {
2448	BSD_ASSERT(fd_format == qm_fd_sg);
2449	m = sg_fd_to_mbuf(dpaa_bp, fd, ifp, count_ptr);
2450	}
2451
2452	/* Account for either the contig buffer or the SGT buffer (depending on
2453	* which case we were in) having been removed from the pool.
2454	*/
2455	(*count_ptr)--;
2456
2457	if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2458	(*ifp->if_input)(ifp, m);
2459	}
2460	#endif /* __rtems__ */
2461	static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal,
2462	struct qman_fq *fq,
2463	const struct qm_dqrr_entry *dq)
2464	{
2465	#ifndef __rtems__
2466	struct rtnl_link_stats64 *percpu_stats;
2467	#endif /* __rtems__ */
2468	struct dpaa_percpu_priv *percpu_priv;
2469	#ifndef __rtems__
2470	const struct qm_fd *fd = &dq->fd;
2471	dma_addr_t addr = qm_fd_addr(fd);
2472	enum qm_fd_format fd_format;
2473	#endif /* __rtems__ */
2474	struct net_device *net_dev;
2475	#ifndef __rtems__
2476	u32 fd_status;
2477	#endif /* __rtems__ */
2478	struct dpaa_bp *dpaa_bp;
2479	struct dpaa_priv *priv;
2480	#ifndef __rtems__
2481	unsigned int skb_len;
2482	struct sk_buff *skb;
2483	#endif /* __rtems__ */
2484	int *count_ptr;
2485
2486	#ifndef __rtems__
2487	fd_status = be32_to_cpu(fd->status);
2488	fd_format = qm_fd_get_format(fd);
2489	#endif /* __rtems__ */
2490	net_dev = ((struct dpaa_fq *)fq)->net_dev;
2491	priv = netdev_priv(net_dev);
2492	dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2493	if (!dpaa_bp)
2494	return qman_cb_dqrr_consume;
2495
2496	#ifndef __rtems__
2497	/* Trace the Rx fd */
2498	trace_dpaa_rx_fd(net_dev, fq, &dq->fd);
2499	#endif /* __rtems__ */
2500
2501	percpu_priv = this_cpu_ptr(priv->percpu_priv);
2502	#ifndef __rtems__
2503	percpu_stats = &percpu_priv->stats;
2504	#endif /* __rtems__ */
2505
2506	if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal)))
2507	return qman_cb_dqrr_stop;
2508
2509	/* Make sure we didn't run out of buffers */
2510	if (unlikely(dpaa_eth_refill_bpools(priv))) {
2511	#ifdef __rtems__
2512	struct ifnet *ifp = net_dev->ifp;
2513	if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2514	#endif /* __rtems__ */
2515	dpaa_fd_release(net_dev, &dq->fd);
2516	return qman_cb_dqrr_consume;
2517	}
2518
2519	#ifndef __rtems__
2520	if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) {
2521	if (net_ratelimit())
2522	netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2523	fd_status & FM_FD_STAT_RX_ERRORS);
2524
2525	percpu_stats->rx_errors++;
2526	dpaa_fd_release(net_dev, fd);
2527	return qman_cb_dqrr_consume;
2528	}
2529
2530	dpaa_bp = dpaa_bpid2pool(fd->bpid);
2531	if (!dpaa_bp)
2532	return qman_cb_dqrr_consume;
2533
2534	dma_unmap_single(dpaa_bp->dev, addr, dpaa_bp->size, DMA_FROM_DEVICE);
2535
2536	/* prefetch the first 64 bytes of the frame or the SGT start */
2537	prefetch(phys_to_virt(addr) + qm_fd_get_offset(fd));
2538
2539	fd_format = qm_fd_get_format(fd);
2540	/* The only FD types that we may receive are contig and S/G */
2541	WARN_ON((fd_format != qm_fd_contig) && (fd_format != qm_fd_sg));
2542
2543	/* Account for either the contig buffer or the SGT buffer (depending on
2544	* which case we were in) having been removed from the pool.
2545	*/
2546	count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
2547	(*count_ptr)--;
2548
2549	if (likely(fd_format == qm_fd_contig))
2550	skb = contig_fd_to_skb(priv, fd);
2551	dpa_fd_release(net_dev, &dq->fd);
2552	else
2553	skb = sg_fd_to_skb(priv, fd);
2554	if (!skb)
2555	return qman_cb_dqrr_consume;
2556
2557	skb->protocol = eth_type_trans(skb, net_dev);
2558
2559	skb_len = skb->len;
2560
2561	if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
2562	return qman_cb_dqrr_consume;
2563
2564	percpu_stats->rx_packets++;
2565	percpu_stats->rx_bytes += skb_len;
2566	#else /* __rtems__ */
2567	count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
2568	dpaa_rx(net_dev, portal, priv, percpu_priv, &dq->fd, fq->fqid,
2569	count_ptr);
2570	#endif /* __rtems__ */
2571
2572	return qman_cb_dqrr_consume;
2573	}
2574
2575	static enum qman_cb_dqrr_result conf_error_dqrr(struct qman_portal *portal,
2576	struct qman_fq *fq,
2577	const struct qm_dqrr_entry *dq)
2578	{
2579	struct dpaa_percpu_priv *percpu_priv;
2580	struct net_device *net_dev;
2581	struct dpaa_priv *priv;
2582
2583	net_dev = ((struct dpaa_fq *)fq)->net_dev;
2584	priv = netdev_priv(net_dev);
2585
2586	percpu_priv = this_cpu_ptr(priv->percpu_priv);
2587
2588	if (dpaa_eth_napi_schedule(percpu_priv, portal))
2589	return qman_cb_dqrr_stop;
2590
2591	dpaa_tx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2592
2593	return qman_cb_dqrr_consume;
2594	}
2595
2596	static enum qman_cb_dqrr_result conf_dflt_dqrr(struct qman_portal *portal,
2597	struct qman_fq *fq,
2598	const struct qm_dqrr_entry *dq)
2599	{
2600	struct dpaa_percpu_priv *percpu_priv;
2601	struct net_device *net_dev;
2602	struct dpaa_priv *priv;
2603
2604	net_dev = ((struct dpaa_fq *)fq)->net_dev;
2605	priv = netdev_priv(net_dev);
2606
2607	#ifndef __rtems__
2608	/* Trace the fd */
2609	trace_dpaa_tx_conf_fd(net_dev, fq, &dq->fd);
2610	#endif /* __rtems__ */
2611
2612	percpu_priv = this_cpu_ptr(priv->percpu_priv);
2613
2614	if (dpaa_eth_napi_schedule(percpu_priv, portal))
2615	return qman_cb_dqrr_stop;
2616
2617	dpaa_tx_conf(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2618
2619	return qman_cb_dqrr_consume;
2620	}
2621
2622	static void egress_ern(struct qman_portal *portal,
2623	struct qman_fq *fq,
2624	const union qm_mr_entry *msg)
2625	{
2626	const struct qm_fd *fd = &msg->ern.fd;
2627	struct dpaa_percpu_priv *percpu_priv;
2628	const struct dpaa_priv *priv;
2629	struct net_device *net_dev;
2630	#ifndef __rtems__
2631	struct sk_buff *skb;
2632	#else /* __rtems__ */
2633	struct ifnet *ifp;
2634	#endif /* __rtems__ */
2635
2636	net_dev = ((struct dpaa_fq *)fq)->net_dev;
2637	priv = netdev_priv(net_dev);
2638	percpu_priv = this_cpu_ptr(priv->percpu_priv);
2639
2640	#ifndef __rtems__
2641	percpu_priv->stats.tx_dropped++;
2642	percpu_priv->stats.tx_fifo_errors++;
2643	#else /* __rtems__ */
2644	ifp = net_dev->ifp;
2645	if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2646	#endif /* __rtems__ */
2647	count_ern(percpu_priv, msg);
2648
2649	#ifndef __rtems__
2650	skb = dpaa_cleanup_tx_fd(priv, fd);
2651	dev_kfree_skb_any(skb);
2652	#else /* __rtems__ */
2653	dpaa_cleanup_tx_fd(ifp, fd);
2654	#endif /* __rtems__ */
2655	}
2656
2657	static const struct dpaa_fq_cbs dpaa_fq_cbs = {
2658	.rx_defq = { .cb = { .dqrr = rx_default_dqrr } },
2659	.tx_defq = { .cb = { .dqrr = conf_dflt_dqrr } },
2660	.rx_errq = { .cb = { .dqrr = rx_error_dqrr } },
2661	.tx_errq = { .cb = { .dqrr = conf_error_dqrr } },
2662	.egress_ern = { .cb = { .ern = egress_ern } }
2663	};
2664
2665	static void dpaa_eth_napi_enable(struct dpaa_priv *priv)
2666	{
2667	#ifndef __rtems__
2668	struct dpaa_percpu_priv *percpu_priv;
2669	int i;
2670
2671	for_each_possible_cpu(i) {
2672	percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2673
2674	percpu_priv->np.down = 0;
2675	napi_enable(&percpu_priv->np.napi);
2676	}
2677	#endif /* __rtems__ */
2678	}
2679
2680	static void dpaa_eth_napi_disable(struct dpaa_priv *priv)
2681	{
2682	#ifndef __rtems__
2683	struct dpaa_percpu_priv *percpu_priv;
2684	int i;
2685
2686	for_each_possible_cpu(i) {
2687	percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2688
2689	percpu_priv->np.down = 1;
2690	napi_disable(&percpu_priv->np.napi);
2691	}
2692	#endif /* __rtems__ */
2693	}
2694
2695	#ifndef __rtems__
2696	static int dpaa_open(struct net_device *net_dev)
2697	#else /* __rtems__ */
2698	int dpa_eth_priv_start(struct net_device *net_dev)
2699	#endif /* __rtems__ */
2700	{
2701	struct mac_device *mac_dev;
2702	struct dpaa_priv *priv;
2703	int err, i;
2704
2705	priv = netdev_priv(net_dev);
2706	mac_dev = priv->mac_dev;
2707	dpaa_eth_napi_enable(priv);
2708
2709	#ifndef __rtems__
2710	net_dev->phydev = mac_dev->init_phy(net_dev, priv->mac_dev);
2711	if (!net_dev->phydev) {
2712	netif_err(priv, ifup, net_dev, "init_phy() failed\n");
2713	err = -ENODEV;
2714	goto phy_init_failed;
2715	}
2716	#endif /* __rtems__ */
2717
2718	for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
2719	err = fman_port_enable(mac_dev->port[i]);
2720	if (err)
2721	goto mac_start_failed;
2722	}
2723
2724	err = priv->mac_dev->start(mac_dev);
2725	if (err < 0) {
2726	netif_err(priv, ifup, net_dev, "mac_dev->start() = %d\n", err);
2727	goto mac_start_failed;
2728	}
2729
2730	#ifndef __rtems__
2731	netif_tx_start_all_queues(net_dev);
2732	#endif /* __rtems__ */
2733
2734	return 0;
2735
2736	mac_start_failed:
2737	for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++)
2738	fman_port_disable(mac_dev->port[i]);
2739
2740	#ifndef __rtems__
2741	phy_init_failed:
2742	#endif /* __rtems__ */
2743	dpaa_eth_napi_disable(priv);
2744
2745	return err;
2746	}
2747
2748	#ifndef __rtems__
2749	static int dpaa_eth_stop(struct net_device *net_dev)
2750	#else /* __rtems__ */
2751	int dpa_eth_priv_stop(struct net_device *net_dev)
2752	#endif /* __rtems__ */
2753	{
2754	struct dpaa_priv *priv;
2755	int err;
2756
2757	err = dpaa_stop(net_dev);
2758
2759	priv = netdev_priv(net_dev);
2760	dpaa_eth_napi_disable(priv);
2761
2762	return err;
2763	}
2764
2765	#ifndef __rtems__
2766	static int dpaa_ioctl(struct net_device net_dev, struct ifreq rq, int cmd)
2767	{
2768	if (!net_dev->phydev)
2769	return -EINVAL;
2770	return phy_mii_ioctl(net_dev->phydev, rq, cmd);
2771	}
2772
2773	static const struct net_device_ops dpaa_ops = {
2774	.ndo_open = dpaa_open,
2775	.ndo_start_xmit = dpaa_start_xmit,
2776	.ndo_stop = dpaa_eth_stop,
2777	.ndo_tx_timeout = dpaa_tx_timeout,
2778	.ndo_get_stats64 = dpaa_get_stats64,
2779	.ndo_set_mac_address = dpaa_set_mac_address,
2780	.ndo_validate_addr = eth_validate_addr,
2781	.ndo_set_rx_mode = dpaa_set_rx_mode,
2782	.ndo_do_ioctl = dpaa_ioctl,
2783	.ndo_setup_tc = dpaa_setup_tc,
2784	};
2785
2786	static int dpaa_napi_add(struct net_device *net_dev)
2787	{
2788	struct dpaa_priv *priv = netdev_priv(net_dev);
2789	struct dpaa_percpu_priv *percpu_priv;
2790	int cpu;
2791
2792	for_each_possible_cpu(cpu) {
2793	percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
2794
2795	netif_napi_add(net_dev, &percpu_priv->np.napi,
2796	dpaa_eth_poll, NAPI_POLL_WEIGHT);
2797	}
2798
2799	return 0;
2800	}
2801	#endif /* __rtems__ */
2802
2803	static void dpaa_napi_del(struct net_device *net_dev)
2804	{
2805	#ifndef __rtems__
2806	struct dpaa_priv *priv = netdev_priv(net_dev);
2807	struct dpaa_percpu_priv *percpu_priv;
2808	int cpu;
2809
2810	for_each_possible_cpu(cpu) {
2811	percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
2812
2813	netif_napi_del(&percpu_priv->np.napi);
2814	}
2815	#endif /* __rtems__ */
2816	}
2817
2818	static inline void dpaa_bp_free_pf(const struct dpaa_bp *bp,
2819	struct bm_buffer *bmb)
2820	{
2821	dma_addr_t addr = bm_buf_addr(bmb);
2822
2823	#ifndef __rtems__
2824	dma_unmap_single(bp->dev, addr, bp->size, DMA_FROM_DEVICE);
2825
2826	skb_free_frag(phys_to_virt(addr));
2827	#else /* __rtems__ */
2828	BSD_ASSERT(0);
2829	m_freem(dpaa_bp_addr_to_mbuf(addr));
2830	#endif /* __rtems__ */
2831	}
2832
2833	/* Alloc the dpaa_bp struct and configure default values */
2834	static struct dpaa_bp dpaa_bp_alloc(struct device dev)
2835	{
2836	struct dpaa_bp *dpaa_bp;
2837
2838	dpaa_bp = devm_kzalloc(dev, sizeof(*dpaa_bp), GFP_KERNEL);
2839	if (!dpaa_bp)
2840	return ERR_PTR(-ENOMEM);
2841
2842	dpaa_bp->bpid = FSL_DPAA_BPID_INV;
2843	dpaa_bp->percpu_count = devm_alloc_percpu(dev, *dpaa_bp->percpu_count);
2844	dpaa_bp->config_count = FSL_DPAA_ETH_MAX_BUF_COUNT;
2845
2846	dpaa_bp->seed_cb = dpaa_bp_seed;
2847	dpaa_bp->free_buf_cb = dpaa_bp_free_pf;
2848
2849	return dpaa_bp;
2850	}
2851
2852	/* Place all ingress FQs (Rx Default, Rx Error) in a dedicated CGR.
2853	* We won't be sending congestion notifications to FMan; for now, we just use
2854	* this CGR to generate enqueue rejections to FMan in order to drop the frames
2855	* before they reach our ingress queues and eat up memory.
2856	*/
2857	static int dpaa_ingress_cgr_init(struct dpaa_priv *priv)
2858	{
2859	struct qm_mcc_initcgr initcgr;
2860	u32 cs_th;
2861	int err;
2862
2863	err = qman_alloc_cgrid(&priv->ingress_cgr.cgrid);
2864	if (err < 0) {
2865	if (netif_msg_drv(priv))
2866	pr_err("Error %d allocating CGR ID\n", err);
2867	goto out_error;
2868	}
2869
2870	/* Enable CS TD, but disable Congestion State Change Notifications. */
2871	memset(&initcgr, 0, sizeof(initcgr));
2872	initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES);
2873	initcgr.cgr.cscn_en = QM_CGR_EN;
2874	cs_th = DPAA_INGRESS_CS_THRESHOLD;
2875	qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
2876
2877	initcgr.we_mask \|= cpu_to_be16(QM_CGR_WE_CSTD_EN);
2878	initcgr.cgr.cstd_en = QM_CGR_EN;
2879
2880	/* This CGR will be associated with the SWP affined to the current CPU.
2881	* However, we'll place all our ingress FQs in it.
2882	*/
2883	err = qman_create_cgr(&priv->ingress_cgr, QMAN_CGR_FLAG_USE_INIT,
2884	&initcgr);
2885	if (err < 0) {
2886	if (netif_msg_drv(priv))
2887	pr_err("Error %d creating ingress CGR with ID %d\n",
2888	err, priv->ingress_cgr.cgrid);
2889	qman_release_cgrid(priv->ingress_cgr.cgrid);
2890	goto out_error;
2891	}
2892	if (netif_msg_drv(priv))
2893	pr_debug("Created ingress CGR %d for netdev with hwaddr %pM\n",
2894	priv->ingress_cgr.cgrid, priv->mac_dev->addr);
2895
2896	priv->use_ingress_cgr = true;
2897
2898	out_error:
2899	return err;
2900	}
2901
2902	#ifndef __rtems__
2903	static const struct of_device_id dpaa_match[];
2904	#endif /* __rtems__ */
2905
2906	static inline u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl)
2907	{
2908	u16 headroom;
2909
2910	/* The frame headroom must accommodate:
2911	* - the driver private data area
2912	* - parse results, hash results, timestamp if selected
2913	* If either hash results or time stamp are selected, both will
2914	* be copied to/from the frame headroom, as TS is located between PR and
2915	* HR in the IC and IC copy size has a granularity of 16bytes
2916	* (see description of FMBM_RICP and FMBM_TICP registers in DPAARM)
2917	*
2918	* Also make sure the headroom is a multiple of data_align bytes
2919	*/
2920	headroom = (u16)(bl->priv_data_size + DPAA_PARSE_RESULTS_SIZE +
2921	DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE);
2922
2923	return DPAA_FD_DATA_ALIGNMENT ? ALIGN(headroom,
2924	DPAA_FD_DATA_ALIGNMENT) :
2925	headroom;
2926	}
2927
2928	#ifndef __rtems__
2929	static int dpaa_eth_probe(struct platform_device *pdev)
2930	#else /* __rtems__ */
2931	int
2932	dpaa_eth_priv_probe(struct platform_device pdev, struct mac_device mac_dev)
2933	#endif /* __rtems__ */
2934	{
2935	struct dpaa_bp *dpaa_bps[DPAA_BPS_NUM] = {NULL};
2936	struct dpaa_percpu_priv *percpu_priv;
2937	struct net_device *net_dev = NULL;
2938	struct dpaa_fq dpaa_fq, tmp;
2939	struct dpaa_priv *priv = NULL;
2940	struct fm_port_fqs port_fqs;
2941	#ifndef __rtems__
2942	struct mac_device *mac_dev;
2943	#endif /* __rtems__ */
2944	int err = 0, i, channel;
2945	struct device *dev;
2946
2947	dev = &pdev->dev;
2948
2949	#ifndef __rtems__
2950	/* Allocate this early, so we can store relevant information in
2951	* the private area
2952	*/
2953	net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TXQ_NUM);
2954	if (!net_dev) {
2955	dev_err(dev, "alloc_etherdev_mq() failed\n");
2956	goto alloc_etherdev_mq_failed;
2957	}
2958	#else /* __rtems__ */
2959	net_dev = &mac_dev->net_dev;
2960	net_dev->priv = malloc(sizeof(*priv), M_KMALLOC, M_WAITOK \| M_ZERO);
2961	#endif /* __rtems__ */
2962
2963	/* Do this here, so we can be verbose early */
2964	#ifndef __rtems__
2965	SET_NETDEV_DEV(net_dev, dev);
2966	#endif /* __rtems__ */
2967	dev_set_drvdata(dev, net_dev);
2968
2969	priv = netdev_priv(net_dev);
2970	priv->net_dev = net_dev;
2971
2972	#ifndef __rtems__
2973	priv->msg_enable = netif_msg_init(debug, DPAA_MSG_DEFAULT);
2974
2975	mac_dev = dpaa_mac_dev_get(pdev);
2976	if (IS_ERR(mac_dev)) {
2977	dev_err(dev, "dpaa_mac_dev_get() failed\n");
2978	err = PTR_ERR(mac_dev);
2979	goto mac_probe_failed;
2980	}
2981
2982	/* If fsl_fm_max_frm is set to a higher value than the all-common 1500,
2983	* we choose conservatively and let the user explicitly set a higher
2984	* MTU via ifconfig. Otherwise, the user may end up with different MTUs
2985	* in the same LAN.
2986	* If on the other hand fsl_fm_max_frm has been chosen below 1500,
2987	* start with the maximum allowed.
2988	*/
2989	net_dev->mtu = min(dpaa_get_max_mtu(), ETH_DATA_LEN);
2990
2991	netdev_dbg(net_dev, "Setting initial MTU on net device: %d\n",
2992	net_dev->mtu);
2993	#endif /* __rtems__ */
2994
2995	priv->buf_layout[RX].priv_data_size = DPAA_RX_PRIV_DATA_SIZE; /* Rx */
2996	priv->buf_layout[TX].priv_data_size = DPAA_TX_PRIV_DATA_SIZE; /* Tx */
2997
2998	#ifndef __rtems__
2999	/* device used for DMA mapping */
3000	arch_setup_dma_ops(dev, 0, 0, NULL, false);
3001	err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(40));
3002	if (err) {
3003	dev_err(dev, "dma_coerce_mask_and_coherent() failed\n");
3004	goto dev_mask_failed;
3005	}
3006	#endif /* __rtems__ */
3007
3008	/* bp init */
3009	for (i = 0; i < DPAA_BPS_NUM; i++) {
3010	int err;
3011
3012	dpaa_bps[i] = dpaa_bp_alloc(dev);
3013	if (IS_ERR(dpaa_bps[i]))
3014	return PTR_ERR(dpaa_bps[i]);
3015	/* the raw size of the buffers used for reception */
3016	dpaa_bps[i]->raw_size = bpool_buffer_raw_size(i, DPAA_BPS_NUM);
3017	/* avoid runtime computations by keeping the usable size here */
3018	dpaa_bps[i]->size = dpaa_bp_size(dpaa_bps[i]->raw_size);
3019	dpaa_bps[i]->dev = dev;
3020
3021	err = dpaa_bp_alloc_pool(dpaa_bps[i]);
3022	if (err < 0) {
3023	dpaa_bps_free(priv);
3024	priv->dpaa_bps[i] = NULL;
3025	goto bp_create_failed;
3026	}
3027	priv->dpaa_bps[i] = dpaa_bps[i];
3028	}
3029
3030	INIT_LIST_HEAD(&priv->dpaa_fq_list);
3031
3032	memset(&port_fqs, 0, sizeof(port_fqs));
3033
3034	err = dpaa_alloc_all_fqs(dev, &priv->dpaa_fq_list, &port_fqs);
3035	if (err < 0) {
3036	dev_err(dev, "dpaa_alloc_all_fqs() failed\n");
3037	goto fq_probe_failed;
3038	}
3039
3040	priv->mac_dev = mac_dev;
3041
3042	channel = dpaa_get_channel();
3043	if (channel < 0) {
3044	dev_err(dev, "dpaa_get_channel() failed\n");
3045	err = channel;
3046	goto get_channel_failed;
3047	}
3048
3049	priv->channel = (u16)channel;
3050
3051	/* Start a thread that will walk the CPUs with affine portals
3052	* and add this pool channel to each's dequeue mask.
3053	*/
3054	dpaa_eth_add_channel(priv->channel);
3055
3056	dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]);
3057
3058	/* Create a congestion group for this netdev, with
3059	* dynamically-allocated CGR ID.
3060	* Must be executed after probing the MAC, but before
3061	* assigning the egress FQs to the CGRs.
3062	*/
3063	err = dpaa_eth_cgr_init(priv);
3064	if (err < 0) {
3065	dev_err(dev, "Error initializing CGR\n");
3066	goto tx_cgr_init_failed;
3067	}
3068
3069	err = dpaa_ingress_cgr_init(priv);
3070	if (err < 0) {
3071	dev_err(dev, "Error initializing ingress CGR\n");
3072	goto rx_cgr_init_failed;
3073	}
3074
3075	/* Add the FQs to the interface, and make them active */
3076	list_for_each_entry_safe(dpaa_fq, tmp, &priv->dpaa_fq_list, list) {
3077	err = dpaa_fq_init(dpaa_fq, false);
3078	if (err < 0)
3079	goto fq_alloc_failed;
3080	}
3081
3082	priv->tx_headroom = dpaa_get_headroom(&priv->buf_layout[TX]);
3083	priv->rx_headroom = dpaa_get_headroom(&priv->buf_layout[RX]);
3084
3085	/* All real interfaces need their ports initialized */
3086	err = dpaa_eth_init_ports(mac_dev, dpaa_bps, DPAA_BPS_NUM, &port_fqs,
3087	&priv->buf_layout[0], dev);
3088	if (err)
3089	goto init_ports_failed;
3090
3091	priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv);
3092	if (!priv->percpu_priv) {
3093	dev_err(dev, "devm_alloc_percpu() failed\n");
3094	err = -ENOMEM;
3095	goto alloc_percpu_failed;
3096	}
3097	#ifndef __rtems__
3098	for_each_possible_cpu(i) {
3099	#else /* __rtems__ */
3100	for (i = 0; i < (int)rtems_get_processor_count(); ++i) {
3101	#endif /* __rtems__ */
3102	percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
3103	memset(percpu_priv, 0, sizeof(*percpu_priv));
3104	}
3105
3106	#ifndef __rtems__
3107	priv->num_tc = 1;
3108	netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM);
3109
3110	/* Initialize NAPI */
3111	err = dpaa_napi_add(net_dev);
3112	if (err < 0)
3113	goto napi_add_failed;
3114
3115	err = dpaa_netdev_init(net_dev, &dpaa_ops, tx_timeout);
3116	if (err < 0)
3117	goto netdev_init_failed;
3118
3119	dpaa_eth_sysfs_init(&net_dev->dev);
3120
3121	netif_info(priv, probe, net_dev, "Probed interface %s\n",
3122	net_dev->name);
3123	#endif /* __rtems__ */
3124
3125	return 0;
3126
3127	#ifndef __rtems__
3128	netdev_init_failed:
3129	napi_add_failed:
3130	#endif /* __rtems__ */
3131	dpaa_napi_del(net_dev);
3132	alloc_percpu_failed:
3133	init_ports_failed:
3134	#ifndef __rtems__
3135	dpaa_fq_free(dev, &priv->dpaa_fq_list);
3136	#endif /* __rtems__ */
3137	fq_alloc_failed:
3138	#ifndef __rtems__
3139	qman_delete_cgr_safe(&priv->ingress_cgr);
3140	qman_release_cgrid(priv->ingress_cgr.cgrid);
3141	#endif /* __rtems__ */
3142	rx_cgr_init_failed:
3143	#ifndef __rtems__
3144	qman_delete_cgr_safe(&priv->cgr_data.cgr);
3145	qman_release_cgrid(priv->cgr_data.cgr.cgrid);
3146	#endif /* __rtems__ */
3147	tx_cgr_init_failed:
3148	get_channel_failed:
3149	dpaa_bps_free(priv);
3150	bp_create_failed:
3151	fq_probe_failed:
3152	#ifndef __rtems__
3153	dev_mask_failed:
3154	mac_probe_failed:
3155	#endif /* __rtems__ */
3156	dev_set_drvdata(dev, NULL);
3157	#ifndef __rtems__
3158	free_netdev(net_dev);
3159	alloc_etherdev_mq_failed:
3160	for (i = 0; i < DPAA_BPS_NUM && dpaa_bps[i]; i++) {
3161	if (atomic_read(&dpaa_bps[i]->refs) == 0)
3162	devm_kfree(dev, dpaa_bps[i]);
3163	}
3164	#else /* __rtems__ */
3165	BSD_ASSERT(0);
3166	#endif /* __rtems__ */
3167	return err;
3168	}
3169
3170	#ifndef __rtems__
3171	static int dpaa_remove(struct platform_device *pdev)
3172	{
3173	struct net_device *net_dev;
3174	struct dpaa_priv *priv;
3175	struct device *dev;
3176	int err;
3177
3178	dev = &pdev->dev;
3179	net_dev = dev_get_drvdata(dev);
3180
3181	priv = netdev_priv(net_dev);
3182
3183	dpaa_eth_sysfs_remove(dev);
3184
3185	dev_set_drvdata(dev, NULL);
3186	unregister_netdev(net_dev);
3187
3188	err = dpaa_fq_free(dev, &priv->dpaa_fq_list);
3189
3190	qman_delete_cgr_safe(&priv->ingress_cgr);
3191	qman_release_cgrid(priv->ingress_cgr.cgrid);
3192	qman_delete_cgr_safe(&priv->cgr_data.cgr);
3193	qman_release_cgrid(priv->cgr_data.cgr.cgrid);
3194
3195	dpaa_napi_del(net_dev);
3196
3197	dpaa_bps_free(priv);
3198
3199	free_netdev(net_dev);
3200
3201	return err;
3202	}
3203	#endif /* __rtems__ */
3204
3205	#ifndef __rtems__
3206	static struct platform_device_id dpaa_devtype[] = {
3207	{
3208	.name = "dpaa-ethernet",
3209	.driver_data = 0,
3210	}, {
3211	}
3212	};
3213	MODULE_DEVICE_TABLE(platform, dpaa_devtype);
3214
3215	static struct platform_driver dpaa_driver = {
3216	.driver = {
3217	.name = KBUILD_MODNAME,
3218	},
3219	.id_table = dpaa_devtype,
3220	.probe = dpaa_eth_probe,
3221	.remove = dpaa_remove
3222	};
3223
3224	static int __init dpaa_load(void)
3225	{
3226	int err;
3227
3228	pr_debug("FSL DPAA Ethernet driver\n");
3229
3230	/* initialize dpaa_eth mirror values */
3231	dpaa_rx_extra_headroom = fman_get_rx_extra_headroom();
3232	dpaa_max_frm = fman_get_max_frm();
3233
3234	err = platform_driver_register(&dpaa_driver);
3235	if (err < 0)
3236	pr_err("Error, platform_driver_register() = %d\n", err);
3237
3238	return err;
3239	}
3240	module_init(dpaa_load);
3241
3242	static void __exit dpaa_unload(void)
3243	{
3244	platform_driver_unregister(&dpaa_driver);
3245
3246	/* Only one channel is used and needs to be released after all
3247	* interfaces are removed
3248	*/
3249	dpaa_release_channel();
3250	}
3251	module_exit(dpaa_unload);
3252
3253	MODULE_LICENSE("Dual BSD/GPL");
3254	MODULE_DESCRIPTION("FSL DPAA Ethernet driver");
3255	#endif /* __rtems__ */

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: rtems-libbsd/linux/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c @ cf40770

Download in other formats: