source: rtems-libbsd/freebsd/sys/sh/pci/pci_bus.c @ af5333e

4.1155-freebsd-126-freebsd-12freebsd-9.3
Last change on this file since af5333e was af5333e, checked in by Sebastian Huber <sebastian.huber@…>, on 11/04/13 at 10:33:00

Update to FreeBSD 8.4
  • Property mode set to 100644
File size: 20.0 KB
Line 
1#include <machine/rtems-bsd-config.h>
2
3/*-
4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice unmodified, this list of conditions, and the following
12 *    disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD$");
31
32#include <rtems/bsd/local/opt_cpu.h>
33
34#include <rtems/bsd/sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/kernel.h>
38#include <sys/malloc.h>
39#include <sys/module.h>
40#include <sys/rman.h>
41#include <sys/sysctl.h>
42
43#include <dev/pci/pcivar.h>
44#include <dev/pci/pcireg.h>
45#include <dev/pci/pcib_private.h>
46#include <isa/isavar.h>
47#ifdef CPU_ELAN
48#include <machine/md_var.h>
49#endif
50#include <machine/legacyvar.h>
51#include <machine/pci_cfgreg.h>
52#include <machine/resource.h>
53
54#include <rtems/bsd/local/pcib_if.h>
55
56#ifndef __rtems__
57static int      pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
58    int pin);
59#else /* __rtems__ */
60int     pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin);
61#endif /* __rtems__ */
62
63
64int
65legacy_pcib_maxslots(device_t dev)
66{
67        return 31;
68}
69
70/* read configuration space register */
71
72#ifdef __rtems__
73uint32_t
74legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
75                        u_int reg, int bytes)
76#else
77u_int32_t
78legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
79                        u_int reg, int bytes)
80#endif
81{
82        return(pci_cfgregread(bus, slot, func, reg, bytes));
83}
84
85/* write configuration space register */
86
87void
88legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
89                         u_int reg, u_int32_t data, int bytes)
90{
91        pci_cfgregwrite(bus, slot, func, reg, data, bytes);
92}
93
94/* Pass MSI requests up to the nexus. */
95
96static int
97legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
98    int *irqs)
99{
100        device_t bus;
101
102        bus = device_get_parent(pcib);
103        return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
104            irqs));
105}
106
107static int
108legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
109{
110        device_t bus;
111
112        bus = device_get_parent(pcib);
113        return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
114}
115
116int
117legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
118    uint32_t *data)
119{
120        device_t bus, hostb;
121        int error, func, slot;
122
123        bus = device_get_parent(pcib);
124        error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
125        if (error)
126                return (error);
127
128        slot = legacy_get_pcislot(pcib);
129        func = legacy_get_pcifunc(pcib);
130        if (slot == -1 || func == -1)
131                return (0);
132        hostb = pci_find_bsf(0, slot, func);
133        KASSERT(hostb != NULL, ("%s: missing hostb for 0:%d:%d", __func__,
134            slot, func));
135        pci_ht_map_msi(hostb, *addr);
136        return (0);
137       
138}
139
140static const char *
141legacy_pcib_is_host_bridge(int bus, int slot, int func,
142                          uint32_t id, uint8_t class, uint8_t subclass,
143                          uint8_t *busnum)
144{
145        const char *s = NULL;
146        static uint8_t pxb[4];  /* hack for 450nx */
147
148        *busnum = 0;
149
150        switch (id) {
151        case 0x12258086:
152                s = "Intel 824?? host to PCI bridge";
153                /* XXX This is a guess */
154                /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
155                *busnum = bus;
156                break;
157        case 0x71208086:
158                s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
159                break;
160        case 0x71228086:
161                s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
162                break;
163        case 0x71248086:
164                s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
165                break;
166        case 0x11308086:
167                s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
168                break;
169        case 0x71808086:
170                s = "Intel 82443LX (440 LX) host to PCI bridge";
171                break;
172        case 0x71908086:
173                s = "Intel 82443BX (440 BX) host to PCI bridge";
174                break;
175        case 0x71928086:
176                s = "Intel 82443BX host to PCI bridge (AGP disabled)";
177                break;
178        case 0x71948086:
179                s = "Intel 82443MX host to PCI bridge";
180                break;
181        case 0x71a08086:
182                s = "Intel 82443GX host to PCI bridge";
183                break;
184        case 0x71a18086:
185                s = "Intel 82443GX host to AGP bridge";
186                break;
187        case 0x71a28086:
188                s = "Intel 82443GX host to PCI bridge (AGP disabled)";
189                break;
190        case 0x84c48086:
191                s = "Intel 82454KX/GX (Orion) host to PCI bridge";
192                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
193                break;
194        case 0x84ca8086:
195                /*
196                 * For the 450nx chipset, there is a whole bundle of
197                 * things pretending to be host bridges. The MIOC will
198                 * be seen first and isn't really a pci bridge (the
199                 * actual busses are attached to the PXB's). We need to
200                 * read the registers of the MIOC to figure out the
201                 * bus numbers for the PXB channels.
202                 *
203                 * Since the MIOC doesn't have a pci bus attached, we
204                 * pretend it wasn't there.
205                 */
206                pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
207                                                0xd0, 1); /* BUSNO[0] */
208                pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
209                                                0xd1, 1) + 1;   /* SUBA[0]+1 */
210                pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
211                                                0xd3, 1); /* BUSNO[1] */
212                pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
213                                                0xd4, 1) + 1;   /* SUBA[1]+1 */
214                return NULL;
215        case 0x84cb8086:
216                switch (slot) {
217                case 0x12:
218                        s = "Intel 82454NX PXB#0, Bus#A";
219                        *busnum = pxb[0];
220                        break;
221                case 0x13:
222                        s = "Intel 82454NX PXB#0, Bus#B";
223                        *busnum = pxb[1];
224                        break;
225                case 0x14:
226                        s = "Intel 82454NX PXB#1, Bus#A";
227                        *busnum = pxb[2];
228                        break;
229                case 0x15:
230                        s = "Intel 82454NX PXB#1, Bus#B";
231                        *busnum = pxb[3];
232                        break;
233                }
234                break;
235        case 0x1A308086:
236                s = "Intel 82845 Host to PCI bridge";
237                break;
238
239                /* AMD -- vendor 0x1022 */
240        case 0x30001022:
241                s = "AMD Elan SC520 host to PCI bridge";
242#ifdef CPU_ELAN
243                init_AMD_Elan_sc520();
244#else
245                printf(
246"*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
247#endif
248                break;
249        case 0x70061022:
250                s = "AMD-751 host to PCI bridge";
251                break;
252        case 0x700e1022:
253                s = "AMD-761 host to PCI bridge";
254                break;
255
256                /* SiS -- vendor 0x1039 */
257        case 0x04961039:
258                s = "SiS 85c496";
259                break;
260        case 0x04061039:
261                s = "SiS 85c501";
262                break;
263        case 0x06011039:
264                s = "SiS 85c601";
265                break;
266        case 0x55911039:
267                s = "SiS 5591 host to PCI bridge";
268                break;
269        case 0x00011039:
270                s = "SiS 5591 host to AGP bridge";
271                break;
272
273                /* VLSI -- vendor 0x1004 */
274        case 0x00051004:
275                s = "VLSI 82C592 Host to PCI bridge";
276                break;
277
278                /* XXX Here is MVP3, I got the datasheet but NO M/B to test it  */
279                /* totally. Please let me know if anything wrong.            -F */
280                /* XXX need info on the MVP3 -- any takers? */
281        case 0x05981106:
282                s = "VIA 82C598MVP (Apollo MVP3) host bridge";
283                break;
284
285                /* AcerLabs -- vendor 0x10b9 */
286                /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
287                /* id is '10b9" but the register always shows "10b9". -Foxfair  */
288        case 0x154110b9:
289                s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
290                break;
291
292                /* OPTi -- vendor 0x1045 */
293        case 0xc7011045:
294                s = "OPTi 82C700 host to PCI bridge";
295                break;
296        case 0xc8221045:
297                s = "OPTi 82C822 host to PCI Bridge";
298                break;
299
300                /* ServerWorks -- vendor 0x1166 */
301        case 0x00051166:
302                s = "ServerWorks NB6536 2.0HE host to PCI bridge";
303                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
304                break;
305
306        case 0x00061166:
307                /* FALLTHROUGH */
308        case 0x00081166:
309                /* FALLTHROUGH */
310        case 0x02011166:
311                /* FALLTHROUGH */
312        case 0x010f1014: /* IBM re-badged ServerWorks chipset */
313                s = "ServerWorks host to PCI bridge";
314                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
315                break;
316
317        case 0x00091166:
318                s = "ServerWorks NB6635 3.0LE host to PCI bridge";
319                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
320                break;
321
322        case 0x00101166:
323                s = "ServerWorks CIOB30 host to PCI bridge";
324                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
325                break;
326
327        case 0x00111166:
328                /* FALLTHROUGH */
329        case 0x03021014: /* IBM re-badged ServerWorks chipset */
330                s = "ServerWorks CMIC-HE host to PCI-X bridge";
331                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
332                break;
333
334                /* XXX unknown chipset, but working */
335        case 0x00171166:
336                /* FALLTHROUGH */
337        case 0x01011166:
338        case 0x01101166:
339        case 0x02251166:
340                s = "ServerWorks host to PCI bridge(unknown chipset)";
341                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
342                break;
343
344                /* Compaq/HP -- vendor 0x0e11 */
345        case 0x60100e11:
346                s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
347                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
348                break;
349
350                /* Integrated Micro Solutions -- vendor 0x10e0 */
351        case 0x884910e0:
352                s = "Integrated Micro Solutions VL Bridge";
353                break;
354
355        default:
356                if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
357                        s = "Host to PCI bridge";
358                break;
359        }
360
361        return s;
362}
363
364/*
365 * Scan the first pci bus for host-pci bridges and add pcib instances
366 * to the nexus for each bridge.
367 */
368static void
369legacy_pcib_identify(driver_t *driver, device_t parent)
370{
371        int bus, slot, func;
372        u_int8_t  hdrtype;
373        int found = 0;
374        int pcifunchigh;
375        int found824xx = 0;
376        int found_orion = 0;
377        device_t child;
378        devclass_t pci_devclass;
379
380        if (pci_cfgregopen() == 0)
381                return;
382        /*
383         * Check to see if we haven't already had a PCI bus added
384         * via some other means.  If we have, bail since otherwise
385         * we're going to end up duplicating it.
386         */
387        if ((pci_devclass = devclass_find("pci")) &&
388                devclass_get_device(pci_devclass, 0))
389                return;
390
391
392        bus = 0;
393 retry:
394        for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
395                func = 0;
396                hdrtype = legacy_pcib_read_config(0, bus, slot, func,
397                                                 PCIR_HDRTYPE, 1);
398                /*
399                 * When enumerating bus devices, the standard says that
400                 * one should check the header type and ignore the slots whose
401                 * header types that the software doesn't know about.  We use
402                 * this to filter out devices.
403                 */
404                if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
405                        continue;
406                if ((hdrtype & PCIM_MFDEV) &&
407                    (!found_orion || hdrtype != 0xff))
408                        pcifunchigh = PCI_FUNCMAX;
409                else
410                        pcifunchigh = 0;
411                for (func = 0; func <= pcifunchigh; func++) {
412                        /*
413                         * Read the IDs and class from the device.
414                         */
415                        u_int32_t id;
416                        u_int8_t class, subclass, busnum;
417                        const char *s;
418                        device_t *devs;
419                        int ndevs, i;
420
421                        id = legacy_pcib_read_config(0, bus, slot, func,
422                                                    PCIR_DEVVENDOR, 4);
423                        if (id == -1)
424                                continue;
425                        class = legacy_pcib_read_config(0, bus, slot, func,
426                                                       PCIR_CLASS, 1);
427                        subclass = legacy_pcib_read_config(0, bus, slot, func,
428                                                          PCIR_SUBCLASS, 1);
429
430                        s = legacy_pcib_is_host_bridge(bus, slot, func,
431                                                      id, class, subclass,
432                                                      &busnum);
433                        if (s == NULL)
434                                continue;
435
436                        /*
437                         * Check to see if the physical bus has already
438                         * been seen.  Eg: hybrid 32 and 64 bit host
439                         * bridges to the same logical bus.
440                         */
441                        if (device_get_children(parent, &devs, &ndevs) == 0) {
442                                for (i = 0; s != NULL && i < ndevs; i++) {
443                                        if (strcmp(device_get_name(devs[i]),
444                                            "pcib") != 0)
445                                                continue;
446                                        if (legacy_get_pcibus(devs[i]) == busnum)
447                                                s = NULL;
448                                }
449                                free(devs, M_TEMP);
450                        }
451
452                        if (s == NULL)
453                                continue;
454                        /*
455                         * Add at priority 100 to make sure we
456                         * go after any motherboard resources
457                         */
458                        child = BUS_ADD_CHILD(parent, 100,
459                                              "pcib", busnum);
460                        device_set_desc(child, s);
461                        legacy_set_pcibus(child, busnum);
462                        legacy_set_pcislot(child, slot);
463                        legacy_set_pcifunc(child, func);
464
465                        found = 1;
466                        if (id == 0x12258086)
467                                found824xx = 1;
468                        if (id == 0x84c48086)
469                                found_orion = 1;
470                }
471        }
472        if (found824xx && bus == 0) {
473                bus++;
474                goto retry;
475        }
476
477        /*
478         * Make sure we add at least one bridge since some old
479         * hardware doesn't actually have a host-pci bridge device.
480         * Note that pci_cfgregopen() thinks we have PCI devices..
481         */
482        if (!found) {
483                if (bootverbose)
484                        printf(
485        "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
486                child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
487                legacy_set_pcibus(child, 0);
488        }
489}
490
491static int
492legacy_pcib_probe(device_t dev)
493{
494
495        if (pci_cfgregopen() == 0)
496                return ENXIO;
497        return -100;
498}
499
500static int
501legacy_pcib_attach(device_t dev)
502{
503        device_t pir;
504        int bus;
505
506        /*
507         * Look for a PCI BIOS interrupt routing table as that will be
508         * our method of routing interrupts if we have one.
509         */
510        bus = pcib_get_bus(dev);
511#ifndef __rtems__
512        if (pci_pir_probe(bus, 0)) {
513                pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
514                if (pir != NULL)
515                        device_probe_and_attach(pir);
516        }
517#else /* __rtems__ */
518#endif /* __rtems__ */
519        device_add_child(dev, "pci", bus);
520        return bus_generic_attach(dev);
521}
522
523int
524legacy_pcib_read_ivar(device_t dev, device_t child, int which,
525    uintptr_t *result)
526{
527
528        switch (which) {
529        case  PCIB_IVAR_DOMAIN:
530                *result = 0;
531                return 0;
532        case  PCIB_IVAR_BUS:
533                *result = legacy_get_pcibus(dev);
534                return 0;
535        }
536        return ENOENT;
537}
538
539int
540legacy_pcib_write_ivar(device_t dev, device_t child, int which,
541    uintptr_t value)
542{
543
544        switch (which) {
545        case  PCIB_IVAR_DOMAIN:
546                return EINVAL;
547        case  PCIB_IVAR_BUS:
548                legacy_set_pcibus(dev, value);
549                return 0;
550        }
551        return ENOENT;
552}
553
554SYSCTL_DECL(_hw_pci);
555
556static unsigned long legacy_host_mem_start = 0x80000000;
557TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start);
558SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN,
559    &legacy_host_mem_start, 0x80000000,
560    "Limit the host bridge memory to being above this address.  Must be\n\
561set at boot via a tunable.");
562
563struct resource *
564legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
565    u_long start, u_long end, u_long count, u_int flags)
566{
567    /*
568     * If no memory preference is given, use upper 32MB slot most
569     * bioses use for their memory window.  Typically other bridges
570     * before us get in the way to assert their preferences on memory.
571     * Hardcoding like this sucks, so a more MD/MI way needs to be
572     * found to do it.  This is typically only used on older laptops
573     * that don't have pci busses behind pci bridge, so assuming > 32MB
574     * is liekly OK.
575     *
576     * However, this can cause problems for other chipsets, so we make
577     * this tunable by hw.pci.host_mem_start.
578     */
579    if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
580        start = legacy_host_mem_start;
581    if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL)
582        start = 0x1000;
583    return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
584        count, flags));
585}
586
587static device_method_t legacy_pcib_methods[] = {
588        /* Device interface */
589        DEVMETHOD(device_identify,      legacy_pcib_identify),
590        DEVMETHOD(device_probe,         legacy_pcib_probe),
591        DEVMETHOD(device_attach,        legacy_pcib_attach),
592        DEVMETHOD(device_shutdown,      bus_generic_shutdown),
593        DEVMETHOD(device_suspend,       bus_generic_suspend),
594        DEVMETHOD(device_resume,        bus_generic_resume),
595
596        /* Bus interface */
597        DEVMETHOD(bus_read_ivar,        legacy_pcib_read_ivar),
598        DEVMETHOD(bus_write_ivar,       legacy_pcib_write_ivar),
599        DEVMETHOD(bus_alloc_resource,   legacy_pcib_alloc_resource),
600        DEVMETHOD(bus_adjust_resource,  bus_generic_adjust_resource),
601        DEVMETHOD(bus_release_resource, bus_generic_release_resource),
602        DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
603        DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
604        DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
605        DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
606
607        /* pcib interface */
608        DEVMETHOD(pcib_maxslots,        legacy_pcib_maxslots),
609        DEVMETHOD(pcib_read_config,     legacy_pcib_read_config),
610        DEVMETHOD(pcib_write_config,    legacy_pcib_write_config),
611        DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
612        DEVMETHOD(pcib_alloc_msi,       legacy_pcib_alloc_msi),
613        DEVMETHOD(pcib_release_msi,     pcib_release_msi),
614        DEVMETHOD(pcib_alloc_msix,      legacy_pcib_alloc_msix),
615        DEVMETHOD(pcib_release_msix,    pcib_release_msix),
616        DEVMETHOD(pcib_map_msi,         legacy_pcib_map_msi),
617
618        DEVMETHOD_END
619};
620
621static devclass_t hostb_devclass;
622
623DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
624DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
625
626
627#ifndef __rtems__
628/*
629 * Install placeholder to claim the resources owned by the
630 * PCI bus interface.  This could be used to extract the
631 * config space registers in the extreme case where the PnP
632 * ID is available and the PCI BIOS isn't, but for now we just
633 * eat the PnP ID and do nothing else.
634 *
635 * XXX we should silence this probe, as it will generally confuse
636 * people.
637 */
638static struct isa_pnp_id pcibus_pnp_ids[] = {
639        { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
640        { 0x080ad041 /* PNP0A08 */, "PCIe Bus" },
641        { 0 }
642};
643
644static int
645pcibus_pnp_probe(device_t dev)
646{
647        int result;
648
649        if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
650                device_quiet(dev);
651        return(result);
652}
653
654static int
655pcibus_pnp_attach(device_t dev)
656{
657        return(0);
658}
659
660static device_method_t pcibus_pnp_methods[] = {
661        /* Device interface */
662        DEVMETHOD(device_probe,         pcibus_pnp_probe),
663        DEVMETHOD(device_attach,        pcibus_pnp_attach),
664        DEVMETHOD(device_detach,        bus_generic_detach),
665        DEVMETHOD(device_shutdown,      bus_generic_shutdown),
666        DEVMETHOD(device_suspend,       bus_generic_suspend),
667        DEVMETHOD(device_resume,        bus_generic_resume),
668        { 0, 0 }
669};
670
671static devclass_t pcibus_pnp_devclass;
672
673DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
674DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
675
676
677/*
678 * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
679 * that appear in the PCIBIOS Interrupt Routing Table to use the routing
680 * table for interrupt routing when possible.
681 */
682static int      pcibios_pcib_probe(device_t bus);
683
684static device_method_t pcibios_pcib_pci_methods[] = {
685        /* Device interface */
686        DEVMETHOD(device_probe,         pcibios_pcib_probe),
687        DEVMETHOD(device_attach,        pcib_attach),
688        DEVMETHOD(device_shutdown,      bus_generic_shutdown),
689        DEVMETHOD(device_suspend,       bus_generic_suspend),
690        DEVMETHOD(device_resume,        bus_generic_resume),
691
692        /* Bus interface */
693        DEVMETHOD(bus_read_ivar,        pcib_read_ivar),
694        DEVMETHOD(bus_write_ivar,       pcib_write_ivar),
695        DEVMETHOD(bus_alloc_resource,   pcib_alloc_resource),
696        DEVMETHOD(bus_release_resource, bus_generic_release_resource),
697        DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
698        DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
699        DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
700        DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
701
702        /* pcib interface */
703        DEVMETHOD(pcib_maxslots,        pcib_maxslots),
704        DEVMETHOD(pcib_read_config,     pcib_read_config),
705        DEVMETHOD(pcib_write_config,    pcib_write_config),
706        DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
707        DEVMETHOD(pcib_alloc_msi,       pcib_alloc_msi),
708        DEVMETHOD(pcib_release_msi,     pcib_release_msi),
709        DEVMETHOD(pcib_alloc_msix,      pcib_alloc_msix),
710        DEVMETHOD(pcib_release_msix,    pcib_release_msix),
711        DEVMETHOD(pcib_map_msi,         pcib_map_msi),
712
713        DEVMETHOD_END
714};
715
716static devclass_t pcib_devclass;
717
718DEFINE_CLASS_0(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
719    sizeof(struct pcib_softc));
720DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
721
722static int
723pcibios_pcib_probe(device_t dev)
724{
725        int bus;
726
727        if ((pci_get_class(dev) != PCIC_BRIDGE) ||
728            (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
729                return (ENXIO);
730        bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
731        if (bus == 0)
732                return (ENXIO);
733        if (!pci_pir_probe(bus, 1))
734                return (ENXIO);
735        device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
736        return (-2000);
737}
738
739static int
740pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
741{
742        return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
743                pci_get_function(dev), pin));
744}
745#endif /* __rtems__ */
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