1 | #include <machine/rtems-bsd-kernel-space.h> |
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2 | |
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3 | /*- |
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4 | * Copyright (c) 1997, Stefan Esser <se@freebsd.org> |
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5 | * All rights reserved. |
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6 | * |
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7 | * Redistribution and use in source and binary forms, with or without |
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8 | * modification, are permitted provided that the following conditions |
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9 | * are met: |
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10 | * 1. Redistributions of source code must retain the above copyright |
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11 | * notice unmodified, this list of conditions, and the following |
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12 | * disclaimer. |
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13 | * 2. Redistributions in binary form must reproduce the above copyright |
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14 | * notice, this list of conditions and the following disclaimer in the |
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15 | * documentation and/or other materials provided with the distribution. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |
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29 | #include <sys/cdefs.h> |
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30 | __FBSDID("$FreeBSD$"); |
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31 | |
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32 | #include <rtems/bsd/local/opt_cpu.h> |
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33 | |
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34 | #include <rtems/bsd/sys/param.h> |
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35 | #include <sys/systm.h> |
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36 | #include <sys/bus.h> |
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37 | #include <sys/kernel.h> |
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38 | #include <sys/malloc.h> |
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39 | #include <sys/module.h> |
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40 | #include <sys/rman.h> |
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41 | #include <sys/sysctl.h> |
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42 | |
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43 | #include <dev/pci/pcivar.h> |
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44 | #include <dev/pci/pcireg.h> |
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45 | #include <dev/pci/pcib_private.h> |
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46 | #include <isa/isavar.h> |
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47 | #ifdef CPU_ELAN |
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48 | #include <machine/md_var.h> |
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49 | #endif |
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50 | #include <machine/legacyvar.h> |
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51 | #include <machine/pci_cfgreg.h> |
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52 | #include <machine/resource.h> |
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53 | |
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54 | #include <rtems/bsd/local/pcib_if.h> |
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55 | |
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56 | int |
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57 | legacy_pcib_maxslots(device_t dev) |
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58 | { |
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59 | return 31; |
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60 | } |
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61 | |
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62 | /* read configuration space register */ |
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63 | |
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64 | uint32_t |
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65 | legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, |
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66 | u_int reg, int bytes) |
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67 | { |
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68 | return(pci_cfgregread(bus, slot, func, reg, bytes)); |
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69 | } |
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70 | |
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71 | /* write configuration space register */ |
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72 | |
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73 | void |
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74 | legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, |
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75 | u_int reg, uint32_t data, int bytes) |
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76 | { |
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77 | pci_cfgregwrite(bus, slot, func, reg, data, bytes); |
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78 | } |
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79 | |
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80 | /* route interrupt */ |
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81 | |
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82 | static int |
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83 | legacy_pcib_route_interrupt(device_t pcib, device_t dev, int pin) |
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84 | { |
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85 | |
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86 | #ifdef __HAVE_PIR |
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87 | return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev), |
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88 | pci_get_function(dev), pin)); |
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89 | #else |
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90 | /* No routing possible */ |
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91 | return (PCI_INVALID_IRQ); |
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92 | #endif |
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93 | } |
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94 | |
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95 | /* Pass MSI requests up to the nexus. */ |
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96 | |
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97 | static int |
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98 | legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, |
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99 | int *irqs) |
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100 | { |
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101 | device_t bus; |
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102 | |
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103 | bus = device_get_parent(pcib); |
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104 | return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, |
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105 | irqs)); |
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106 | } |
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107 | |
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108 | static int |
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109 | legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq) |
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110 | { |
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111 | device_t bus; |
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112 | |
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113 | bus = device_get_parent(pcib); |
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114 | return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); |
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115 | } |
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116 | |
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117 | int |
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118 | legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, |
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119 | uint32_t *data) |
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120 | { |
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121 | device_t bus, hostb; |
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122 | int error, func, slot; |
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123 | |
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124 | bus = device_get_parent(pcib); |
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125 | error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); |
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126 | if (error) |
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127 | return (error); |
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128 | |
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129 | slot = legacy_get_pcislot(pcib); |
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130 | func = legacy_get_pcifunc(pcib); |
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131 | if (slot == -1 || func == -1) |
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132 | return (0); |
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133 | hostb = pci_find_bsf(0, slot, func); |
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134 | KASSERT(hostb != NULL, ("%s: missing hostb for 0:%d:%d", __func__, |
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135 | slot, func)); |
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136 | pci_ht_map_msi(hostb, *addr); |
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137 | return (0); |
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138 | |
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139 | } |
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140 | |
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141 | static const char * |
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142 | legacy_pcib_is_host_bridge(int bus, int slot, int func, |
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143 | uint32_t id, uint8_t class, uint8_t subclass, |
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144 | uint8_t *busnum) |
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145 | { |
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146 | #ifdef __i386__ |
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147 | const char *s = NULL; |
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148 | static uint8_t pxb[4]; /* hack for 450nx */ |
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149 | |
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150 | *busnum = 0; |
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151 | |
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152 | switch (id) { |
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153 | case 0x12258086: |
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154 | s = "Intel 824?? host to PCI bridge"; |
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155 | /* XXX This is a guess */ |
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156 | /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */ |
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157 | *busnum = bus; |
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158 | break; |
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159 | case 0x71208086: |
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160 | s = "Intel 82810 (i810 GMCH) Host To Hub bridge"; |
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161 | break; |
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162 | case 0x71228086: |
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163 | s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge"; |
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164 | break; |
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165 | case 0x71248086: |
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166 | s = "Intel 82810E (i810E GMCH) Host To Hub bridge"; |
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167 | break; |
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168 | case 0x11308086: |
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169 | s = "Intel 82815 (i815 GMCH) Host To Hub bridge"; |
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170 | break; |
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171 | case 0x71808086: |
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172 | s = "Intel 82443LX (440 LX) host to PCI bridge"; |
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173 | break; |
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174 | case 0x71908086: |
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175 | s = "Intel 82443BX (440 BX) host to PCI bridge"; |
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176 | break; |
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177 | case 0x71928086: |
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178 | s = "Intel 82443BX host to PCI bridge (AGP disabled)"; |
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179 | break; |
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180 | case 0x71948086: |
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181 | s = "Intel 82443MX host to PCI bridge"; |
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182 | break; |
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183 | case 0x71a08086: |
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184 | s = "Intel 82443GX host to PCI bridge"; |
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185 | break; |
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186 | case 0x71a18086: |
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187 | s = "Intel 82443GX host to AGP bridge"; |
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188 | break; |
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189 | case 0x71a28086: |
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190 | s = "Intel 82443GX host to PCI bridge (AGP disabled)"; |
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191 | break; |
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192 | case 0x84c48086: |
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193 | s = "Intel 82454KX/GX (Orion) host to PCI bridge"; |
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194 | *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1); |
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195 | break; |
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196 | case 0x84ca8086: |
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197 | /* |
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198 | * For the 450nx chipset, there is a whole bundle of |
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199 | * things pretending to be host bridges. The MIOC will |
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200 | * be seen first and isn't really a pci bridge (the |
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201 | * actual busses are attached to the PXB's). We need to |
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202 | * read the registers of the MIOC to figure out the |
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203 | * bus numbers for the PXB channels. |
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204 | * |
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205 | * Since the MIOC doesn't have a pci bus attached, we |
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206 | * pretend it wasn't there. |
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207 | */ |
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208 | pxb[0] = legacy_pcib_read_config(0, bus, slot, func, |
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209 | 0xd0, 1); /* BUSNO[0] */ |
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210 | pxb[1] = legacy_pcib_read_config(0, bus, slot, func, |
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211 | 0xd1, 1) + 1; /* SUBA[0]+1 */ |
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212 | pxb[2] = legacy_pcib_read_config(0, bus, slot, func, |
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213 | 0xd3, 1); /* BUSNO[1] */ |
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214 | pxb[3] = legacy_pcib_read_config(0, bus, slot, func, |
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215 | 0xd4, 1) + 1; /* SUBA[1]+1 */ |
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216 | return NULL; |
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217 | case 0x84cb8086: |
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218 | switch (slot) { |
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219 | case 0x12: |
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220 | s = "Intel 82454NX PXB#0, Bus#A"; |
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221 | *busnum = pxb[0]; |
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222 | break; |
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223 | case 0x13: |
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224 | s = "Intel 82454NX PXB#0, Bus#B"; |
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225 | *busnum = pxb[1]; |
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226 | break; |
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227 | case 0x14: |
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228 | s = "Intel 82454NX PXB#1, Bus#A"; |
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229 | *busnum = pxb[2]; |
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230 | break; |
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231 | case 0x15: |
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232 | s = "Intel 82454NX PXB#1, Bus#B"; |
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233 | *busnum = pxb[3]; |
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234 | break; |
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235 | } |
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236 | break; |
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237 | case 0x1A308086: |
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238 | s = "Intel 82845 Host to PCI bridge"; |
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239 | break; |
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240 | |
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241 | /* AMD -- vendor 0x1022 */ |
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242 | case 0x30001022: |
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243 | s = "AMD Elan SC520 host to PCI bridge"; |
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244 | #ifdef CPU_ELAN |
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245 | init_AMD_Elan_sc520(); |
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246 | #else |
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247 | printf( |
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248 | "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n"); |
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249 | #endif |
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250 | break; |
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251 | case 0x70061022: |
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252 | s = "AMD-751 host to PCI bridge"; |
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253 | break; |
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254 | case 0x700e1022: |
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255 | s = "AMD-761 host to PCI bridge"; |
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256 | break; |
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257 | |
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258 | /* SiS -- vendor 0x1039 */ |
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259 | case 0x04961039: |
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260 | s = "SiS 85c496"; |
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261 | break; |
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262 | case 0x04061039: |
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263 | s = "SiS 85c501"; |
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264 | break; |
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265 | case 0x06011039: |
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266 | s = "SiS 85c601"; |
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267 | break; |
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268 | case 0x55911039: |
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269 | s = "SiS 5591 host to PCI bridge"; |
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270 | break; |
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271 | case 0x00011039: |
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272 | s = "SiS 5591 host to AGP bridge"; |
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273 | break; |
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274 | |
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275 | /* VLSI -- vendor 0x1004 */ |
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276 | case 0x00051004: |
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277 | s = "VLSI 82C592 Host to PCI bridge"; |
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278 | break; |
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279 | |
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280 | /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */ |
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281 | /* totally. Please let me know if anything wrong. -F */ |
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282 | /* XXX need info on the MVP3 -- any takers? */ |
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283 | case 0x05981106: |
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284 | s = "VIA 82C598MVP (Apollo MVP3) host bridge"; |
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285 | break; |
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286 | |
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287 | /* AcerLabs -- vendor 0x10b9 */ |
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288 | /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */ |
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289 | /* id is '10b9" but the register always shows "10b9". -Foxfair */ |
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290 | case 0x154110b9: |
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291 | s = "AcerLabs M1541 (Aladdin-V) PCI host bridge"; |
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292 | break; |
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293 | |
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294 | /* OPTi -- vendor 0x1045 */ |
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295 | case 0xc7011045: |
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296 | s = "OPTi 82C700 host to PCI bridge"; |
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297 | break; |
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298 | case 0xc8221045: |
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299 | s = "OPTi 82C822 host to PCI Bridge"; |
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300 | break; |
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301 | |
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302 | /* ServerWorks -- vendor 0x1166 */ |
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303 | case 0x00051166: |
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304 | s = "ServerWorks NB6536 2.0HE host to PCI bridge"; |
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305 | *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); |
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306 | break; |
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307 | |
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308 | case 0x00061166: |
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309 | /* FALLTHROUGH */ |
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310 | case 0x00081166: |
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311 | /* FALLTHROUGH */ |
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312 | case 0x02011166: |
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313 | /* FALLTHROUGH */ |
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314 | case 0x010f1014: /* IBM re-badged ServerWorks chipset */ |
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315 | s = "ServerWorks host to PCI bridge"; |
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316 | *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); |
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317 | break; |
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318 | |
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319 | case 0x00091166: |
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320 | s = "ServerWorks NB6635 3.0LE host to PCI bridge"; |
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321 | *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); |
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322 | break; |
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323 | |
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324 | case 0x00101166: |
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325 | s = "ServerWorks CIOB30 host to PCI bridge"; |
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326 | *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); |
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327 | break; |
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328 | |
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329 | case 0x00111166: |
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330 | /* FALLTHROUGH */ |
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331 | case 0x03021014: /* IBM re-badged ServerWorks chipset */ |
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332 | s = "ServerWorks CMIC-HE host to PCI-X bridge"; |
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333 | *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); |
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334 | break; |
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335 | |
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336 | /* XXX unknown chipset, but working */ |
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337 | case 0x00171166: |
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338 | /* FALLTHROUGH */ |
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339 | case 0x01011166: |
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340 | case 0x01101166: |
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341 | case 0x02251166: |
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342 | s = "ServerWorks host to PCI bridge(unknown chipset)"; |
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343 | *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); |
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344 | break; |
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345 | |
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346 | /* Compaq/HP -- vendor 0x0e11 */ |
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347 | case 0x60100e11: |
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348 | s = "Compaq/HP Model 6010 HotPlug PCI Bridge"; |
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349 | *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1); |
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350 | break; |
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351 | |
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352 | /* Integrated Micro Solutions -- vendor 0x10e0 */ |
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353 | case 0x884910e0: |
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354 | s = "Integrated Micro Solutions VL Bridge"; |
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355 | break; |
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356 | |
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357 | default: |
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358 | if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST) |
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359 | s = "Host to PCI bridge"; |
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360 | break; |
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361 | } |
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362 | |
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363 | return s; |
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364 | #else |
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365 | const char *s = NULL; |
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366 | |
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367 | *busnum = 0; |
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368 | if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST) |
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369 | s = "Host to PCI bridge"; |
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370 | return s; |
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371 | #endif |
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372 | } |
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373 | |
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374 | /* |
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375 | * Scan the first pci bus for host-pci bridges and add pcib instances |
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376 | * to the nexus for each bridge. |
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377 | */ |
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378 | static void |
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379 | legacy_pcib_identify(driver_t *driver, device_t parent) |
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380 | { |
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381 | int bus, slot, func; |
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382 | uint8_t hdrtype; |
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383 | int found = 0; |
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384 | int pcifunchigh; |
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385 | int found824xx = 0; |
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386 | int found_orion = 0; |
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387 | device_t child; |
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388 | devclass_t pci_devclass; |
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389 | |
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390 | if (pci_cfgregopen() == 0) |
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391 | return; |
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392 | /* |
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393 | * Check to see if we haven't already had a PCI bus added |
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394 | * via some other means. If we have, bail since otherwise |
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395 | * we're going to end up duplicating it. |
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396 | */ |
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397 | if ((pci_devclass = devclass_find("pci")) && |
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398 | devclass_get_device(pci_devclass, 0)) |
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399 | return; |
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400 | |
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401 | |
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402 | bus = 0; |
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403 | retry: |
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404 | for (slot = 0; slot <= PCI_SLOTMAX; slot++) { |
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405 | func = 0; |
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406 | hdrtype = legacy_pcib_read_config(0, bus, slot, func, |
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407 | PCIR_HDRTYPE, 1); |
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408 | /* |
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409 | * When enumerating bus devices, the standard says that |
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410 | * one should check the header type and ignore the slots whose |
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411 | * header types that the software doesn't know about. We use |
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412 | * this to filter out devices. |
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413 | */ |
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414 | if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) |
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415 | continue; |
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416 | if ((hdrtype & PCIM_MFDEV) && |
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417 | (!found_orion || hdrtype != 0xff)) |
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418 | pcifunchigh = PCI_FUNCMAX; |
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419 | else |
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420 | pcifunchigh = 0; |
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421 | for (func = 0; func <= pcifunchigh; func++) { |
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422 | /* |
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423 | * Read the IDs and class from the device. |
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424 | */ |
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425 | uint32_t id; |
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426 | uint8_t class, subclass, busnum; |
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427 | const char *s; |
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428 | device_t *devs; |
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429 | int ndevs, i; |
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430 | |
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431 | id = legacy_pcib_read_config(0, bus, slot, func, |
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432 | PCIR_DEVVENDOR, 4); |
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433 | if (id == -1) |
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434 | continue; |
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435 | class = legacy_pcib_read_config(0, bus, slot, func, |
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436 | PCIR_CLASS, 1); |
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437 | subclass = legacy_pcib_read_config(0, bus, slot, func, |
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438 | PCIR_SUBCLASS, 1); |
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439 | |
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440 | s = legacy_pcib_is_host_bridge(bus, slot, func, |
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441 | id, class, subclass, |
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442 | &busnum); |
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443 | if (s == NULL) |
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444 | continue; |
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445 | |
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446 | /* |
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447 | * Check to see if the physical bus has already |
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448 | * been seen. Eg: hybrid 32 and 64 bit host |
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449 | * bridges to the same logical bus. |
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450 | */ |
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451 | if (device_get_children(parent, &devs, &ndevs) == 0) { |
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452 | for (i = 0; s != NULL && i < ndevs; i++) { |
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453 | if (strcmp(device_get_name(devs[i]), |
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454 | "pcib") != 0) |
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455 | continue; |
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456 | if (legacy_get_pcibus(devs[i]) == busnum) |
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457 | s = NULL; |
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458 | } |
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459 | free(devs, M_TEMP); |
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460 | } |
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461 | |
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462 | if (s == NULL) |
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463 | continue; |
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464 | /* |
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465 | * Add at priority 100 to make sure we |
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466 | * go after any motherboard resources |
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467 | */ |
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468 | child = BUS_ADD_CHILD(parent, 100, |
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469 | "pcib", busnum); |
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470 | device_set_desc(child, s); |
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471 | legacy_set_pcibus(child, busnum); |
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472 | legacy_set_pcislot(child, slot); |
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473 | legacy_set_pcifunc(child, func); |
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474 | |
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475 | found = 1; |
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476 | if (id == 0x12258086) |
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477 | found824xx = 1; |
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478 | if (id == 0x84c48086) |
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479 | found_orion = 1; |
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480 | } |
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481 | } |
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482 | if (found824xx && bus == 0) { |
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483 | bus++; |
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484 | goto retry; |
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485 | } |
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486 | |
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487 | /* |
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488 | * Make sure we add at least one bridge since some old |
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489 | * hardware doesn't actually have a host-pci bridge device. |
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490 | * Note that pci_cfgregopen() thinks we have PCI devices.. |
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491 | */ |
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492 | if (!found) { |
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493 | if (bootverbose) |
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494 | printf( |
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495 | "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n"); |
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496 | child = BUS_ADD_CHILD(parent, 100, "pcib", 0); |
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497 | legacy_set_pcibus(child, 0); |
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498 | } |
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499 | } |
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500 | |
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501 | static int |
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502 | legacy_pcib_probe(device_t dev) |
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503 | { |
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504 | |
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505 | if (pci_cfgregopen() == 0) |
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506 | return ENXIO; |
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507 | return -100; |
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508 | } |
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509 | |
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510 | static int |
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511 | legacy_pcib_attach(device_t dev) |
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512 | { |
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513 | #ifdef __HAVE_PIR |
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514 | device_t pir; |
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515 | #endif |
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516 | int bus; |
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517 | |
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518 | bus = pcib_get_bus(dev); |
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519 | #ifdef __HAVE_PIR |
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520 | /* |
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521 | * Look for a PCI BIOS interrupt routing table as that will be |
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522 | * our method of routing interrupts if we have one. |
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523 | */ |
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524 | if (pci_pir_probe(bus, 0)) { |
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525 | pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0); |
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526 | if (pir != NULL) |
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527 | device_probe_and_attach(pir); |
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528 | } |
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529 | #endif |
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530 | device_add_child(dev, "pci", bus); |
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531 | return bus_generic_attach(dev); |
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532 | } |
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533 | |
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534 | int |
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535 | legacy_pcib_read_ivar(device_t dev, device_t child, int which, |
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536 | uintptr_t *result) |
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537 | { |
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538 | |
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539 | switch (which) { |
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540 | case PCIB_IVAR_DOMAIN: |
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541 | *result = 0; |
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542 | return 0; |
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543 | case PCIB_IVAR_BUS: |
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544 | *result = legacy_get_pcibus(dev); |
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545 | return 0; |
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546 | } |
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547 | return ENOENT; |
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548 | } |
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549 | |
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550 | int |
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551 | legacy_pcib_write_ivar(device_t dev, device_t child, int which, |
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552 | uintptr_t value) |
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553 | { |
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554 | |
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555 | switch (which) { |
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556 | case PCIB_IVAR_DOMAIN: |
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557 | return EINVAL; |
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558 | case PCIB_IVAR_BUS: |
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559 | legacy_set_pcibus(dev, value); |
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560 | return 0; |
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561 | } |
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562 | return ENOENT; |
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563 | } |
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564 | |
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565 | /* |
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566 | * Helper routine for x86 Host-PCI bridge driver resource allocation. |
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567 | * This is used to adjust the start address of wildcard allocation |
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568 | * requests to avoid low addresses that are known to be problematic. |
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569 | * |
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570 | * If no memory preference is given, use upper 32MB slot most BIOSes |
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571 | * use for their memory window. This is typically only used on older |
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572 | * laptops that don't have PCI busses behind a PCI bridge, so assuming |
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573 | * > 32MB is likely OK. |
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574 | * |
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575 | * However, this can cause problems for other chipsets, so we make |
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576 | * this tunable by hw.pci.host_mem_start. |
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577 | */ |
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578 | SYSCTL_DECL(_hw_pci); |
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579 | |
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580 | static unsigned long host_mem_start = 0x80000000; |
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581 | TUNABLE_ULONG("hw.pci.host_mem_start", &host_mem_start); |
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582 | SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN, &host_mem_start, |
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583 | 0, "Limit the host bridge memory to being above this address."); |
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584 | |
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585 | u_long |
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586 | hostb_alloc_start(int type, u_long start, u_long end, u_long count) |
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587 | { |
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588 | |
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589 | if (start + count - 1 != end) { |
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590 | if (type == SYS_RES_MEMORY && start < host_mem_start) |
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591 | start = host_mem_start; |
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592 | if (type == SYS_RES_IOPORT && start < 0x1000) |
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593 | start = 0x1000; |
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594 | } |
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595 | return (start); |
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596 | } |
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597 | |
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598 | struct resource * |
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599 | legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, |
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600 | u_long start, u_long end, u_long count, u_int flags) |
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601 | { |
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602 | |
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603 | start = hostb_alloc_start(type, start, end, count); |
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604 | return (bus_generic_alloc_resource(dev, child, type, rid, start, end, |
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605 | count, flags)); |
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606 | } |
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607 | |
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608 | static device_method_t legacy_pcib_methods[] = { |
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609 | /* Device interface */ |
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610 | DEVMETHOD(device_identify, legacy_pcib_identify), |
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611 | DEVMETHOD(device_probe, legacy_pcib_probe), |
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612 | DEVMETHOD(device_attach, legacy_pcib_attach), |
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613 | DEVMETHOD(device_shutdown, bus_generic_shutdown), |
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614 | DEVMETHOD(device_suspend, bus_generic_suspend), |
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615 | DEVMETHOD(device_resume, bus_generic_resume), |
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616 | |
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617 | /* Bus interface */ |
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618 | DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar), |
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619 | DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar), |
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620 | DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource), |
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621 | DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), |
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622 | DEVMETHOD(bus_release_resource, bus_generic_release_resource), |
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623 | DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), |
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624 | DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), |
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625 | DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), |
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626 | DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), |
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627 | |
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628 | /* pcib interface */ |
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629 | DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots), |
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630 | DEVMETHOD(pcib_read_config, legacy_pcib_read_config), |
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631 | DEVMETHOD(pcib_write_config, legacy_pcib_write_config), |
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632 | DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt), |
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633 | DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi), |
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634 | DEVMETHOD(pcib_release_msi, pcib_release_msi), |
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635 | DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix), |
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636 | DEVMETHOD(pcib_release_msix, pcib_release_msix), |
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637 | DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi), |
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638 | |
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639 | DEVMETHOD_END |
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640 | }; |
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641 | |
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642 | static devclass_t hostb_devclass; |
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643 | |
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644 | DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1); |
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645 | DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0); |
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646 | |
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647 | |
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648 | /* |
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649 | * Install placeholder to claim the resources owned by the |
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650 | * PCI bus interface. This could be used to extract the |
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651 | * config space registers in the extreme case where the PnP |
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652 | * ID is available and the PCI BIOS isn't, but for now we just |
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653 | * eat the PnP ID and do nothing else. |
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654 | * |
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655 | * XXX we should silence this probe, as it will generally confuse |
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656 | * people. |
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657 | */ |
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658 | static struct isa_pnp_id pcibus_pnp_ids[] = { |
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659 | { 0x030ad041 /* PNP0A03 */, "PCI Bus" }, |
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660 | { 0x080ad041 /* PNP0A08 */, "PCIe Bus" }, |
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661 | { 0 } |
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662 | }; |
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663 | |
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664 | static int |
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665 | pcibus_pnp_probe(device_t dev) |
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666 | { |
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667 | int result; |
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668 | |
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669 | if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0) |
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670 | device_quiet(dev); |
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671 | return(result); |
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672 | } |
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673 | |
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674 | static int |
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675 | pcibus_pnp_attach(device_t dev) |
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676 | { |
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677 | return(0); |
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678 | } |
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679 | |
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680 | static device_method_t pcibus_pnp_methods[] = { |
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681 | /* Device interface */ |
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682 | DEVMETHOD(device_probe, pcibus_pnp_probe), |
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683 | DEVMETHOD(device_attach, pcibus_pnp_attach), |
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684 | DEVMETHOD(device_detach, bus_generic_detach), |
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685 | DEVMETHOD(device_shutdown, bus_generic_shutdown), |
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686 | DEVMETHOD(device_suspend, bus_generic_suspend), |
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687 | DEVMETHOD(device_resume, bus_generic_resume), |
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688 | { 0, 0 } |
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689 | }; |
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690 | |
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691 | static devclass_t pcibus_pnp_devclass; |
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692 | |
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693 | DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1); |
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694 | DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0); |
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695 | |
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696 | #ifdef __HAVE_PIR |
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697 | /* |
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698 | * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges |
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699 | * that appear in the PCIBIOS Interrupt Routing Table to use the routing |
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700 | * table for interrupt routing when possible. |
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701 | */ |
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702 | static int pcibios_pcib_probe(device_t bus); |
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703 | |
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704 | static device_method_t pcibios_pcib_pci_methods[] = { |
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705 | /* Device interface */ |
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706 | DEVMETHOD(device_probe, pcibios_pcib_probe), |
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707 | |
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708 | /* pcib interface */ |
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709 | DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt), |
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710 | |
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711 | {0, 0} |
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712 | }; |
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713 | |
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714 | static devclass_t pcib_devclass; |
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715 | |
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716 | DEFINE_CLASS_1(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods, |
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717 | sizeof(struct pcib_softc), pcib_driver); |
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718 | DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0); |
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719 | |
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720 | static int |
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721 | pcibios_pcib_probe(device_t dev) |
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722 | { |
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723 | int bus; |
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724 | |
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725 | if ((pci_get_class(dev) != PCIC_BRIDGE) || |
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726 | (pci_get_subclass(dev) != PCIS_BRIDGE_PCI)) |
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727 | return (ENXIO); |
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728 | bus = pci_read_config(dev, PCIR_SECBUS_1, 1); |
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729 | if (bus == 0) |
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730 | return (ENXIO); |
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731 | if (!pci_pir_probe(bus, 1)) |
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732 | return (ENXIO); |
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733 | device_set_desc(dev, "PCIBIOS PCI-PCI bridge"); |
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734 | return (-2000); |
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735 | } |
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736 | #endif |
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