source: rtems-libbsd/freebsd/sys/sh/pci/pci_bus.c @ 66659ff

4.1155-freebsd-126-freebsd-12freebsd-9.3
Last change on this file since 66659ff was 66659ff, checked in by Sebastian Huber <sebastian.huber@…>, on 11/06/13 at 15:20:21

Update to FreeBSD 9.2

  • Property mode set to 100644
File size: 19.0 KB
Line 
1#include <machine/rtems-bsd-kernel-space.h>
2
3/*-
4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice unmodified, this list of conditions, and the following
12 *    disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD$");
31
32#include <rtems/bsd/local/opt_cpu.h>
33
34#include <rtems/bsd/sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/kernel.h>
38#include <sys/malloc.h>
39#include <sys/module.h>
40#include <sys/rman.h>
41#include <sys/sysctl.h>
42
43#include <dev/pci/pcivar.h>
44#include <dev/pci/pcireg.h>
45#include <dev/pci/pcib_private.h>
46#include <isa/isavar.h>
47#ifdef CPU_ELAN
48#include <machine/md_var.h>
49#endif
50#include <machine/legacyvar.h>
51#include <machine/pci_cfgreg.h>
52#include <machine/resource.h>
53
54#include <rtems/bsd/local/pcib_if.h>
55
56int
57legacy_pcib_maxslots(device_t dev)
58{
59        return 31;
60}
61
62/* read configuration space register */
63
64uint32_t
65legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
66                        u_int reg, int bytes)
67{
68        return(pci_cfgregread(bus, slot, func, reg, bytes));
69}
70
71/* write configuration space register */
72
73void
74legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
75                         u_int reg, uint32_t data, int bytes)
76{
77        pci_cfgregwrite(bus, slot, func, reg, data, bytes);
78}
79
80/* route interrupt */
81
82static int
83legacy_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
84{
85
86#ifdef __HAVE_PIR
87        return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
88            pci_get_function(dev), pin));
89#else
90        /* No routing possible */
91        return (PCI_INVALID_IRQ);
92#endif
93}
94
95/* Pass MSI requests up to the nexus. */
96
97static int
98legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
99    int *irqs)
100{
101        device_t bus;
102
103        bus = device_get_parent(pcib);
104        return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
105            irqs));
106}
107
108static int
109legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
110{
111        device_t bus;
112
113        bus = device_get_parent(pcib);
114        return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
115}
116
117int
118legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
119    uint32_t *data)
120{
121        device_t bus, hostb;
122        int error, func, slot;
123
124        bus = device_get_parent(pcib);
125        error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
126        if (error)
127                return (error);
128
129        slot = legacy_get_pcislot(pcib);
130        func = legacy_get_pcifunc(pcib);
131        if (slot == -1 || func == -1)
132                return (0);
133        hostb = pci_find_bsf(0, slot, func);
134        KASSERT(hostb != NULL, ("%s: missing hostb for 0:%d:%d", __func__,
135            slot, func));
136        pci_ht_map_msi(hostb, *addr);
137        return (0);
138       
139}
140
141static const char *
142legacy_pcib_is_host_bridge(int bus, int slot, int func,
143                          uint32_t id, uint8_t class, uint8_t subclass,
144                          uint8_t *busnum)
145{
146#ifdef __i386__
147        const char *s = NULL;
148        static uint8_t pxb[4];  /* hack for 450nx */
149
150        *busnum = 0;
151
152        switch (id) {
153        case 0x12258086:
154                s = "Intel 824?? host to PCI bridge";
155                /* XXX This is a guess */
156                /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
157                *busnum = bus;
158                break;
159        case 0x71208086:
160                s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
161                break;
162        case 0x71228086:
163                s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
164                break;
165        case 0x71248086:
166                s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
167                break;
168        case 0x11308086:
169                s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
170                break;
171        case 0x71808086:
172                s = "Intel 82443LX (440 LX) host to PCI bridge";
173                break;
174        case 0x71908086:
175                s = "Intel 82443BX (440 BX) host to PCI bridge";
176                break;
177        case 0x71928086:
178                s = "Intel 82443BX host to PCI bridge (AGP disabled)";
179                break;
180        case 0x71948086:
181                s = "Intel 82443MX host to PCI bridge";
182                break;
183        case 0x71a08086:
184                s = "Intel 82443GX host to PCI bridge";
185                break;
186        case 0x71a18086:
187                s = "Intel 82443GX host to AGP bridge";
188                break;
189        case 0x71a28086:
190                s = "Intel 82443GX host to PCI bridge (AGP disabled)";
191                break;
192        case 0x84c48086:
193                s = "Intel 82454KX/GX (Orion) host to PCI bridge";
194                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
195                break;
196        case 0x84ca8086:
197                /*
198                 * For the 450nx chipset, there is a whole bundle of
199                 * things pretending to be host bridges. The MIOC will
200                 * be seen first and isn't really a pci bridge (the
201                 * actual busses are attached to the PXB's). We need to
202                 * read the registers of the MIOC to figure out the
203                 * bus numbers for the PXB channels.
204                 *
205                 * Since the MIOC doesn't have a pci bus attached, we
206                 * pretend it wasn't there.
207                 */
208                pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
209                                                0xd0, 1); /* BUSNO[0] */
210                pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
211                                                0xd1, 1) + 1;   /* SUBA[0]+1 */
212                pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
213                                                0xd3, 1); /* BUSNO[1] */
214                pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
215                                                0xd4, 1) + 1;   /* SUBA[1]+1 */
216                return NULL;
217        case 0x84cb8086:
218                switch (slot) {
219                case 0x12:
220                        s = "Intel 82454NX PXB#0, Bus#A";
221                        *busnum = pxb[0];
222                        break;
223                case 0x13:
224                        s = "Intel 82454NX PXB#0, Bus#B";
225                        *busnum = pxb[1];
226                        break;
227                case 0x14:
228                        s = "Intel 82454NX PXB#1, Bus#A";
229                        *busnum = pxb[2];
230                        break;
231                case 0x15:
232                        s = "Intel 82454NX PXB#1, Bus#B";
233                        *busnum = pxb[3];
234                        break;
235                }
236                break;
237        case 0x1A308086:
238                s = "Intel 82845 Host to PCI bridge";
239                break;
240
241                /* AMD -- vendor 0x1022 */
242        case 0x30001022:
243                s = "AMD Elan SC520 host to PCI bridge";
244#ifdef CPU_ELAN
245                init_AMD_Elan_sc520();
246#else
247                printf(
248"*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
249#endif
250                break;
251        case 0x70061022:
252                s = "AMD-751 host to PCI bridge";
253                break;
254        case 0x700e1022:
255                s = "AMD-761 host to PCI bridge";
256                break;
257
258                /* SiS -- vendor 0x1039 */
259        case 0x04961039:
260                s = "SiS 85c496";
261                break;
262        case 0x04061039:
263                s = "SiS 85c501";
264                break;
265        case 0x06011039:
266                s = "SiS 85c601";
267                break;
268        case 0x55911039:
269                s = "SiS 5591 host to PCI bridge";
270                break;
271        case 0x00011039:
272                s = "SiS 5591 host to AGP bridge";
273                break;
274
275                /* VLSI -- vendor 0x1004 */
276        case 0x00051004:
277                s = "VLSI 82C592 Host to PCI bridge";
278                break;
279
280                /* XXX Here is MVP3, I got the datasheet but NO M/B to test it  */
281                /* totally. Please let me know if anything wrong.            -F */
282                /* XXX need info on the MVP3 -- any takers? */
283        case 0x05981106:
284                s = "VIA 82C598MVP (Apollo MVP3) host bridge";
285                break;
286
287                /* AcerLabs -- vendor 0x10b9 */
288                /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
289                /* id is '10b9" but the register always shows "10b9". -Foxfair  */
290        case 0x154110b9:
291                s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
292                break;
293
294                /* OPTi -- vendor 0x1045 */
295        case 0xc7011045:
296                s = "OPTi 82C700 host to PCI bridge";
297                break;
298        case 0xc8221045:
299                s = "OPTi 82C822 host to PCI Bridge";
300                break;
301
302                /* ServerWorks -- vendor 0x1166 */
303        case 0x00051166:
304                s = "ServerWorks NB6536 2.0HE host to PCI bridge";
305                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
306                break;
307
308        case 0x00061166:
309                /* FALLTHROUGH */
310        case 0x00081166:
311                /* FALLTHROUGH */
312        case 0x02011166:
313                /* FALLTHROUGH */
314        case 0x010f1014: /* IBM re-badged ServerWorks chipset */
315                s = "ServerWorks host to PCI bridge";
316                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
317                break;
318
319        case 0x00091166:
320                s = "ServerWorks NB6635 3.0LE host to PCI bridge";
321                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
322                break;
323
324        case 0x00101166:
325                s = "ServerWorks CIOB30 host to PCI bridge";
326                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
327                break;
328
329        case 0x00111166:
330                /* FALLTHROUGH */
331        case 0x03021014: /* IBM re-badged ServerWorks chipset */
332                s = "ServerWorks CMIC-HE host to PCI-X bridge";
333                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
334                break;
335
336                /* XXX unknown chipset, but working */
337        case 0x00171166:
338                /* FALLTHROUGH */
339        case 0x01011166:
340        case 0x01101166:
341        case 0x02251166:
342                s = "ServerWorks host to PCI bridge(unknown chipset)";
343                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
344                break;
345
346                /* Compaq/HP -- vendor 0x0e11 */
347        case 0x60100e11:
348                s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
349                *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
350                break;
351
352                /* Integrated Micro Solutions -- vendor 0x10e0 */
353        case 0x884910e0:
354                s = "Integrated Micro Solutions VL Bridge";
355                break;
356
357        default:
358                if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
359                        s = "Host to PCI bridge";
360                break;
361        }
362
363        return s;
364#else
365        const char *s = NULL;
366
367        *busnum = 0;
368        if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
369                s = "Host to PCI bridge";
370        return s;
371#endif
372}
373
374/*
375 * Scan the first pci bus for host-pci bridges and add pcib instances
376 * to the nexus for each bridge.
377 */
378static void
379legacy_pcib_identify(driver_t *driver, device_t parent)
380{
381        int bus, slot, func;
382        uint8_t  hdrtype;
383        int found = 0;
384        int pcifunchigh;
385        int found824xx = 0;
386        int found_orion = 0;
387        device_t child;
388        devclass_t pci_devclass;
389
390        if (pci_cfgregopen() == 0)
391                return;
392        /*
393         * Check to see if we haven't already had a PCI bus added
394         * via some other means.  If we have, bail since otherwise
395         * we're going to end up duplicating it.
396         */
397        if ((pci_devclass = devclass_find("pci")) &&
398                devclass_get_device(pci_devclass, 0))
399                return;
400
401
402        bus = 0;
403 retry:
404        for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
405                func = 0;
406                hdrtype = legacy_pcib_read_config(0, bus, slot, func,
407                                                 PCIR_HDRTYPE, 1);
408                /*
409                 * When enumerating bus devices, the standard says that
410                 * one should check the header type and ignore the slots whose
411                 * header types that the software doesn't know about.  We use
412                 * this to filter out devices.
413                 */
414                if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
415                        continue;
416                if ((hdrtype & PCIM_MFDEV) &&
417                    (!found_orion || hdrtype != 0xff))
418                        pcifunchigh = PCI_FUNCMAX;
419                else
420                        pcifunchigh = 0;
421                for (func = 0; func <= pcifunchigh; func++) {
422                        /*
423                         * Read the IDs and class from the device.
424                         */
425                        uint32_t id;
426                        uint8_t class, subclass, busnum;
427                        const char *s;
428                        device_t *devs;
429                        int ndevs, i;
430
431                        id = legacy_pcib_read_config(0, bus, slot, func,
432                                                    PCIR_DEVVENDOR, 4);
433                        if (id == -1)
434                                continue;
435                        class = legacy_pcib_read_config(0, bus, slot, func,
436                                                       PCIR_CLASS, 1);
437                        subclass = legacy_pcib_read_config(0, bus, slot, func,
438                                                          PCIR_SUBCLASS, 1);
439
440                        s = legacy_pcib_is_host_bridge(bus, slot, func,
441                                                      id, class, subclass,
442                                                      &busnum);
443                        if (s == NULL)
444                                continue;
445
446                        /*
447                         * Check to see if the physical bus has already
448                         * been seen.  Eg: hybrid 32 and 64 bit host
449                         * bridges to the same logical bus.
450                         */
451                        if (device_get_children(parent, &devs, &ndevs) == 0) {
452                                for (i = 0; s != NULL && i < ndevs; i++) {
453                                        if (strcmp(device_get_name(devs[i]),
454                                            "pcib") != 0)
455                                                continue;
456                                        if (legacy_get_pcibus(devs[i]) == busnum)
457                                                s = NULL;
458                                }
459                                free(devs, M_TEMP);
460                        }
461
462                        if (s == NULL)
463                                continue;
464                        /*
465                         * Add at priority 100 to make sure we
466                         * go after any motherboard resources
467                         */
468                        child = BUS_ADD_CHILD(parent, 100,
469                                              "pcib", busnum);
470                        device_set_desc(child, s);
471                        legacy_set_pcibus(child, busnum);
472                        legacy_set_pcislot(child, slot);
473                        legacy_set_pcifunc(child, func);
474
475                        found = 1;
476                        if (id == 0x12258086)
477                                found824xx = 1;
478                        if (id == 0x84c48086)
479                                found_orion = 1;
480                }
481        }
482        if (found824xx && bus == 0) {
483                bus++;
484                goto retry;
485        }
486
487        /*
488         * Make sure we add at least one bridge since some old
489         * hardware doesn't actually have a host-pci bridge device.
490         * Note that pci_cfgregopen() thinks we have PCI devices..
491         */
492        if (!found) {
493                if (bootverbose)
494                        printf(
495        "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
496                child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
497                legacy_set_pcibus(child, 0);
498        }
499}
500
501static int
502legacy_pcib_probe(device_t dev)
503{
504
505        if (pci_cfgregopen() == 0)
506                return ENXIO;
507        return -100;
508}
509
510static int
511legacy_pcib_attach(device_t dev)
512{
513#ifdef __HAVE_PIR
514        device_t pir;
515#endif
516        int bus;
517
518        bus = pcib_get_bus(dev);
519#ifdef __HAVE_PIR
520        /*
521         * Look for a PCI BIOS interrupt routing table as that will be
522         * our method of routing interrupts if we have one.
523         */
524        if (pci_pir_probe(bus, 0)) {
525                pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
526                if (pir != NULL)
527                        device_probe_and_attach(pir);
528        }
529#endif
530        device_add_child(dev, "pci", bus);
531        return bus_generic_attach(dev);
532}
533
534int
535legacy_pcib_read_ivar(device_t dev, device_t child, int which,
536    uintptr_t *result)
537{
538
539        switch (which) {
540        case  PCIB_IVAR_DOMAIN:
541                *result = 0;
542                return 0;
543        case  PCIB_IVAR_BUS:
544                *result = legacy_get_pcibus(dev);
545                return 0;
546        }
547        return ENOENT;
548}
549
550int
551legacy_pcib_write_ivar(device_t dev, device_t child, int which,
552    uintptr_t value)
553{
554
555        switch (which) {
556        case  PCIB_IVAR_DOMAIN:
557                return EINVAL;
558        case  PCIB_IVAR_BUS:
559                legacy_set_pcibus(dev, value);
560                return 0;
561        }
562        return ENOENT;
563}
564
565/*
566 * Helper routine for x86 Host-PCI bridge driver resource allocation.
567 * This is used to adjust the start address of wildcard allocation
568 * requests to avoid low addresses that are known to be problematic.
569 *
570 * If no memory preference is given, use upper 32MB slot most BIOSes
571 * use for their memory window.  This is typically only used on older
572 * laptops that don't have PCI busses behind a PCI bridge, so assuming
573 * > 32MB is likely OK.
574 *     
575 * However, this can cause problems for other chipsets, so we make
576 * this tunable by hw.pci.host_mem_start.
577 */
578SYSCTL_DECL(_hw_pci);
579
580static unsigned long host_mem_start = 0x80000000;
581TUNABLE_ULONG("hw.pci.host_mem_start", &host_mem_start);
582SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN, &host_mem_start,
583    0, "Limit the host bridge memory to being above this address.");
584
585u_long
586hostb_alloc_start(int type, u_long start, u_long end, u_long count)
587{
588
589        if (start + count - 1 != end) {
590                if (type == SYS_RES_MEMORY && start < host_mem_start)
591                        start = host_mem_start;
592                if (type == SYS_RES_IOPORT && start < 0x1000)
593                        start = 0x1000;
594        }
595        return (start);
596}
597
598struct resource *
599legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
600    u_long start, u_long end, u_long count, u_int flags)
601{
602
603    start = hostb_alloc_start(type, start, end, count);
604    return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
605        count, flags));
606}
607
608static device_method_t legacy_pcib_methods[] = {
609        /* Device interface */
610        DEVMETHOD(device_identify,      legacy_pcib_identify),
611        DEVMETHOD(device_probe,         legacy_pcib_probe),
612        DEVMETHOD(device_attach,        legacy_pcib_attach),
613        DEVMETHOD(device_shutdown,      bus_generic_shutdown),
614        DEVMETHOD(device_suspend,       bus_generic_suspend),
615        DEVMETHOD(device_resume,        bus_generic_resume),
616
617        /* Bus interface */
618        DEVMETHOD(bus_read_ivar,        legacy_pcib_read_ivar),
619        DEVMETHOD(bus_write_ivar,       legacy_pcib_write_ivar),
620        DEVMETHOD(bus_alloc_resource,   legacy_pcib_alloc_resource),
621        DEVMETHOD(bus_adjust_resource,  bus_generic_adjust_resource),
622        DEVMETHOD(bus_release_resource, bus_generic_release_resource),
623        DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
624        DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
625        DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
626        DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
627
628        /* pcib interface */
629        DEVMETHOD(pcib_maxslots,        legacy_pcib_maxslots),
630        DEVMETHOD(pcib_read_config,     legacy_pcib_read_config),
631        DEVMETHOD(pcib_write_config,    legacy_pcib_write_config),
632        DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
633        DEVMETHOD(pcib_alloc_msi,       legacy_pcib_alloc_msi),
634        DEVMETHOD(pcib_release_msi,     pcib_release_msi),
635        DEVMETHOD(pcib_alloc_msix,      legacy_pcib_alloc_msix),
636        DEVMETHOD(pcib_release_msix,    pcib_release_msix),
637        DEVMETHOD(pcib_map_msi,         legacy_pcib_map_msi),
638
639        DEVMETHOD_END
640};
641
642static devclass_t hostb_devclass;
643
644DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
645DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
646
647
648/*
649 * Install placeholder to claim the resources owned by the
650 * PCI bus interface.  This could be used to extract the
651 * config space registers in the extreme case where the PnP
652 * ID is available and the PCI BIOS isn't, but for now we just
653 * eat the PnP ID and do nothing else.
654 *
655 * XXX we should silence this probe, as it will generally confuse
656 * people.
657 */
658static struct isa_pnp_id pcibus_pnp_ids[] = {
659        { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
660        { 0x080ad041 /* PNP0A08 */, "PCIe Bus" },
661        { 0 }
662};
663
664static int
665pcibus_pnp_probe(device_t dev)
666{
667        int result;
668
669        if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
670                device_quiet(dev);
671        return(result);
672}
673
674static int
675pcibus_pnp_attach(device_t dev)
676{
677        return(0);
678}
679
680static device_method_t pcibus_pnp_methods[] = {
681        /* Device interface */
682        DEVMETHOD(device_probe,         pcibus_pnp_probe),
683        DEVMETHOD(device_attach,        pcibus_pnp_attach),
684        DEVMETHOD(device_detach,        bus_generic_detach),
685        DEVMETHOD(device_shutdown,      bus_generic_shutdown),
686        DEVMETHOD(device_suspend,       bus_generic_suspend),
687        DEVMETHOD(device_resume,        bus_generic_resume),
688        { 0, 0 }
689};
690
691static devclass_t pcibus_pnp_devclass;
692
693DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
694DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
695
696#ifdef __HAVE_PIR
697/*
698 * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
699 * that appear in the PCIBIOS Interrupt Routing Table to use the routing
700 * table for interrupt routing when possible.
701 */
702static int      pcibios_pcib_probe(device_t bus);
703
704static device_method_t pcibios_pcib_pci_methods[] = {
705        /* Device interface */
706        DEVMETHOD(device_probe,         pcibios_pcib_probe),
707
708        /* pcib interface */
709        DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
710
711        {0, 0}
712};
713
714static devclass_t pcib_devclass;
715
716DEFINE_CLASS_1(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
717    sizeof(struct pcib_softc), pcib_driver);
718DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
719
720static int
721pcibios_pcib_probe(device_t dev)
722{
723        int bus;
724
725        if ((pci_get_class(dev) != PCIC_BRIDGE) ||
726            (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
727                return (ENXIO);
728        bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
729        if (bus == 0)
730                return (ENXIO);
731        if (!pci_pir_probe(bus, 1))
732                return (ENXIO);
733        device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
734        return (-2000);
735}
736#endif
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