| 1 | /*- |
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| 2 | * Copyright (c) 2001 The NetBSD Foundation, Inc. |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * 1. Redistributions of source code must retain the above copyright |
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| 9 | * notice, this list of conditions and the following disclaimer. |
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| 10 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 11 | * notice, this list of conditions and the following disclaimer in the |
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| 12 | * documentation and/or other materials provided with the distribution. |
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| 13 | * 3. All advertising materials mentioning features or use of this software |
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| 14 | * must display the following acknowledgement: |
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| 15 | * This product includes software developed by the NetBSD |
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| 16 | * Foundation, Inc. and its contributors. |
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| 17 | * 4. Neither the name of The NetBSD Foundation nor the names of its |
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| 18 | * contributors may be used to endorse or promote products derived |
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| 19 | * from this software without specific prior written permission. |
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| 20 | * |
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| 21 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
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| 22 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
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| 23 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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| 24 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
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| 25 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 31 | * POSSIBILITY OF SUCH DAMAGE. |
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| 32 | * |
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| 33 | * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ |
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| 34 | * $FreeBSD$ |
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| 35 | */ |
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| 36 | #ifndef _POWERPC_SPR_H_ |
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| 37 | #define _POWERPC_SPR_H_ |
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| 38 | |
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| 39 | #ifndef _LOCORE |
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| 40 | #define mtspr(reg, val) \ |
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| 41 | __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) |
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| 42 | #define mfspr(reg) \ |
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| 43 | ( { register_t val; \ |
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| 44 | __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ |
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| 45 | val; } ) |
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| 46 | |
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| 47 | /* The following routines allow manipulation of the full 64-bit width |
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| 48 | * of SPRs on 64 bit CPUs in bridge mode */ |
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| 49 | |
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| 50 | #define mtspr64(reg,valhi,vallo,scratch) \ |
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| 51 | __asm __volatile(" \ |
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| 52 | mfmsr %0; \ |
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| 53 | insrdi %0,%5,1,0; \ |
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| 54 | mtmsrd %0; \ |
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| 55 | isync; \ |
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| 56 | \ |
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| 57 | sld %1,%1,%4; \ |
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| 58 | or %1,%1,%2; \ |
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| 59 | mtspr %3,%1; \ |
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| 60 | srd %1,%1,%4; \ |
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| 61 | \ |
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| 62 | clrldi %0,%0,1; \ |
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| 63 | mtmsrd %0; \ |
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| 64 | isync;" \ |
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| 65 | : "=r"(scratch), "=r"(valhi) : "r"(vallo), "K"(reg), "r"(32), "r"(1)) |
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| 66 | |
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| 67 | #define mfspr64upper(reg,scratch) \ |
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| 68 | ( { register_t val; \ |
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| 69 | __asm __volatile(" \ |
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| 70 | mfmsr %0; \ |
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| 71 | insrdi %0,%4,1,0; \ |
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| 72 | mtmsrd %0; \ |
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| 73 | isync; \ |
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| 74 | \ |
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| 75 | mfspr %1,%2; \ |
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| 76 | srd %1,%1,%3; \ |
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| 77 | \ |
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| 78 | clrldi %0,%0,1; \ |
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| 79 | mtmsrd %0; \ |
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| 80 | isync;" \ |
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| 81 | : "=r"(scratch), "=r"(val) : "K"(reg), "r"(32), "r"(1)); \ |
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| 82 | val; } ) |
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| 83 | |
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| 84 | #endif /* _LOCORE */ |
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| 85 | |
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| 86 | /* |
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| 87 | * Special Purpose Register declarations. |
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| 88 | * |
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| 89 | * The first column in the comments indicates which PowerPC |
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| 90 | * architectures the SPR is valid on - 4 for 4xx series, |
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| 91 | * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series. |
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| 92 | */ |
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| 93 | |
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| 94 | #define SPR_MQ 0x000 /* .6. 601 MQ register */ |
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| 95 | #define SPR_XER 0x001 /* 468 Fixed Point Exception Register */ |
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| 96 | #define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */ |
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| 97 | #define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */ |
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| 98 | #define SPR_LR 0x008 /* 468 Link Register */ |
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| 99 | #define SPR_CTR 0x009 /* 468 Count Register */ |
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| 100 | #define SPR_DSISR 0x012 /* .68 DSI exception source */ |
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| 101 | #define DSISR_DIRECT 0x80000000 /* Direct-store error exception */ |
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| 102 | #define DSISR_NOTFOUND 0x40000000 /* Translation not found */ |
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| 103 | #define DSISR_PROTECT 0x08000000 /* Memory access not permitted */ |
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| 104 | #define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */ |
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| 105 | #define DSISR_STORE 0x02000000 /* Store operation */ |
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| 106 | #define DSISR_DABR 0x00400000 /* DABR match */ |
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| 107 | #define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */ |
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| 108 | #define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */ |
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| 109 | #define SPR_DAR 0x013 /* .68 Data Address Register */ |
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| 110 | #define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */ |
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| 111 | #define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */ |
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| 112 | #define SPR_DEC 0x016 /* .68 DECrementer register */ |
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| 113 | #define SPR_SDR1 0x019 /* .68 Page table base address register */ |
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| 114 | #define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */ |
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| 115 | #define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */ |
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| 116 | #define SPR_DECAR 0x036 /* ..8 Decrementer auto reload */ |
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| 117 | #define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */ |
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| 118 | #define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */ |
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| 119 | #define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */ |
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| 120 | #define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */ |
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| 121 | #define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */ |
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| 122 | #define SPR_SPRG0 0x110 /* 468 SPR General 0 */ |
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| 123 | #define SPR_SPRG1 0x111 /* 468 SPR General 1 */ |
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| 124 | #define SPR_SPRG2 0x112 /* 468 SPR General 2 */ |
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| 125 | #define SPR_SPRG3 0x113 /* 468 SPR General 3 */ |
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| 126 | #define SPR_SPRG4 0x114 /* 4.. SPR General 4 */ |
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| 127 | #define SPR_SPRG5 0x115 /* 4.. SPR General 5 */ |
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| 128 | #define SPR_SPRG6 0x116 /* 4.. SPR General 6 */ |
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| 129 | #define SPR_SPRG7 0x117 /* 4.. SPR General 7 */ |
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| 130 | #define SPR_SCOMC 0x114 /* ... SCOM Address Register (970) */ |
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| 131 | #define SPR_SCOMD 0x115 /* ... SCOM Data Register (970) */ |
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| 132 | #define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */ |
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| 133 | #define SPR_EAR 0x11a /* .68 External Access Register */ |
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| 134 | #define SPR_PVR 0x11f /* 468 Processor Version Register */ |
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| 135 | #define MPC601 0x0001 |
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| 136 | #define MPC603 0x0003 |
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| 137 | #define MPC604 0x0004 |
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| 138 | #define MPC602 0x0005 |
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| 139 | #define MPC603e 0x0006 |
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| 140 | #define MPC603ev 0x0007 |
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| 141 | #define MPC750 0x0008 |
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| 142 | #define MPC604ev 0x0009 |
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| 143 | #define MPC7400 0x000c |
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| 144 | #define MPC620 0x0014 |
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| 145 | #define IBM403 0x0020 |
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| 146 | #define IBM401A1 0x0021 |
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| 147 | #define IBM401B2 0x0022 |
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| 148 | #define IBM401C2 0x0023 |
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| 149 | #define IBM401D2 0x0024 |
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| 150 | #define IBM401E2 0x0025 |
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| 151 | #define IBM401F2 0x0026 |
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| 152 | #define IBM401G2 0x0027 |
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| 153 | #define IBM970 0x0039 |
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| 154 | #define IBM970FX 0x003c |
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| 155 | #define IBMPOWER3 0x0041 |
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| 156 | #define IBM970MP 0x0044 |
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| 157 | #define IBM970GX 0x0045 |
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| 158 | #define MPC860 0x0050 |
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| 159 | #define MPC8240 0x0081 |
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| 160 | #define IBM405GP 0x4011 |
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| 161 | #define IBM405L 0x4161 |
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| 162 | #define IBM750FX 0x7000 |
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| 163 | #define MPC745X_P(v) ((v & 0xFFF8) == 0x8000) |
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| 164 | #define MPC7450 0x8000 |
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| 165 | #define MPC7455 0x8001 |
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| 166 | #define MPC7457 0x8002 |
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| 167 | #define MPC7447A 0x8003 |
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| 168 | #define MPC7448 0x8004 |
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| 169 | #define MPC7410 0x800c |
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| 170 | #define MPC8245 0x8081 |
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| 171 | #define FSL_E500v1 0x8020 |
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| 172 | #define FSL_E500v2 0x8021 |
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| 173 | |
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| 174 | #define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */ |
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| 175 | #define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */ |
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| 176 | #define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */ |
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| 177 | #define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */ |
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| 178 | #define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */ |
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| 179 | #define SPR_IBAT2U 0x214 /* .6. Instruction BAT Reg 2 Upper */ |
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| 180 | #define SPR_IBAT2L 0x215 /* .6. Instruction BAT Reg 2 Lower */ |
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| 181 | #define SPR_IBAT3U 0x216 /* .6. Instruction BAT Reg 3 Upper */ |
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| 182 | #define SPR_IBAT3L 0x217 /* .6. Instruction BAT Reg 3 Lower */ |
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| 183 | #define SPR_DBAT0U 0x218 /* .6. Data BAT Reg 0 Upper */ |
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| 184 | #define SPR_DBAT0L 0x219 /* .6. Data BAT Reg 0 Lower */ |
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| 185 | #define SPR_DBAT1U 0x21a /* .6. Data BAT Reg 1 Upper */ |
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| 186 | #define SPR_DBAT1L 0x21b /* .6. Data BAT Reg 1 Lower */ |
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| 187 | #define SPR_DBAT2U 0x21c /* .6. Data BAT Reg 2 Upper */ |
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| 188 | #define SPR_DBAT2L 0x21d /* .6. Data BAT Reg 2 Lower */ |
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| 189 | #define SPR_DBAT3U 0x21e /* .6. Data BAT Reg 3 Upper */ |
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| 190 | #define SPR_DBAT3L 0x21f /* .6. Data BAT Reg 3 Lower */ |
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| 191 | #define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */ |
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| 192 | #define IC_CST_IEN 0x80000000 /* I cache is ENabled (RO) */ |
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| 193 | #define IC_CST_CMD_INVALL 0x0c000000 /* I cache invalidate all */ |
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| 194 | #define IC_CST_CMD_UNLOCKALL 0x0a000000 /* I cache unlock all */ |
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| 195 | #define IC_CST_CMD_UNLOCK 0x08000000 /* I cache unlock block */ |
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| 196 | #define IC_CST_CMD_LOADLOCK 0x06000000 /* I cache load & lock block */ |
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| 197 | #define IC_CST_CMD_DISABLE 0x04000000 /* I cache disable */ |
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| 198 | #define IC_CST_CMD_ENABLE 0x02000000 /* I cache enable */ |
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| 199 | #define IC_CST_CCER1 0x00200000 /* I cache error type 1 (RO) */ |
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| 200 | #define IC_CST_CCER2 0x00100000 /* I cache error type 2 (RO) */ |
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| 201 | #define IC_CST_CCER3 0x00080000 /* I cache error type 3 (RO) */ |
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| 202 | #define SPR_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */ |
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| 203 | #define SPR_IC_ADR 0x231 /* ..8 Instruction Cache Address */ |
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| 204 | #define SPR_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */ |
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| 205 | #define SPR_IC_DAT 0x232 /* ..8 Instruction Cache Data */ |
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| 206 | #define SPR_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */ |
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| 207 | #define SPR_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */ |
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| 208 | #define SPR_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */ |
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| 209 | #define SPR_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */ |
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| 210 | #define SPR_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */ |
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| 211 | #define SPR_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */ |
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| 212 | #define SPR_DC_CST 0x230 /* ..8 Data Cache CSR */ |
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| 213 | #define DC_CST_DEN 0x80000000 /* D cache ENabled (RO) */ |
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| 214 | #define DC_CST_DFWT 0x40000000 /* D cache Force Write-Thru (RO) */ |
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| 215 | #define DC_CST_LES 0x20000000 /* D cache Little Endian Swap (RO) */ |
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| 216 | #define DC_CST_CMD_FLUSH 0x0e000000 /* D cache invalidate all */ |
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| 217 | #define DC_CST_CMD_INVALL 0x0c000000 /* D cache invalidate all */ |
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| 218 | #define DC_CST_CMD_UNLOCKALL 0x0a000000 /* D cache unlock all */ |
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| 219 | #define DC_CST_CMD_UNLOCK 0x08000000 /* D cache unlock block */ |
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| 220 | #define DC_CST_CMD_CLRLESWAP 0x07000000 /* D cache clr little-endian swap */ |
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| 221 | #define DC_CST_CMD_LOADLOCK 0x06000000 /* D cache load & lock block */ |
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| 222 | #define DC_CST_CMD_SETLESWAP 0x05000000 /* D cache set little-endian swap */ |
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| 223 | #define DC_CST_CMD_DISABLE 0x04000000 /* D cache disable */ |
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| 224 | #define DC_CST_CMD_CLRFWT 0x03000000 /* D cache clear forced write-thru */ |
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| 225 | #define DC_CST_CMD_ENABLE 0x02000000 /* D cache enable */ |
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| 226 | #define DC_CST_CMD_SETFWT 0x01000000 /* D cache set forced write-thru */ |
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| 227 | #define DC_CST_CCER1 0x00200000 /* D cache error type 1 (RO) */ |
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| 228 | #define DC_CST_CCER2 0x00100000 /* D cache error type 2 (RO) */ |
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| 229 | #define DC_CST_CCER3 0x00080000 /* D cache error type 3 (RO) */ |
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| 230 | #define SPR_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */ |
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| 231 | #define SPR_DC_ADR 0x231 /* ..8 Data Cache Address */ |
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| 232 | #define SPR_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */ |
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| 233 | #define SPR_DC_DAT 0x232 /* ..8 Data Cache Data */ |
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| 234 | #define SPR_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */ |
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| 235 | #define SPR_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */ |
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| 236 | #define SPR_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */ |
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| 237 | #define SPR_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */ |
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| 238 | #define SPR_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */ |
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| 239 | #define SPR_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */ |
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| 240 | #define SPR_MI_CTR 0x310 /* ..8 IMMU control */ |
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| 241 | #define Mx_CTR_GPM 0x80000000 /* Group Protection Mode */ |
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| 242 | #define Mx_CTR_PPM 0x40000000 /* Page Protection Mode */ |
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| 243 | #define Mx_CTR_CIDEF 0x20000000 /* Cache-Inhibit DEFault */ |
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| 244 | #define MD_CTR_WTDEF 0x20000000 /* Write-Through DEFault */ |
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| 245 | #define Mx_CTR_RSV4 0x08000000 /* Reserve 4 TLB entries */ |
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| 246 | #define MD_CTR_TWAM 0x04000000 /* TableWalk Assist Mode */ |
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| 247 | #define Mx_CTR_PPCS 0x02000000 /* Priv/user state compare mode */ |
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| 248 | #define Mx_CTR_TLB_INDX 0x000001f0 /* TLB index mask */ |
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| 249 | #define Mx_CTR_TLB_INDX_BITPOS 8 /* TLB index shift */ |
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| 250 | #define SPR_MI_AP 0x312 /* ..8 IMMU access protection */ |
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| 251 | #define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) /* access is supervisor */ |
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| 252 | #define Mx_GP_PAGE (1 << (2*(15-(n)))) /* access is page protect */ |
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| 253 | #define Mx_GP_SWAPPED (2 << (2*(15-(n)))) /* access is swapped */ |
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| 254 | #define Mx_GP_USER (3 << (2*(15-(n)))) /* access is user */ |
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| 255 | #define SPR_MI_EPN 0x313 /* ..8 IMMU effective number */ |
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| 256 | #define Mx_EPN_EPN 0xfffff000 /* Effective Page Number mask */ |
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| 257 | #define Mx_EPN_EV 0x00000020 /* Entry Valid */ |
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| 258 | #define Mx_EPN_ASID 0x0000000f /* Address Space ID */ |
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| 259 | #define SPR_MI_TWC 0x315 /* ..8 IMMU tablewalk control */ |
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| 260 | #define MD_TWC_L2TB 0xfffff000 /* Level-2 Tablewalk Base */ |
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| 261 | #define Mx_TWC_APG 0x000001e0 /* Access Protection Group */ |
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| 262 | #define Mx_TWC_G 0x00000010 /* Guarded memory */ |
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| 263 | #define Mx_TWC_PS 0x0000000c /* Page Size (L1) */ |
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| 264 | #define MD_TWC_WT 0x00000002 /* Write-Through */ |
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| 265 | #define Mx_TWC_V 0x00000001 /* Entry Valid */ |
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| 266 | #define SPR_MI_RPN 0x316 /* ..8 IMMU real (phys) page number */ |
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| 267 | #define Mx_RPN_RPN 0xfffff000 /* Real Page Number */ |
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| 268 | #define Mx_RPN_PP 0x00000ff0 /* Page Protection */ |
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| 269 | #define Mx_RPN_SPS 0x00000008 /* Small Page Size */ |
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| 270 | #define Mx_RPN_SH 0x00000004 /* SHared page */ |
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| 271 | #define Mx_RPN_CI 0x00000002 /* Cache Inhibit */ |
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| 272 | #define Mx_RPN_V 0x00000001 /* Valid */ |
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| 273 | #define SPR_MD_CTR 0x318 /* ..8 DMMU control */ |
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| 274 | #define SPR_M_CASID 0x319 /* ..8 CASID */ |
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| 275 | #define M_CASID 0x0000000f /* Current AS Id */ |
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| 276 | #define SPR_MD_AP 0x31a /* ..8 DMMU access protection */ |
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| 277 | #define SPR_MD_EPN 0x31b /* ..8 DMMU effective number */ |
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| 278 | #define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */ |
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| 279 | #define M_TWB_L1TB 0xfffff000 /* level-1 translation base */ |
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| 280 | #define M_TWB_L1INDX 0x00000ffc /* level-1 index */ |
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| 281 | #define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */ |
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| 282 | #define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */ |
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| 283 | #define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */ |
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| 284 | #define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */ |
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| 285 | #define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */ |
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| 286 | #define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */ |
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| 287 | #define SPR_MD_CAM 0x338 /* ..8 IMMU CAM entry read */ |
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| 288 | #define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */ |
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| 289 | #define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */ |
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| 290 | #define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */ |
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| 291 | #define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */ |
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| 292 | #define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */ |
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| 293 | #define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */ |
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| 294 | #define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */ |
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| 295 | #define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */ |
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| 296 | #define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */ |
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| 297 | #define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */ |
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| 298 | #define SPR_PID 0x3b1 /* 4.. Process ID */ |
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| 299 | #define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */ |
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| 300 | #define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */ |
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| 301 | #define SPR_CCR0 0x3b3 /* 4.. Core Configuration Register 0 */ |
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| 302 | #define SPR_IAC3 0x3b4 /* 4.. Instruction Address Compare 3 */ |
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| 303 | #define SPR_IAC4 0x3b5 /* 4.. Instruction Address Compare 4 */ |
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| 304 | #define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */ |
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| 305 | #define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */ |
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| 306 | #define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */ |
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| 307 | |
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| 308 | #define SPR_970MMCR0 0x31b /* ... Monitor Mode Control Register 0 (PPC 970) */ |
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| 309 | #define SPR_970MMCR1 0x31e /* ... Monitor Mode Control Register 1 (PPC 970) */ |
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| 310 | #define SPR_970MMCRA 0x312 /* ... Monitor Mode Control Register 2 (PPC 970) */ |
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| 311 | #define SPR_970MMCR0 0x31b /* ... Monitor Mode Control Register 0 (PPC 970) */ |
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| 312 | #define SPR_970PMC1 0x313 /* ... PMC 1 */ |
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| 313 | #define SPR_970PMC2 0x314 /* ... PMC 2 */ |
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| 314 | #define SPR_970PMC3 0x315 /* ... PMC 3 */ |
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| 315 | #define SPR_970PMC4 0x316 /* ... PMC 4 */ |
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| 316 | #define SPR_970PMC5 0x317 /* ... PMC 5 */ |
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| 317 | #define SPR_970PMC6 0x318 /* ... PMC 6 */ |
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| 318 | #define SPR_970PMC7 0x319 /* ... PMC 7 */ |
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| 319 | #define SPR_970PMC8 0x31a /* ... PMC 8 */ |
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| 320 | |
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| 321 | #define SPR_MMCR0_FC 0x80000000 /* Freeze counters */ |
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| 322 | #define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */ |
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| 323 | #define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */ |
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| 324 | #define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */ |
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| 325 | #define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */ |
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| 326 | #define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */ |
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| 327 | #define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */ |
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| 328 | #define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */ |
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| 329 | #define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */ |
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| 330 | #define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */ |
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| 331 | #define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */ |
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| 332 | #define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */ |
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| 333 | #define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */ |
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| 334 | #define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ |
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| 335 | #define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ |
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| 336 | #define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ |
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| 337 | #define SPR_MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector */ |
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| 338 | #define SPR_MMCR0_PMC2SEL(x) ((x) << 0) /* PMC2 selector */ |
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| 339 | #define SPR_970MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */ |
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| 340 | #define SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */ |
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| 341 | #define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */ |
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| 342 | #define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */ |
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| 343 | #define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */ |
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| 344 | #define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */ |
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| 345 | #define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */ |
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| 346 | #define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */ |
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| 347 | #define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */ |
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| 348 | #define SPR_MMCR1_PMC3SEL(x) ((x) << 27) /* PMC 3 selector */ |
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| 349 | #define SPR_MMCR1_PMC4SEL(x) ((x) << 22) /* PMC 4 selector */ |
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| 350 | #define SPR_MMCR1_PMC5SEL(x) ((x) << 17) /* PMC 5 selector */ |
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| 351 | #define SPR_MMCR1_PMC6SEL(x) ((x) << 11) /* PMC 6 selector */ |
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| 352 | |
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| 353 | #define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */ |
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| 354 | #define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */ |
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| 355 | #define SPR_PMC4 0x3be /* .6. Performance Counter Register 4 */ |
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| 356 | #define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */ |
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| 357 | #define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */ |
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| 358 | #define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */ |
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| 359 | #define SPR_ICDBDR 0x3d3 /* 4.. Instruction Cache Debug Data Register */ |
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| 360 | #define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */ |
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| 361 | #define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */ |
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| 362 | #define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */ |
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| 363 | #define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */ |
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| 364 | #define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */ |
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| 365 | #define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */ |
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| 366 | #define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */ |
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| 367 | #define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */ |
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| 368 | #define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */ |
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| 369 | |
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| 370 | #define SPR_TSR 0x150 /* ..8 Timer Status Register */ |
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| 371 | #define SPR_TCR 0x154 /* ..8 Timer Control Register */ |
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| 372 | |
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| 373 | #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ |
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| 374 | #define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */ |
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| 375 | #define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */ |
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| 376 | #define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */ |
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| 377 | #define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */ |
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| 378 | #define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */ |
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| 379 | #define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */ |
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| 380 | #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ |
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| 381 | #define TSR_DIS 0x08000000 /* Decrementer Interrupt Status */ |
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| 382 | #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ |
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| 383 | |
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| 384 | #define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */ |
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| 385 | #define TCR_WP_2_17 0x00000000 /* 2**17 clocks */ |
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| 386 | #define TCR_WP_2_21 0x40000000 /* 2**21 clocks */ |
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| 387 | #define TCR_WP_2_25 0x80000000 /* 2**25 clocks */ |
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| 388 | #define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */ |
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| 389 | #define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */ |
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| 390 | #define TCR_WRC_NONE 0x00000000 /* No watchdog reset */ |
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| 391 | #define TCR_WRC_CORE 0x10000000 /* Core reset */ |
|---|
| 392 | #define TCR_WRC_CHIP 0x20000000 /* Chip reset */ |
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| 393 | #define TCR_WRC_SYSTEM 0x30000000 /* System reset */ |
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| 394 | #define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */ |
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| 395 | #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ |
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| 396 | #define TCR_DIE 0x04000000 /* Pecrementer Interrupt Enable */ |
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| 397 | #define TCR_FP_MASK 0x03000000 /* FIT Period */ |
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| 398 | #define TCR_FP_2_9 0x00000000 /* 2**9 clocks */ |
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| 399 | #define TCR_FP_2_13 0x01000000 /* 2**13 clocks */ |
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| 400 | #define TCR_FP_2_17 0x02000000 /* 2**17 clocks */ |
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| 401 | #define TCR_FP_2_21 0x03000000 /* 2**21 clocks */ |
|---|
| 402 | #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ |
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| 403 | #define TCR_ARE 0x00400000 /* Auto Reload Enable */ |
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| 404 | |
|---|
| 405 | #define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */ |
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| 406 | #define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */ |
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| 407 | #define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */ |
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| 408 | #define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ |
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| 409 | #define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ |
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| 410 | #define SPR_HID4 0x3f4 /* ..8 Hardware Implementation Register 4 */ |
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| 411 | #define SPR_HID5 0x3f6 /* ..8 Hardware Implementation Register 5 */ |
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| 412 | |
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| 413 | #if defined(AIM) |
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| 414 | #define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */ |
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| 415 | #define DBSR_IC 0x80000000 /* Instruction completion debug event */ |
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| 416 | #define DBSR_BT 0x40000000 /* Branch Taken debug event */ |
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| 417 | #define DBSR_EDE 0x20000000 /* Exception debug event */ |
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| 418 | #define DBSR_TIE 0x10000000 /* Trap Instruction debug event */ |
|---|
| 419 | #define DBSR_UDE 0x08000000 /* Unconditional debug event */ |
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| 420 | #define DBSR_IA1 0x04000000 /* IAC1 debug event */ |
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| 421 | #define DBSR_IA2 0x02000000 /* IAC2 debug event */ |
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| 422 | #define DBSR_DR1 0x01000000 /* DAC1 Read debug event */ |
|---|
| 423 | #define DBSR_DW1 0x00800000 /* DAC1 Write debug event */ |
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| 424 | #define DBSR_DR2 0x00400000 /* DAC2 Read debug event */ |
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| 425 | #define DBSR_DW2 0x00200000 /* DAC2 Write debug event */ |
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| 426 | #define DBSR_IDE 0x00100000 /* Imprecise debug event */ |
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| 427 | #define DBSR_IA3 0x00080000 /* IAC3 debug event */ |
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| 428 | #define DBSR_IA4 0x00040000 /* IAC4 debug event */ |
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| 429 | #define DBSR_MRR 0x00000300 /* Most recent reset */ |
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| 430 | #define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */ |
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| 431 | #define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */ |
|---|
| 432 | #define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */ |
|---|
| 433 | #define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */ |
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| 434 | #define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */ |
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| 435 | #define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */ |
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| 436 | #define SPR_PIR 0x3ff /* .6. Processor Identification Register */ |
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| 437 | #elif defined(E500) |
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| 438 | #define SPR_PIR 0x11e /* ..8 Processor Identification Register */ |
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| 439 | #define SPR_DBSR 0x130 /* ..8 Debug Status Register */ |
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| 440 | #define DBSR_IDE 0x80000000 /* Imprecise debug event. */ |
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| 441 | #define DBSR_UDE 0x40000000 /* Unconditional debug event. */ |
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| 442 | #define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */ |
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| 443 | #define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */ |
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| 444 | #define DBSR_BRT 0x04000000 /* Branch taken debug event. */ |
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| 445 | #define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */ |
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| 446 | #define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */ |
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| 447 | #define DBSR_IAC1 0x00800000 /* Instr. address compare #1. */ |
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| 448 | #define DBSR_IAC2 0x00400000 /* Instr. address compare #2. */ |
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| 449 | #define DBSR_IAC3 0x00200000 /* Instr. address compare #3. */ |
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| 450 | #define DBSR_IAC4 0x00100000 /* Instr. address compare #4. */ |
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| 451 | #define DBSR_DAC1R 0x00080000 /* Data addr. read compare #1. */ |
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| 452 | #define DBSR_DAC1W 0x00040000 /* Data addr. write compare #1. */ |
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| 453 | #define DBSR_DAC2R 0x00020000 /* Data addr. read compare #2. */ |
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| 454 | #define DBSR_DAC2W 0x00010000 /* Data addr. write compare #2. */ |
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| 455 | #define DBSR_RET 0x00008000 /* Return debug event. */ |
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| 456 | #define SPR_DBCR0 0x134 /* ..8 Debug Control Register 0 */ |
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| 457 | #define SPR_DBCR1 0x135 /* ..8 Debug Control Register 1 */ |
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| 458 | #define SPR_IAC1 0x138 /* ..8 Instruction Address Compare 1 */ |
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| 459 | #define SPR_IAC2 0x139 /* ..8 Instruction Address Compare 2 */ |
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| 460 | #define SPR_DAC1 0x13c /* ..8 Data Address Compare 1 */ |
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| 461 | #define SPR_DAC2 0x13d /* ..8 Data Address Compare 2 */ |
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| 462 | #endif |
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| 463 | |
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| 464 | #define DBCR0_EDM 0x80000000 /* External Debug Mode */ |
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| 465 | #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ |
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| 466 | #define DBCR0_RST_MASK 0x30000000 /* ReSeT */ |
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| 467 | #define DBCR0_RST_NONE 0x00000000 /* No action */ |
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| 468 | #define DBCR0_RST_CORE 0x10000000 /* Core reset */ |
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| 469 | #define DBCR0_RST_CHIP 0x20000000 /* Chip reset */ |
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| 470 | #define DBCR0_RST_SYSTEM 0x30000000 /* System reset */ |
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| 471 | #define DBCR0_IC 0x08000000 /* Instruction Completion debug event */ |
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| 472 | #define DBCR0_BT 0x04000000 /* Branch Taken debug event */ |
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| 473 | #define DBCR0_EDE 0x02000000 /* Exception Debug Event */ |
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| 474 | #define DBCR0_TDE 0x01000000 /* Trap Debug Event */ |
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| 475 | #define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */ |
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| 476 | #define DBCR0_IA2 0x00400000 /* IAC 2 debug event */ |
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| 477 | #define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */ |
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| 478 | #define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */ |
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| 479 | #define DBCR0_IA3 0x00080000 /* IAC 3 debug event */ |
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| 480 | #define DBCR0_IA4 0x00040000 /* IAC 4 debug event */ |
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| 481 | #define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */ |
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| 482 | #define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */ |
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| 483 | #define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */ |
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| 484 | #define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */ |
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| 485 | #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ |
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| 486 | |
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| 487 | #define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */ |
|---|
| 488 | #define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */ |
|---|
| 489 | #define SPR_MSSCR0 0x3f6 /* .6. Memory SubSystem Control Register */ |
|---|
| 490 | #define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */ |
|---|
| 491 | #define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */ |
|---|
| 492 | #define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */ |
|---|
| 493 | #define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/ |
|---|
| 494 | #define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */ |
|---|
| 495 | #define MSSCR0_MBO 0x00400000 /* 9: must be one */ |
|---|
| 496 | #define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */ |
|---|
| 497 | #define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */ |
|---|
| 498 | #define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */ |
|---|
| 499 | #define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ |
|---|
| 500 | #define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ |
|---|
| 501 | #define L2CR_L2E 0x80000000 /* 0: L2 enable */ |
|---|
| 502 | #define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */ |
|---|
| 503 | #define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */ |
|---|
| 504 | #define L2SIZ_2M 0x00000000 |
|---|
| 505 | #define L2SIZ_256K 0x10000000 |
|---|
| 506 | #define L2SIZ_512K 0x20000000 |
|---|
| 507 | #define L2SIZ_1M 0x30000000 |
|---|
| 508 | #define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */ |
|---|
| 509 | #define L2CLK_DIS 0x00000000 /* disable L2 clock */ |
|---|
| 510 | #define L2CLK_10 0x02000000 /* core clock / 1 */ |
|---|
| 511 | #define L2CLK_15 0x04000000 /* / 1.5 */ |
|---|
| 512 | #define L2CLK_20 0x08000000 /* / 2 */ |
|---|
| 513 | #define L2CLK_25 0x0a000000 /* / 2.5 */ |
|---|
| 514 | #define L2CLK_30 0x0c000000 /* / 3 */ |
|---|
| 515 | #define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */ |
|---|
| 516 | #define L2RAM_FLOWTHRU_BURST 0x00000000 |
|---|
| 517 | #define L2RAM_PIPELINE_BURST 0x01000000 |
|---|
| 518 | #define L2RAM_PIPELINE_LATE 0x01800000 |
|---|
| 519 | #define L2CR_L2DO 0x00400000 /* 9: L2 data-only. |
|---|
| 520 | Setting this bit disables instruction |
|---|
| 521 | caching. */ |
|---|
| 522 | #define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */ |
|---|
| 523 | #define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable). |
|---|
| 524 | Enables automatic operation of the |
|---|
| 525 | L2ZZ (low-power mode) signal. */ |
|---|
| 526 | #define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */ |
|---|
| 527 | #define L2CR_L2TS 0x00040000 /* 13: L2 test support. */ |
|---|
| 528 | #define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */ |
|---|
| 529 | #define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */ |
|---|
| 530 | #define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */ |
|---|
| 531 | #define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */ |
|---|
| 532 | #define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */ |
|---|
| 533 | #define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */ |
|---|
| 534 | #define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */ |
|---|
| 535 | #define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */ |
|---|
| 536 | #define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */ |
|---|
| 537 | #define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */ |
|---|
| 538 | /* progress (read only). */ |
|---|
| 539 | |
|---|
| 540 | #define SPR_L3CR 0x3fa /* .6. L3 Control Register */ |
|---|
| 541 | #define L3CR_L3E 0x80000000 /* 0: L3 enable */ |
|---|
| 542 | #define L3CR_L3PE 0x40000000 /* 1: L3 data parity enable */ |
|---|
| 543 | #define L3CR_L3APE 0x20000000 |
|---|
| 544 | #define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ |
|---|
| 545 | #define L3CR_L3CLKEN 0x08000000 /* 4: Enables L3_CLK[0:1] */ |
|---|
| 546 | #define L3CR_L3CLK 0x03800000 |
|---|
| 547 | #define L3CR_L3IO 0x00400000 |
|---|
| 548 | #define L3CR_L3CLKEXT 0x00200000 |
|---|
| 549 | #define L3CR_L3CKSPEXT 0x00100000 |
|---|
| 550 | #define L3CR_L3OH1 0x00080000 |
|---|
| 551 | #define L3CR_L3SPO 0x00040000 |
|---|
| 552 | #define L3CR_L3CKSP 0x00030000 |
|---|
| 553 | #define L3CR_L3PSP 0x0000e000 |
|---|
| 554 | #define L3CR_L3REP 0x00001000 |
|---|
| 555 | #define L3CR_L3HWF 0x00000800 |
|---|
| 556 | #define L3CR_L3I 0x00000400 /* 21: L3 global invalidate */ |
|---|
| 557 | #define L3CR_L3RT 0x00000300 |
|---|
| 558 | #define L3CR_L3NIRCA 0x00000080 |
|---|
| 559 | #define L3CR_L3DO 0x00000040 |
|---|
| 560 | #define L3CR_PMEN 0x00000004 |
|---|
| 561 | #define L3CR_PMSIZ 0x00000003 |
|---|
| 562 | |
|---|
| 563 | #define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */ |
|---|
| 564 | #define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */ |
|---|
| 565 | #define SPR_THRM1 0x3fc /* .6. Thermal Management Register */ |
|---|
| 566 | #define SPR_THRM2 0x3fd /* .6. Thermal Management Register */ |
|---|
| 567 | #define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */ |
|---|
| 568 | #define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */ |
|---|
| 569 | #define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */ |
|---|
| 570 | #define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */ |
|---|
| 571 | #define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */ |
|---|
| 572 | #define SPR_THRM_VALID 0x00000001 /* Valid bit */ |
|---|
| 573 | #define SPR_THRM3 0x3fe /* .6. Thermal Management Register */ |
|---|
| 574 | #define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */ |
|---|
| 575 | #define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */ |
|---|
| 576 | #define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */ |
|---|
| 577 | |
|---|
| 578 | /* Time Base Register declarations */ |
|---|
| 579 | #define TBR_TBL 0x10c /* 468 Time Base Lower - read */ |
|---|
| 580 | #define TBR_TBU 0x10d /* 468 Time Base Upper - read */ |
|---|
| 581 | #define TBR_TBWL 0x11c /* 468 Time Base Lower - supervisor, write */ |
|---|
| 582 | #define TBR_TBWU 0x11d /* 468 Time Base Upper - supervisor, write */ |
|---|
| 583 | |
|---|
| 584 | /* Performance counter declarations */ |
|---|
| 585 | #define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */ |
|---|
| 586 | |
|---|
| 587 | /* The first five countable [non-]events are common to many PMC's */ |
|---|
| 588 | #define PMCN_NONE 0 /* Count nothing */ |
|---|
| 589 | #define PMCN_CYCLES 1 /* Processor cycles */ |
|---|
| 590 | #define PMCN_ICOMP 2 /* Instructions completed */ |
|---|
| 591 | #define PMCN_TBLTRANS 3 /* TBL bit transitions */ |
|---|
| 592 | #define PCMN_IDISPATCH 4 /* Instructions dispatched */ |
|---|
| 593 | |
|---|
| 594 | /* Similar things for the 970 PMC direct counters */ |
|---|
| 595 | #define PMC970N_NONE 0x8 /* Count nothing */ |
|---|
| 596 | #define PMC970N_CYCLES 0xf /* Processor cycles */ |
|---|
| 597 | #define PMC970N_ICOMP 0x9 /* Instructions completed */ |
|---|
| 598 | |
|---|
| 599 | #if defined(AIM) |
|---|
| 600 | |
|---|
| 601 | #define SPR_ESR 0x3d4 /* 4.. Exception Syndrome Register */ |
|---|
| 602 | #define ESR_MCI 0x80000000 /* Machine check - instruction */ |
|---|
| 603 | #define ESR_PIL 0x08000000 /* Program interrupt - illegal */ |
|---|
| 604 | #define ESR_PPR 0x04000000 /* Program interrupt - privileged */ |
|---|
| 605 | #define ESR_PTR 0x02000000 /* Program interrupt - trap */ |
|---|
| 606 | #define ESR_ST 0x01000000 /* Store operation */ |
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| 607 | #define ESR_DST 0x00800000 /* Data storage interrupt - store fault */ |
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| 608 | #define ESR_DIZ 0x00800000 /* Data/instruction storage interrupt - zone fault */ |
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| 609 | #define ESR_U0F 0x00008000 /* Data storage interrupt - U0 fault */ |
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| 610 | |
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| 611 | #elif defined(E500) |
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| 612 | |
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| 613 | #define SPR_ESR 0x003e /* ..8 Exception Syndrome Register */ |
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| 614 | #define ESR_PIL 0x08000000 /* Program interrupt - illegal */ |
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| 615 | #define ESR_PPR 0x04000000 /* Program interrupt - privileged */ |
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| 616 | #define ESR_PTR 0x02000000 /* Program interrupt - trap */ |
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| 617 | #define ESR_ST 0x00800000 /* Store operation */ |
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| 618 | #define ESR_DLK 0x00200000 /* Data storage, D cache locking */ |
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| 619 | #define ESR_ILK 0x00100000 /* Data storage, I cache locking */ |
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| 620 | #define ESR_BO 0x00020000 /* Data/instruction storage, byte ordering */ |
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| 621 | #define ESR_SPE 0x00000080 /* SPE exception bit */ |
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| 622 | |
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| 623 | #define SPR_CSRR0 0x03a /* ..8 58 Critical SRR0 */ |
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| 624 | #define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */ |
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| 625 | #define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */ |
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| 626 | #define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */ |
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| 627 | |
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| 628 | #define SPR_SVR 0x3ff /* ..8 1023 System Version Register */ |
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| 629 | #define SVR_MPC8533 0x803c |
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| 630 | #define SVR_MPC8533E 0x8034 |
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| 631 | #define SVR_MPC8541 0x8072 |
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| 632 | #define SVR_MPC8541E 0x807a |
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| 633 | #define SVR_MPC8548 0x8031 |
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| 634 | #define SVR_MPC8548E 0x8039 |
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| 635 | #define SVR_MPC8555 0x8071 |
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| 636 | #define SVR_MPC8555E 0x8079 |
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| 637 | #define SVR_MPC8572 0x80e0 |
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| 638 | #define SVR_MPC8572E 0x80e8 |
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| 639 | #define SVR_VER(svr) (((svr) >> 16) & 0xffff) |
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| 640 | |
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| 641 | #define SPR_PID0 0x030 /* ..8 Process ID Register 0 */ |
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| 642 | #define SPR_PID1 0x279 /* ..8 Process ID Register 1 */ |
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| 643 | #define SPR_PID2 0x27a /* ..8 Process ID Register 2 */ |
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| 644 | |
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| 645 | #define SPR_TLB0CFG 0x2B0 /* ..8 TLB 0 Config Register */ |
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| 646 | #define SPR_TLB1CFG 0x2B1 /* ..8 TLB 1 Config Register */ |
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| 647 | #define TLBCFG_ASSOC_MASK 0xff000000 /* Associativity of TLB */ |
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| 648 | #define TLBCFG_ASSOC_SHIFT 24 |
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| 649 | #define TLBCFG_NENTRY_MASK 0x00000fff /* Number of entries in TLB */ |
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| 650 | |
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| 651 | #define SPR_IVPR 0x03f /* ..8 Interrupt Vector Prefix Register */ |
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| 652 | #define SPR_IVOR0 0x190 /* ..8 Critical input */ |
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| 653 | #define SPR_IVOR1 0x191 /* ..8 Machine check */ |
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| 654 | #define SPR_IVOR2 0x192 |
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| 655 | #define SPR_IVOR3 0x193 |
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| 656 | #define SPR_IVOR4 0x194 |
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| 657 | #define SPR_IVOR5 0x195 |
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| 658 | #define SPR_IVOR6 0x196 |
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| 659 | #define SPR_IVOR7 0x197 |
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| 660 | #define SPR_IVOR8 0x198 |
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| 661 | #define SPR_IVOR9 0x199 |
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| 662 | #define SPR_IVOR10 0x19a |
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| 663 | #define SPR_IVOR11 0x19b |
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| 664 | #define SPR_IVOR12 0x19c |
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| 665 | #define SPR_IVOR13 0x19d |
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| 666 | #define SPR_IVOR14 0x19e |
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| 667 | #define SPR_IVOR15 0x19f |
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| 668 | #define SPR_IVOR32 0x210 |
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| 669 | #define SPR_IVOR33 0x211 |
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| 670 | #define SPR_IVOR34 0x212 |
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| 671 | #define SPR_IVOR35 0x213 |
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| 672 | |
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| 673 | #define SPR_MAS0 0x270 /* ..8 MMU Assist Register 0 Book-E/e500 */ |
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| 674 | #define SPR_MAS1 0x271 /* ..8 MMU Assist Register 1 Book-E/e500 */ |
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| 675 | #define SPR_MAS2 0x272 /* ..8 MMU Assist Register 2 Book-E/e500 */ |
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| 676 | #define SPR_MAS3 0x273 /* ..8 MMU Assist Register 3 Book-E/e500 */ |
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| 677 | #define SPR_MAS4 0x274 /* ..8 MMU Assist Register 4 Book-E/e500 */ |
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| 678 | #define SPR_MAS5 0x275 /* ..8 MMU Assist Register 5 Book-E */ |
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| 679 | #define SPR_MAS6 0x276 /* ..8 MMU Assist Register 6 Book-E/e500 */ |
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| 680 | #define SPR_MAS7 0x3B0 /* ..8 MMU Assist Register 7 Book-E/e500 */ |
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| 681 | |
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| 682 | #define SPR_L1CSR0 0x3F2 /* ..8 L1 Cache Control and Status Register 0 */ |
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| 683 | #define L1CSR0_DCPE 0x00010000 /* Data Cache Parity Enable */ |
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| 684 | #define L1CSR0_DCLFR 0x00000100 /* Data Cache Lock Bits Flash Reset */ |
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| 685 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ |
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| 686 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ |
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| 687 | #define SPR_L1CSR1 0x3F3 /* ..8 L1 Cache Control and Status Register 1 */ |
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| 688 | #define L1CSR1_ICPE 0x00010000 /* Instruction Cache Parity Enable */ |
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| 689 | #define L1CSR1_ICLFR 0x00000100 /* Instruction Cache Lock Bits Flash Reset */ |
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| 690 | #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ |
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| 691 | #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ |
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| 692 | |
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| 693 | #define SPR_BUCSR 0x3F5 /* ..8 Branch Unit Control and Status Register */ |
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| 694 | #define BUCSR_BPEN 0x00000001 /* Branch Prediction Enable */ |
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| 695 | |
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| 696 | #endif /* #elif defined(E500) */ |
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| 697 | |
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| 698 | #endif /* !_POWERPC_SPR_H_ */ |
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