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sff8472.h @ 09bbedc

55-freebsd-126-freebsd-12

Last change on this file since 09bbedc was c40e45b, checked in by Sebastian Huber <sebastian.huber@…>, on 10/07/16 at 13:10:20

Update to FreeBSD head 2016-08-23

Git mirror commit 9fe7c416e6abb28b1398fd3e5687099846800cfd.

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1	/*-
2	* Copyright (c) 2013 George V. Neville-Neil
3	* All rights reserved.
4	*
5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions
7	* are met:
8	* 1. Redistributions of source code must retain the above copyright
9	* notice, this list of conditions and the following disclaimer.
10	* 2. Redistributions in binary form must reproduce the above copyright
11	* notice, this list of conditions and the following disclaimer in the
12	* documentation and/or other materials provided with the distribution.
13	*
14	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24	* SUCH DAMAGE.
25	*
26	* $FreeBSD$
27	*/
28
29	/*
30	* The following set of constants are from Document SFF-8472
31	* "Diagnostic Monitoring Interface for Optical Transceivers" revision
32	* 11.3 published by the SFF Committee on June 11, 2013
33	*
34	* The SFF standard defines two ranges of addresses, each 255 bytes
35	* long for the storage of data and diagnostics on cables, such as
36	* SFP+ optics and TwinAx cables. The ranges are defined in the
37	* following way:
38	*
39	* Base Address 0xa0 (Identification Data)
40	* 0-95 Serial ID Defined by SFP MSA
41	* 96-127 Vendor Specific Data
42	* 128-255 Reserved
43	*
44	* Base Address 0xa2 (Diagnostic Data)
45	* 0-55 Alarm and Warning Thresholds
46	* 56-95 Cal Constants
47	* 96-119 Real Time Diagnostic Interface
48	* 120-127 Vendor Specific
49	* 128-247 User Writable EEPROM
50	* 248-255 Vendor Specific
51	*
52	* Note that not all addresses are supported. Where support is
53	* optional this is noted and instructions for checking for the
54	* support are supplied.
55	*
56	* All these values are read across an I2C (i squared C) bus. Any
57	* device wishing to read these addresses must first have support for
58	* i2c calls. The Chelsio T4/T5 driver (dev/cxgbe) is one such
59	* driver.
60	*/
61
62
63	/* Table 3.1 Two-wire interface ID: Data Fields */
64
65	enum {
66	SFF_8472_BASE = 0xa0, /* Base address for all our queries. */
67	SFF_8472_ID = 0, /* Transceiver Type (Table 3.2) */
68	SFF_8472_EXT_ID = 1, /* Extended transceiver type (Table 3.3) */
69	SFF_8472_CONNECTOR = 2, /* Connector type (Table 3.4) */
70	SFF_8472_TRANS_START = 3, /* Elec or Optical Compatibility
71	* (Table 3.5) */
72	SFF_8472_TRANS_END = 10,
73	SFF_8472_ENCODING = 11, /* Encoding Code for high speed
74	* serial encoding algorithm (see
75	* Table 3.6) */
76	SFF_8472_BITRATE = 12, /* Nominal signaling rate, units
77	* of 100MBd. (see details for
78	* rates > 25.0Gb/s) */
79	SFF_8472_RATEID = 13, /* Type of rate select
80	* functionality (see Table
81	* 3.6a) */
82	SFF_8472_LEN_SMF_KM = 14, /* Link length supported for single
83	* mode fiber, units of km */
84	SFF_8472_LEN_SMF = 15, /* Link length supported for single
85	* mode fiber, units of 100 m */
86	SFF_8472_LEN_50UM = 16, /* Link length supported for 50 um
87	* OM2 fiber, units of 10 m */
88	SFF_8472_LEN_625UM = 17, /* Link length supported for 62.5
89	* um OM1 fiber, units of 10 m */
90	SFF_8472_LEN_OM4 = 18, /* Link length supported for 50um
91	* OM4 fiber, units of 10m.
92	* Alternatively copper or direct
93	* attach cable, units of m */
94	SFF_8472_LEN_OM3 = 19, /* Link length supported for 50 um OM3 fiber, units of 10 m */
95	SFF_8472_VENDOR_START = 20, /* Vendor name [Address A0h, Bytes
96	* 20-35] */
97	SFF_8472_VENDOR_END = 35,
98	SFF_8472_TRANS = 36, /* Transceiver Code for electronic
99	* or optical compatibility (see
100	* Table 3.5) */
101	SFF_8472_VENDOR_OUI_START = 37, /* Vendor OUI SFP vendor IEEE
102	* company ID */
103	SFF_8472_VENDOR_OUI_END = 39,
104	SFF_8472_PN_START = 40, /* Vendor PN */
105	SFF_8472_PN_END = 55,
106	SFF_8472_REV_START = 56, /* Vendor Revision */
107	SFF_8472_REV_END = 59,
108	SFF_8472_WAVELEN_START = 60, /* Wavelength Laser wavelength
109	* (Passive/Active Cable
110	* Specification Compliance) */
111	SFF_8472_WAVELEN_END = 61,
112	SFF_8472_CC_BASE = 63, /* CC_BASE Check code for Base ID
113	* Fields (addresses 0 to 62) */
114
115	/*
116	* Extension Fields (optional) check the options before reading other
117	* addresses.
118	*/
119	SFF_8472_OPTIONS_MSB = 64, /* Options Indicates which optional
120	* transceiver signals are
121	* implemented */
122	SFF_8472_OPTIONS_LSB = 65, /* (see Table 3.7) */
123	SFF_8472_BR_MAX = 66, /* BR max Upper bit rate margin,
124	* units of % (see details for
125	* rates > 25.0Gb/s) */
126	SFF_8472_BR_MIN = 67, /* Lower bit rate margin, units of
127	* % (see details for rates >
128	* 25.0Gb/s) */
129	SFF_8472_SN_START = 68, /* Vendor SN [Address A0h, Bytes 68-83] */
130	SFF_8472_SN_END = 83,
131	SFF_8472_DATE_START = 84, /* Date code Vendorâs manufacturing
132	* date code (see Table 3.8) */
133	SFF_8472_DATE_END = 91,
134	SFF_8472_DIAG_TYPE = 92, /* Diagnostic Monitoring Type
135	* Indicates which type of
136	* diagnostic monitoring is
137	* implemented (if any) in the
138	* transceiver (see Table 3.9)
139	*/
140
141	SFF_8472_ENHANCED = 93, /* Enhanced Options Indicates which
142	* optional enhanced features are
143	* implemented (if any) in the
144	* transceiver (see Table 3.10) */
145	SFF_8472_COMPLIANCE = 94, /* SFF-8472 Compliance Indicates
146	* which revision of SFF-8472 the
147	* transceiver complies with. (see
148	* Table 3.12)*/
149	SFF_8472_CC_EXT = 95, /* Check code for the Extended ID
150	* Fields (addresses 64 to 94)
151	*/
152
153	SFF_8472_VENDOR_RSRVD_START = 96,
154	SFF_8472_VENDOR_RSRVD_END = 127,
155
156	SFF_8472_RESERVED_START = 128,
157	SFF_8472_RESERVED_END = 255
158	};
159
160	#define SFF_8472_DIAG_IMPL (1 << 6) /* Required to be 1 */
161	#define SFF_8472_DIAG_INTERNAL (1 << 5) /* Internal measurements. */
162	#define SFF_8472_DIAG_EXTERNAL (1 << 4) /* External measurements. */
163	#define SFF_8472_DIAG_POWER (1 << 3) /* Power measurement type */
164	#define SFF_8472_DIAG_ADDR_CHG (1 << 2) /* Address change required.
165	* See SFF-8472 doc. */
166
167	/*
168	* Diagnostics are available at the two wire address 0xa2. All
169	* diagnostics are OPTIONAL so you should check 0xa0 registers 92 to
170	* see which, if any are supported.
171	*/
172
173	enum {SFF_8472_DIAG = 0xa2}; /* Base address for diagnostics. */
174
175	/*
176	* Table 3.15 Alarm and Warning Thresholds All values are 2 bytes
177	* and MUST be read in a single read operation starting at the MSB
178	*/
179
180	enum {
181	SFF_8472_TEMP_HIGH_ALM = 0, /* Temp High Alarm */
182	SFF_8472_TEMP_LOW_ALM = 2, /* Temp Low Alarm */
183	SFF_8472_TEMP_HIGH_WARN = 4, /* Temp High Warning */
184	SFF_8472_TEMP_LOW_WARN = 6, /* Temp Low Warning */
185	SFF_8472_VOLTAGE_HIGH_ALM = 8, /* Voltage High Alarm */
186	SFF_8472_VOLTAGE_LOW_ALM = 10, /* Voltage Low Alarm */
187	SFF_8472_VOLTAGE_HIGH_WARN = 12, /* Voltage High Warning */
188	SFF_8472_VOLTAGE_LOW_WARN = 14, /* Voltage Low Warning */
189	SFF_8472_BIAS_HIGH_ALM = 16, /* Bias High Alarm */
190	SFF_8472_BIAS_LOW_ALM = 18, /* Bias Low Alarm */
191	SFF_8472_BIAS_HIGH_WARN = 20, /* Bias High Warning */
192	SFF_8472_BIAS_LOW_WARN = 22, /* Bias Low Warning */
193	SFF_8472_TX_POWER_HIGH_ALM = 24, /* TX Power High Alarm */
194	SFF_8472_TX_POWER_LOW_ALM = 26, /* TX Power Low Alarm */
195	SFF_8472_TX_POWER_HIGH_WARN = 28, /* TX Power High Warning */
196	SFF_8472_TX_POWER_LOW_WARN = 30, /* TX Power Low Warning */
197	SFF_8472_RX_POWER_HIGH_ALM = 32, /* RX Power High Alarm */
198	SFF_8472_RX_POWER_LOW_ALM = 34, /* RX Power Low Alarm */
199	SFF_8472_RX_POWER_HIGH_WARN = 36, /* RX Power High Warning */
200	SFF_8472_RX_POWER_LOW_WARN = 38, /* RX Power Low Warning */
201
202	SFF_8472_RX_POWER4 = 56, /* Rx_PWR(4) Single precision
203	* floating point calibration data
204	* - Rx optical power. Bit 7 of
205	* byte 56 is MSB. Bit 0 of byte
206	* 59 is LSB. Rx_PWR(4) should be
207	* set to zero for âinternally
208	* calibratedâ devices. */
209	SFF_8472_RX_POWER3 = 60, /* Rx_PWR(3) Single precision
210	* floating point calibration data
211	* - Rx optical power. Bit 7 of
212	* byte 60 is MSB. Bit 0 of byte 63
213	* is LSB. Rx_PWR(3) should be set
214	* to zero for âinternally
215	* calibratedâ devices.*/
216	SFF_8472_RX_POWER2 = 64, /* Rx_PWR(2) Single precision
217	* floating point calibration data,
218	* Rx optical power. Bit 7 of byte
219	* 64 is MSB, bit 0 of byte 67 is
220	* LSB. Rx_PWR(2) should be set to
221	* zero for âinternally calibratedâ
222	* devices. */
223	SFF_8472_RX_POWER1 = 68, /* Rx_PWR(1) Single precision
224	* floating point calibration data,
225	* Rx optical power. Bit 7 of byte
226	* 68 is MSB, bit 0 of byte 71 is
227	* LSB. Rx_PWR(1) should be set to
228	* 1 for âinternally calibratedâ
229	* devices. */
230	SFF_8472_RX_POWER0 = 72, /* Rx_PWR(0) Single precision
231	* floating point calibration data,
232	* Rx optical power. Bit 7 of byte
233	* 72 is MSB, bit 0 of byte 75 is
234	* LSB. Rx_PWR(0) should be set to
235	* zero for âinternally calibratedâ
236	* devices. */
237	SFF_8472_TX_I_SLOPE = 76, /* Tx_I(Slope) Fixed decimal
238	* (unsigned) calibration data,
239	* laser bias current. Bit 7 of
240	* byte 76 is MSB, bit 0 of byte 77
241	* is LSB. Tx_I(Slope) should be
242	* set to 1 for âinternally
243	* calibratedâ devices. */
244	SFF_8472_TX_I_OFFSET = 78, /* Tx_I(Offset) Fixed decimal
245	* (signed twoâs complement)
246	* calibration data, laser bias
247	* current. Bit 7 of byte 78 is
248	* MSB, bit 0 of byte 79 is
249	* LSB. Tx_I(Offset) should be set
250	* to zero for âinternally
251	* calibratedâ devices. */
252	SFF_8472_TX_POWER_SLOPE = 80, /* Tx_PWR(Slope) Fixed decimal
253	* (unsigned) calibration data,
254	* transmitter coupled output
255	* power. Bit 7 of byte 80 is MSB,
256	* bit 0 of byte 81 is LSB.
257	* Tx_PWR(Slope) should be set to 1
258	* for âinternally calibratedâ
259	* devices. */
260	SFF_8472_TX_POWER_OFFSET = 82, /* Tx_PWR(Offset) Fixed decimal
261	* (signed twoâs complement)
262	* calibration data, transmitter
263	* coupled output power. Bit 7 of
264	* byte 82 is MSB, bit 0 of byte 83
265	* is LSB. Tx_PWR(Offset) should be
266	* set to zero for âinternally
267	* calibratedâ devices. */
268	SFF_8472_T_SLOPE = 84, /* T (Slope) Fixed decimal
269	* (unsigned) calibration data,
270	* internal module temperature. Bit
271	* 7 of byte 84 is MSB, bit 0 of
272	* byte 85 is LSB. T(Slope) should
273	* be set to 1 for âinternally
274	* calibratedâ devices. */
275	SFF_8472_T_OFFSET = 86, /* T (Offset) Fixed decimal (signed
276	* twoâs complement) calibration
277	* data, internal module
278	* temperature. Bit 7 of byte 86 is
279	* MSB, bit 0 of byte 87 is LSB.
280	* T(Offset) should be set to zero
281	* for âinternally calibratedâ
282	* devices. */
283	SFF_8472_V_SLOPE = 88, /* V (Slope) Fixed decimal
284	* (unsigned) calibration data,
285	* internal module supply
286	* voltage. Bit 7 of byte 88 is
287	* MSB, bit 0 of byte 89 is
288	* LSB. V(Slope) should be set to 1
289	* for âinternally calibratedâ
290	* devices. */
291	SFF_8472_V_OFFSET = 90, /* V (Offset) Fixed decimal (signed
292	* twoâs complement) calibration
293	* data, internal module supply
294	* voltage. Bit 7 of byte 90 is
295	* MSB. Bit 0 of byte 91 is
296	* LSB. V(Offset) should be set to
297	* zero for âinternally calibratedâ
298	* devices. */
299	SFF_8472_CHECKSUM = 95, /* Checksum Byte 95 contains the
300	* low order 8 bits of the sum of
301	* bytes 0 â 94. */
302	/* Internal measurements. */
303
304	SFF_8472_TEMP = 96, /* Internally measured module temperature. */
305	SFF_8472_VCC = 98, /* Internally measured supply
306	* voltage in transceiver.
307	*/
308	SFF_8472_TX_BIAS = 100, /* Internally measured TX Bias Current. */
309	SFF_8472_TX_POWER = 102, /* Measured TX output power. */
310	SFF_8472_RX_POWER = 104, /* Measured RX input power. */
311
312	SFF_8472_STATUS = 110 /* See below */
313	};
314	/* Status Bits Described */
315
316	/*
317	* TX Disable State Digital state of the TX Disable Input Pin. Updated
318	* within 100ms of change on pin.
319	*/
320	#define SFF_8472_STATUS_TX_DISABLE (1 << 7)
321
322	/*
323	* Select Read/write bit that allows software disable of
324	* laser. Writing â1â disables laser. See Table 3.11 for
325	* enable/disable timing requirements. This bit is âORâd with the hard
326	* TX_DISABLE pin value. Note, per SFP MSA TX_DISABLE pin is default
327	* enabled unless pulled low by hardware. If Soft TX Disable is not
328	* implemented, the transceiver ignores the value of this bit. Default
329	* power up value is zero/low.
330	*/
331	#define SFF_8472_STATUS_SOFT_TX_DISABLE (1 << 6)
332
333	/*
334	* RS(1) State Digital state of SFP input pin AS(1) per SFF-8079 or
335	* RS(1) per SFF-8431. Updated within 100ms of change on pin. See A2h
336	* Byte 118, Bit 3 for Soft RS(1) Select control information.
337	*/
338	#define SFF_8472_RS_STATE (1 << 5)
339
340	/*
341	* Rate_Select State [aka. âRS(0)â] Digital state of the SFP
342	* Rate_Select Input Pin. Updated within 100ms of change on pin. Note:
343	* This pin is also known as AS(0) in SFF-8079 and RS(0) in SFF-8431.
344	*/
345	#define SFF_8472_STATUS_SELECT_STATE (1 << 4)
346
347	/*
348	* Read/write bit that allows software rate select control. Writing
349	* â1â selects full bandwidth operation. This bit is âORâd with the
350	* hard Rate_Select, AS(0) or RS(0) pin value. See Table 3.11 for
351	* timing requirements. Default at power up is logic zero/low. If Soft
352	* Rate Select is not implemented, the transceiver ignores the value
353	* of this bit. Note: Specific transceiver behaviors of this bit are
354	* identified in Table 3.6a and referenced documents. See Table 3.18a,
355	* byte 118, bit 3 for Soft RS(1) Select.
356	*/
357	#define SFF_8472_STATUS_SOFT_RATE_SELECT (1 << 3)
358
359	/*
360	* TX Fault State Digital state of the TX Fault Output Pin. Updated
361	* within 100ms of change on pin.
362	*/
363	#define SFF_8472_STATUS_TX_FAULT_STATE (1 << 2)
364
365	/*
366	* Digital state of the RX_LOS Output Pin. Updated within 100ms of
367	* change on pin.
368	*/
369	#define SFF_8472_STATUS_RX_LOS (1 << 1)
370
371	/*
372	* Indicates transceiver has achieved power up and data is ready. Bit
373	* remains high until data is ready to be read at which time the
374	* device sets the bit low.
375	*/
376	#define SFF_8472_STATUS_DATA_READY (1 << 0)
377
378	/*
379	* Table 3.2 Identifier values.
380	* Identifier constants has taken from SFF-8024 rev 2.9 table 4.1
381	* (as referenced by table 3.2 footer)
382	* */
383	enum {
384	SFF_8024_ID_UNKNOWN = 0x0, /* Unknown or unspecified */
385	SFF_8024_ID_GBIC = 0x1, /* GBIC */
386	SFF_8024_ID_SFF = 0x2, /* Module soldered to motherboard (ex: SFF)*/
387	SFF_8024_ID_SFP = 0x3, /* SFP or SFP âPlusâ */
388	SFF_8024_ID_XBI = 0x4, /* 300 pin XBI */
389	SFF_8024_ID_XENPAK = 0x5, /* Xenpak */
390	SFF_8024_ID_XFP = 0x6, /* XFP */
391	SFF_8024_ID_XFF = 0x7, /* XFF */
392	SFF_8024_ID_XFPE = 0x8, /* XFP-E */
393	SFF_8024_ID_XPAK = 0x9, /* XPAk */
394	SFF_8024_ID_X2 = 0xA, /* X2 */
395	SFF_8024_ID_DWDM_SFP = 0xB, /* DWDM-SFP */
396	SFF_8024_ID_QSFP = 0xC, /* QSFP */
397	SFF_8024_ID_QSFPPLUS = 0xD, /* QSFP+ */
398	SFF_8024_ID_CXP = 0xE, /* CXP */
399	SFF_8024_ID_HD4X = 0xF, /* Shielded Mini Multilane HD 4X */
400	SFF_8024_ID_HD8X = 0x10, /* Shielded Mini Multilane HD 8X */
401	SFF_8024_ID_QSFP28 = 0x11, /* QSFP28 */
402	SFF_8024_ID_CXP2 = 0x12, /* CXP2 (aka CXP28) */
403	SFF_8024_ID_CDFP = 0x13, /* CDFP (Style 1/Style 2) */
404	SFF_8024_ID_SMM4 = 0x14, /* Shielded Mini Multilate HD 4X Fanout */
405	SFF_8024_ID_SMM8 = 0x15, /* Shielded Mini Multilate HD 8X Fanout */
406	SFF_8024_ID_CDFP3 = 0x16, /* CDFP (Style3) */
407	SFF_8024_ID_LAST = SFF_8024_ID_CDFP3
408	};
409
410	static const char *sff_8024_id[SFF_8024_ID_LAST + 1] = {"Unknown",
411	"GBIC",
412	"SFF",
413	"SFP/SFP+/SFP28",
414	"XBI",
415	"Xenpak",
416	"XFP",
417	"XFF",
418	"XFP-E",
419	"XPAK",
420	"X2",
421	"DWDM-SFP/SFP+",
422	"QSFP",
423	"QSFP+",
424	"CXP",
425	"HD4X",
426	"HD8X",
427	"QSFP28",
428	"CXP2",
429	"CDFP",
430	"SMM4",
431	"SMM8",
432	"CDFP3"};
433
434	/* Keep compatibility with old definitions */
435	#define SFF_8472_ID_UNKNOWN SFF_8024_ID_UNKNOWN
436	#define SFF_8472_ID_GBIC SFF_8024_ID_GBIC
437	#define SFF_8472_ID_SFF SFF_8024_ID_SFF
438	#define SFF_8472_ID_SFP SFF_8024_ID_SFP
439	#define SFF_8472_ID_XBI SFF_8024_ID_XBI
440	#define SFF_8472_ID_XENPAK SFF_8024_ID_XENPAK
441	#define SFF_8472_ID_XFP SFF_8024_ID_XFP
442	#define SFF_8472_ID_XFF SFF_8024_ID_XFF
443	#define SFF_8472_ID_XFPE SFF_8024_ID_XFPE
444	#define SFF_8472_ID_XPAK SFF_8024_ID_XPAK
445	#define SFF_8472_ID_X2 SFF_8024_ID_X2
446	#define SFF_8472_ID_DWDM_SFP SFF_8024_ID_DWDM_SFP
447	#define SFF_8472_ID_QSFP SFF_8024_ID_QSFP
448	#define SFF_8472_ID_LAST SFF_8024_ID_LAST
449
450	#define sff_8472_id sff_8024_id
451
452	/*
453	* Table 3.9 Diagnostic Monitoring Type (byte 92)
454	* bits described.
455	*/
456
457	/*
458	* Digital diagnostic monitoring implemented.
459	* Set to 1 for transceivers implementing DDM.
460	*/
461	#define SFF_8472_DDM_DONE (1 << 6)
462
463	/*
464	* Measurements are internally calibrated.
465	*/
466	#define SFF_8472_DDM_INTERNAL (1 << 5)
467
468	/*
469	* Measurements are externally calibrated.
470	*/
471	#define SFF_8472_DDM_EXTERNAL (1 << 4)
472
473	/*
474	* Received power measurement type
475	* 0 = OMA, 1 = average power
476	*/
477	#define SFF_8472_DDM_PMTYPE (1 << 3)
478
479	/* Table 3.13 and 3.14 Temperature Conversion Values */
480	#define SFF_8472_TEMP_SIGN (1 << 15)
481	#define SFF_8472_TEMP_SHIFT 8
482	#define SFF_8472_TEMP_MSK 0xEF00
483	#define SFF_8472_TEMP_FRAC 0x00FF
484
485	/* Internal Callibration Conversion factors */
486
487	/*
488	* Represented as a 16 bit unsigned integer with the voltage defined
489	* as the full 16 bit value (0 â 65535) with LSB equal to 100 uVolt,
490	* yielding a total range of 0 to +6.55 Volts.
491	*/
492	#define SFF_8472_VCC_FACTOR 10000.0
493
494	/*
495	* Represented as a 16 bit unsigned integer with the current defined
496	* as the full 16 bit value (0 â 65535) with LSB equal to 2 uA,
497	* yielding a total range of 0 to 131 mA.
498	*/
499
500	#define SFF_8472_BIAS_FACTOR 2000.0
501
502	/*
503	* Represented as a 16 bit unsigned integer with the power defined as
504	* the full 16 bit value (0 â 65535) with LSB equal to 0.1 uW,
505	* yielding a total range of 0 to 6.5535 mW (~ -40 to +8.2 dBm).
506	*/
507
508	#define SFF_8472_POWER_FACTOR 10000.0

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