1 | /* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */ |
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2 | |
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3 | /*- |
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4 | * Copyright (c) 2002-2004 Juli Mallett. All rights reserved. |
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5 | * |
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6 | * Redistribution and use in source and binary forms, with or without |
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7 | * modification, are permitted provided that the following conditions |
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8 | * are met: |
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9 | * 1. Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * 2. Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * |
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15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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16 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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17 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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18 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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19 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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20 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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21 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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22 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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23 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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24 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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25 | * SUCH DAMAGE. |
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26 | */ |
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27 | /* |
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28 | * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved. |
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29 | * |
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30 | * Redistribution and use in source and binary forms, with or without |
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31 | * modification, are permitted provided that the following conditions |
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32 | * are met: |
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33 | * 1. Redistributions of source code must retain the above copyright |
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34 | * notice, this list of conditions and the following disclaimer. |
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35 | * 2. Redistributions in binary form must reproduce the above copyright |
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36 | * notice, this list of conditions and the following disclaimer in the |
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37 | * documentation and/or other materials provided with the distribution. |
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38 | * 3. All advertising materials mentioning features or use of this software |
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39 | * must display the following acknowledgement: |
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40 | * This product includes software developed by Per Fogelstrom. |
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41 | * 4. The name of the author may not be used to endorse or promote products |
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42 | * derived from this software without specific prior written permission |
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43 | * |
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44 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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45 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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46 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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47 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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48 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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49 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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50 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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51 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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52 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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53 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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54 | * |
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55 | * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta |
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56 | * $FreeBSD$ |
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57 | */ |
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58 | |
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59 | #ifndef _MACHINE_CPUFUNC_H_ |
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60 | #define _MACHINE_CPUFUNC_H_ |
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61 | |
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62 | #include <rtems/bsd/sys/types.h> |
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63 | #include <machine/cpuregs.h> |
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64 | |
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65 | /* |
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66 | * These functions are required by user-land atomi ops |
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67 | */ |
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68 | |
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69 | static __inline void |
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70 | mips_barrier(void) |
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71 | { |
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72 | #ifdef CPU_CNMIPS |
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73 | __compiler_membar(); |
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74 | #else |
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75 | __asm __volatile (".set noreorder\n\t" |
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76 | "nop\n\t" |
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77 | "nop\n\t" |
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78 | "nop\n\t" |
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79 | "nop\n\t" |
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80 | "nop\n\t" |
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81 | "nop\n\t" |
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82 | "nop\n\t" |
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83 | "nop\n\t" |
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84 | ".set reorder\n\t" |
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85 | : : : "memory"); |
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86 | #endif |
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87 | } |
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88 | |
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89 | static __inline void |
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90 | mips_cp0_sync(void) |
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91 | { |
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92 | __asm __volatile (__XSTRING(COP0_SYNC)); |
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93 | } |
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94 | |
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95 | static __inline void |
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96 | mips_wbflush(void) |
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97 | { |
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98 | #if defined(CPU_CNMIPS) |
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99 | __asm __volatile (".set noreorder\n\t" |
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100 | "syncw\n\t" |
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101 | ".set reorder\n" |
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102 | : : : "memory"); |
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103 | #else |
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104 | __asm __volatile ("sync" : : : "memory"); |
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105 | mips_barrier(); |
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106 | #endif |
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107 | } |
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108 | |
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109 | static __inline void |
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110 | mips_read_membar(void) |
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111 | { |
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112 | /* Nil */ |
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113 | } |
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114 | |
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115 | static __inline void |
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116 | mips_write_membar(void) |
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117 | { |
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118 | mips_wbflush(); |
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119 | } |
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120 | |
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121 | #ifdef _KERNEL |
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122 | /* |
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123 | * XXX |
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124 | * It would be nice to add variants that read/write register_t, to avoid some |
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125 | * ABI checks. |
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126 | */ |
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127 | #if defined(__mips_n32) || defined(__mips_n64) |
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128 | #define MIPS_RW64_COP0(n,r) \ |
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129 | static __inline uint64_t \ |
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130 | mips_rd_ ## n (void) \ |
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131 | { \ |
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132 | int v0; \ |
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133 | __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \ |
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134 | : [v0] "=&r"(v0)); \ |
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135 | mips_barrier(); \ |
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136 | return (v0); \ |
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137 | } \ |
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138 | static __inline void \ |
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139 | mips_wr_ ## n (uint64_t a0) \ |
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140 | { \ |
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141 | __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \ |
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142 | __XSTRING(COP0_SYNC)";" \ |
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143 | "nop;" \ |
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144 | "nop;" \ |
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145 | : \ |
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146 | : [a0] "r"(a0)); \ |
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147 | mips_barrier(); \ |
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148 | } struct __hack |
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149 | |
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150 | #define MIPS_RW64_COP0_SEL(n,r,s) \ |
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151 | static __inline uint64_t \ |
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152 | mips_rd_ ## n(void) \ |
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153 | { \ |
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154 | int v0; \ |
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155 | __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \ |
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156 | : [v0] "=&r"(v0)); \ |
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157 | mips_barrier(); \ |
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158 | return (v0); \ |
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159 | } \ |
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160 | static __inline void \ |
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161 | mips_wr_ ## n(uint64_t a0) \ |
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162 | { \ |
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163 | __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \ |
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164 | __XSTRING(COP0_SYNC)";" \ |
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165 | : \ |
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166 | : [a0] "r"(a0)); \ |
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167 | mips_barrier(); \ |
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168 | } struct __hack |
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169 | |
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170 | #if defined(__mips_n64) |
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171 | MIPS_RW64_COP0(excpc, MIPS_COP_0_EXC_PC); |
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172 | MIPS_RW64_COP0(entryhi, MIPS_COP_0_TLB_HI); |
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173 | MIPS_RW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); |
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174 | #ifdef CPU_CNMIPS |
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175 | MIPS_RW64_COP0_SEL(cvmcount, MIPS_COP_0_COUNT, 6); |
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176 | MIPS_RW64_COP0_SEL(cvmctl, MIPS_COP_0_COUNT, 7); |
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177 | MIPS_RW64_COP0_SEL(cvmmemctl, MIPS_COP_0_COMPARE, 7); |
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178 | MIPS_RW64_COP0_SEL(icache_err, MIPS_COP_0_CACHE_ERR, 0); |
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179 | MIPS_RW64_COP0_SEL(dcache_err, MIPS_COP_0_CACHE_ERR, 1); |
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180 | #endif |
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181 | #endif |
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182 | #if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */ |
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183 | MIPS_RW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0); |
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184 | MIPS_RW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1); |
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185 | #endif |
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186 | MIPS_RW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT); |
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187 | |
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188 | #undef MIPS_RW64_COP0 |
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189 | #undef MIPS_RW64_COP0_SEL |
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190 | #endif |
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191 | |
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192 | #define MIPS_RW32_COP0(n,r) \ |
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193 | static __inline uint32_t \ |
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194 | mips_rd_ ## n (void) \ |
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195 | { \ |
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196 | int v0; \ |
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197 | __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \ |
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198 | : [v0] "=&r"(v0)); \ |
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199 | mips_barrier(); \ |
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200 | return (v0); \ |
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201 | } \ |
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202 | static __inline void \ |
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203 | mips_wr_ ## n (uint32_t a0) \ |
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204 | { \ |
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205 | __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \ |
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206 | __XSTRING(COP0_SYNC)";" \ |
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207 | "nop;" \ |
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208 | "nop;" \ |
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209 | : \ |
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210 | : [a0] "r"(a0)); \ |
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211 | mips_barrier(); \ |
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212 | } struct __hack |
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213 | |
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214 | #define MIPS_RW32_COP0_SEL(n,r,s) \ |
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215 | static __inline uint32_t \ |
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216 | mips_rd_ ## n(void) \ |
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217 | { \ |
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218 | int v0; \ |
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219 | __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \ |
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220 | : [v0] "=&r"(v0)); \ |
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221 | mips_barrier(); \ |
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222 | return (v0); \ |
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223 | } \ |
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224 | static __inline void \ |
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225 | mips_wr_ ## n(uint32_t a0) \ |
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226 | { \ |
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227 | __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \ |
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228 | __XSTRING(COP0_SYNC)";" \ |
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229 | "nop;" \ |
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230 | "nop;" \ |
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231 | : \ |
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232 | : [a0] "r"(a0)); \ |
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233 | mips_barrier(); \ |
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234 | } struct __hack |
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235 | |
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236 | #ifdef CPU_CNMIPS |
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237 | static __inline void mips_sync_icache (void) |
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238 | { |
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239 | __asm __volatile ( |
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240 | ".set push\n" |
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241 | ".set mips64\n" |
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242 | ".word 0x041f0000\n" /* xxx ICACHE */ |
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243 | "nop\n" |
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244 | ".set pop\n" |
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245 | : : ); |
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246 | } |
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247 | #endif |
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248 | |
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249 | MIPS_RW32_COP0(compare, MIPS_COP_0_COMPARE); |
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250 | MIPS_RW32_COP0(config, MIPS_COP_0_CONFIG); |
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251 | MIPS_RW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1); |
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252 | MIPS_RW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2); |
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253 | MIPS_RW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3); |
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254 | #ifdef CPU_CNMIPS |
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255 | MIPS_RW32_COP0_SEL(config4, MIPS_COP_0_CONFIG, 4); |
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256 | #endif |
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257 | #ifdef CPU_NLM |
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258 | MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6); |
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259 | MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7); |
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260 | #endif |
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261 | MIPS_RW32_COP0(count, MIPS_COP_0_COUNT); |
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262 | MIPS_RW32_COP0(index, MIPS_COP_0_TLB_INDEX); |
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263 | MIPS_RW32_COP0(wired, MIPS_COP_0_TLB_WIRED); |
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264 | MIPS_RW32_COP0(cause, MIPS_COP_0_CAUSE); |
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265 | #if !defined(__mips_n64) |
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266 | MIPS_RW32_COP0(excpc, MIPS_COP_0_EXC_PC); |
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267 | #endif |
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268 | MIPS_RW32_COP0(status, MIPS_COP_0_STATUS); |
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269 | |
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270 | /* XXX: Some of these registers are specific to MIPS32. */ |
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271 | #if !defined(__mips_n64) |
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272 | MIPS_RW32_COP0(entryhi, MIPS_COP_0_TLB_HI); |
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273 | MIPS_RW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); |
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274 | #endif |
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275 | #if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */ |
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276 | MIPS_RW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0); |
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277 | MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1); |
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278 | #endif |
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279 | MIPS_RW32_COP0(prid, MIPS_COP_0_PRID); |
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280 | /* XXX 64-bit? */ |
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281 | MIPS_RW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1); |
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282 | MIPS_RW32_COP0(watchlo, MIPS_COP_0_WATCH_LO); |
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283 | MIPS_RW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1); |
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284 | MIPS_RW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2); |
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285 | MIPS_RW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3); |
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286 | MIPS_RW32_COP0(watchhi, MIPS_COP_0_WATCH_HI); |
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287 | MIPS_RW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1); |
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288 | MIPS_RW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2); |
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289 | MIPS_RW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3); |
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290 | |
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291 | MIPS_RW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0); |
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292 | MIPS_RW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1); |
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293 | MIPS_RW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2); |
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294 | MIPS_RW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3); |
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295 | |
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296 | #undef MIPS_RW32_COP0 |
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297 | #undef MIPS_RW32_COP0_SEL |
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298 | |
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299 | static __inline register_t |
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300 | intr_disable(void) |
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301 | { |
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302 | register_t s; |
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303 | |
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304 | s = mips_rd_status(); |
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305 | mips_wr_status(s & ~MIPS_SR_INT_IE); |
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306 | |
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307 | return (s & MIPS_SR_INT_IE); |
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308 | } |
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309 | |
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310 | static __inline register_t |
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311 | intr_enable(void) |
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312 | { |
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313 | register_t s; |
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314 | |
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315 | s = mips_rd_status(); |
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316 | mips_wr_status(s | MIPS_SR_INT_IE); |
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317 | |
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318 | return (s); |
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319 | } |
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320 | |
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321 | static __inline void |
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322 | intr_restore(register_t ie) |
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323 | { |
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324 | if (ie == MIPS_SR_INT_IE) { |
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325 | intr_enable(); |
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326 | } |
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327 | } |
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328 | |
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329 | static __inline uint32_t |
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330 | set_intr_mask(uint32_t mask) |
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331 | { |
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332 | uint32_t ostatus; |
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333 | |
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334 | ostatus = mips_rd_status(); |
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335 | mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK); |
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336 | mips_wr_status(mask); |
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337 | return (ostatus); |
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338 | } |
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339 | |
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340 | static __inline uint32_t |
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341 | get_intr_mask(void) |
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342 | { |
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343 | |
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344 | return (mips_rd_status() & MIPS_SR_INT_MASK); |
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345 | } |
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346 | |
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347 | static __inline void |
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348 | breakpoint(void) |
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349 | { |
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350 | __asm __volatile ("break"); |
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351 | } |
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352 | |
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353 | #if defined(__GNUC__) && !defined(__mips_o32) |
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354 | static inline uint64_t |
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355 | mips3_ld(const volatile uint64_t *va) |
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356 | { |
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357 | uint64_t rv; |
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358 | |
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359 | #if defined(_LP64) |
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360 | rv = *va; |
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361 | #else |
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362 | __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); |
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363 | #endif |
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364 | |
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365 | return (rv); |
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366 | } |
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367 | |
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368 | static inline void |
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369 | mips3_sd(volatile uint64_t *va, uint64_t v) |
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370 | { |
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371 | #if defined(_LP64) |
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372 | *va = v; |
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373 | #else |
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374 | __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); |
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375 | #endif |
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376 | } |
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377 | #else |
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378 | uint64_t mips3_ld(volatile uint64_t *va); |
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379 | void mips3_sd(volatile uint64_t *, uint64_t); |
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380 | #endif /* __GNUC__ */ |
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381 | |
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382 | #endif /* _KERNEL */ |
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383 | |
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384 | #define readb(va) (*(volatile uint8_t *) (va)) |
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385 | #define readw(va) (*(volatile uint16_t *) (va)) |
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386 | #define readl(va) (*(volatile uint32_t *) (va)) |
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387 | |
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388 | #define writeb(va, d) (*(volatile uint8_t *) (va) = (d)) |
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389 | #define writew(va, d) (*(volatile uint16_t *) (va) = (d)) |
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390 | #define writel(va, d) (*(volatile uint32_t *) (va) = (d)) |
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391 | |
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392 | /* |
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393 | * I/O macros. |
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394 | */ |
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395 | |
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396 | #define outb(a,v) (*(volatile unsigned char*)(a) = (v)) |
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397 | #define out8(a,v) (*(volatile unsigned char*)(a) = (v)) |
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398 | #define outw(a,v) (*(volatile unsigned short*)(a) = (v)) |
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399 | #define out16(a,v) outw(a,v) |
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400 | #define outl(a,v) (*(volatile unsigned int*)(a) = (v)) |
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401 | #define out32(a,v) outl(a,v) |
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402 | #define inb(a) (*(volatile unsigned char*)(a)) |
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403 | #define in8(a) (*(volatile unsigned char*)(a)) |
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404 | #define inw(a) (*(volatile unsigned short*)(a)) |
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405 | #define in16(a) inw(a) |
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406 | #define inl(a) (*(volatile unsigned int*)(a)) |
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407 | #define in32(a) inl(a) |
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408 | |
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409 | #define out8rb(a,v) (*(volatile unsigned char*)(a) = (v)) |
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410 | #define out16rb(a,v) (__out16rb((volatile uint16_t *)(a), v)) |
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411 | #define out32rb(a,v) (__out32rb((volatile uint32_t *)(a), v)) |
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412 | #define in8rb(a) (*(volatile unsigned char*)(a)) |
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413 | #define in16rb(a) (__in16rb((volatile uint16_t *)(a))) |
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414 | #define in32rb(a) (__in32rb((volatile uint32_t *)(a))) |
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415 | |
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416 | #define _swap_(x) (((x) >> 24) | ((x) << 24) | \ |
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417 | (((x) >> 8) & 0xff00) | (((x) & 0xff00) << 8)) |
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418 | |
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419 | static __inline void __out32rb(volatile uint32_t *, uint32_t); |
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420 | static __inline void __out16rb(volatile uint16_t *, uint16_t); |
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421 | static __inline uint32_t __in32rb(volatile uint32_t *); |
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422 | static __inline uint16_t __in16rb(volatile uint16_t *); |
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423 | |
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424 | static __inline void |
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425 | __out32rb(volatile uint32_t *a, uint32_t v) |
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426 | { |
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427 | uint32_t _v_ = v; |
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428 | |
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429 | _v_ = _swap_(_v_); |
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430 | out32(a, _v_); |
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431 | } |
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432 | |
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433 | static __inline void |
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434 | __out16rb(volatile uint16_t *a, uint16_t v) |
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435 | { |
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436 | uint16_t _v_; |
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437 | |
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438 | _v_ = ((v >> 8) & 0xff) | (v << 8); |
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439 | out16(a, _v_); |
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440 | } |
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441 | |
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442 | static __inline uint32_t |
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443 | __in32rb(volatile uint32_t *a) |
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444 | { |
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445 | uint32_t _v_; |
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446 | |
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447 | _v_ = in32(a); |
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448 | _v_ = _swap_(_v_); |
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449 | return _v_; |
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450 | } |
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451 | |
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452 | static __inline uint16_t |
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453 | __in16rb(volatile uint16_t *a) |
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454 | { |
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455 | uint16_t _v_; |
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456 | |
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457 | _v_ = in16(a); |
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458 | _v_ = ((_v_ >> 8) & 0xff) | (_v_ << 8); |
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459 | return _v_; |
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460 | } |
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461 | |
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462 | void insb(uint8_t *, uint8_t *,int); |
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463 | void insw(uint16_t *, uint16_t *,int); |
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464 | void insl(uint32_t *, uint32_t *,int); |
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465 | void outsb(uint8_t *, const uint8_t *,int); |
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466 | void outsw(uint16_t *, const uint16_t *,int); |
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467 | void outsl(uint32_t *, const uint32_t *,int); |
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468 | u_int loadandclear(volatile u_int *addr); |
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469 | |
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470 | #endif /* !_MACHINE_CPUFUNC_H_ */ |
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