source: rtems-libbsd/freebsd/sys/dev/usb/net/if_auereg.h @ d145449

55-freebsd-126-freebsd-12
Last change on this file since d145449 was d145449, checked in by Christian Mauderer <Christian.Mauderer@…>, on 11/14/16 at 12:30:48

Import USB and USB WLAN from FreeBSD.
  • Property mode set to 100644
File size: 6.9 KB
Line 
1/*-
2 * Copyright (c) 1997, 1998, 1999
3 *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 *    must display the following acknowledgement:
15 *      This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 *    may be used to endorse or promote products derived from this software
18 *    without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD$
33 */
34
35/*
36 * Register definitions for ADMtek Pegasus AN986 USB to Ethernet
37 * chip. The Pegasus uses a total of four USB endpoints: the control
38 * endpoint (0), a bulk read endpoint for receiving packets (1),
39 * a bulk write endpoint for sending packets (2) and an interrupt
40 * endpoint for passing RX and TX status (3). Endpoint 0 is used
41 * to read and write the ethernet module's registers. All registers
42 * are 8 bits wide.
43 *
44 * Packet transfer is done in 64 byte chunks. The last chunk in a
45 * transfer is denoted by having a length less that 64 bytes. For
46 * the RX case, the data includes an optional RX status word.
47 */
48
49#define AUE_UR_READREG          0xF0
50#define AUE_UR_WRITEREG         0xF1
51
52#define AUE_CONFIG_INDEX        0       /* config number 1 */
53#define AUE_IFACE_IDX           0
54
55/*
56 * Note that while the ADMtek technically has four endpoints, the control
57 * endpoint (endpoint 0) is regarded as special by the USB code and drivers
58 * don't have direct access to it (we access it using usbd_do_request()
59 * when reading/writing registers.  Consequently, our endpoint indexes
60 * don't match those in the ADMtek Pegasus manual: we consider the RX data
61 * endpoint to be index 0 and work up from there.
62 */
63enum {
64        AUE_BULK_DT_WR,
65        AUE_BULK_DT_RD,
66        AUE_INTR_DT_RD,
67        AUE_N_TRANSFER,
68};
69
70#define AUE_INTR_PKTLEN         0x8
71
72#define AUE_CTL0                0x00
73#define AUE_CTL1                0x01
74#define AUE_CTL2                0x02
75#define AUE_MAR0                0x08
76#define AUE_MAR1                0x09
77#define AUE_MAR2                0x0A
78#define AUE_MAR3                0x0B
79#define AUE_MAR4                0x0C
80#define AUE_MAR5                0x0D
81#define AUE_MAR6                0x0E
82#define AUE_MAR7                0x0F
83#define AUE_MAR                 AUE_MAR0
84#define AUE_PAR0                0x10
85#define AUE_PAR1                0x11
86#define AUE_PAR2                0x12
87#define AUE_PAR3                0x13
88#define AUE_PAR4                0x14
89#define AUE_PAR5                0x15
90#define AUE_PAR                 AUE_PAR0
91#define AUE_PAUSE0              0x18
92#define AUE_PAUSE1              0x19
93#define AUE_PAUSE               AUE_PAUSE0
94#define AUE_RX_FLOWCTL_CNT      0x1A
95#define AUE_RX_FLOWCTL_FIFO     0x1B
96#define AUE_REG_1D              0x1D
97#define AUE_EE_REG              0x20
98#define AUE_EE_DATA0            0x21
99#define AUE_EE_DATA1            0x22
100#define AUE_EE_DATA             AUE_EE_DATA0
101#define AUE_EE_CTL              0x23
102#define AUE_PHY_ADDR            0x25
103#define AUE_PHY_DATA0           0x26
104#define AUE_PHY_DATA1           0x27
105#define AUE_PHY_DATA            AUE_PHY_DATA0
106#define AUE_PHY_CTL             0x28
107#define AUE_USB_STS             0x2A
108#define AUE_TXSTAT0             0x2B
109#define AUE_TXSTAT1             0x2C
110#define AUE_TXSTAT              AUE_TXSTAT0
111#define AUE_RXSTAT              0x2D
112#define AUE_PKTLOST0            0x2E
113#define AUE_PKTLOST1            0x2F
114#define AUE_PKTLOST             AUE_PKTLOST0
115
116#define AUE_REG_7B              0x7B
117#define AUE_GPIO0               0x7E
118#define AUE_GPIO1               0x7F
119#define AUE_REG_81              0x81
120
121#define AUE_CTL0_INCLUDE_RXCRC  0x01
122#define AUE_CTL0_ALLMULTI       0x02
123#define AUE_CTL0_STOP_BACKOFF   0x04
124#define AUE_CTL0_RXSTAT_APPEND  0x08
125#define AUE_CTL0_WAKEON_ENB     0x10
126#define AUE_CTL0_RXPAUSE_ENB    0x20
127#define AUE_CTL0_RX_ENB         0x40
128#define AUE_CTL0_TX_ENB         0x80
129
130#define AUE_CTL1_HOMELAN        0x04
131#define AUE_CTL1_RESETMAC       0x08
132#define AUE_CTL1_SPEEDSEL       0x10    /* 0 = 10mbps, 1 = 100mbps */
133#define AUE_CTL1_DUPLEX         0x20    /* 0 = half, 1 = full */
134#define AUE_CTL1_DELAYHOME      0x40
135
136#define AUE_CTL2_EP3_CLR        0x01    /* reading EP3 clrs status regs */
137#define AUE_CTL2_RX_BADFRAMES   0x02
138#define AUE_CTL2_RX_PROMISC     0x04
139#define AUE_CTL2_LOOPBACK       0x08
140#define AUE_CTL2_EEPROMWR_ENB   0x10
141#define AUE_CTL2_EEPROM_LOAD    0x20
142
143#define AUE_EECTL_WRITE         0x01
144#define AUE_EECTL_READ          0x02
145#define AUE_EECTL_DONE          0x04
146
147#define AUE_PHYCTL_PHYREG       0x1F
148#define AUE_PHYCTL_WRITE        0x20
149#define AUE_PHYCTL_READ         0x40
150#define AUE_PHYCTL_DONE         0x80
151
152#define AUE_USBSTS_SUSPEND      0x01
153#define AUE_USBSTS_RESUME       0x02
154
155#define AUE_TXSTAT0_JABTIMO     0x04
156#define AUE_TXSTAT0_CARLOSS     0x08
157#define AUE_TXSTAT0_NOCARRIER   0x10
158#define AUE_TXSTAT0_LATECOLL    0x20
159#define AUE_TXSTAT0_EXCESSCOLL  0x40
160#define AUE_TXSTAT0_UNDERRUN    0x80
161
162#define AUE_TXSTAT1_PKTCNT      0x0F
163#define AUE_TXSTAT1_FIFO_EMPTY  0x40
164#define AUE_TXSTAT1_FIFO_FULL   0x80
165
166#define AUE_RXSTAT_OVERRUN      0x01
167#define AUE_RXSTAT_PAUSE        0x02
168
169#define AUE_GPIO_IN0            0x01
170#define AUE_GPIO_OUT0           0x02
171#define AUE_GPIO_SEL0           0x04
172#define AUE_GPIO_IN1            0x08
173#define AUE_GPIO_OUT1           0x10
174#define AUE_GPIO_SEL1           0x20
175
176#define AUE_TIMEOUT             100     /* 10*ms */
177#define AUE_MIN_FRAMELEN        60
178
179#define AUE_RXSTAT_MCAST        0x01
180#define AUE_RXSTAT_GIANT        0x02
181#define AUE_RXSTAT_RUNT         0x04
182#define AUE_RXSTAT_CRCERR       0x08
183#define AUE_RXSTAT_DRIBBLE      0x10
184#define AUE_RXSTAT_MASK         0x1E
185
186#define GET_MII(sc)             uether_getmii(&(sc)->sc_ue)
187
188struct aue_intrpkt {
189        uint8_t aue_txstat0;
190        uint8_t aue_txstat1;
191        uint8_t aue_rxstat;
192        uint8_t aue_rxlostpkt0;
193        uint8_t aue_rxlostpkt1;
194        uint8_t aue_wakeupstat;
195        uint8_t aue_rsvd;
196} __packed;
197
198struct aue_rxpkt {
199        uint16_t aue_pktlen;
200        uint8_t aue_rxstat;
201        uint8_t pad;
202} __packed;
203
204struct aue_softc {
205        struct usb_ether        sc_ue;
206        struct mtx              sc_mtx;
207        struct usb_xfer *sc_xfer[AUE_N_TRANSFER];
208
209        int                     sc_flags;
210#define AUE_FLAG_LSYS           0x0001  /* use Linksys reset */
211#define AUE_FLAG_PNA            0x0002  /* has Home PNA */
212#define AUE_FLAG_PII            0x0004  /* Pegasus II chip */
213#define AUE_FLAG_LINK           0x0008  /* wait for link to come up */
214#define AUE_FLAG_VER_2          0x0200  /* chip is version 2 */
215#define AUE_FLAG_DUAL_PHY       0x0400  /* chip has two transcivers */
216};
217
218#define AUE_LOCK(_sc)           mtx_lock(&(_sc)->sc_mtx)
219#define AUE_UNLOCK(_sc)         mtx_unlock(&(_sc)->sc_mtx)
220#define AUE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t)
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