Context Navigation

source: rtems-libbsd/freebsd/sys/dev/usb/controller/musb_otg.c @ bd3c01a

55-freebsd-126-freebsd-12

Last change on this file since bd3c01a was bd3c01a, checked in by Sichen Zhao <1473996754@…>, on 07/13/17 at 02:24:04
Import am335x usb driver file from FreeBSD.
Property mode set to `100644`
File size: 96.5 KB

Line
1	#include <machine/rtems-bsd-kernel-space.h>
2
3	/* $FreeBSD$ */
4	/*-
5	* Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions
9	* are met:
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	*
16	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26	* SUCH DAMAGE.
27	*/
28
29	/*
30	* Thanks to Mentor Graphics for providing a reference driver for this USB chip
31	* at their homepage.
32	*/
33
34	/*
35	* This file contains the driver for the Mentor Graphics Inventra USB
36	* 2.0 High Speed Dual-Role controller.
37	*
38	*/
39
40	#ifdef USB_GLOBAL_INCLUDE_FILE
41	#include USB_GLOBAL_INCLUDE_FILE
42	#else
43	#include <sys/stdint.h>
44	#include <sys/stddef.h>
45	#include <sys/param.h>
46	#include <sys/queue.h>
47	#include <sys/types.h>
48	#include <sys/systm.h>
49	#include <sys/kernel.h>
50	#include <sys/bus.h>
51	#include <sys/module.h>
52	#include <sys/lock.h>
53	#include <sys/mutex.h>
54	#include <sys/condvar.h>
55	#include <sys/sysctl.h>
56	#include <sys/sx.h>
57	#include <rtems/bsd/sys/unistd.h>
58	#include <sys/callout.h>
59	#include <sys/malloc.h>
60	#include <sys/priv.h>
61
62	#include <dev/usb/usb.h>
63	#include <dev/usb/usbdi.h>
64
65	#define USB_DEBUG_VAR musbotgdebug
66
67	#include <dev/usb/usb_core.h>
68	#include <dev/usb/usb_debug.h>
69	#include <dev/usb/usb_busdma.h>
70	#include <dev/usb/usb_process.h>
71	#include <dev/usb/usb_transfer.h>
72	#include <dev/usb/usb_device.h>
73	#include <dev/usb/usb_hub.h>
74	#include <dev/usb/usb_util.h>
75
76	#include <dev/usb/usb_controller.h>
77	#include <dev/usb/usb_bus.h>
78	#endif /* USB_GLOBAL_INCLUDE_FILE */
79
80	#include <dev/usb/controller/musb_otg.h>
81
82	#define MUSBOTG_INTR_ENDPT 1
83
84	#define MUSBOTG_BUS2SC(bus) \
85	((struct musbotg_softc )(((uint8_t )(bus)) - \
86	USB_P2U(&(((struct musbotg_softc *)0)->sc_bus))))
87
88	#define MUSBOTG_PC2SC(pc) \
89	MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
90
91	#ifdef USB_DEBUG
92	static int musbotgdebug = 0;
93
94	static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg");
95	SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RWTUN,
96	&musbotgdebug, 0, "Debug level");
97	#endif
98
99	#define MAX_NAK_TO 16
100
101	/* prototypes */
102
103	static const struct usb_bus_methods musbotg_bus_methods;
104	static const struct usb_pipe_methods musbotg_device_bulk_methods;
105	static const struct usb_pipe_methods musbotg_device_ctrl_methods;
106	static const struct usb_pipe_methods musbotg_device_intr_methods;
107	static const struct usb_pipe_methods musbotg_device_isoc_methods;
108
109	/* Control transfers: Device mode */
110	static musbotg_cmd_t musbotg_dev_ctrl_setup_rx;
111	static musbotg_cmd_t musbotg_dev_ctrl_data_rx;
112	static musbotg_cmd_t musbotg_dev_ctrl_data_tx;
113	static musbotg_cmd_t musbotg_dev_ctrl_status;
114
115	/* Control transfers: Host mode */
116	static musbotg_cmd_t musbotg_host_ctrl_setup_tx;
117	static musbotg_cmd_t musbotg_host_ctrl_data_rx;
118	static musbotg_cmd_t musbotg_host_ctrl_data_tx;
119	static musbotg_cmd_t musbotg_host_ctrl_status_rx;
120	static musbotg_cmd_t musbotg_host_ctrl_status_tx;
121
122	/* Bulk, Interrupt, Isochronous: Device mode */
123	static musbotg_cmd_t musbotg_dev_data_rx;
124	static musbotg_cmd_t musbotg_dev_data_tx;
125
126	/* Bulk, Interrupt, Isochronous: Host mode */
127	static musbotg_cmd_t musbotg_host_data_rx;
128	static musbotg_cmd_t musbotg_host_data_tx;
129
130	static void musbotg_device_done(struct usb_xfer *, usb_error_t);
131	static void musbotg_do_poll(struct usb_bus *);
132	static void musbotg_standard_done(struct usb_xfer *);
133	static void musbotg_interrupt_poll(struct musbotg_softc *);
134	static void musbotg_root_intr(struct musbotg_softc *);
135	static int musbotg_channel_alloc(struct musbotg_softc , struct musbotg_td td, uint8_t);
136	static void musbotg_channel_free(struct musbotg_softc , struct musbotg_td td);
137	static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on);
138
139	/*
140	* Here is a configuration that the chip supports.
141	*/
142	static const struct usb_hw_ep_profile musbotg_ep_profile[1] = {
143
144	[0] = {
145	.max_in_frame_size = 64,/* fixed */
146	.max_out_frame_size = 64, /* fixed */
147	.is_simplex = 1,
148	.support_control = 1,
149	}
150	};
151
152	static int
153	musbotg_channel_alloc(struct musbotg_softc sc, struct musbotg_td td, uint8_t is_tx)
154	{
155	int ch;
156	int ep;
157
158	ep = td->ep_no;
159
160	/* In device mode each EP got its own channel */
161	if (sc->sc_mode == MUSB2_DEVICE_MODE) {
162	musbotg_ep_int_set(sc, ep, 1);
163	return (ep);
164	}
165
166	/*
167	* All control transactions go through EP0
168	*/
169	if (ep == 0) {
170	if (sc->sc_channel_mask & (1 << 0))
171	return (-1);
172	sc->sc_channel_mask \|= (1 << 0);
173	musbotg_ep_int_set(sc, ep, 1);
174	return (0);
175	}
176
177	for (ch = sc->sc_ep_max; ch != 0; ch--) {
178	if (sc->sc_channel_mask & (1 << ch))
179	continue;
180
181	/* check FIFO size requirement */
182	if (is_tx) {
183	if (td->max_frame_size >
184	sc->sc_hw_ep_profile[ch].max_in_frame_size)
185	continue;
186	} else {
187	if (td->max_frame_size >
188	sc->sc_hw_ep_profile[ch].max_out_frame_size)
189	continue;
190	}
191	sc->sc_channel_mask \|= (1 << ch);
192	musbotg_ep_int_set(sc, ch, 1);
193	return (ch);
194	}
195
196	DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask);
197
198	return (-1);
199	}
200
201	static void
202	musbotg_channel_free(struct musbotg_softc sc, struct musbotg_td td)
203	{
204
205	DPRINTFN(1, "ep_no=%d\n", td->channel);
206
207	if (sc->sc_mode == MUSB2_DEVICE_MODE)
208	return;
209
210	if (td == NULL)
211	return;
212	if (td->channel == -1)
213	return;
214
215	musbotg_ep_int_set(sc, td->channel, 0);
216	sc->sc_channel_mask &= ~(1 << td->channel);
217
218	td->channel = -1;
219	}
220
221	static void
222	musbotg_get_hw_ep_profile(struct usb_device *udev,
223	const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
224	{
225	struct musbotg_softc *sc;
226
227	sc = MUSBOTG_BUS2SC(udev->bus);
228
229	if (ep_addr == 0) {
230	/* control endpoint */
231	*ppf = musbotg_ep_profile;
232	} else if (ep_addr <= sc->sc_ep_max) {
233	/* other endpoints */
234	*ppf = sc->sc_hw_ep_profile + ep_addr;
235	} else {
236	*ppf = NULL;
237	}
238	}
239
240	static void
241	musbotg_clocks_on(struct musbotg_softc *sc)
242	{
243	if (sc->sc_flags.clocks_off &&
244	sc->sc_flags.port_powered) {
245
246	DPRINTFN(4, "\n");
247
248	if (sc->sc_clocks_on) {
249	(sc->sc_clocks_on) (sc->sc_clocks_arg);
250	}
251	sc->sc_flags.clocks_off = 0;
252
253	/* XXX enable Transceiver */
254	}
255	}
256
257	static void
258	musbotg_clocks_off(struct musbotg_softc *sc)
259	{
260	if (!sc->sc_flags.clocks_off) {
261
262	DPRINTFN(4, "\n");
263
264	/* XXX disable Transceiver */
265
266	if (sc->sc_clocks_off) {
267	(sc->sc_clocks_off) (sc->sc_clocks_arg);
268	}
269	sc->sc_flags.clocks_off = 1;
270	}
271	}
272
273	static void
274	musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
275	{
276	uint8_t temp;
277
278	temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
279	if (on)
280	temp \|= MUSB2_MASK_SOFTC;
281	else
282	temp &= ~MUSB2_MASK_SOFTC;
283
284	MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
285	}
286
287	static void
288	musbotg_pull_up(struct musbotg_softc *sc)
289	{
290	/* pullup D+, if possible */
291
292	if (!sc->sc_flags.d_pulled_up &&
293	sc->sc_flags.port_powered) {
294	sc->sc_flags.d_pulled_up = 1;
295	musbotg_pull_common(sc, 1);
296	}
297	}
298
299	static void
300	musbotg_pull_down(struct musbotg_softc *sc)
301	{
302	/* pulldown D+, if possible */
303
304	if (sc->sc_flags.d_pulled_up) {
305	sc->sc_flags.d_pulled_up = 0;
306	musbotg_pull_common(sc, 0);
307	}
308	}
309
310	static void
311	musbotg_suspend_host(struct musbotg_softc *sc)
312	{
313	uint8_t temp;
314
315	if (sc->sc_flags.status_suspend) {
316	return;
317	}
318
319	temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
320	temp \|= MUSB2_MASK_SUSPMODE;
321	MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
322	sc->sc_flags.status_suspend = 1;
323	}
324
325	static void
326	musbotg_wakeup_host(struct musbotg_softc *sc)
327	{
328	uint8_t temp;
329
330	if (!(sc->sc_flags.status_suspend)) {
331	return;
332	}
333
334	temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
335	temp &= ~MUSB2_MASK_SUSPMODE;
336	temp \|= MUSB2_MASK_RESUME;
337	MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
338
339	/* wait 20 milliseconds */
340	/* Wait for reset to complete. */
341	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
342
343	temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
344	temp &= ~MUSB2_MASK_RESUME;
345	MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
346
347	sc->sc_flags.status_suspend = 0;
348	}
349
350	static void
351	musbotg_wakeup_peer(struct musbotg_softc *sc)
352	{
353	uint8_t temp;
354
355	if (!(sc->sc_flags.status_suspend)) {
356	return;
357	}
358
359	temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
360	temp \|= MUSB2_MASK_RESUME;
361	MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
362
363	/* wait 8 milliseconds */
364	/* Wait for reset to complete. */
365	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
366
367	temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
368	temp &= ~MUSB2_MASK_RESUME;
369	MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
370	}
371
372	static void
373	musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
374	{
375	DPRINTFN(4, "addr=%d\n", addr);
376	addr &= 0x7F;
377	MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr);
378	}
379
380	static uint8_t
381	musbotg_dev_ctrl_setup_rx(struct musbotg_td *td)
382	{
383	struct musbotg_softc *sc;
384	struct usb_device_request req;
385	uint16_t count;
386	uint8_t csr;
387
388	/* get pointer to softc */
389	sc = MUSBOTG_PC2SC(td->pc);
390
391	if (td->channel == -1)
392	td->channel = musbotg_channel_alloc(sc, td, 0);
393
394	/* EP0 is busy, wait */
395	if (td->channel == -1)
396	return (1);
397
398	DPRINTFN(1, "ep_no=%d\n", td->channel);
399
400	/* select endpoint 0 */
401	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
402
403	/* read out FIFO status */
404	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
405
406	DPRINTFN(4, "csr=0x%02x\n", csr);
407
408	/*
409	* NOTE: If DATAEND is set we should not call the
410	* callback, hence the status stage is not complete.
411	*/
412	if (csr & MUSB2_MASK_CSR0L_DATAEND) {
413	/* do not stall at this point */
414	td->did_stall = 1;
415	/* wait for interrupt */
416	DPRINTFN(1, "CSR0 DATAEND\n");
417	goto not_complete;
418	}
419
420	if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
421	/* clear SENTSTALL */
422	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
423	/* get latest status */
424	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
425	/* update EP0 state */
426	sc->sc_ep0_busy = 0;
427	}
428	if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
429	/* clear SETUPEND */
430	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
431	MUSB2_MASK_CSR0L_SETUPEND_CLR);
432	/* get latest status */
433	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
434	/* update EP0 state */
435	sc->sc_ep0_busy = 0;
436	}
437	if (sc->sc_ep0_busy) {
438	DPRINTFN(1, "EP0 BUSY\n");
439	goto not_complete;
440	}
441	if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
442	goto not_complete;
443	}
444	/* get the packet byte count */
445	count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
446
447	/* verify data length */
448	if (count != td->remainder) {
449	DPRINTFN(1, "Invalid SETUP packet "
450	"length, %d bytes\n", count);
451	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
452	MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
453	/* don't clear stall */
454	td->did_stall = 1;
455	goto not_complete;
456	}
457	if (count != sizeof(req)) {
458	DPRINTFN(1, "Unsupported SETUP packet "
459	"length, %d bytes\n", count);
460	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
461	MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
462	/* don't clear stall */
463	td->did_stall = 1;
464	goto not_complete;
465	}
466	/* clear did stall flag */
467	td->did_stall = 0;
468
469	/* receive data */
470	bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
471	MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
472
473	/* copy data into real buffer */
474	usbd_copy_in(td->pc, 0, &req, sizeof(req));
475
476	td->offset = sizeof(req);
477	td->remainder = 0;
478
479	/* set pending command */
480	sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
481
482	/* we need set stall or dataend after this */
483	sc->sc_ep0_busy = 1;
484
485	/* sneak peek the set address */
486	if ((req.bmRequestType == UT_WRITE_DEVICE) &&
487	(req.bRequest == UR_SET_ADDRESS)) {
488	sc->sc_dv_addr = req.wValue[0] & 0x7F;
489	} else {
490	sc->sc_dv_addr = 0xFF;
491	}
492
493	musbotg_channel_free(sc, td);
494	return (0); /* complete */
495
496	not_complete:
497	/* abort any ongoing transfer */
498	if (!td->did_stall) {
499	DPRINTFN(4, "stalling\n");
500	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
501	MUSB2_MASK_CSR0L_SENDSTALL);
502	td->did_stall = 1;
503	}
504	return (1); /* not complete */
505	}
506
507	static uint8_t
508	musbotg_host_ctrl_setup_tx(struct musbotg_td *td)
509	{
510	struct musbotg_softc *sc;
511	struct usb_device_request req;
512	uint8_t csr, csrh;
513
514	/* get pointer to softc */
515	sc = MUSBOTG_PC2SC(td->pc);
516
517	if (td->channel == -1)
518	td->channel = musbotg_channel_alloc(sc, td, 1);
519
520	/* EP0 is busy, wait */
521	if (td->channel == -1)
522	return (1);
523
524	DPRINTFN(1, "ep_no=%d\n", td->channel);
525
526	/* select endpoint 0 */
527	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
528
529	/* read out FIFO status */
530	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
531	DPRINTFN(4, "csr=0x%02x\n", csr);
532
533	/* Not ready yet yet */
534	if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
535	return (1);
536
537	/* Failed */
538	if (csr & (MUSB2_MASK_CSR0L_RXSTALL \|
539	MUSB2_MASK_CSR0L_ERROR))
540	{
541	/* Clear status bit */
542	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
543	DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
544	td->error = 1;
545	}
546
547	if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
548	DPRINTFN(1, "NAK timeout\n");
549
550	if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
551	csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
552	csrh \|= MUSB2_MASK_CSR0H_FFLUSH;
553	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
554	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
555	if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
556	csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
557	csrh \|= MUSB2_MASK_CSR0H_FFLUSH;
558	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
559	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
560	}
561	}
562
563	csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
564	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
565
566	td->error = 1;
567	}
568
569	if (td->error) {
570	musbotg_channel_free(sc, td);
571	return (0);
572	}
573
574	/* Fifo is not empty and there is no NAK timeout */
575	if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
576	return (1);
577
578	/* check if we are complete */
579	if (td->remainder == 0) {
580	/* we are complete */
581	musbotg_channel_free(sc, td);
582	return (0);
583	}
584
585	/* copy data into real buffer */
586	usbd_copy_out(td->pc, 0, &req, sizeof(req));
587
588	/* send data */
589	bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
590	MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
591
592	/* update offset and remainder */
593	td->offset += sizeof(req);
594	td->remainder -= sizeof(req);
595
596
597	MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
598	MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
599	MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
600	MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
601	MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
602
603	/* write command */
604	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
605	MUSB2_MASK_CSR0L_TXPKTRDY \|
606	MUSB2_MASK_CSR0L_SETUPPKT);
607
608	/* Just to be consistent, not used above */
609	td->transaction_started = 1;
610
611	return (1); /* in progress */
612	}
613
614	/* Control endpoint only data handling functions (RX/TX/SYNC) */
615
616	static uint8_t
617	musbotg_dev_ctrl_data_rx(struct musbotg_td *td)
618	{
619	struct usb_page_search buf_res;
620	struct musbotg_softc *sc;
621	uint16_t count;
622	uint8_t csr;
623	uint8_t got_short;
624
625	/* get pointer to softc */
626	sc = MUSBOTG_PC2SC(td->pc);
627
628	/* select endpoint 0 */
629	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
630
631	/* check if a command is pending */
632	if (sc->sc_ep0_cmd) {
633	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
634	sc->sc_ep0_cmd = 0;
635	}
636	/* read out FIFO status */
637	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
638
639	DPRINTFN(4, "csr=0x%02x\n", csr);
640
641	got_short = 0;
642
643	if (csr & (MUSB2_MASK_CSR0L_SETUPEND \|
644	MUSB2_MASK_CSR0L_SENTSTALL)) {
645	if (td->remainder == 0) {
646	/*
647	* We are actually complete and have
648	* received the next SETUP
649	*/
650	DPRINTFN(4, "faking complete\n");
651	return (0); /* complete */
652	}
653	/*
654	* USB Host Aborted the transfer.
655	*/
656	td->error = 1;
657	return (0); /* complete */
658	}
659	if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
660	return (1); /* not complete */
661	}
662	/* get the packet byte count */
663	count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
664
665	/* verify the packet byte count */
666	if (count != td->max_frame_size) {
667	if (count < td->max_frame_size) {
668	/* we have a short packet */
669	td->short_pkt = 1;
670	got_short = 1;
671	} else {
672	/* invalid USB packet */
673	td->error = 1;
674	return (0); /* we are complete */
675	}
676	}
677	/* verify the packet byte count */
678	if (count > td->remainder) {
679	/* invalid USB packet */
680	td->error = 1;
681	return (0); /* we are complete */
682	}
683	while (count > 0) {
684	uint32_t temp;
685
686	usbd_get_page(td->pc, td->offset, &buf_res);
687
688	/* get correct length */
689	if (buf_res.length > count) {
690	buf_res.length = count;
691	}
692	/* check for unaligned memory address */
693	if (USB_P2U(buf_res.buffer) & 3) {
694
695	temp = count & ~3;
696
697	if (temp) {
698	/* receive data 4 bytes at a time */
699	bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
700	MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
701	temp / 4);
702	}
703	temp = count & 3;
704	if (temp) {
705	/* receive data 1 byte at a time */
706	bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
707	MUSB2_REG_EPFIFO(0),
708	(void *)(&sc->sc_bounce_buf[count / 4]), temp);
709	}
710	usbd_copy_in(td->pc, td->offset,
711	sc->sc_bounce_buf, count);
712
713	/* update offset and remainder */
714	td->offset += count;
715	td->remainder -= count;
716	break;
717	}
718	/* check if we can optimise */
719	if (buf_res.length >= 4) {
720
721	/* receive data 4 bytes at a time */
722	bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
723	MUSB2_REG_EPFIFO(0), buf_res.buffer,
724	buf_res.length / 4);
725
726	temp = buf_res.length & ~3;
727
728	/* update counters */
729	count -= temp;
730	td->offset += temp;
731	td->remainder -= temp;
732	continue;
733	}
734	/* receive data */
735	bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
736	MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
737
738	/* update counters */
739	count -= buf_res.length;
740	td->offset += buf_res.length;
741	td->remainder -= buf_res.length;
742	}
743
744	/* check if we are complete */
745	if ((td->remainder == 0) \|\| got_short) {
746	if (td->short_pkt) {
747	/* we are complete */
748	sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
749	return (0);
750	}
751	/* else need to receive a zero length packet */
752	}
753	/* write command - need more data */
754	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
755	MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
756	return (1); /* not complete */
757	}
758
759	static uint8_t
760	musbotg_dev_ctrl_data_tx(struct musbotg_td *td)
761	{
762	struct usb_page_search buf_res;
763	struct musbotg_softc *sc;
764	uint16_t count;
765	uint8_t csr;
766
767	/* get pointer to softc */
768	sc = MUSBOTG_PC2SC(td->pc);
769
770	/* select endpoint 0 */
771	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
772
773	/* check if a command is pending */
774	if (sc->sc_ep0_cmd) {
775	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
776	sc->sc_ep0_cmd = 0;
777	}
778	/* read out FIFO status */
779	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
780
781	DPRINTFN(4, "csr=0x%02x\n", csr);
782
783	if (csr & (MUSB2_MASK_CSR0L_SETUPEND \|
784	MUSB2_MASK_CSR0L_SENTSTALL)) {
785	/*
786	* The current transfer was aborted
787	* by the USB Host
788	*/
789	td->error = 1;
790	return (0); /* complete */
791	}
792	if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
793	return (1); /* not complete */
794	}
795	count = td->max_frame_size;
796	if (td->remainder < count) {
797	/* we have a short packet */
798	td->short_pkt = 1;
799	count = td->remainder;
800	}
801	while (count > 0) {
802	uint32_t temp;
803
804	usbd_get_page(td->pc, td->offset, &buf_res);
805
806	/* get correct length */
807	if (buf_res.length > count) {
808	buf_res.length = count;
809	}
810	/* check for unaligned memory address */
811	if (USB_P2U(buf_res.buffer) & 3) {
812
813	usbd_copy_out(td->pc, td->offset,
814	sc->sc_bounce_buf, count);
815
816	temp = count & ~3;
817
818	if (temp) {
819	/* transmit data 4 bytes at a time */
820	bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
821	MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
822	temp / 4);
823	}
824	temp = count & 3;
825	if (temp) {
826	/* receive data 1 byte at a time */
827	bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
828	MUSB2_REG_EPFIFO(0),
829	((void *)&sc->sc_bounce_buf[count / 4]), temp);
830	}
831	/* update offset and remainder */
832	td->offset += count;
833	td->remainder -= count;
834	break;
835	}
836	/* check if we can optimise */
837	if (buf_res.length >= 4) {
838
839	/* transmit data 4 bytes at a time */
840	bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
841	MUSB2_REG_EPFIFO(0), buf_res.buffer,
842	buf_res.length / 4);
843
844	temp = buf_res.length & ~3;
845
846	/* update counters */
847	count -= temp;
848	td->offset += temp;
849	td->remainder -= temp;
850	continue;
851	}
852	/* transmit data */
853	bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
854	MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
855
856	/* update counters */
857	count -= buf_res.length;
858	td->offset += buf_res.length;
859	td->remainder -= buf_res.length;
860	}
861
862	/* check remainder */
863	if (td->remainder == 0) {
864	if (td->short_pkt) {
865	sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY;
866	return (0); /* complete */
867	}
868	/* else we need to transmit a short packet */
869	}
870	/* write command */
871	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
872	MUSB2_MASK_CSR0L_TXPKTRDY);
873
874	return (1); /* not complete */
875	}
876
877	static uint8_t
878	musbotg_host_ctrl_data_rx(struct musbotg_td *td)
879	{
880	struct usb_page_search buf_res;
881	struct musbotg_softc *sc;
882	uint16_t count;
883	uint8_t csr;
884	uint8_t got_short;
885
886	/* get pointer to softc */
887	sc = MUSBOTG_PC2SC(td->pc);
888
889	if (td->channel == -1)
890	td->channel = musbotg_channel_alloc(sc, td, 0);
891
892	/* EP0 is busy, wait */
893	if (td->channel == -1)
894	return (1);
895
896	DPRINTFN(1, "ep_no=%d\n", td->channel);
897
898	/* select endpoint 0 */
899	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
900
901	/* read out FIFO status */
902	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
903
904	DPRINTFN(4, "csr=0x%02x\n", csr);
905
906	got_short = 0;
907	if (!td->transaction_started) {
908	td->transaction_started = 1;
909
910	MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
911
912	MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
913	td->dev_addr);
914	MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
915	MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
916	MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
917
918	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
919	MUSB2_MASK_CSR0L_REQPKT);
920
921	return (1);
922	}
923
924	if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
925	csr &= ~MUSB2_MASK_CSR0L_REQPKT;
926	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
927
928	csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
929	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
930
931	td->error = 1;
932	}
933
934	/* Failed */
935	if (csr & (MUSB2_MASK_CSR0L_RXSTALL \|
936	MUSB2_MASK_CSR0L_ERROR))
937	{
938	/* Clear status bit */
939	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
940	DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
941	td->error = 1;
942	}
943
944	if (td->error) {
945	musbotg_channel_free(sc, td);
946	return (0); /* we are complete */
947	}
948
949	if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY))
950	return (1); /* not yet */
951
952	/* get the packet byte count */
953	count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
954
955	/* verify the packet byte count */
956	if (count != td->max_frame_size) {
957	if (count < td->max_frame_size) {
958	/* we have a short packet */
959	td->short_pkt = 1;
960	got_short = 1;
961	} else {
962	/* invalid USB packet */
963	td->error = 1;
964	musbotg_channel_free(sc, td);
965	return (0); /* we are complete */
966	}
967	}
968	/* verify the packet byte count */
969	if (count > td->remainder) {
970	/* invalid USB packet */
971	td->error = 1;
972	musbotg_channel_free(sc, td);
973	return (0); /* we are complete */
974	}
975	while (count > 0) {
976	uint32_t temp;
977
978	usbd_get_page(td->pc, td->offset, &buf_res);
979
980	/* get correct length */
981	if (buf_res.length > count) {
982	buf_res.length = count;
983	}
984	/* check for unaligned memory address */
985	if (USB_P2U(buf_res.buffer) & 3) {
986
987	temp = count & ~3;
988
989	if (temp) {
990	/* receive data 4 bytes at a time */
991	bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
992	MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
993	temp / 4);
994	}
995	temp = count & 3;
996	if (temp) {
997	/* receive data 1 byte at a time */
998	bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
999	MUSB2_REG_EPFIFO(0),
1000	(void *)(&sc->sc_bounce_buf[count / 4]), temp);
1001	}
1002	usbd_copy_in(td->pc, td->offset,
1003	sc->sc_bounce_buf, count);
1004
1005	/* update offset and remainder */
1006	td->offset += count;
1007	td->remainder -= count;
1008	break;
1009	}
1010	/* check if we can optimise */
1011	if (buf_res.length >= 4) {
1012
1013	/* receive data 4 bytes at a time */
1014	bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1015	MUSB2_REG_EPFIFO(0), buf_res.buffer,
1016	buf_res.length / 4);
1017
1018	temp = buf_res.length & ~3;
1019
1020	/* update counters */
1021	count -= temp;
1022	td->offset += temp;
1023	td->remainder -= temp;
1024	continue;
1025	}
1026	/* receive data */
1027	bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1028	MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
1029
1030	/* update counters */
1031	count -= buf_res.length;
1032	td->offset += buf_res.length;
1033	td->remainder -= buf_res.length;
1034	}
1035
1036	csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY;
1037	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1038
1039	/* check if we are complete */
1040	if ((td->remainder == 0) \|\| got_short) {
1041	if (td->short_pkt) {
1042	/* we are complete */
1043
1044	musbotg_channel_free(sc, td);
1045	return (0);
1046	}
1047	/* else need to receive a zero length packet */
1048	}
1049
1050	td->transaction_started = 1;
1051	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1052	MUSB2_MASK_CSR0L_REQPKT);
1053
1054	return (1); /* not complete */
1055	}
1056
1057	static uint8_t
1058	musbotg_host_ctrl_data_tx(struct musbotg_td *td)
1059	{
1060	struct usb_page_search buf_res;
1061	struct musbotg_softc *sc;
1062	uint16_t count;
1063	uint8_t csr, csrh;
1064
1065	/* get pointer to softc */
1066	sc = MUSBOTG_PC2SC(td->pc);
1067
1068	if (td->channel == -1)
1069	td->channel = musbotg_channel_alloc(sc, td, 1);
1070
1071	/* No free EPs */
1072	if (td->channel == -1)
1073	return (1);
1074
1075	DPRINTFN(1, "ep_no=%d\n", td->channel);
1076
1077	/* select endpoint */
1078	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1079
1080	/* read out FIFO status */
1081	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1082	DPRINTFN(4, "csr=0x%02x\n", csr);
1083
1084	if (csr & (MUSB2_MASK_CSR0L_RXSTALL \|
1085	MUSB2_MASK_CSR0L_ERROR)) {
1086	/* clear status bits */
1087	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1088	td->error = 1;
1089	}
1090
1091	if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) {
1092
1093	if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1094	csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1095	csrh \|= MUSB2_MASK_CSR0H_FFLUSH;
1096	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1097	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1098	if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1099	csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1100	csrh \|= MUSB2_MASK_CSR0H_FFLUSH;
1101	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1102	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1103	}
1104	}
1105
1106	csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1107	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1108
1109	td->error = 1;
1110	}
1111
1112
1113	if (td->error) {
1114	musbotg_channel_free(sc, td);
1115	return (0); /* complete */
1116	}
1117
1118	/*
1119	* Wait while FIFO is empty.
1120	* Do not flush it because it will cause transactions
1121	* with size more then packet size. It might upset
1122	* some devices
1123	*/
1124	if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY)
1125	return (1);
1126
1127	/* Packet still being processed */
1128	if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1129	return (1);
1130
1131	if (td->transaction_started) {
1132	/* check remainder */
1133	if (td->remainder == 0) {
1134	if (td->short_pkt) {
1135	musbotg_channel_free(sc, td);
1136	return (0); /* complete */
1137	}
1138	/* else we need to transmit a short packet */
1139	}
1140
1141	/* We're not complete - more transactions required */
1142	td->transaction_started = 0;
1143	}
1144
1145	/* check for short packet */
1146	count = td->max_frame_size;
1147	if (td->remainder < count) {
1148	/* we have a short packet */
1149	td->short_pkt = 1;
1150	count = td->remainder;
1151	}
1152
1153	while (count > 0) {
1154	uint32_t temp;
1155
1156	usbd_get_page(td->pc, td->offset, &buf_res);
1157
1158	/* get correct length */
1159	if (buf_res.length > count) {
1160	buf_res.length = count;
1161	}
1162	/* check for unaligned memory address */
1163	if (USB_P2U(buf_res.buffer) & 3) {
1164
1165	usbd_copy_out(td->pc, td->offset,
1166	sc->sc_bounce_buf, count);
1167
1168	temp = count & ~3;
1169
1170	if (temp) {
1171	/* transmit data 4 bytes at a time */
1172	bus_space_write_multi_4(sc->sc_io_tag,
1173	sc->sc_io_hdl, MUSB2_REG_EPFIFO(0),
1174	sc->sc_bounce_buf, temp / 4);
1175	}
1176	temp = count & 3;
1177	if (temp) {
1178	/* receive data 1 byte at a time */
1179	bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1180	MUSB2_REG_EPFIFO(0),
1181	((void *)&sc->sc_bounce_buf[count / 4]), temp);
1182	}
1183	/* update offset and remainder */
1184	td->offset += count;
1185	td->remainder -= count;
1186	break;
1187	}
1188	/* check if we can optimise */
1189	if (buf_res.length >= 4) {
1190
1191	/* transmit data 4 bytes at a time */
1192	bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1193	MUSB2_REG_EPFIFO(0), buf_res.buffer,
1194	buf_res.length / 4);
1195
1196	temp = buf_res.length & ~3;
1197
1198	/* update counters */
1199	count -= temp;
1200	td->offset += temp;
1201	td->remainder -= temp;
1202	continue;
1203	}
1204	/* transmit data */
1205	bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1206	MUSB2_REG_EPFIFO(0), buf_res.buffer,
1207	buf_res.length);
1208
1209	/* update counters */
1210	count -= buf_res.length;
1211	td->offset += buf_res.length;
1212	td->remainder -= buf_res.length;
1213	}
1214
1215	/* Function address */
1216	MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1217	MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1218	MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1219	MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1220
1221	/* TX NAK timeout */
1222	MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1223
1224	/* write command */
1225	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1226	MUSB2_MASK_CSR0L_TXPKTRDY);
1227
1228	td->transaction_started = 1;
1229
1230	return (1); /* not complete */
1231	}
1232
1233	static uint8_t
1234	musbotg_dev_ctrl_status(struct musbotg_td *td)
1235	{
1236	struct musbotg_softc *sc;
1237	uint8_t csr;
1238
1239	/* get pointer to softc */
1240	sc = MUSBOTG_PC2SC(td->pc);
1241
1242	/* select endpoint 0 */
1243	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1244
1245	if (sc->sc_ep0_busy) {
1246	sc->sc_ep0_busy = 0;
1247	sc->sc_ep0_cmd \|= MUSB2_MASK_CSR0L_DATAEND;
1248	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
1249	sc->sc_ep0_cmd = 0;
1250	}
1251	/* read out FIFO status */
1252	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1253
1254	DPRINTFN(4, "csr=0x%02x\n", csr);
1255
1256	if (csr & MUSB2_MASK_CSR0L_DATAEND) {
1257	/* wait for interrupt */
1258	return (1); /* not complete */
1259	}
1260	if (sc->sc_dv_addr != 0xFF) {
1261	/* write function address */
1262	musbotg_set_address(sc, sc->sc_dv_addr);
1263	}
1264
1265	musbotg_channel_free(sc, td);
1266	return (0); /* complete */
1267	}
1268
1269	static uint8_t
1270	musbotg_host_ctrl_status_rx(struct musbotg_td *td)
1271	{
1272	struct musbotg_softc *sc;
1273	uint8_t csr, csrh;
1274
1275	/* get pointer to softc */
1276	sc = MUSBOTG_PC2SC(td->pc);
1277
1278	if (td->channel == -1)
1279	td->channel = musbotg_channel_alloc(sc, td, 0);
1280
1281	/* EP0 is busy, wait */
1282	if (td->channel == -1)
1283	return (1);
1284
1285	DPRINTFN(1, "ep_no=%d\n", td->channel);
1286
1287	/* select endpoint 0 */
1288	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1289
1290	if (!td->transaction_started) {
1291	MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
1292	td->dev_addr);
1293
1294	MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
1295	MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
1296	MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1297
1298	/* RX NAK timeout */
1299	MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1300
1301	td->transaction_started = 1;
1302
1303	/* Disable PING */
1304	csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1305	csrh \|= MUSB2_MASK_CSR0H_PING_DIS;
1306	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1307
1308	/* write command */
1309	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1310	MUSB2_MASK_CSR0L_STATUSPKT \|
1311	MUSB2_MASK_CSR0L_REQPKT);
1312
1313	return (1); /* Just started */
1314
1315	}
1316
1317	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1318
1319	DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr);
1320
1321	if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) {
1322	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1323	MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
1324	musbotg_channel_free(sc, td);
1325	return (0); /* complete */
1326	}
1327
1328	if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
1329	csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT \|
1330	MUSB2_MASK_CSR0L_REQPKT);
1331	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1332
1333	csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1334	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1335	td->error = 1;
1336	}
1337
1338	/* Failed */
1339	if (csr & (MUSB2_MASK_CSR0L_RXSTALL \|
1340	MUSB2_MASK_CSR0L_ERROR))
1341	{
1342	/* Clear status bit */
1343	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1344	DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1345	td->error = 1;
1346	}
1347
1348	if (td->error) {
1349	musbotg_channel_free(sc, td);
1350	return (0);
1351	}
1352
1353	return (1); /* Not ready yet */
1354	}
1355
1356	static uint8_t
1357	musbotg_host_ctrl_status_tx(struct musbotg_td *td)
1358	{
1359	struct musbotg_softc *sc;
1360	uint8_t csr;
1361
1362	/* get pointer to softc */
1363	sc = MUSBOTG_PC2SC(td->pc);
1364
1365	if (td->channel == -1)
1366	td->channel = musbotg_channel_alloc(sc, td, 1);
1367
1368	/* EP0 is busy, wait */
1369	if (td->channel == -1)
1370	return (1);
1371
1372	DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started,
1373	td->dev_addr,td->haddr,td->hport, td->transfer_type);
1374
1375	/* select endpoint 0 */
1376	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1377
1378	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1379	DPRINTFN(4, "csr=0x%02x\n", csr);
1380
1381	/* Not yet */
1382	if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1383	return (1);
1384
1385	/* Failed */
1386	if (csr & (MUSB2_MASK_CSR0L_RXSTALL \|
1387	MUSB2_MASK_CSR0L_ERROR))
1388	{
1389	/* Clear status bit */
1390	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1391	DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1392	td->error = 1;
1393	musbotg_channel_free(sc, td);
1394	return (0); /* complete */
1395	}
1396
1397	if (td->transaction_started) {
1398	musbotg_channel_free(sc, td);
1399	return (0); /* complete */
1400	}
1401
1402	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS);
1403
1404	MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1405	MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1406	MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1407	MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1408
1409	/* TX NAK timeout */
1410	MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1411
1412	td->transaction_started = 1;
1413
1414	/* write command */
1415	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1416	MUSB2_MASK_CSR0L_STATUSPKT \|
1417	MUSB2_MASK_CSR0L_TXPKTRDY);
1418
1419	return (1); /* wait for interrupt */
1420	}
1421
1422	static uint8_t
1423	musbotg_dev_data_rx(struct musbotg_td *td)
1424	{
1425	struct usb_page_search buf_res;
1426	struct musbotg_softc *sc;
1427	uint16_t count;
1428	uint8_t csr;
1429	uint8_t to;
1430	uint8_t got_short;
1431
1432	to = 8; /* don't loop forever! */
1433	got_short = 0;
1434
1435	/* get pointer to softc */
1436	sc = MUSBOTG_PC2SC(td->pc);
1437
1438	if (td->channel == -1)
1439	td->channel = musbotg_channel_alloc(sc, td, 0);
1440
1441	/* EP0 is busy, wait */
1442	if (td->channel == -1)
1443	return (1);
1444
1445	/* select endpoint */
1446	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1447
1448	repeat:
1449	/* read out FIFO status */
1450	csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1451
1452	DPRINTFN(4, "csr=0x%02x\n", csr);
1453
1454	/* clear overrun */
1455	if (csr & MUSB2_MASK_CSRL_RXOVERRUN) {
1456	/* make sure we don't clear "RXPKTRDY" */
1457	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1458	MUSB2_MASK_CSRL_RXPKTRDY);
1459	}
1460
1461	/* check status */
1462	if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY))
1463	return (1); /* not complete */
1464
1465	/* get the packet byte count */
1466	count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1467
1468	DPRINTFN(4, "count=0x%04x\n", count);
1469
1470	/*
1471	* Check for short or invalid packet:
1472	*/
1473	if (count != td->max_frame_size) {
1474	if (count < td->max_frame_size) {
1475	/* we have a short packet */
1476	td->short_pkt = 1;
1477	got_short = 1;
1478	} else {
1479	/* invalid USB packet */
1480	td->error = 1;
1481	musbotg_channel_free(sc, td);
1482	return (0); /* we are complete */
1483	}
1484	}
1485	/* verify the packet byte count */
1486	if (count > td->remainder) {
1487	/* invalid USB packet */
1488	td->error = 1;
1489	musbotg_channel_free(sc, td);
1490	return (0); /* we are complete */
1491	}
1492	while (count > 0) {
1493	uint32_t temp;
1494
1495	usbd_get_page(td->pc, td->offset, &buf_res);
1496
1497	/* get correct length */
1498	if (buf_res.length > count) {
1499	buf_res.length = count;
1500	}
1501	/* check for unaligned memory address */
1502	if (USB_P2U(buf_res.buffer) & 3) {
1503
1504	temp = count & ~3;
1505
1506	if (temp) {
1507	/* receive data 4 bytes at a time */
1508	bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1509	MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1510	temp / 4);
1511	}
1512	temp = count & 3;
1513	if (temp) {
1514	/* receive data 1 byte at a time */
1515	bus_space_read_multi_1(sc->sc_io_tag,
1516	sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1517	((void *)&sc->sc_bounce_buf[count / 4]), temp);
1518	}
1519	usbd_copy_in(td->pc, td->offset,
1520	sc->sc_bounce_buf, count);
1521
1522	/* update offset and remainder */
1523	td->offset += count;
1524	td->remainder -= count;
1525	break;
1526	}
1527	/* check if we can optimise */
1528	if (buf_res.length >= 4) {
1529
1530	/* receive data 4 bytes at a time */
1531	bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1532	MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1533	buf_res.length / 4);
1534
1535	temp = buf_res.length & ~3;
1536
1537	/* update counters */
1538	count -= temp;
1539	td->offset += temp;
1540	td->remainder -= temp;
1541	continue;
1542	}
1543	/* receive data */
1544	bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1545	MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1546	buf_res.length);
1547
1548	/* update counters */
1549	count -= buf_res.length;
1550	td->offset += buf_res.length;
1551	td->remainder -= buf_res.length;
1552	}
1553
1554	/* clear status bits */
1555	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1556
1557	/* check if we are complete */
1558	if ((td->remainder == 0) \|\| got_short) {
1559	if (td->short_pkt) {
1560	/* we are complete */
1561	musbotg_channel_free(sc, td);
1562	return (0);
1563	}
1564	/* else need to receive a zero length packet */
1565	}
1566	if (--to) {
1567	goto repeat;
1568	}
1569	return (1); /* not complete */
1570	}
1571
1572	static uint8_t
1573	musbotg_dev_data_tx(struct musbotg_td *td)
1574	{
1575	struct usb_page_search buf_res;
1576	struct musbotg_softc *sc;
1577	uint16_t count;
1578	uint8_t csr;
1579	uint8_t to;
1580
1581	to = 8; /* don't loop forever! */
1582
1583	/* get pointer to softc */
1584	sc = MUSBOTG_PC2SC(td->pc);
1585
1586	if (td->channel == -1)
1587	td->channel = musbotg_channel_alloc(sc, td, 1);
1588
1589	/* EP0 is busy, wait */
1590	if (td->channel == -1)
1591	return (1);
1592
1593	/* select endpoint */
1594	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1595
1596	repeat:
1597
1598	/* read out FIFO status */
1599	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1600
1601	DPRINTFN(4, "csr=0x%02x\n", csr);
1602
1603	if (csr & (MUSB2_MASK_CSRL_TXINCOMP \|
1604	MUSB2_MASK_CSRL_TXUNDERRUN)) {
1605	/* clear status bits */
1606	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1607	}
1608	if (csr & MUSB2_MASK_CSRL_TXPKTRDY) {
1609	return (1); /* not complete */
1610	}
1611	/* check for short packet */
1612	count = td->max_frame_size;
1613	if (td->remainder < count) {
1614	/* we have a short packet */
1615	td->short_pkt = 1;
1616	count = td->remainder;
1617	}
1618	while (count > 0) {
1619	uint32_t temp;
1620
1621	usbd_get_page(td->pc, td->offset, &buf_res);
1622
1623	/* get correct length */
1624	if (buf_res.length > count) {
1625	buf_res.length = count;
1626	}
1627	/* check for unaligned memory address */
1628	if (USB_P2U(buf_res.buffer) & 3) {
1629
1630	usbd_copy_out(td->pc, td->offset,
1631	sc->sc_bounce_buf, count);
1632
1633	temp = count & ~3;
1634
1635	if (temp) {
1636	/* transmit data 4 bytes at a time */
1637	bus_space_write_multi_4(sc->sc_io_tag,
1638	sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1639	sc->sc_bounce_buf, temp / 4);
1640	}
1641	temp = count & 3;
1642	if (temp) {
1643	/* receive data 1 byte at a time */
1644	bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1645	MUSB2_REG_EPFIFO(td->channel),
1646	((void *)&sc->sc_bounce_buf[count / 4]), temp);
1647	}
1648	/* update offset and remainder */
1649	td->offset += count;
1650	td->remainder -= count;
1651	break;
1652	}
1653	/* check if we can optimise */
1654	if (buf_res.length >= 4) {
1655
1656	/* transmit data 4 bytes at a time */
1657	bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1658	MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1659	buf_res.length / 4);
1660
1661	temp = buf_res.length & ~3;
1662
1663	/* update counters */
1664	count -= temp;
1665	td->offset += temp;
1666	td->remainder -= temp;
1667	continue;
1668	}
1669	/* transmit data */
1670	bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1671	MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1672	buf_res.length);
1673
1674	/* update counters */
1675	count -= buf_res.length;
1676	td->offset += buf_res.length;
1677	td->remainder -= buf_res.length;
1678	}
1679
1680	/* Max packet size */
1681	MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
1682
1683	/* write command */
1684	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1685	MUSB2_MASK_CSRL_TXPKTRDY);
1686
1687	/* check remainder */
1688	if (td->remainder == 0) {
1689	if (td->short_pkt) {
1690	musbotg_channel_free(sc, td);
1691	return (0); /* complete */
1692	}
1693	/* else we need to transmit a short packet */
1694	}
1695	if (--to) {
1696	goto repeat;
1697	}
1698	return (1); /* not complete */
1699	}
1700
1701	static uint8_t
1702	musbotg_host_data_rx(struct musbotg_td *td)
1703	{
1704	struct usb_page_search buf_res;
1705	struct musbotg_softc *sc;
1706	uint16_t count;
1707	uint8_t csr, csrh;
1708	uint8_t to;
1709	uint8_t got_short;
1710
1711	/* get pointer to softc */
1712	sc = MUSBOTG_PC2SC(td->pc);
1713
1714	if (td->channel == -1)
1715	td->channel = musbotg_channel_alloc(sc, td, 0);
1716
1717	/* No free EPs */
1718	if (td->channel == -1)
1719	return (1);
1720
1721	DPRINTFN(1, "ep_no=%d\n", td->channel);
1722
1723	to = 8; /* don't loop forever! */
1724	got_short = 0;
1725
1726	/* select endpoint */
1727	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1728
1729	repeat:
1730	/* read out FIFO status */
1731	csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1732	DPRINTFN(4, "csr=0x%02x\n", csr);
1733
1734	if (!td->transaction_started) {
1735	/* Function address */
1736	MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel),
1737	td->dev_addr);
1738
1739	/* SPLIT transaction */
1740	MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel),
1741	td->haddr);
1742	MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel),
1743	td->hport);
1744
1745	/* RX NAK timeout */
1746	if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
1747	MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0);
1748	else
1749	MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1750
1751	/* Protocol, speed, device endpoint */
1752	MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1753
1754	/* Max packet size */
1755	MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet);
1756
1757	/* Data Toggle */
1758	csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1759	DPRINTFN(4, "csrh=0x%02x\n", csrh);
1760
1761	csrh \|= MUSB2_MASK_CSRH_RXDT_WREN;
1762	if (td->toggle)
1763	csrh \|= MUSB2_MASK_CSRH_RXDT_VAL;
1764	else
1765	csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL;
1766
1767	/* Set data toggle */
1768	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1769
1770	/* write command */
1771	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1772	MUSB2_MASK_CSRL_RXREQPKT);
1773
1774	td->transaction_started = 1;
1775	return (1);
1776	}
1777
1778	/* clear NAK timeout */
1779	if (csr & MUSB2_MASK_CSRL_RXNAKTO) {
1780	DPRINTFN(4, "NAK Timeout\n");
1781	if (csr & MUSB2_MASK_CSRL_RXREQPKT) {
1782	csr &= ~MUSB2_MASK_CSRL_RXREQPKT;
1783	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1784
1785	csr &= ~MUSB2_MASK_CSRL_RXNAKTO;
1786	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1787	}
1788
1789	td->error = 1;
1790	}
1791
1792	if (csr & MUSB2_MASK_CSRL_RXERROR) {
1793	DPRINTFN(4, "RXERROR\n");
1794	td->error = 1;
1795	}
1796
1797	if (csr & MUSB2_MASK_CSRL_RXSTALL) {
1798	DPRINTFN(4, "RXSTALL\n");
1799	td->error = 1;
1800	}
1801
1802	if (td->error) {
1803	musbotg_channel_free(sc, td);
1804	return (0); /* we are complete */
1805	}
1806
1807	if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) {
1808	/* No data available yet */
1809	return (1);
1810	}
1811
1812	td->toggle ^= 1;
1813	/* get the packet byte count */
1814	count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1815	DPRINTFN(4, "count=0x%04x\n", count);
1816
1817	/*
1818	* Check for short or invalid packet:
1819	*/
1820	if (count != td->max_frame_size) {
1821	if (count < td->max_frame_size) {
1822	/* we have a short packet */
1823	td->short_pkt = 1;
1824	got_short = 1;
1825	} else {
1826	/* invalid USB packet */
1827	td->error = 1;
1828	musbotg_channel_free(sc, td);
1829	return (0); /* we are complete */
1830	}
1831	}
1832
1833	/* verify the packet byte count */
1834	if (count > td->remainder) {
1835	/* invalid USB packet */
1836	td->error = 1;
1837	musbotg_channel_free(sc, td);
1838	return (0); /* we are complete */
1839	}
1840
1841	while (count > 0) {
1842	uint32_t temp;
1843
1844	usbd_get_page(td->pc, td->offset, &buf_res);
1845
1846	/* get correct length */
1847	if (buf_res.length > count) {
1848	buf_res.length = count;
1849	}
1850	/* check for unaligned memory address */
1851	if (USB_P2U(buf_res.buffer) & 3) {
1852
1853	temp = count & ~3;
1854
1855	if (temp) {
1856	/* receive data 4 bytes at a time */
1857	bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1858	MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1859	temp / 4);
1860	}
1861	temp = count & 3;
1862	if (temp) {
1863	/* receive data 1 byte at a time */
1864	bus_space_read_multi_1(sc->sc_io_tag,
1865	sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1866	((void *)&sc->sc_bounce_buf[count / 4]), temp);
1867	}
1868	usbd_copy_in(td->pc, td->offset,
1869	sc->sc_bounce_buf, count);
1870
1871	/* update offset and remainder */
1872	td->offset += count;
1873	td->remainder -= count;
1874	break;
1875	}
1876	/* check if we can optimise */
1877	if (buf_res.length >= 4) {
1878
1879	/* receive data 4 bytes at a time */
1880	bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1881	MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1882	buf_res.length / 4);
1883
1884	temp = buf_res.length & ~3;
1885
1886	/* update counters */
1887	count -= temp;
1888	td->offset += temp;
1889	td->remainder -= temp;
1890	continue;
1891	}
1892	/* receive data */
1893	bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1894	MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1895	buf_res.length);
1896
1897	/* update counters */
1898	count -= buf_res.length;
1899	td->offset += buf_res.length;
1900	td->remainder -= buf_res.length;
1901	}
1902
1903	/* clear status bits */
1904	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1905
1906	/* check if we are complete */
1907	if ((td->remainder == 0) \|\| got_short) {
1908	if (td->short_pkt) {
1909	/* we are complete */
1910	musbotg_channel_free(sc, td);
1911	return (0);
1912	}
1913	/* else need to receive a zero length packet */
1914	}
1915
1916	/* Reset transaction state and restart */
1917	td->transaction_started = 0;
1918
1919	if (--to)
1920	goto repeat;
1921
1922	return (1); /* not complete */
1923	}
1924
1925	static uint8_t
1926	musbotg_host_data_tx(struct musbotg_td *td)
1927	{
1928	struct usb_page_search buf_res;
1929	struct musbotg_softc *sc;
1930	uint16_t count;
1931	uint8_t csr, csrh;
1932
1933	/* get pointer to softc */
1934	sc = MUSBOTG_PC2SC(td->pc);
1935
1936	if (td->channel == -1)
1937	td->channel = musbotg_channel_alloc(sc, td, 1);
1938
1939	/* No free EPs */
1940	if (td->channel == -1)
1941	return (1);
1942
1943	DPRINTFN(1, "ep_no=%d\n", td->channel);
1944
1945	/* select endpoint */
1946	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1947
1948	/* read out FIFO status */
1949	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1950	DPRINTFN(4, "csr=0x%02x\n", csr);
1951
1952	if (csr & (MUSB2_MASK_CSRL_TXSTALLED \|
1953	MUSB2_MASK_CSRL_TXERROR)) {
1954	/* clear status bits */
1955	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1956	td->error = 1;
1957	musbotg_channel_free(sc, td);
1958	return (0); /* complete */
1959	}
1960
1961	if (csr & MUSB2_MASK_CSRL_TXNAKTO) {
1962	/*
1963	* Flush TX FIFO before clearing NAK TO
1964	*/
1965	if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1966	csr \|= MUSB2_MASK_CSRL_TXFFLUSH;
1967	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1968	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1969	if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1970	csr \|= MUSB2_MASK_CSRL_TXFFLUSH;
1971	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1972	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1973	}
1974	}
1975
1976	csr &= ~MUSB2_MASK_CSRL_TXNAKTO;
1977	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1978
1979	td->error = 1;
1980	musbotg_channel_free(sc, td);
1981	return (0); /* complete */
1982	}
1983
1984	/*
1985	* Wait while FIFO is empty.
1986	* Do not flush it because it will cause transactions
1987	* with size more then packet size. It might upset
1988	* some devices
1989	*/
1990	if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY)
1991	return (1);
1992
1993	/* Packet still being processed */
1994	if (csr & MUSB2_MASK_CSRL_TXPKTRDY)
1995	return (1);
1996
1997	if (td->transaction_started) {
1998	/* check remainder */
1999	if (td->remainder == 0) {
2000	if (td->short_pkt) {
2001	musbotg_channel_free(sc, td);
2002	return (0); /* complete */
2003	}
2004	/* else we need to transmit a short packet */
2005	}
2006
2007	/* We're not complete - more transactions required */
2008	td->transaction_started = 0;
2009	}
2010
2011	/* check for short packet */
2012	count = td->max_frame_size;
2013	if (td->remainder < count) {
2014	/* we have a short packet */
2015	td->short_pkt = 1;
2016	count = td->remainder;
2017	}
2018
2019	while (count > 0) {
2020	uint32_t temp;
2021
2022	usbd_get_page(td->pc, td->offset, &buf_res);
2023
2024	/* get correct length */
2025	if (buf_res.length > count) {
2026	buf_res.length = count;
2027	}
2028	/* check for unaligned memory address */
2029	if (USB_P2U(buf_res.buffer) & 3) {
2030
2031	usbd_copy_out(td->pc, td->offset,
2032	sc->sc_bounce_buf, count);
2033
2034	temp = count & ~3;
2035
2036	if (temp) {
2037	/* transmit data 4 bytes at a time */
2038	bus_space_write_multi_4(sc->sc_io_tag,
2039	sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
2040	sc->sc_bounce_buf, temp / 4);
2041	}
2042	temp = count & 3;
2043	if (temp) {
2044	/* receive data 1 byte at a time */
2045	bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2046	MUSB2_REG_EPFIFO(td->channel),
2047	((void *)&sc->sc_bounce_buf[count / 4]), temp);
2048	}
2049	/* update offset and remainder */
2050	td->offset += count;
2051	td->remainder -= count;
2052	break;
2053	}
2054	/* check if we can optimise */
2055	if (buf_res.length >= 4) {
2056
2057	/* transmit data 4 bytes at a time */
2058	bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
2059	MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2060	buf_res.length / 4);
2061
2062	temp = buf_res.length & ~3;
2063
2064	/* update counters */
2065	count -= temp;
2066	td->offset += temp;
2067	td->remainder -= temp;
2068	continue;
2069	}
2070	/* transmit data */
2071	bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2072	MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2073	buf_res.length);
2074
2075	/* update counters */
2076	count -= buf_res.length;
2077	td->offset += buf_res.length;
2078	td->remainder -= buf_res.length;
2079	}
2080
2081	/* Function address */
2082	MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel),
2083	td->dev_addr);
2084
2085	/* SPLIT transaction */
2086	MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel),
2087	td->haddr);
2088	MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel),
2089	td->hport);
2090
2091	/* TX NAK timeout */
2092	if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
2093	MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0);
2094	else
2095	MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
2096
2097	/* Protocol, speed, device endpoint */
2098	MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
2099
2100	/* Max packet size */
2101	MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
2102
2103	if (!td->transaction_started) {
2104	csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
2105	DPRINTFN(4, "csrh=0x%02x\n", csrh);
2106
2107	csrh \|= MUSB2_MASK_CSRH_TXDT_WREN;
2108	if (td->toggle)
2109	csrh \|= MUSB2_MASK_CSRH_TXDT_VAL;
2110	else
2111	csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL;
2112
2113	/* Set data toggle */
2114	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
2115	}
2116
2117	/* write command */
2118	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2119	MUSB2_MASK_CSRL_TXPKTRDY);
2120
2121	/* Update Data Toggle */
2122	td->toggle ^= 1;
2123	td->transaction_started = 1;
2124
2125	return (1); /* not complete */
2126	}
2127
2128	static uint8_t
2129	musbotg_xfer_do_fifo(struct usb_xfer *xfer)
2130	{
2131	struct musbotg_softc *sc;
2132	struct musbotg_td *td;
2133
2134	DPRINTFN(8, "\n");
2135	sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2136
2137	td = xfer->td_transfer_cache;
2138	while (1) {
2139
2140	if ((td->func) (td)) {
2141	/* operation in progress */
2142	break;
2143	}
2144
2145	if (((void *)td) == xfer->td_transfer_last) {
2146	goto done;
2147	}
2148	if (td->error) {
2149	goto done;
2150	} else if (td->remainder > 0) {
2151	/*
2152	* We had a short transfer. If there is no alternate
2153	* next, stop processing !
2154	*/
2155	if (!td->alt_next) {
2156	goto done;
2157	}
2158	}
2159	/*
2160	* Fetch the next transfer descriptor and transfer
2161	* some flags to the next transfer descriptor
2162	*/
2163	td = td->obj_next;
2164	xfer->td_transfer_cache = td;
2165	}
2166
2167	return (1); /* not complete */
2168	done:
2169	/* compute all actual lengths */
2170	musbotg_standard_done(xfer);
2171
2172	return (0); /* complete */
2173	}
2174
2175	static void
2176	musbotg_interrupt_poll(struct musbotg_softc *sc)
2177	{
2178	struct usb_xfer *xfer;
2179
2180	repeat:
2181	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2182	if (!musbotg_xfer_do_fifo(xfer)) {
2183	/* queue has been modified */
2184	goto repeat;
2185	}
2186	}
2187	}
2188
2189	void
2190	musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
2191	{
2192	DPRINTFN(4, "vbus = %u\n", is_on);
2193
2194	USB_BUS_LOCK(&sc->sc_bus);
2195	if (is_on) {
2196	if (!sc->sc_flags.status_vbus) {
2197	sc->sc_flags.status_vbus = 1;
2198
2199	/* complete root HUB interrupt endpoint */
2200	musbotg_root_intr(sc);
2201	}
2202	} else {
2203	if (sc->sc_flags.status_vbus) {
2204	sc->sc_flags.status_vbus = 0;
2205	sc->sc_flags.status_bus_reset = 0;
2206	sc->sc_flags.status_suspend = 0;
2207	sc->sc_flags.change_suspend = 0;
2208	sc->sc_flags.change_connect = 1;
2209
2210	/* complete root HUB interrupt endpoint */
2211	musbotg_root_intr(sc);
2212	}
2213	}
2214
2215	USB_BUS_UNLOCK(&sc->sc_bus);
2216	}
2217
2218	void
2219	musbotg_connect_interrupt(struct musbotg_softc *sc)
2220	{
2221	USB_BUS_LOCK(&sc->sc_bus);
2222	sc->sc_flags.change_connect = 1;
2223
2224	/* complete root HUB interrupt endpoint */
2225	musbotg_root_intr(sc);
2226	USB_BUS_UNLOCK(&sc->sc_bus);
2227	}
2228
2229	void
2230	musbotg_interrupt(struct musbotg_softc *sc,
2231	uint16_t rxstat, uint16_t txstat, uint8_t stat)
2232	{
2233	uint16_t rx_status;
2234	uint16_t tx_status;
2235	uint8_t usb_status;
2236	uint8_t temp;
2237	uint8_t to = 2;
2238
2239	USB_BUS_LOCK(&sc->sc_bus);
2240
2241	repeat:
2242
2243	/* read all interrupt registers */
2244	usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB);
2245
2246	/* read all FIFO interrupts */
2247	rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX);
2248	tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX);
2249	rx_status \|= rxstat;
2250	tx_status \|= txstat;
2251	usb_status \|= stat;
2252
2253	/* Clear platform flags after first time */
2254	rxstat = 0;
2255	txstat = 0;
2256	stat = 0;
2257
2258	/* check for any bus state change interrupts */
2259
2260	if (usb_status & (MUSB2_MASK_IRESET \|
2261	MUSB2_MASK_IRESUME \| MUSB2_MASK_ISUSP \|
2262	MUSB2_MASK_ICONN \| MUSB2_MASK_IDISC \|
2263	MUSB2_MASK_IVBUSERR)) {
2264
2265	DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status);
2266
2267	if (usb_status & MUSB2_MASK_IRESET) {
2268
2269	/* set correct state */
2270	sc->sc_flags.status_bus_reset = 1;
2271	sc->sc_flags.status_suspend = 0;
2272	sc->sc_flags.change_suspend = 0;
2273	sc->sc_flags.change_connect = 1;
2274
2275	/* determine line speed */
2276	temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
2277	if (temp & MUSB2_MASK_HSMODE)
2278	sc->sc_flags.status_high_speed = 1;
2279	else
2280	sc->sc_flags.status_high_speed = 0;
2281
2282	/*
2283	* After reset all interrupts are on and we need to
2284	* turn them off!
2285	*/
2286	temp = MUSB2_MASK_IRESET;
2287	/* disable resume interrupt */
2288	temp &= ~MUSB2_MASK_IRESUME;
2289	/* enable suspend interrupt */
2290	temp \|= MUSB2_MASK_ISUSP;
2291	MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2292	/* disable TX and RX interrupts */
2293	MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
2294	MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
2295	}
2296	/*
2297	* If RXRSM and RXSUSP is set at the same time we interpret
2298	* that like RESUME. Resume is set when there is at least 3
2299	* milliseconds of inactivity on the USB BUS.
2300	*/
2301	if (usb_status & MUSB2_MASK_IRESUME) {
2302	if (sc->sc_flags.status_suspend) {
2303	sc->sc_flags.status_suspend = 0;
2304	sc->sc_flags.change_suspend = 1;
2305
2306	temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2307	/* disable resume interrupt */
2308	temp &= ~MUSB2_MASK_IRESUME;
2309	/* enable suspend interrupt */
2310	temp \|= MUSB2_MASK_ISUSP;
2311	MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2312	}
2313	} else if (usb_status & MUSB2_MASK_ISUSP) {
2314	if (!sc->sc_flags.status_suspend) {
2315	sc->sc_flags.status_suspend = 1;
2316	sc->sc_flags.change_suspend = 1;
2317
2318	temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2319	/* disable suspend interrupt */
2320	temp &= ~MUSB2_MASK_ISUSP;
2321	/* enable resume interrupt */
2322	temp \|= MUSB2_MASK_IRESUME;
2323	MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2324	}
2325	}
2326	if (usb_status &
2327	(MUSB2_MASK_ICONN \| MUSB2_MASK_IDISC))
2328	sc->sc_flags.change_connect = 1;
2329
2330	/*
2331	* Host Mode: There is no IRESET so assume bus is
2332	* always in reset state once device is connected.
2333	*/
2334	if (sc->sc_mode == MUSB2_HOST_MODE) {
2335	/* check for VBUS error in USB host mode */
2336	if (usb_status & MUSB2_MASK_IVBUSERR) {
2337	temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
2338	temp \|= MUSB2_MASK_SESS;
2339	MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
2340	}
2341	if (usb_status & MUSB2_MASK_ICONN)
2342	sc->sc_flags.status_bus_reset = 1;
2343	if (usb_status & MUSB2_MASK_IDISC)
2344	sc->sc_flags.status_bus_reset = 0;
2345	}
2346
2347	/* complete root HUB interrupt endpoint */
2348	musbotg_root_intr(sc);
2349	}
2350	/* check for any endpoint interrupts */
2351
2352	if (rx_status \|\| tx_status) {
2353	DPRINTFN(4, "real endpoint interrupt "
2354	"rx=0x%04x, tx=0x%04x\n", rx_status, tx_status);
2355	}
2356	/* poll one time regardless of FIFO status */
2357
2358	musbotg_interrupt_poll(sc);
2359
2360	if (--to)
2361	goto repeat;
2362
2363	USB_BUS_UNLOCK(&sc->sc_bus);
2364	}
2365
2366	static void
2367	musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp)
2368	{
2369	struct musbotg_td *td;
2370
2371	/* get current Transfer Descriptor */
2372	td = temp->td_next;
2373	temp->td = td;
2374
2375	/* prepare for next TD */
2376	temp->td_next = td->obj_next;
2377
2378	/* fill out the Transfer Descriptor */
2379	td->func = temp->func;
2380	td->pc = temp->pc;
2381	td->offset = temp->offset;
2382	td->remainder = temp->len;
2383	td->error = 0;
2384	td->transaction_started = 0;
2385	td->did_stall = temp->did_stall;
2386	td->short_pkt = temp->short_pkt;
2387	td->alt_next = temp->setup_alt_next;
2388	td->channel = temp->channel;
2389	td->dev_addr = temp->dev_addr;
2390	td->haddr = temp->haddr;
2391	td->hport = temp->hport;
2392	td->transfer_type = temp->transfer_type;
2393	}
2394
2395	static void
2396	musbotg_setup_standard_chain(struct usb_xfer *xfer)
2397	{
2398	struct musbotg_std_temp temp;
2399	struct musbotg_softc *sc;
2400	struct musbotg_td *td;
2401	uint32_t x;
2402	uint8_t ep_no;
2403	uint8_t xfer_type;
2404	enum usb_dev_speed speed;
2405	int tx;
2406	int dev_addr;
2407
2408	DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n",
2409	xfer->address, UE_GET_ADDR(xfer->endpointno),
2410	xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
2411
2412	sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2413	ep_no = (xfer->endpointno & UE_ADDR);
2414
2415	temp.max_frame_size = xfer->max_frame_size;
2416
2417	td = xfer->td_start[0];
2418	xfer->td_transfer_first = td;
2419	xfer->td_transfer_cache = td;
2420
2421	/* setup temp */
2422	dev_addr = xfer->address;
2423
2424	xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE;
2425
2426	temp.pc = NULL;
2427	temp.td = NULL;
2428	temp.td_next = xfer->td_start[0];
2429	temp.offset = 0;
2430	temp.setup_alt_next = xfer->flags_int.short_frames_ok \|\|
2431	xfer->flags_int.isochronous_xfr;
2432	temp.did_stall = !xfer->flags_int.control_stall;
2433	temp.channel = -1;
2434	temp.dev_addr = dev_addr;
2435	temp.haddr = xfer->xroot->udev->hs_hub_addr;
2436	temp.hport = xfer->xroot->udev->hs_port_no;
2437
2438	if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2439	speed = usbd_get_speed(xfer->xroot->udev);
2440
2441	switch (speed) {
2442	case USB_SPEED_LOW:
2443	temp.transfer_type = MUSB2_MASK_TI_SPEED_LO;
2444	break;
2445	case USB_SPEED_FULL:
2446	temp.transfer_type = MUSB2_MASK_TI_SPEED_FS;
2447	break;
2448	case USB_SPEED_HIGH:
2449	temp.transfer_type = MUSB2_MASK_TI_SPEED_HS;
2450	break;
2451	default:
2452	temp.transfer_type = 0;
2453	DPRINTFN(-1, "Invalid USB speed: %d\n", speed);
2454	break;
2455	}
2456
2457	switch (xfer_type) {
2458	case UE_CONTROL:
2459	temp.transfer_type \|= MUSB2_MASK_TI_PROTO_CTRL;
2460	break;
2461	case UE_ISOCHRONOUS:
2462	temp.transfer_type \|= MUSB2_MASK_TI_PROTO_ISOC;
2463	break;
2464	case UE_BULK:
2465	temp.transfer_type \|= MUSB2_MASK_TI_PROTO_BULK;
2466	break;
2467	case UE_INTERRUPT:
2468	temp.transfer_type \|= MUSB2_MASK_TI_PROTO_INTR;
2469	break;
2470	default:
2471	DPRINTFN(-1, "Invalid USB transfer type: %d\n",
2472	xfer_type);
2473	break;
2474	}
2475
2476	temp.transfer_type \|= ep_no;
2477	td->toggle = xfer->endpoint->toggle_next;
2478	}
2479
2480	/* check if we should prepend a setup message */
2481
2482	if (xfer->flags_int.control_xfr) {
2483	if (xfer->flags_int.control_hdr) {
2484
2485	if (xfer->flags_int.usb_mode == USB_MODE_DEVICE)
2486	temp.func = &musbotg_dev_ctrl_setup_rx;
2487	else
2488	temp.func = &musbotg_host_ctrl_setup_tx;
2489
2490	temp.len = xfer->frlengths[0];
2491	temp.pc = xfer->frbuffers + 0;
2492	temp.short_pkt = temp.len ? 1 : 0;
2493
2494	musbotg_setup_standard_chain_sub(&temp);
2495	}
2496	x = 1;
2497	} else {
2498	x = 0;
2499	}
2500
2501	tx = 0;
2502
2503	if (x != xfer->nframes) {
2504	if (xfer->endpointno & UE_DIR_IN)
2505	tx = 1;
2506
2507	if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2508	tx = !tx;
2509
2510	if (tx) {
2511	if (xfer->flags_int.control_xfr)
2512	temp.func = &musbotg_host_ctrl_data_tx;
2513	else
2514	temp.func = &musbotg_host_data_tx;
2515	} else {
2516	if (xfer->flags_int.control_xfr)
2517	temp.func = &musbotg_host_ctrl_data_rx;
2518	else
2519	temp.func = &musbotg_host_data_rx;
2520	}
2521
2522	} else {
2523	if (tx) {
2524	if (xfer->flags_int.control_xfr)
2525	temp.func = &musbotg_dev_ctrl_data_tx;
2526	else
2527	temp.func = &musbotg_dev_data_tx;
2528	} else {
2529	if (xfer->flags_int.control_xfr)
2530	temp.func = &musbotg_dev_ctrl_data_rx;
2531	else
2532	temp.func = &musbotg_dev_data_rx;
2533	}
2534	}
2535
2536	/* setup "pc" pointer */
2537	temp.pc = xfer->frbuffers + x;
2538	}
2539	while (x != xfer->nframes) {
2540
2541	/* DATA0 / DATA1 message */
2542
2543	temp.len = xfer->frlengths[x];
2544
2545	x++;
2546
2547	if (x == xfer->nframes) {
2548	if (xfer->flags_int.control_xfr) {
2549	if (xfer->flags_int.control_act) {
2550	temp.setup_alt_next = 0;
2551	}
2552	} else {
2553	temp.setup_alt_next = 0;
2554	}
2555	}
2556	if (temp.len == 0) {
2557
2558	/* make sure that we send an USB packet */
2559
2560	temp.short_pkt = 0;
2561
2562	} else {
2563
2564	if (xfer->flags_int.isochronous_xfr) {
2565	/* isochronous data transfer */
2566	/* don't force short */
2567	temp.short_pkt = 1;
2568	} else {
2569	/* regular data transfer */
2570	temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
2571	}
2572	}
2573
2574	musbotg_setup_standard_chain_sub(&temp);
2575
2576	if (xfer->flags_int.isochronous_xfr) {
2577	temp.offset += temp.len;
2578	} else {
2579	/* get next Page Cache pointer */
2580	temp.pc = xfer->frbuffers + x;
2581	}
2582	}
2583
2584	/* check for control transfer */
2585	if (xfer->flags_int.control_xfr) {
2586
2587	/* always setup a valid "pc" pointer for status and sync */
2588	temp.pc = xfer->frbuffers + 0;
2589	temp.len = 0;
2590	temp.short_pkt = 0;
2591	temp.setup_alt_next = 0;
2592
2593	/* check if we should append a status stage */
2594	if (!xfer->flags_int.control_act) {
2595	/*
2596	* Send a DATA1 message and invert the current
2597	* endpoint direction.
2598	*/
2599	if (sc->sc_mode == MUSB2_DEVICE_MODE)
2600	temp.func = &musbotg_dev_ctrl_status;
2601	else {
2602	if (xfer->endpointno & UE_DIR_IN)
2603	temp.func = musbotg_host_ctrl_status_tx;
2604	else
2605	temp.func = musbotg_host_ctrl_status_rx;
2606	}
2607	musbotg_setup_standard_chain_sub(&temp);
2608	}
2609	}
2610	/* must have at least one frame! */
2611	td = temp.td;
2612	xfer->td_transfer_last = td;
2613	}
2614
2615	static void
2616	musbotg_timeout(void *arg)
2617	{
2618	struct usb_xfer *xfer = arg;
2619
2620	DPRINTFN(1, "xfer=%p\n", xfer);
2621
2622	USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2623
2624	/* transfer is transferred */
2625	musbotg_device_done(xfer, USB_ERR_TIMEOUT);
2626	}
2627
2628	static void
2629	musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on)
2630	{
2631	uint16_t temp;
2632
2633	/*
2634	* Only enable the endpoint interrupt when we are
2635	* actually waiting for data, hence we are dealing
2636	* with level triggered interrupts !
2637	*/
2638	DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on);
2639
2640	if (channel == -1)
2641	return;
2642
2643	if (channel == 0) {
2644	temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2645	if (on)
2646	temp \|= MUSB2_MASK_EPINT(0);
2647	else
2648	temp &= ~MUSB2_MASK_EPINT(0);
2649
2650	MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2651	} else {
2652	temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE);
2653	if (on)
2654	temp \|= MUSB2_MASK_EPINT(channel);
2655	else
2656	temp &= ~MUSB2_MASK_EPINT(channel);
2657	MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp);
2658
2659	temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2660	if (on)
2661	temp \|= MUSB2_MASK_EPINT(channel);
2662	else
2663	temp &= ~MUSB2_MASK_EPINT(channel);
2664	MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2665	}
2666
2667	if (sc->sc_ep_int_set)
2668	sc->sc_ep_int_set(sc, channel, on);
2669	}
2670
2671	static void
2672	musbotg_start_standard_chain(struct usb_xfer *xfer)
2673	{
2674	DPRINTFN(8, "\n");
2675
2676	/* poll one time */
2677	if (musbotg_xfer_do_fifo(xfer)) {
2678
2679	DPRINTFN(14, "enabled interrupts on endpoint\n");
2680
2681	/* put transfer on interrupt queue */
2682	usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2683
2684	/* start timeout, if any */
2685	if (xfer->timeout != 0) {
2686	usbd_transfer_timeout_ms(xfer,
2687	&musbotg_timeout, xfer->timeout);
2688	}
2689	}
2690	}
2691
2692	static void
2693	musbotg_root_intr(struct musbotg_softc *sc)
2694	{
2695	DPRINTFN(8, "\n");
2696
2697	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2698
2699	/* set port bit */
2700	sc->sc_hub_idata[0] = 0x02; /* we only have one port */
2701
2702	uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2703	sizeof(sc->sc_hub_idata));
2704	}
2705
2706	static usb_error_t
2707	musbotg_standard_done_sub(struct usb_xfer *xfer)
2708	{
2709	struct musbotg_td *td;
2710	uint32_t len;
2711	uint8_t error;
2712
2713	DPRINTFN(8, "\n");
2714
2715	td = xfer->td_transfer_cache;
2716
2717	do {
2718	len = td->remainder;
2719
2720	xfer->endpoint->toggle_next = td->toggle;
2721
2722	if (xfer->aframes != xfer->nframes) {
2723	/*
2724	* Verify the length and subtract
2725	* the remainder from "frlengths[]":
2726	*/
2727	if (len > xfer->frlengths[xfer->aframes]) {
2728	td->error = 1;
2729	} else {
2730	xfer->frlengths[xfer->aframes] -= len;
2731	}
2732	}
2733	/* Check for transfer error */
2734	if (td->error) {
2735	/* the transfer is finished */
2736	error = 1;
2737	td = NULL;
2738	break;
2739	}
2740	/* Check for short transfer */
2741	if (len > 0) {
2742	if (xfer->flags_int.short_frames_ok \|\|
2743	xfer->flags_int.isochronous_xfr) {
2744	/* follow alt next */
2745	if (td->alt_next) {
2746	td = td->obj_next;
2747	} else {
2748	td = NULL;
2749	}
2750	} else {
2751	/* the transfer is finished */
2752	td = NULL;
2753	}
2754	error = 0;
2755	break;
2756	}
2757	td = td->obj_next;
2758
2759	/* this USB frame is complete */
2760	error = 0;
2761	break;
2762
2763	} while (0);
2764
2765	/* update transfer cache */
2766
2767	xfer->td_transfer_cache = td;
2768
2769	return (error ?
2770	USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
2771	}
2772
2773	static void
2774	musbotg_standard_done(struct usb_xfer *xfer)
2775	{
2776	usb_error_t err = 0;
2777
2778	DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n",
2779	xfer, xfer->endpoint);
2780
2781	/* reset scanner */
2782
2783	xfer->td_transfer_cache = xfer->td_transfer_first;
2784
2785	if (xfer->flags_int.control_xfr) {
2786
2787	if (xfer->flags_int.control_hdr) {
2788
2789	err = musbotg_standard_done_sub(xfer);
2790	}
2791	xfer->aframes = 1;
2792
2793	if (xfer->td_transfer_cache == NULL) {
2794	goto done;
2795	}
2796	}
2797	while (xfer->aframes != xfer->nframes) {
2798
2799	err = musbotg_standard_done_sub(xfer);
2800	xfer->aframes++;
2801
2802	if (xfer->td_transfer_cache == NULL) {
2803	goto done;
2804	}
2805	}
2806
2807	if (xfer->flags_int.control_xfr &&
2808	!xfer->flags_int.control_act) {
2809
2810	err = musbotg_standard_done_sub(xfer);
2811	}
2812	done:
2813	musbotg_device_done(xfer, err);
2814	}
2815
2816	/------------------------------------------------------------------------
2817	* musbotg_device_done
2818	*
2819	* NOTE: this function can be called more than one time on the
2820	* same USB transfer!
2821	------------------------------------------------------------------------/
2822	static void
2823	musbotg_device_done(struct usb_xfer *xfer, usb_error_t error)
2824	{
2825	struct musbotg_td *td;
2826	struct musbotg_softc *sc;
2827
2828	USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2829
2830	DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n",
2831	xfer, xfer->endpoint, error);
2832
2833	DPRINTFN(14, "disabled interrupts on endpoint\n");
2834
2835	sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2836	td = xfer->td_transfer_cache;
2837
2838	if (td && (td->channel != -1))
2839	musbotg_channel_free(sc, td);
2840
2841	/* dequeue transfer and start next transfer */
2842	usbd_transfer_done(xfer, error);
2843	}
2844
2845	static void
2846	musbotg_xfer_stall(struct usb_xfer *xfer)
2847	{
2848	musbotg_device_done(xfer, USB_ERR_STALLED);
2849	}
2850
2851	static void
2852	musbotg_set_stall(struct usb_device *udev,
2853	struct usb_endpoint ep, uint8_t did_stall)
2854	{
2855	struct musbotg_softc *sc;
2856	uint8_t ep_no;
2857
2858	USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2859
2860	DPRINTFN(4, "endpoint=%p\n", ep);
2861
2862	/* set FORCESTALL */
2863	sc = MUSBOTG_BUS2SC(udev->bus);
2864
2865	ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2866
2867	/* select endpoint */
2868	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2869
2870	if (ep->edesc->bEndpointAddress & UE_DIR_IN) {
2871	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2872	MUSB2_MASK_CSRL_TXSENDSTALL);
2873	} else {
2874	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2875	MUSB2_MASK_CSRL_RXSENDSTALL);
2876	}
2877	}
2878
2879	static void
2880	musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket,
2881	uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2882	{
2883	uint16_t mps;
2884	uint16_t temp;
2885	uint8_t csr;
2886
2887	if (ep_type == UE_CONTROL) {
2888	/* clearing stall is not needed */
2889	return;
2890	}
2891	/* select endpoint */
2892	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2893
2894	/* compute max frame size */
2895	mps = wMaxPacket & 0x7FF;
2896	switch ((wMaxPacket >> 11) & 3) {
2897	case 1:
2898	mps *= 2;
2899	break;
2900	case 2:
2901	mps *= 3;
2902	break;
2903	default:
2904	break;
2905	}
2906
2907	if (ep_dir == UE_DIR_IN) {
2908
2909	temp = 0;
2910
2911	/* Configure endpoint */
2912	switch (ep_type) {
2913	case UE_INTERRUPT:
2914	MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2915	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2916	MUSB2_MASK_CSRH_TXMODE \| temp);
2917	break;
2918	case UE_ISOCHRONOUS:
2919	MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2920	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2921	MUSB2_MASK_CSRH_TXMODE \|
2922	MUSB2_MASK_CSRH_TXISO \| temp);
2923	break;
2924	case UE_BULK:
2925	MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2926	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2927	MUSB2_MASK_CSRH_TXMODE \| temp);
2928	break;
2929	default:
2930	break;
2931	}
2932
2933	/* Need to flush twice in case of double bufring */
2934	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2935	if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2936	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2937	MUSB2_MASK_CSRL_TXFFLUSH);
2938	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2939	if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2940	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2941	MUSB2_MASK_CSRL_TXFFLUSH);
2942	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2943	}
2944	}
2945	/* reset data toggle */
2946	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2947	MUSB2_MASK_CSRL_TXDT_CLR);
2948	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2949	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2950
2951	/* set double/single buffering */
2952	temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS);
2953	if (mps <= (sc->sc_hw_ep_profile[ep_no].
2954	max_in_frame_size / 2)) {
2955	/* double buffer */
2956	temp &= ~(1 << ep_no);
2957	} else {
2958	/* single buffer */
2959	temp \|= (1 << ep_no);
2960	}
2961	MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp);
2962
2963	/* clear sent stall */
2964	if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) {
2965	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2966	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2967	}
2968	} else {
2969
2970	temp = 0;
2971
2972	/* Configure endpoint */
2973	switch (ep_type) {
2974	case UE_INTERRUPT:
2975	MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2976	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2977	MUSB2_MASK_CSRH_RXNYET \| temp);
2978	break;
2979	case UE_ISOCHRONOUS:
2980	MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2981	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2982	MUSB2_MASK_CSRH_RXNYET \|
2983	MUSB2_MASK_CSRH_RXISO \| temp);
2984	break;
2985	case UE_BULK:
2986	MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2987	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp);
2988	break;
2989	default:
2990	break;
2991	}
2992
2993	/* Need to flush twice in case of double bufring */
2994	csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2995	if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2996	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2997	MUSB2_MASK_CSRL_RXFFLUSH);
2998	csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2999	if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
3000	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
3001	MUSB2_MASK_CSRL_RXFFLUSH);
3002	csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
3003	}
3004	}
3005	/* reset data toggle */
3006	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
3007	MUSB2_MASK_CSRL_RXDT_CLR);
3008	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3009	csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
3010
3011	/* set double/single buffering */
3012	temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS);
3013	if (mps <= (sc->sc_hw_ep_profile[ep_no].
3014	max_out_frame_size / 2)) {
3015	/* double buffer */
3016	temp &= ~(1 << ep_no);
3017	} else {
3018	/* single buffer */
3019	temp \|= (1 << ep_no);
3020	}
3021	MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp);
3022
3023	/* clear sent stall */
3024	if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) {
3025	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3026	}
3027	}
3028	}
3029
3030	static void
3031	musbotg_clear_stall(struct usb_device udev, struct usb_endpoint ep)
3032	{
3033	struct musbotg_softc *sc;
3034	struct usb_endpoint_descriptor *ed;
3035
3036	DPRINTFN(4, "endpoint=%p\n", ep);
3037
3038	USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3039
3040	/* check mode */
3041	if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3042	/* not supported */
3043	return;
3044	}
3045	/* get softc */
3046	sc = MUSBOTG_BUS2SC(udev->bus);
3047
3048	/* get endpoint descriptor */
3049	ed = ep->edesc;
3050
3051	/* reset endpoint */
3052	musbotg_clear_stall_sub(sc,
3053	UGETW(ed->wMaxPacketSize),
3054	(ed->bEndpointAddress & UE_ADDR),
3055	(ed->bmAttributes & UE_XFERTYPE),
3056	(ed->bEndpointAddress & (UE_DIR_IN \| UE_DIR_OUT)));
3057	}
3058
3059	usb_error_t
3060	musbotg_init(struct musbotg_softc *sc)
3061	{
3062	struct usb_hw_ep_profile *pf;
3063	uint16_t offset;
3064	uint8_t nrx;
3065	uint8_t ntx;
3066	uint8_t temp;
3067	uint8_t fsize;
3068	uint8_t frx;
3069	uint8_t ftx;
3070	uint8_t dynfifo;
3071
3072	DPRINTFN(1, "start\n");
3073
3074	/* set up the bus structure */
3075	sc->sc_bus.usbrev = USB_REV_2_0;
3076	sc->sc_bus.methods = &musbotg_bus_methods;
3077
3078	USB_BUS_LOCK(&sc->sc_bus);
3079
3080	/* turn on clocks */
3081
3082	if (sc->sc_clocks_on) {
3083	(sc->sc_clocks_on) (sc->sc_clocks_arg);
3084	}
3085
3086	/* wait a little for things to stabilise */
3087	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
3088
3089	/* disable all interrupts */
3090
3091	temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3092	DPRINTF("pre-DEVCTL=0x%02x\n", temp);
3093
3094	MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3095	MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3096	MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3097
3098	/* disable pullup */
3099
3100	musbotg_pull_common(sc, 0);
3101
3102	/* wait a little bit (10ms) */
3103	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3104
3105
3106	/* disable double packet buffering */
3107	MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF);
3108	MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF);
3109
3110	/* enable HighSpeed and ISO Update flags */
3111
3112	MUSB2_WRITE_1(sc, MUSB2_REG_POWER,
3113	MUSB2_MASK_HSENAB \| MUSB2_MASK_ISOUPD);
3114
3115	if (sc->sc_mode == MUSB2_DEVICE_MODE) {
3116	/* clear Session bit, if set */
3117	temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3118	temp &= ~MUSB2_MASK_SESS;
3119	MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3120	} else {
3121	/* Enter session for Host mode */
3122	temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3123	temp \|= MUSB2_MASK_SESS;
3124	MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3125	}
3126
3127	/* wait a little for things to stabilise */
3128	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
3129
3130	DPRINTF("DEVCTL=0x%02x\n", temp);
3131
3132	/* disable testmode */
3133
3134	MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0);
3135
3136	/* set default value */
3137
3138	MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0);
3139
3140	/* select endpoint index 0 */
3141
3142	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
3143
3144	/* read out number of endpoints */
3145
3146	nrx =
3147	(MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16);
3148
3149	ntx =
3150	(MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16);
3151
3152	/* these numbers exclude the control endpoint */
3153
3154	DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx);
3155
3156	sc->sc_ep_max = (nrx > ntx) ? nrx : ntx;
3157	if (sc->sc_ep_max == 0) {
3158	DPRINTFN(2, "ERROR: Looks like the clocks are off!\n");
3159	}
3160	/* read out configuration data */
3161
3162	sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA);
3163
3164	DPRINTFN(2, "Config Data: 0x%02x\n",
3165	sc->sc_conf_data);
3166
3167	dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0;
3168
3169	if (dynfifo) {
3170	device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, "
3171	"assuming 16Kbytes of FIFO RAM\n");
3172	}
3173
3174	DPRINTFN(2, "HW version: 0x%04x\n",
3175	MUSB2_READ_1(sc, MUSB2_REG_HWVERS));
3176
3177	/* initialise endpoint profiles */
3178
3179	offset = 0;
3180
3181	for (temp = 1; temp <= sc->sc_ep_max; temp++) {
3182	pf = sc->sc_hw_ep_profile + temp;
3183
3184	/* select endpoint */
3185	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp);
3186
3187	fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE);
3188	frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;
3189	ftx = (fsize & MUSB2_MASK_TX_FSIZE);
3190
3191	DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n",
3192	temp, ftx, frx, dynfifo);
3193
3194	if (dynfifo) {
3195	if (frx && (temp <= nrx)) {
3196	if (temp == 1) {
3197	frx = 12; /* 4K */
3198	MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3199	MUSB2_VAL_FIFOSZ_4096 \|
3200	MUSB2_MASK_FIFODB);
3201	} else if (temp < 8) {
3202	frx = 10; /* 1K */
3203	MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3204	MUSB2_VAL_FIFOSZ_512 \|
3205	MUSB2_MASK_FIFODB);
3206	} else {
3207	frx = 7; /* 128 bytes */
3208	MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3209	MUSB2_VAL_FIFOSZ_128);
3210	}
3211
3212	MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD,
3213	offset >> 3);
3214
3215	offset += (1 << frx);
3216	}
3217	if (ftx && (temp <= ntx)) {
3218	if (temp == 1) {
3219	ftx = 12; /* 4K */
3220	MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3221	MUSB2_VAL_FIFOSZ_4096 \|
3222	MUSB2_MASK_FIFODB);
3223	} else if (temp < 8) {
3224	ftx = 10; /* 1K */
3225	MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3226	MUSB2_VAL_FIFOSZ_512 \|
3227	MUSB2_MASK_FIFODB);
3228	} else {
3229	ftx = 7; /* 128 bytes */
3230	MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3231	MUSB2_VAL_FIFOSZ_128);
3232	}
3233
3234	MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD,
3235	offset >> 3);
3236
3237	offset += (1 << ftx);
3238	}
3239	}
3240
3241	if (frx && ftx && (temp <= nrx) && (temp <= ntx)) {
3242	pf->max_in_frame_size = 1 << ftx;
3243	pf->max_out_frame_size = 1 << frx;
3244	pf->is_simplex = 0; /* duplex */
3245	pf->support_multi_buffer = 1;
3246	pf->support_bulk = 1;
3247	pf->support_interrupt = 1;
3248	pf->support_isochronous = 1;
3249	pf->support_in = 1;
3250	pf->support_out = 1;
3251	} else if (frx && (temp <= nrx)) {
3252	pf->max_out_frame_size = 1 << frx;
3253	pf->max_in_frame_size = 0;
3254	pf->is_simplex = 1; /* simplex */
3255	pf->support_multi_buffer = 1;
3256	pf->support_bulk = 1;
3257	pf->support_interrupt = 1;
3258	pf->support_isochronous = 1;
3259	pf->support_out = 1;
3260	} else if (ftx && (temp <= ntx)) {
3261	pf->max_in_frame_size = 1 << ftx;
3262	pf->max_out_frame_size = 0;
3263	pf->is_simplex = 1; /* simplex */
3264	pf->support_multi_buffer = 1;
3265	pf->support_bulk = 1;
3266	pf->support_interrupt = 1;
3267	pf->support_isochronous = 1;
3268	pf->support_in = 1;
3269	}
3270	}
3271
3272	DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset);
3273
3274	/* turn on default interrupts */
3275
3276	if (sc->sc_mode == MUSB2_HOST_MODE)
3277	MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff);
3278	else
3279	MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE,
3280	MUSB2_MASK_IRESET);
3281
3282	musbotg_clocks_off(sc);
3283
3284	USB_BUS_UNLOCK(&sc->sc_bus);
3285
3286	/* catch any lost interrupts */
3287
3288	musbotg_do_poll(&sc->sc_bus);
3289
3290	return (0); /* success */
3291	}
3292
3293	void
3294	musbotg_uninit(struct musbotg_softc *sc)
3295	{
3296	USB_BUS_LOCK(&sc->sc_bus);
3297
3298	/* disable all interrupts */
3299	MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3300	MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3301	MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3302
3303	sc->sc_flags.port_powered = 0;
3304	sc->sc_flags.status_vbus = 0;
3305	sc->sc_flags.status_bus_reset = 0;
3306	sc->sc_flags.status_suspend = 0;
3307	sc->sc_flags.change_suspend = 0;
3308	sc->sc_flags.change_connect = 1;
3309
3310	musbotg_pull_down(sc);
3311	musbotg_clocks_off(sc);
3312	USB_BUS_UNLOCK(&sc->sc_bus);
3313	}
3314
3315	static void
3316	musbotg_do_poll(struct usb_bus *bus)
3317	{
3318	struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
3319
3320	USB_BUS_LOCK(&sc->sc_bus);
3321	musbotg_interrupt_poll(sc);
3322	USB_BUS_UNLOCK(&sc->sc_bus);
3323	}
3324
3325	/------------------------------------------------------------------------
3326	* musbotg bulk support
3327	------------------------------------------------------------------------/
3328	static void
3329	musbotg_device_bulk_open(struct usb_xfer *xfer)
3330	{
3331	return;
3332	}
3333
3334	static void
3335	musbotg_device_bulk_close(struct usb_xfer *xfer)
3336	{
3337	musbotg_device_done(xfer, USB_ERR_CANCELLED);
3338	}
3339
3340	static void
3341	musbotg_device_bulk_enter(struct usb_xfer *xfer)
3342	{
3343	return;
3344	}
3345
3346	static void
3347	musbotg_device_bulk_start(struct usb_xfer *xfer)
3348	{
3349	/* setup TDs */
3350	musbotg_setup_standard_chain(xfer);
3351	musbotg_start_standard_chain(xfer);
3352	}
3353
3354	static const struct usb_pipe_methods musbotg_device_bulk_methods =
3355	{
3356	.open = musbotg_device_bulk_open,
3357	.close = musbotg_device_bulk_close,
3358	.enter = musbotg_device_bulk_enter,
3359	.start = musbotg_device_bulk_start,
3360	};
3361
3362	/------------------------------------------------------------------------
3363	* musbotg control support
3364	------------------------------------------------------------------------/
3365	static void
3366	musbotg_device_ctrl_open(struct usb_xfer *xfer)
3367	{
3368	return;
3369	}
3370
3371	static void
3372	musbotg_device_ctrl_close(struct usb_xfer *xfer)
3373	{
3374	musbotg_device_done(xfer, USB_ERR_CANCELLED);
3375	}
3376
3377	static void
3378	musbotg_device_ctrl_enter(struct usb_xfer *xfer)
3379	{
3380	return;
3381	}
3382
3383	static void
3384	musbotg_device_ctrl_start(struct usb_xfer *xfer)
3385	{
3386	/* setup TDs */
3387	musbotg_setup_standard_chain(xfer);
3388	musbotg_start_standard_chain(xfer);
3389	}
3390
3391	static const struct usb_pipe_methods musbotg_device_ctrl_methods =
3392	{
3393	.open = musbotg_device_ctrl_open,
3394	.close = musbotg_device_ctrl_close,
3395	.enter = musbotg_device_ctrl_enter,
3396	.start = musbotg_device_ctrl_start,
3397	};
3398
3399	/------------------------------------------------------------------------
3400	* musbotg interrupt support
3401	------------------------------------------------------------------------/
3402	static void
3403	musbotg_device_intr_open(struct usb_xfer *xfer)
3404	{
3405	return;
3406	}
3407
3408	static void
3409	musbotg_device_intr_close(struct usb_xfer *xfer)
3410	{
3411	musbotg_device_done(xfer, USB_ERR_CANCELLED);
3412	}
3413
3414	static void
3415	musbotg_device_intr_enter(struct usb_xfer *xfer)
3416	{
3417	return;
3418	}
3419
3420	static void
3421	musbotg_device_intr_start(struct usb_xfer *xfer)
3422	{
3423	/* setup TDs */
3424	musbotg_setup_standard_chain(xfer);
3425	musbotg_start_standard_chain(xfer);
3426	}
3427
3428	static const struct usb_pipe_methods musbotg_device_intr_methods =
3429	{
3430	.open = musbotg_device_intr_open,
3431	.close = musbotg_device_intr_close,
3432	.enter = musbotg_device_intr_enter,
3433	.start = musbotg_device_intr_start,
3434	};
3435
3436	/------------------------------------------------------------------------
3437	* musbotg full speed isochronous support
3438	------------------------------------------------------------------------/
3439	static void
3440	musbotg_device_isoc_open(struct usb_xfer *xfer)
3441	{
3442	return;
3443	}
3444
3445	static void
3446	musbotg_device_isoc_close(struct usb_xfer *xfer)
3447	{
3448	musbotg_device_done(xfer, USB_ERR_CANCELLED);
3449	}
3450
3451	static void
3452	musbotg_device_isoc_enter(struct usb_xfer *xfer)
3453	{
3454	struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
3455	uint32_t temp;
3456	uint32_t nframes;
3457	uint32_t fs_frames;
3458
3459	DPRINTFN(5, "xfer=%p next=%d nframes=%d\n",
3460	xfer, xfer->endpoint->isoc_next, xfer->nframes);
3461
3462	/* get the current frame index */
3463
3464	nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME);
3465
3466	/*
3467	* check if the frame index is within the window where the frames
3468	* will be inserted
3469	*/
3470	temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME;
3471
3472	if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
3473	fs_frames = (xfer->nframes + 7) / 8;
3474	} else {
3475	fs_frames = xfer->nframes;
3476	}
3477
3478	if ((xfer->endpoint->is_synced == 0) \|\|
3479	(temp < fs_frames)) {
3480	/*
3481	* If there is data underflow or the pipe queue is
3482	* empty we schedule the transfer a few frames ahead
3483	* of the current frame position. Else two isochronous
3484	* transfers might overlap.
3485	*/
3486	xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME;
3487	xfer->endpoint->is_synced = 1;
3488	DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next);
3489	}
3490	/*
3491	* compute how many milliseconds the insertion is ahead of the
3492	* current frame position:
3493	*/
3494	temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME;
3495
3496	/*
3497	* pre-compute when the isochronous transfer will be finished:
3498	*/
3499	xfer->isoc_time_complete =
3500	usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
3501	fs_frames;
3502
3503	/* compute frame number for next insertion */
3504	xfer->endpoint->isoc_next += fs_frames;
3505
3506	/* setup TDs */
3507	musbotg_setup_standard_chain(xfer);
3508	}
3509
3510	static void
3511	musbotg_device_isoc_start(struct usb_xfer *xfer)
3512	{
3513	/* start TD chain */
3514	musbotg_start_standard_chain(xfer);
3515	}
3516
3517	static const struct usb_pipe_methods musbotg_device_isoc_methods =
3518	{
3519	.open = musbotg_device_isoc_open,
3520	.close = musbotg_device_isoc_close,
3521	.enter = musbotg_device_isoc_enter,
3522	.start = musbotg_device_isoc_start,
3523	};
3524
3525	/------------------------------------------------------------------------
3526	* musbotg root control support
3527	------------------------------------------------------------------------
3528	* Simulate a hardware HUB by handling all the necessary requests.
3529	------------------------------------------------------------------------/
3530
3531	static const struct usb_device_descriptor musbotg_devd = {
3532	.bLength = sizeof(struct usb_device_descriptor),
3533	.bDescriptorType = UDESC_DEVICE,
3534	.bcdUSB = {0x00, 0x02},
3535	.bDeviceClass = UDCLASS_HUB,
3536	.bDeviceSubClass = UDSUBCLASS_HUB,
3537	.bDeviceProtocol = UDPROTO_HSHUBSTT,
3538	.bMaxPacketSize = 64,
3539	.bcdDevice = {0x00, 0x01},
3540	.iManufacturer = 1,
3541	.iProduct = 2,
3542	.bNumConfigurations = 1,
3543	};
3544
3545	static const struct usb_device_qualifier musbotg_odevd = {
3546	.bLength = sizeof(struct usb_device_qualifier),
3547	.bDescriptorType = UDESC_DEVICE_QUALIFIER,
3548	.bcdUSB = {0x00, 0x02},
3549	.bDeviceClass = UDCLASS_HUB,
3550	.bDeviceSubClass = UDSUBCLASS_HUB,
3551	.bDeviceProtocol = UDPROTO_FSHUB,
3552	.bMaxPacketSize0 = 0,
3553	.bNumConfigurations = 0,
3554	};
3555
3556	static const struct musbotg_config_desc musbotg_confd = {
3557	.confd = {
3558	.bLength = sizeof(struct usb_config_descriptor),
3559	.bDescriptorType = UDESC_CONFIG,
3560	.wTotalLength[0] = sizeof(musbotg_confd),
3561	.bNumInterface = 1,
3562	.bConfigurationValue = 1,
3563	.iConfiguration = 0,
3564	.bmAttributes = UC_SELF_POWERED,
3565	.bMaxPower = 0,
3566	},
3567	.ifcd = {
3568	.bLength = sizeof(struct usb_interface_descriptor),
3569	.bDescriptorType = UDESC_INTERFACE,
3570	.bNumEndpoints = 1,
3571	.bInterfaceClass = UICLASS_HUB,
3572	.bInterfaceSubClass = UISUBCLASS_HUB,
3573	.bInterfaceProtocol = 0,
3574	},
3575	.endpd = {
3576	.bLength = sizeof(struct usb_endpoint_descriptor),
3577	.bDescriptorType = UDESC_ENDPOINT,
3578	.bEndpointAddress = (UE_DIR_IN \| MUSBOTG_INTR_ENDPT),
3579	.bmAttributes = UE_INTERRUPT,
3580	.wMaxPacketSize[0] = 8,
3581	.bInterval = 255,
3582	},
3583	};
3584
3585	#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3586
3587	static const struct usb_hub_descriptor_min musbotg_hubd = {
3588	.bDescLength = sizeof(musbotg_hubd),
3589	.bDescriptorType = UDESC_HUB,
3590	.bNbrPorts = 1,
3591	HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH \| UHD_OC_INDIVIDUAL)),
3592	.bPwrOn2PwrGood = 50,
3593	.bHubContrCurrent = 0,
3594	.DeviceRemovable = {0}, /* port is removable */
3595	};
3596
3597	#define STRING_VENDOR \
3598	"M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s"
3599
3600	#define STRING_PRODUCT \
3601	"O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
3602
3603	USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor);
3604	USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product);
3605
3606	static usb_error_t
3607	musbotg_roothub_exec(struct usb_device *udev,
3608	struct usb_device_request req, const void pptr, uint16_t plength)
3609	{
3610	struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
3611	const void *ptr;
3612	uint16_t len;
3613	uint16_t value;
3614	uint16_t index;
3615	uint8_t reg;
3616	usb_error_t err;
3617
3618	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3619
3620	/* buffer reset */
3621	ptr = (const void *)&sc->sc_hub_temp;
3622	len = 0;
3623	err = 0;
3624
3625	value = UGETW(req->wValue);
3626	index = UGETW(req->wIndex);
3627
3628	/* demultiplex the control request */
3629
3630	switch (req->bmRequestType) {
3631	case UT_READ_DEVICE:
3632	switch (req->bRequest) {
3633	case UR_GET_DESCRIPTOR:
3634	goto tr_handle_get_descriptor;
3635	case UR_GET_CONFIG:
3636	goto tr_handle_get_config;
3637	case UR_GET_STATUS:
3638	goto tr_handle_get_status;
3639	default:
3640	goto tr_stalled;
3641	}
3642	break;
3643
3644	case UT_WRITE_DEVICE:
3645	switch (req->bRequest) {
3646	case UR_SET_ADDRESS:
3647	goto tr_handle_set_address;
3648	case UR_SET_CONFIG:
3649	goto tr_handle_set_config;
3650	case UR_CLEAR_FEATURE:
3651	goto tr_valid; /* nop */
3652	case UR_SET_DESCRIPTOR:
3653	goto tr_valid; /* nop */
3654	case UR_SET_FEATURE:
3655	default:
3656	goto tr_stalled;
3657	}
3658	break;
3659
3660	case UT_WRITE_ENDPOINT:
3661	switch (req->bRequest) {
3662	case UR_CLEAR_FEATURE:
3663	switch (UGETW(req->wValue)) {
3664	case UF_ENDPOINT_HALT:
3665	goto tr_handle_clear_halt;
3666	case UF_DEVICE_REMOTE_WAKEUP:
3667	goto tr_handle_clear_wakeup;
3668	default:
3669	goto tr_stalled;
3670	}
3671	break;
3672	case UR_SET_FEATURE:
3673	switch (UGETW(req->wValue)) {
3674	case UF_ENDPOINT_HALT:
3675	goto tr_handle_set_halt;
3676	case UF_DEVICE_REMOTE_WAKEUP:
3677	goto tr_handle_set_wakeup;
3678	default:
3679	goto tr_stalled;
3680	}
3681	break;
3682	case UR_SYNCH_FRAME:
3683	goto tr_valid; /* nop */
3684	default:
3685	goto tr_stalled;
3686	}
3687	break;
3688
3689	case UT_READ_ENDPOINT:
3690	switch (req->bRequest) {
3691	case UR_GET_STATUS:
3692	goto tr_handle_get_ep_status;
3693	default:
3694	goto tr_stalled;
3695	}
3696	break;
3697
3698	case UT_WRITE_INTERFACE:
3699	switch (req->bRequest) {
3700	case UR_SET_INTERFACE:
3701	goto tr_handle_set_interface;
3702	case UR_CLEAR_FEATURE:
3703	goto tr_valid; /* nop */
3704	case UR_SET_FEATURE:
3705	default:
3706	goto tr_stalled;
3707	}
3708	break;
3709
3710	case UT_READ_INTERFACE:
3711	switch (req->bRequest) {
3712	case UR_GET_INTERFACE:
3713	goto tr_handle_get_interface;
3714	case UR_GET_STATUS:
3715	goto tr_handle_get_iface_status;
3716	default:
3717	goto tr_stalled;
3718	}
3719	break;
3720
3721	case UT_WRITE_CLASS_INTERFACE:
3722	case UT_WRITE_VENDOR_INTERFACE:
3723	/* XXX forward */
3724	break;
3725
3726	case UT_READ_CLASS_INTERFACE:
3727	case UT_READ_VENDOR_INTERFACE:
3728	/* XXX forward */
3729	break;
3730
3731	case UT_WRITE_CLASS_DEVICE:
3732	switch (req->bRequest) {
3733	case UR_CLEAR_FEATURE:
3734	goto tr_valid;
3735	case UR_SET_DESCRIPTOR:
3736	case UR_SET_FEATURE:
3737	break;
3738	default:
3739	goto tr_stalled;
3740	}
3741	break;
3742
3743	case UT_WRITE_CLASS_OTHER:
3744	switch (req->bRequest) {
3745	case UR_CLEAR_FEATURE:
3746	goto tr_handle_clear_port_feature;
3747	case UR_SET_FEATURE:
3748	goto tr_handle_set_port_feature;
3749	case UR_CLEAR_TT_BUFFER:
3750	case UR_RESET_TT:
3751	case UR_STOP_TT:
3752	goto tr_valid;
3753
3754	default:
3755	goto tr_stalled;
3756	}
3757	break;
3758
3759	case UT_READ_CLASS_OTHER:
3760	switch (req->bRequest) {
3761	case UR_GET_TT_STATE:
3762	goto tr_handle_get_tt_state;
3763	case UR_GET_STATUS:
3764	goto tr_handle_get_port_status;
3765	default:
3766	goto tr_stalled;
3767	}
3768	break;
3769
3770	case UT_READ_CLASS_DEVICE:
3771	switch (req->bRequest) {
3772	case UR_GET_DESCRIPTOR:
3773	goto tr_handle_get_class_descriptor;
3774	case UR_GET_STATUS:
3775	goto tr_handle_get_class_status;
3776
3777	default:
3778	goto tr_stalled;
3779	}
3780	break;
3781	default:
3782	goto tr_stalled;
3783	}
3784	goto tr_valid;
3785
3786	tr_handle_get_descriptor:
3787	switch (value >> 8) {
3788	case UDESC_DEVICE:
3789	if (value & 0xff) {
3790	goto tr_stalled;
3791	}
3792	len = sizeof(musbotg_devd);
3793	ptr = (const void *)&musbotg_devd;
3794	goto tr_valid;
3795	case UDESC_DEVICE_QUALIFIER:
3796	if (value & 0xff) {
3797	goto tr_stalled;
3798	}
3799	len = sizeof(musbotg_odevd);
3800	ptr = (const void *)&musbotg_odevd;
3801	goto tr_valid;
3802	case UDESC_CONFIG:
3803	if (value & 0xff) {
3804	goto tr_stalled;
3805	}
3806	len = sizeof(musbotg_confd);
3807	ptr = (const void *)&musbotg_confd;
3808	goto tr_valid;
3809	case UDESC_STRING:
3810	switch (value & 0xff) {
3811	case 0: /* Language table */
3812	len = sizeof(usb_string_lang_en);
3813	ptr = (const void *)&usb_string_lang_en;
3814	goto tr_valid;
3815
3816	case 1: /* Vendor */
3817	len = sizeof(musbotg_vendor);
3818	ptr = (const void *)&musbotg_vendor;
3819	goto tr_valid;
3820
3821	case 2: /* Product */
3822	len = sizeof(musbotg_product);
3823	ptr = (const void *)&musbotg_product;
3824	goto tr_valid;
3825	default:
3826	break;
3827	}
3828	break;
3829	default:
3830	goto tr_stalled;
3831	}
3832	goto tr_stalled;
3833
3834	tr_handle_get_config:
3835	len = 1;
3836	sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3837	goto tr_valid;
3838
3839	tr_handle_get_status:
3840	len = 2;
3841	USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3842	goto tr_valid;
3843
3844	tr_handle_set_address:
3845	if (value & 0xFF00) {
3846	goto tr_stalled;
3847	}
3848	sc->sc_rt_addr = value;
3849	goto tr_valid;
3850
3851	tr_handle_set_config:
3852	if (value >= 2) {
3853	goto tr_stalled;
3854	}
3855	sc->sc_conf = value;
3856	goto tr_valid;
3857
3858	tr_handle_get_interface:
3859	len = 1;
3860	sc->sc_hub_temp.wValue[0] = 0;
3861	goto tr_valid;
3862
3863	tr_handle_get_tt_state:
3864	tr_handle_get_class_status:
3865	tr_handle_get_iface_status:
3866	tr_handle_get_ep_status:
3867	len = 2;
3868	USETW(sc->sc_hub_temp.wValue, 0);
3869	goto tr_valid;
3870
3871	tr_handle_set_halt:
3872	tr_handle_set_interface:
3873	tr_handle_set_wakeup:
3874	tr_handle_clear_wakeup:
3875	tr_handle_clear_halt:
3876	goto tr_valid;
3877
3878	tr_handle_clear_port_feature:
3879	if (index != 1) {
3880	goto tr_stalled;
3881	}
3882	DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
3883
3884	switch (value) {
3885	case UHF_PORT_SUSPEND:
3886	if (sc->sc_mode == MUSB2_HOST_MODE)
3887	musbotg_wakeup_host(sc);
3888	else
3889	musbotg_wakeup_peer(sc);
3890	break;
3891
3892	case UHF_PORT_ENABLE:
3893	sc->sc_flags.port_enabled = 0;
3894	break;
3895
3896	case UHF_C_PORT_ENABLE:
3897	sc->sc_flags.change_enabled = 0;
3898	break;
3899
3900	case UHF_C_PORT_OVER_CURRENT:
3901	sc->sc_flags.change_over_current = 0;
3902	break;
3903
3904	case UHF_C_PORT_RESET:
3905	sc->sc_flags.change_reset = 0;
3906	break;
3907
3908	case UHF_PORT_TEST:
3909	case UHF_PORT_INDICATOR:
3910	/* nops */
3911	break;
3912
3913	case UHF_PORT_POWER:
3914	sc->sc_flags.port_powered = 0;
3915	musbotg_pull_down(sc);
3916	musbotg_clocks_off(sc);
3917	break;
3918	case UHF_C_PORT_CONNECTION:
3919	sc->sc_flags.change_connect = 0;
3920	break;
3921	case UHF_C_PORT_SUSPEND:
3922	sc->sc_flags.change_suspend = 0;
3923	break;
3924	default:
3925	err = USB_ERR_IOERROR;
3926	goto done;
3927	}
3928	goto tr_valid;
3929
3930	tr_handle_set_port_feature:
3931	if (index != 1) {
3932	goto tr_stalled;
3933	}
3934	DPRINTFN(8, "UR_SET_PORT_FEATURE\n");
3935
3936	switch (value) {
3937	case UHF_PORT_ENABLE:
3938	sc->sc_flags.port_enabled = 1;
3939	break;
3940	case UHF_PORT_SUSPEND:
3941	if (sc->sc_mode == MUSB2_HOST_MODE)
3942	musbotg_suspend_host(sc);
3943	break;
3944
3945	case UHF_PORT_RESET:
3946	if (sc->sc_mode == MUSB2_HOST_MODE) {
3947	reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3948	reg \|= MUSB2_MASK_RESET;
3949	MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3950
3951	/* Wait for 20 msec */
3952	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5);
3953
3954	reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3955	reg &= ~MUSB2_MASK_RESET;
3956	MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3957
3958	/* determine line speed */
3959	reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3960	if (reg & MUSB2_MASK_HSMODE)
3961	sc->sc_flags.status_high_speed = 1;
3962	else
3963	sc->sc_flags.status_high_speed = 0;
3964
3965	sc->sc_flags.change_reset = 1;
3966	} else
3967	err = USB_ERR_IOERROR;
3968	break;
3969
3970	case UHF_PORT_TEST:
3971	case UHF_PORT_INDICATOR:
3972	/* nops */
3973	break;
3974	case UHF_PORT_POWER:
3975	sc->sc_flags.port_powered = 1;
3976	break;
3977	default:
3978	err = USB_ERR_IOERROR;
3979	goto done;
3980	}
3981	goto tr_valid;
3982
3983	tr_handle_get_port_status:
3984
3985	DPRINTFN(8, "UR_GET_PORT_STATUS\n");
3986
3987	if (index != 1) {
3988	goto tr_stalled;
3989	}
3990	if (sc->sc_flags.status_vbus) {
3991	musbotg_clocks_on(sc);
3992	musbotg_pull_up(sc);
3993	} else {
3994	musbotg_pull_down(sc);
3995	musbotg_clocks_off(sc);
3996	}
3997
3998	/* Select Device Side Mode */
3999	if (sc->sc_mode == MUSB2_DEVICE_MODE)
4000	value = UPS_PORT_MODE_DEVICE;
4001	else
4002	value = 0;
4003
4004	if (sc->sc_flags.status_high_speed) {
4005	value \|= UPS_HIGH_SPEED;
4006	}
4007	if (sc->sc_flags.port_powered) {
4008	value \|= UPS_PORT_POWER;
4009	}
4010	if (sc->sc_flags.port_enabled) {
4011	value \|= UPS_PORT_ENABLED;
4012	}
4013
4014	if (sc->sc_flags.port_over_current)
4015	value \|= UPS_OVERCURRENT_INDICATOR;
4016
4017	if (sc->sc_flags.status_vbus &&
4018	sc->sc_flags.status_bus_reset) {
4019	value \|= UPS_CURRENT_CONNECT_STATUS;
4020	}
4021	if (sc->sc_flags.status_suspend) {
4022	value \|= UPS_SUSPEND;
4023	}
4024	USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4025
4026	value = 0;
4027
4028	if (sc->sc_flags.change_connect) {
4029	value \|= UPS_C_CONNECT_STATUS;
4030
4031	if (sc->sc_mode == MUSB2_DEVICE_MODE) {
4032	if (sc->sc_flags.status_vbus &&
4033	sc->sc_flags.status_bus_reset) {
4034	/* reset EP0 state */
4035	sc->sc_ep0_busy = 0;
4036	sc->sc_ep0_cmd = 0;
4037	}
4038	}
4039	}
4040	if (sc->sc_flags.change_suspend)
4041	value \|= UPS_C_SUSPEND;
4042	if (sc->sc_flags.change_reset)
4043	value \|= UPS_C_PORT_RESET;
4044	if (sc->sc_flags.change_over_current)
4045	value \|= UPS_C_OVERCURRENT_INDICATOR;
4046
4047	USETW(sc->sc_hub_temp.ps.wPortChange, value);
4048	len = sizeof(sc->sc_hub_temp.ps);
4049	goto tr_valid;
4050
4051	tr_handle_get_class_descriptor:
4052	if (value & 0xFF) {
4053	goto tr_stalled;
4054	}
4055	ptr = (const void *)&musbotg_hubd;
4056	len = sizeof(musbotg_hubd);
4057	goto tr_valid;
4058
4059	tr_stalled:
4060	err = USB_ERR_STALLED;
4061	tr_valid:
4062	done:
4063	*plength = len;
4064	*pptr = ptr;
4065	return (err);
4066	}
4067
4068	static void
4069	musbotg_xfer_setup(struct usb_setup_params *parm)
4070	{
4071	struct musbotg_softc *sc;
4072	struct usb_xfer *xfer;
4073	void *last_obj;
4074	uint32_t ntd;
4075	uint32_t n;
4076	uint8_t ep_no;
4077
4078	sc = MUSBOTG_BUS2SC(parm->udev->bus);
4079	xfer = parm->curr_xfer;
4080
4081	/*
4082	* NOTE: This driver does not use any of the parameters that
4083	* are computed from the following values. Just set some
4084	* reasonable dummies:
4085	*/
4086	parm->hc_max_packet_size = 0x400;
4087	parm->hc_max_frame_size = 0xc00;
4088
4089	if ((parm->methods == &musbotg_device_isoc_methods) \|\|
4090	(parm->methods == &musbotg_device_intr_methods))
4091	parm->hc_max_packet_count = 3;
4092	else
4093	parm->hc_max_packet_count = 1;
4094
4095	usbd_transfer_setup_sub(parm);
4096
4097	/*
4098	* compute maximum number of TDs
4099	*/
4100	if (parm->methods == &musbotg_device_ctrl_methods) {
4101
4102	ntd = xfer->nframes + 1 /* STATUS / + 1 / SYNC */ ;
4103
4104	} else if (parm->methods == &musbotg_device_bulk_methods) {
4105
4106	ntd = xfer->nframes + 1 /* SYNC */ ;
4107
4108	} else if (parm->methods == &musbotg_device_intr_methods) {
4109
4110	ntd = xfer->nframes + 1 /* SYNC */ ;
4111
4112	} else if (parm->methods == &musbotg_device_isoc_methods) {
4113
4114	ntd = xfer->nframes + 1 /* SYNC */ ;
4115
4116	} else {
4117
4118	ntd = 0;
4119	}
4120
4121	/*
4122	* check if "usbd_transfer_setup_sub" set an error
4123	*/
4124	if (parm->err) {
4125	return;
4126	}
4127	/*
4128	* allocate transfer descriptors
4129	*/
4130	last_obj = NULL;
4131
4132	ep_no = xfer->endpointno & UE_ADDR;
4133
4134	/*
4135	* Check for a valid endpoint profile in USB device mode:
4136	*/
4137	if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4138	const struct usb_hw_ep_profile *pf;
4139
4140	musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4141
4142	if (pf == NULL) {
4143	/* should not happen */
4144	parm->err = USB_ERR_INVAL;
4145	return;
4146	}
4147	}
4148
4149	/* align data */
4150	parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4151
4152	for (n = 0; n != ntd; n++) {
4153
4154	struct musbotg_td *td;
4155
4156	if (parm->buf) {
4157
4158	td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4159
4160	/* init TD */
4161	td->max_frame_size = xfer->max_frame_size;
4162	td->reg_max_packet = xfer->max_packet_size \|
4163	((xfer->max_packet_count - 1) << 11);
4164	td->ep_no = ep_no;
4165	td->obj_next = last_obj;
4166
4167	last_obj = td;
4168	}
4169	parm->size[0] += sizeof(*td);
4170	}
4171
4172	xfer->td_start[0] = last_obj;
4173	}
4174
4175	static void
4176	musbotg_xfer_unsetup(struct usb_xfer *xfer)
4177	{
4178	return;
4179	}
4180
4181	static void
4182	musbotg_get_dma_delay(struct usb_device udev, uint32_t pus)
4183	{
4184	struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4185
4186	if (sc->sc_mode == MUSB2_HOST_MODE)
4187	pus = 2000; / microseconds */
4188	else
4189	*pus = 0;
4190	}
4191
4192	static void
4193	musbotg_ep_init(struct usb_device udev, struct usb_endpoint_descriptor edesc,
4194	struct usb_endpoint *ep)
4195	{
4196	struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4197
4198	DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
4199	ep, udev->address,
4200	edesc->bEndpointAddress, udev->flags.usb_mode,
4201	sc->sc_rt_addr);
4202
4203	if (udev->device_index != sc->sc_rt_addr) {
4204	switch (edesc->bmAttributes & UE_XFERTYPE) {
4205	case UE_CONTROL:
4206	ep->methods = &musbotg_device_ctrl_methods;
4207	break;
4208	case UE_INTERRUPT:
4209	ep->methods = &musbotg_device_intr_methods;
4210	break;
4211	case UE_ISOCHRONOUS:
4212	ep->methods = &musbotg_device_isoc_methods;
4213	break;
4214	case UE_BULK:
4215	ep->methods = &musbotg_device_bulk_methods;
4216	break;
4217	default:
4218	/* do nothing */
4219	break;
4220	}
4221	}
4222	}
4223
4224	static void
4225	musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4226	{
4227	struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
4228
4229	switch (state) {
4230	case USB_HW_POWER_SUSPEND:
4231	musbotg_uninit(sc);
4232	break;
4233	case USB_HW_POWER_SHUTDOWN:
4234	musbotg_uninit(sc);
4235	break;
4236	case USB_HW_POWER_RESUME:
4237	musbotg_init(sc);
4238	break;
4239	default:
4240	break;
4241	}
4242	}
4243
4244	static const struct usb_bus_methods musbotg_bus_methods =
4245	{
4246	.endpoint_init = &musbotg_ep_init,
4247	.get_dma_delay = &musbotg_get_dma_delay,
4248	.xfer_setup = &musbotg_xfer_setup,
4249	.xfer_unsetup = &musbotg_xfer_unsetup,
4250	.get_hw_ep_profile = &musbotg_get_hw_ep_profile,
4251	.xfer_stall = &musbotg_xfer_stall,
4252	.set_stall = &musbotg_set_stall,
4253	.clear_stall = &musbotg_clear_stall,
4254	.roothub_exec = &musbotg_roothub_exec,
4255	.xfer_poll = &musbotg_do_poll,
4256	.set_hw_power_sleep = &musbotg_set_hw_power_sleep,
4257	};

Note: See TracBrowser for help on using the repository browser.

Download in other formats: