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source: rtems-libbsd/freebsd/sys/dev/usb/controller/ehci.c @ 165dd8e

4.1155-freebsd-126-freebsd-12freebsd-9.3

Last change on this file since 165dd8e was 165dd8e, checked in by Sebastian Huber <sebastian.huber@…>, on 04/08/15 at 13:37:49
Update to FreeBSD Stable/9 2015-04-08
Property mode set to `100644`
File size: 94.2 KB

Line
1	#include <machine/rtems-bsd-kernel-space.h>
2
3	/*-
4	* Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
5	* Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved.
6	* Copyright (c) 2004 Lennart Augustsson. All rights reserved.
7	* Copyright (c) 2004 Charles M. Hannum. All rights reserved.
8	*
9	* Redistribution and use in source and binary forms, with or without
10	* modification, are permitted provided that the following conditions
11	* are met:
12	* 1. Redistributions of source code must retain the above copyright
13	* notice, this list of conditions and the following disclaimer.
14	* 2. Redistributions in binary form must reproduce the above copyright
15	* notice, this list of conditions and the following disclaimer in the
16	* documentation and/or other materials provided with the distribution.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*/
30
31	/*
32	* USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
33	*
34	* The EHCI 0.96 spec can be found at
35	* http://developer.intel.com/technology/usb/download/ehci-r096.pdf
36	* The EHCI 1.0 spec can be found at
37	* http://developer.intel.com/technology/usb/download/ehci-r10.pdf
38	* and the USB 2.0 spec at
39	* http://www.usb.org/developers/docs/usb_20.zip
40	*
41	*/
42
43	/*
44	* TODO:
45	* 1) command failures are not recovered correctly
46	*/
47
48	#include <sys/cdefs.h>
49	__FBSDID("$FreeBSD$");
50
51	#include <sys/stdint.h>
52	#include <sys/stddef.h>
53	#include <rtems/bsd/sys/param.h>
54	#include <sys/queue.h>
55	#include <rtems/bsd/sys/types.h>
56	#include <sys/systm.h>
57	#include <sys/kernel.h>
58	#include <sys/bus.h>
59	#include <sys/module.h>
60	#include <rtems/bsd/sys/lock.h>
61	#include <sys/mutex.h>
62	#include <sys/condvar.h>
63	#include <sys/sysctl.h>
64	#include <sys/sx.h>
65	#include <rtems/bsd/sys/unistd.h>
66	#include <sys/callout.h>
67	#include <sys/malloc.h>
68	#include <sys/priv.h>
69
70	#include <dev/usb/usb.h>
71	#include <dev/usb/usbdi.h>
72
73	#define USB_DEBUG_VAR ehcidebug
74
75	#include <dev/usb/usb_core.h>
76	#include <dev/usb/usb_debug.h>
77	#include <dev/usb/usb_busdma.h>
78	#include <dev/usb/usb_process.h>
79	#include <dev/usb/usb_transfer.h>
80	#include <dev/usb/usb_device.h>
81	#include <dev/usb/usb_hub.h>
82	#include <dev/usb/usb_util.h>
83
84	#include <dev/usb/usb_controller.h>
85	#include <dev/usb/usb_bus.h>
86	#include <dev/usb/controller/ehci.h>
87	#include <dev/usb/controller/ehcireg.h>
88
89	#define EHCI_BUS2SC(bus) \
90	((ehci_softc_t )(((uint8_t )(bus)) - \
91	((uint8_t )&(((ehci_softc_t )0)->sc_bus))))
92
93	#ifdef USB_DEBUG
94	static int ehcidebug = 0;
95	static int ehcinohighspeed = 0;
96	static int ehciiaadbug = 0;
97	static int ehcilostintrbug = 0;
98
99	static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
100	SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW \| CTLFLAG_TUN,
101	&ehcidebug, 0, "Debug level");
102	TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug);
103	SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW \| CTLFLAG_TUN,
104	&ehcinohighspeed, 0, "Disable High Speed USB");
105	TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed);
106	SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW \| CTLFLAG_TUN,
107	&ehciiaadbug, 0, "Enable doorbell bug workaround");
108	TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug);
109	SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW \| CTLFLAG_TUN,
110	&ehcilostintrbug, 0, "Enable lost interrupt bug workaround");
111	TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug);
112
113
114	static void ehci_dump_regs(ehci_softc_t *sc);
115	static void ehci_dump_sqh(ehci_softc_t sc, ehci_qh_t sqh);
116
117	#endif
118
119	#define EHCI_INTR_ENDPT 1
120
121	extern struct usb_bus_methods ehci_bus_methods;
122	extern struct usb_pipe_methods ehci_device_bulk_methods;
123	extern struct usb_pipe_methods ehci_device_ctrl_methods;
124	extern struct usb_pipe_methods ehci_device_intr_methods;
125	extern struct usb_pipe_methods ehci_device_isoc_fs_methods;
126	extern struct usb_pipe_methods ehci_device_isoc_hs_methods;
127
128	static void ehci_do_poll(struct usb_bus *);
129	static void ehci_device_done(struct usb_xfer *, usb_error_t);
130	static uint8_t ehci_check_transfer(struct usb_xfer *);
131	static void ehci_timeout(void *);
132	static void ehci_poll_timeout(void *);
133
134	static void ehci_root_intr(ehci_softc_t *sc);
135
136	struct ehci_std_temp {
137	ehci_softc_t *sc;
138	struct usb_page_cache *pc;
139	ehci_qtd_t *td;
140	ehci_qtd_t *td_next;
141	uint32_t average;
142	uint32_t qtd_status;
143	uint32_t len;
144	uint16_t max_frame_size;
145	uint8_t shortpkt;
146	uint8_t auto_data_toggle;
147	uint8_t setup_alt_next;
148	uint8_t last_frame;
149	};
150
151	void
152	ehci_iterate_hw_softc(struct usb_bus bus, usb_bus_mem_sub_cb_t cb)
153	{
154	ehci_softc_t *sc = EHCI_BUS2SC(bus);
155	uint32_t i;
156
157	cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
158	sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN);
159
160	cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg,
161	sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN);
162
163	cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg,
164	sizeof(ehci_qh_t), EHCI_QH_ALIGN);
165
166	for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
167	cb(bus, sc->sc_hw.intr_start_pc + i,
168	sc->sc_hw.intr_start_pg + i,
169	sizeof(ehci_qh_t), EHCI_QH_ALIGN);
170	}
171
172	for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
173	cb(bus, sc->sc_hw.isoc_hs_start_pc + i,
174	sc->sc_hw.isoc_hs_start_pg + i,
175	sizeof(ehci_itd_t), EHCI_ITD_ALIGN);
176	}
177
178	for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
179	cb(bus, sc->sc_hw.isoc_fs_start_pc + i,
180	sc->sc_hw.isoc_fs_start_pg + i,
181	sizeof(ehci_sitd_t), EHCI_SITD_ALIGN);
182	}
183	}
184
185	usb_error_t
186	ehci_reset(ehci_softc_t *sc)
187	{
188	uint32_t hcr;
189	int i;
190
191	EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
192	for (i = 0; i < 100; i++) {
193	usb_pause_mtx(NULL, hz / 128);
194	hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
195	if (!hcr) {
196	if (sc->sc_flags & (EHCI_SCFLG_SETMODE \| EHCI_SCFLG_BIGEMMIO)) {
197	/*
198	* Force USBMODE as requested. Controllers
199	* may have multiple operating modes.
200	*/
201	uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE);
202	if (sc->sc_flags & EHCI_SCFLG_SETMODE) {
203	usbmode = (usbmode &~ EHCI_UM_CM) \| EHCI_UM_CM_HOST;
204	device_printf(sc->sc_bus.bdev,
205	"set host controller mode\n");
206	}
207	if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) {
208	usbmode = (usbmode &~ EHCI_UM_ES) \| EHCI_UM_ES_BE;
209	device_printf(sc->sc_bus.bdev,
210	"set big-endian mode\n");
211	}
212	EOWRITE4(sc, EHCI_USBMODE, usbmode);
213	}
214	return (0);
215	}
216	}
217	device_printf(sc->sc_bus.bdev, "reset timeout\n");
218	return (USB_ERR_IOERROR);
219	}
220
221	static usb_error_t
222	ehci_hcreset(ehci_softc_t *sc)
223	{
224	uint32_t hcr;
225	int i;
226
227	EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
228	for (i = 0; i < 100; i++) {
229	usb_pause_mtx(NULL, hz / 128);
230	hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
231	if (hcr)
232	break;
233	}
234	if (!hcr)
235	/*
236	* Fall through and try reset anyway even though
237	* Table 2-9 in the EHCI spec says this will result
238	* in undefined behavior.
239	*/
240	device_printf(sc->sc_bus.bdev, "stop timeout\n");
241
242	return (ehci_reset(sc));
243	}
244
245	static int
246	ehci_init_sub(struct ehci_softc *sc)
247	{
248	struct usb_page_search buf_res;
249	uint32_t cparams;
250	uint32_t hcr;
251	uint8_t i;
252
253	cparams = EREAD4(sc, EHCI_HCCPARAMS);
254
255	DPRINTF("cparams=0x%x\n", cparams);
256
257	if (EHCI_HCC_64BIT(cparams)) {
258	DPRINTF("HCC uses 64-bit structures\n");
259
260	/* MUST clear segment register if 64 bit capable */
261	EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
262	}
263
264	usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
265	EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
266
267	usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
268	EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr \| EHCI_LINK_QH);
269
270	/* enable interrupts */
271	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
272
273	/* turn on controller */
274	EOWRITE4(sc, EHCI_USBCMD,
275	EHCI_CMD_ITC_1 \| /* 1 microframes interrupt delay */
276	(EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) \|
277	EHCI_CMD_ASE \|
278	EHCI_CMD_PSE \|
279	EHCI_CMD_RS);
280
281	/* Take over port ownership */
282	EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
283
284	for (i = 0; i < 100; i++) {
285	usb_pause_mtx(NULL, hz / 128);
286	hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
287	if (!hcr) {
288	break;
289	}
290	}
291	if (hcr) {
292	device_printf(sc->sc_bus.bdev, "run timeout\n");
293	return (USB_ERR_IOERROR);
294	}
295	return (USB_ERR_NORMAL_COMPLETION);
296	}
297
298	usb_error_t
299	ehci_init(ehci_softc_t *sc)
300	{
301	struct usb_page_search buf_res;
302	uint32_t version;
303	uint32_t sparams;
304	uint16_t i;
305	uint16_t x;
306	uint16_t y;
307	uint16_t bit;
308	usb_error_t err = 0;
309
310	DPRINTF("start\n");
311
312	usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0);
313	usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0);
314
315	sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
316
317	#ifdef USB_DEBUG
318	if (ehciiaadbug)
319	sc->sc_flags \|= EHCI_SCFLG_IAADBUG;
320	if (ehcilostintrbug)
321	sc->sc_flags \|= EHCI_SCFLG_LOSTINTRBUG;
322	if (ehcidebug > 2) {
323	ehci_dump_regs(sc);
324	}
325	#endif
326
327	version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
328	device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
329	version >> 8, version & 0xff);
330
331	sparams = EREAD4(sc, EHCI_HCSPARAMS);
332	DPRINTF("sparams=0x%x\n", sparams);
333
334	sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
335	sc->sc_bus.usbrev = USB_REV_2_0;
336
337	if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) {
338	/* Reset the controller */
339	DPRINTF("%s: resetting\n",
340	device_get_nameunit(sc->sc_bus.bdev));
341
342	err = ehci_hcreset(sc);
343	if (err) {
344	device_printf(sc->sc_bus.bdev, "reset timeout\n");
345	return (err);
346	}
347	}
348
349	/*
350	* use current frame-list-size selection 0: 10244 bytes 1: 5124
351	* bytes 2: 256*4 bytes 3: unknown
352	*/
353	if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) {
354	device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n");
355	return (USB_ERR_IOERROR);
356	}
357	/* set up the bus struct */
358	sc->sc_bus.methods = &ehci_bus_methods;
359
360	sc->sc_eintrs = EHCI_NORMAL_INTRS;
361
362	if (1) {
363	struct ehci_qh_sub *qh;
364
365	usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res);
366
367	qh = buf_res.buffer;
368
369	sc->sc_terminate_self = htohc32(sc, buf_res.physaddr);
370
371	/* init terminate TD */
372	qh->qtd_next =
373	htohc32(sc, EHCI_LINK_TERMINATE);
374	qh->qtd_altnext =
375	htohc32(sc, EHCI_LINK_TERMINATE);
376	qh->qtd_status =
377	htohc32(sc, EHCI_QTD_HALTED);
378	}
379
380	for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
381	ehci_qh_t *qh;
382
383	usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res);
384
385	qh = buf_res.buffer;
386
387	/* initialize page cache pointer */
388
389	qh->page_cache = sc->sc_hw.intr_start_pc + i;
390
391	/* store a pointer to queue head */
392
393	sc->sc_intr_p_last[i] = qh;
394
395	qh->qh_self =
396	htohc32(sc, buf_res.physaddr) \|
397	htohc32(sc, EHCI_LINK_QH);
398
399	qh->qh_endp =
400	htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
401	qh->qh_endphub =
402	htohc32(sc, EHCI_QH_SET_MULT(1));
403	qh->qh_curqtd = 0;
404
405	qh->qh_qtd.qtd_next =
406	htohc32(sc, EHCI_LINK_TERMINATE);
407	qh->qh_qtd.qtd_altnext =
408	htohc32(sc, EHCI_LINK_TERMINATE);
409	qh->qh_qtd.qtd_status =
410	htohc32(sc, EHCI_QTD_HALTED);
411	}
412
413	/*
414	* the QHs are arranged to give poll intervals that are
415	* powers of 2 times 1ms
416	*/
417	bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
418	while (bit) {
419	x = bit;
420	while (x & bit) {
421	ehci_qh_t *qh_x;
422	ehci_qh_t *qh_y;
423
424	y = (x ^ bit) \| (bit / 2);
425
426	qh_x = sc->sc_intr_p_last[x];
427	qh_y = sc->sc_intr_p_last[y];
428
429	/*
430	* the next QH has half the poll interval
431	*/
432	qh_x->qh_link = qh_y->qh_self;
433
434	x++;
435	}
436	bit >>= 1;
437	}
438
439	if (1) {
440	ehci_qh_t *qh;
441
442	qh = sc->sc_intr_p_last[0];
443
444	/* the last (1ms) QH terminates */
445	qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE);
446	}
447	for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
448	ehci_sitd_t *sitd;
449	ehci_itd_t *itd;
450
451	usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res);
452
453	sitd = buf_res.buffer;
454
455	/* initialize page cache pointer */
456
457	sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i;
458
459	/* store a pointer to the transfer descriptor */
460
461	sc->sc_isoc_fs_p_last[i] = sitd;
462
463	/* initialize full speed isochronous */
464
465	sitd->sitd_self =
466	htohc32(sc, buf_res.physaddr) \|
467	htohc32(sc, EHCI_LINK_SITD);
468
469	sitd->sitd_back =
470	htohc32(sc, EHCI_LINK_TERMINATE);
471
472	sitd->sitd_next =
473	sc->sc_intr_p_last[i \| (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self;
474
475
476	usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res);
477
478	itd = buf_res.buffer;
479
480	/* initialize page cache pointer */
481
482	itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i;
483
484	/* store a pointer to the transfer descriptor */
485
486	sc->sc_isoc_hs_p_last[i] = itd;
487
488	/* initialize high speed isochronous */
489
490	itd->itd_self =
491	htohc32(sc, buf_res.physaddr) \|
492	htohc32(sc, EHCI_LINK_ITD);
493
494	itd->itd_next =
495	sitd->sitd_self;
496	}
497
498	usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
499
500	if (1) {
501	uint32_t *pframes;
502
503	pframes = buf_res.buffer;
504
505	/*
506	* execution order:
507	* pframes -> high speed isochronous ->
508	* full speed isochronous -> interrupt QH's
509	*/
510	for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) {
511	pframes[i] = sc->sc_isoc_hs_p_last
512	[i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
513	}
514	}
515	usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
516
517	if (1) {
518
519	ehci_qh_t *qh;
520
521	qh = buf_res.buffer;
522
523	/* initialize page cache pointer */
524
525	qh->page_cache = &sc->sc_hw.async_start_pc;
526
527	/* store a pointer to the queue head */
528
529	sc->sc_async_p_last = qh;
530
531	/* init dummy QH that starts the async list */
532
533	qh->qh_self =
534	htohc32(sc, buf_res.physaddr) \|
535	htohc32(sc, EHCI_LINK_QH);
536
537	/* fill the QH */
538	qh->qh_endp =
539	htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) \| EHCI_QH_HRECL);
540	qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1));
541	qh->qh_link = qh->qh_self;
542	qh->qh_curqtd = 0;
543
544	/* fill the overlay qTD */
545	qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE);
546	qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE);
547	qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED);
548	}
549	/* flush all cache into memory */
550
551	usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc);
552
553	#ifdef USB_DEBUG
554	if (ehcidebug) {
555	ehci_dump_sqh(sc, sc->sc_async_p_last);
556	}
557	#endif
558
559	/* finial setup */
560	err = ehci_init_sub(sc);
561
562	if (!err) {
563	/* catch any lost interrupts */
564	ehci_do_poll(&sc->sc_bus);
565	}
566	return (err);
567	}
568
569	/*
570	* shut down the controller when the system is going down
571	*/
572	void
573	ehci_detach(ehci_softc_t *sc)
574	{
575	USB_BUS_LOCK(&sc->sc_bus);
576
577	usb_callout_stop(&sc->sc_tmo_pcd);
578	usb_callout_stop(&sc->sc_tmo_poll);
579
580	EOWRITE4(sc, EHCI_USBINTR, 0);
581	USB_BUS_UNLOCK(&sc->sc_bus);
582
583	if (ehci_hcreset(sc)) {
584	DPRINTF("reset failed!\n");
585	}
586
587	/* XXX let stray task complete */
588	usb_pause_mtx(NULL, hz / 20);
589
590	usb_callout_drain(&sc->sc_tmo_pcd);
591	usb_callout_drain(&sc->sc_tmo_poll);
592	}
593
594	#ifndef __rtems__
595	static void
596	#else /* __rtems__ */
597	void
598	#endif /* __rtems__ */
599	ehci_suspend(ehci_softc_t *sc)
600	{
601	DPRINTF("stopping the HC\n");
602
603	/* reset HC */
604	ehci_hcreset(sc);
605	}
606
607	#ifndef __rtems__
608	static void
609	#else /* __rtems__ */
610	void
611	#endif /* __rtems__ */
612	ehci_resume(ehci_softc_t *sc)
613	{
614	/* reset HC */
615	ehci_hcreset(sc);
616
617	/* setup HC */
618	ehci_init_sub(sc);
619
620	/* catch any lost interrupts */
621	ehci_do_poll(&sc->sc_bus);
622	}
623
624	#ifdef USB_DEBUG
625	static void
626	ehci_dump_regs(ehci_softc_t *sc)
627	{
628	uint32_t i;
629
630	i = EOREAD4(sc, EHCI_USBCMD);
631	printf("cmd=0x%08x\n", i);
632
633	if (i & EHCI_CMD_ITC_1)
634	printf(" EHCI_CMD_ITC_1\n");
635	if (i & EHCI_CMD_ITC_2)
636	printf(" EHCI_CMD_ITC_2\n");
637	if (i & EHCI_CMD_ITC_4)
638	printf(" EHCI_CMD_ITC_4\n");
639	if (i & EHCI_CMD_ITC_8)
640	printf(" EHCI_CMD_ITC_8\n");
641	if (i & EHCI_CMD_ITC_16)
642	printf(" EHCI_CMD_ITC_16\n");
643	if (i & EHCI_CMD_ITC_32)
644	printf(" EHCI_CMD_ITC_32\n");
645	if (i & EHCI_CMD_ITC_64)
646	printf(" EHCI_CMD_ITC_64\n");
647	if (i & EHCI_CMD_ASPME)
648	printf(" EHCI_CMD_ASPME\n");
649	if (i & EHCI_CMD_ASPMC)
650	printf(" EHCI_CMD_ASPMC\n");
651	if (i & EHCI_CMD_LHCR)
652	printf(" EHCI_CMD_LHCR\n");
653	if (i & EHCI_CMD_IAAD)
654	printf(" EHCI_CMD_IAAD\n");
655	if (i & EHCI_CMD_ASE)
656	printf(" EHCI_CMD_ASE\n");
657	if (i & EHCI_CMD_PSE)
658	printf(" EHCI_CMD_PSE\n");
659	if (i & EHCI_CMD_FLS_M)
660	printf(" EHCI_CMD_FLS_M\n");
661	if (i & EHCI_CMD_HCRESET)
662	printf(" EHCI_CMD_HCRESET\n");
663	if (i & EHCI_CMD_RS)
664	printf(" EHCI_CMD_RS\n");
665
666	i = EOREAD4(sc, EHCI_USBSTS);
667
668	printf("sts=0x%08x\n", i);
669
670	if (i & EHCI_STS_ASS)
671	printf(" EHCI_STS_ASS\n");
672	if (i & EHCI_STS_PSS)
673	printf(" EHCI_STS_PSS\n");
674	if (i & EHCI_STS_REC)
675	printf(" EHCI_STS_REC\n");
676	if (i & EHCI_STS_HCH)
677	printf(" EHCI_STS_HCH\n");
678	if (i & EHCI_STS_IAA)
679	printf(" EHCI_STS_IAA\n");
680	if (i & EHCI_STS_HSE)
681	printf(" EHCI_STS_HSE\n");
682	if (i & EHCI_STS_FLR)
683	printf(" EHCI_STS_FLR\n");
684	if (i & EHCI_STS_PCD)
685	printf(" EHCI_STS_PCD\n");
686	if (i & EHCI_STS_ERRINT)
687	printf(" EHCI_STS_ERRINT\n");
688	if (i & EHCI_STS_INT)
689	printf(" EHCI_STS_INT\n");
690
691	printf("ien=0x%08x\n",
692	EOREAD4(sc, EHCI_USBINTR));
693	printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
694	EOREAD4(sc, EHCI_FRINDEX),
695	EOREAD4(sc, EHCI_CTRLDSSEGMENT),
696	EOREAD4(sc, EHCI_PERIODICLISTBASE),
697	EOREAD4(sc, EHCI_ASYNCLISTADDR));
698	for (i = 1; i <= sc->sc_noport; i++) {
699	printf("port %d status=0x%08x\n", i,
700	EOREAD4(sc, EHCI_PORTSC(i)));
701	}
702	}
703
704	static void
705	ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type)
706	{
707	link = hc32toh(sc, link);
708	printf("0x%08x", link);
709	if (link & EHCI_LINK_TERMINATE)
710	printf("<T>");
711	else {
712	printf("<");
713	if (type) {
714	switch (EHCI_LINK_TYPE(link)) {
715	case EHCI_LINK_ITD:
716	printf("ITD");
717	break;
718	case EHCI_LINK_QH:
719	printf("QH");
720	break;
721	case EHCI_LINK_SITD:
722	printf("SITD");
723	break;
724	case EHCI_LINK_FSTN:
725	printf("FSTN");
726	break;
727	}
728	}
729	printf(">");
730	}
731	}
732
733	static void
734	ehci_dump_qtd(ehci_softc_t sc, ehci_qtd_t qtd)
735	{
736	uint32_t s;
737
738	printf(" next=");
739	ehci_dump_link(sc, qtd->qtd_next, 0);
740	printf(" altnext=");
741	ehci_dump_link(sc, qtd->qtd_altnext, 0);
742	printf("\n");
743	s = hc32toh(sc, qtd->qtd_status);
744	printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
745	s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
746	EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
747	printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n",
748	EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s),
749	(s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE",
750	(s & EHCI_QTD_HALTED) ? "-HALTED" : "",
751	(s & EHCI_QTD_BUFERR) ? "-BUFERR" : "",
752	(s & EHCI_QTD_BABBLE) ? "-BABBLE" : "",
753	(s & EHCI_QTD_XACTERR) ? "-XACTERR" : "",
754	(s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "",
755	(s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "",
756	(s & EHCI_QTD_PINGSTATE) ? "-PING" : "");
757
758	for (s = 0; s < 5; s++) {
759	printf(" buffer[%d]=0x%08x\n", s,
760	hc32toh(sc, qtd->qtd_buffer[s]));
761	}
762	for (s = 0; s < 5; s++) {
763	printf(" buffer_hi[%d]=0x%08x\n", s,
764	hc32toh(sc, qtd->qtd_buffer_hi[s]));
765	}
766	}
767
768	static uint8_t
769	ehci_dump_sqtd(ehci_softc_t sc, ehci_qtd_t sqtd)
770	{
771	uint8_t temp;
772
773	usb_pc_cpu_invalidate(sqtd->page_cache);
774	printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self));
775	ehci_dump_qtd(sc, sqtd);
776	temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0;
777	return (temp);
778	}
779
780	static void
781	ehci_dump_sqtds(ehci_softc_t sc, ehci_qtd_t sqtd)
782	{
783	uint16_t i;
784	uint8_t stop;
785
786	stop = 0;
787	for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) {
788	stop = ehci_dump_sqtd(sc, sqtd);
789	}
790	if (sqtd) {
791	printf("dump aborted, too many TDs\n");
792	}
793	}
794
795	static void
796	ehci_dump_sqh(ehci_softc_t sc, ehci_qh_t qh)
797	{
798	uint32_t endp;
799	uint32_t endphub;
800
801	usb_pc_cpu_invalidate(qh->page_cache);
802	printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F);
803	printf(" link=");
804	ehci_dump_link(sc, qh->qh_link, 1);
805	printf("\n");
806	endp = hc32toh(sc, qh->qh_endp);
807	printf(" endp=0x%08x\n", endp);
808	printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
809	EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
810	EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
811	EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
812	printf(" mpl=0x%x ctl=%d nrl=%d\n",
813	EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
814	EHCI_QH_GET_NRL(endp));
815	endphub = hc32toh(sc, qh->qh_endphub);
816	printf(" endphub=0x%08x\n", endphub);
817	printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
818	EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
819	EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
820	EHCI_QH_GET_MULT(endphub));
821	printf(" curqtd=");
822	ehci_dump_link(sc, qh->qh_curqtd, 0);
823	printf("\n");
824	printf("Overlay qTD:\n");
825	ehci_dump_qtd(sc, (void *)&qh->qh_qtd);
826	}
827
828	static void
829	ehci_dump_sitd(ehci_softc_t sc, ehci_sitd_t sitd)
830	{
831	usb_pc_cpu_invalidate(sitd->page_cache);
832	printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F);
833	printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next));
834	printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n",
835	hc32toh(sc, sitd->sitd_portaddr),
836	(sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN))
837	? "in" : "out",
838	EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)),
839	EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)),
840	EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)),
841	EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr)));
842	printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask));
843	printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status),
844	(sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "",
845	EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status)));
846	printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n",
847	hc32toh(sc, sitd->sitd_back),
848	hc32toh(sc, sitd->sitd_bp[0]),
849	hc32toh(sc, sitd->sitd_bp[1]),
850	hc32toh(sc, sitd->sitd_bp_hi[0]),
851	hc32toh(sc, sitd->sitd_bp_hi[1]));
852	}
853
854	static void
855	ehci_dump_itd(ehci_softc_t sc, ehci_itd_t itd)
856	{
857	usb_pc_cpu_invalidate(itd->page_cache);
858	printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F);
859	printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next));
860	printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]),
861	(itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
862	printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]),
863	(itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
864	printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]),
865	(itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
866	printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]),
867	(itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
868	printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]),
869	(itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
870	printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]),
871	(itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
872	printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]),
873	(itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
874	printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]),
875	(itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
876	printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0]));
877	printf(" addr=0x%02x; endpt=0x%01x\n",
878	EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])),
879	EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0])));
880	printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1]));
881	printf(" dir=%s; mpl=0x%02x\n",
882	(hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out",
883	EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1])));
884	printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n",
885	hc32toh(sc, itd->itd_bp[2]),
886	hc32toh(sc, itd->itd_bp[3]),
887	hc32toh(sc, itd->itd_bp[4]),
888	hc32toh(sc, itd->itd_bp[5]),
889	hc32toh(sc, itd->itd_bp[6]));
890	printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n"
891	" 0x%08x,0x%08x,0x%08x\n",
892	hc32toh(sc, itd->itd_bp_hi[0]),
893	hc32toh(sc, itd->itd_bp_hi[1]),
894	hc32toh(sc, itd->itd_bp_hi[2]),
895	hc32toh(sc, itd->itd_bp_hi[3]),
896	hc32toh(sc, itd->itd_bp_hi[4]),
897	hc32toh(sc, itd->itd_bp_hi[5]),
898	hc32toh(sc, itd->itd_bp_hi[6]));
899	}
900
901	static void
902	ehci_dump_isoc(ehci_softc_t *sc)
903	{
904	ehci_itd_t *itd;
905	ehci_sitd_t *sitd;
906	uint16_t max = 1000;
907	uint16_t pos;
908
909	pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) &
910	(EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
911
912	printf("%s: isochronous dump from frame 0x%03x:\n",
913	__FUNCTION__, pos);
914
915	itd = sc->sc_isoc_hs_p_last[pos];
916	sitd = sc->sc_isoc_fs_p_last[pos];
917
918	while (itd && max && max--) {
919	ehci_dump_itd(sc, itd);
920	itd = itd->prev;
921	}
922
923	while (sitd && max && max--) {
924	ehci_dump_sitd(sc, sitd);
925	sitd = sitd->prev;
926	}
927	}
928
929	#endif
930
931	static void
932	ehci_transfer_intr_enqueue(struct usb_xfer *xfer)
933	{
934	/* check for early completion */
935	if (ehci_check_transfer(xfer)) {
936	return;
937	}
938	/* put transfer on interrupt queue */
939	usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
940
941	/* start timeout, if any */
942	if (xfer->timeout != 0) {
943	usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout);
944	}
945	}
946
947	#define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last)
948	static ehci_sitd_t *
949	_ehci_append_fs_td(ehci_sitd_t std, ehci_sitd_t last)
950	{
951	DPRINTFN(11, "%p to %p\n", std, last);
952
953	/* (sc->sc_bus.mtx) must be locked */
954
955	std->next = last->next;
956	std->sitd_next = last->sitd_next;
957
958	std->prev = last;
959
960	usb_pc_cpu_flush(std->page_cache);
961
962	/*
963	* the last->next->prev is never followed: std->next->prev = std;
964	*/
965	last->next = std;
966	last->sitd_next = std->sitd_self;
967
968	usb_pc_cpu_flush(last->page_cache);
969
970	return (std);
971	}
972
973	#define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last)
974	static ehci_itd_t *
975	_ehci_append_hs_td(ehci_itd_t std, ehci_itd_t last)
976	{
977	DPRINTFN(11, "%p to %p\n", std, last);
978
979	/* (sc->sc_bus.mtx) must be locked */
980
981	std->next = last->next;
982	std->itd_next = last->itd_next;
983
984	std->prev = last;
985
986	usb_pc_cpu_flush(std->page_cache);
987
988	/*
989	* the last->next->prev is never followed: std->next->prev = std;
990	*/
991	last->next = std;
992	last->itd_next = std->itd_self;
993
994	usb_pc_cpu_flush(last->page_cache);
995
996	return (std);
997	}
998
999	#define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last)
1000	static ehci_qh_t *
1001	_ehci_append_qh(ehci_qh_t sqh, ehci_qh_t last)
1002	{
1003	DPRINTFN(11, "%p to %p\n", sqh, last);
1004
1005	if (sqh->prev != NULL) {
1006	/* should not happen */
1007	DPRINTFN(0, "QH already linked!\n");
1008	return (last);
1009	}
1010	/* (sc->sc_bus.mtx) must be locked */
1011
1012	sqh->next = last->next;
1013	sqh->qh_link = last->qh_link;
1014
1015	sqh->prev = last;
1016
1017	usb_pc_cpu_flush(sqh->page_cache);
1018
1019	/*
1020	* the last->next->prev is never followed: sqh->next->prev = sqh;
1021	*/
1022
1023	last->next = sqh;
1024	last->qh_link = sqh->qh_self;
1025
1026	usb_pc_cpu_flush(last->page_cache);
1027
1028	return (sqh);
1029	}
1030
1031	#define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last)
1032	static ehci_sitd_t *
1033	_ehci_remove_fs_td(ehci_sitd_t std, ehci_sitd_t last)
1034	{
1035	DPRINTFN(11, "%p from %p\n", std, last);
1036
1037	/* (sc->sc_bus.mtx) must be locked */
1038
1039	std->prev->next = std->next;
1040	std->prev->sitd_next = std->sitd_next;
1041
1042	usb_pc_cpu_flush(std->prev->page_cache);
1043
1044	if (std->next) {
1045	std->next->prev = std->prev;
1046	usb_pc_cpu_flush(std->next->page_cache);
1047	}
1048	return ((last == std) ? std->prev : last);
1049	}
1050
1051	#define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last)
1052	static ehci_itd_t *
1053	_ehci_remove_hs_td(ehci_itd_t std, ehci_itd_t last)
1054	{
1055	DPRINTFN(11, "%p from %p\n", std, last);
1056
1057	/* (sc->sc_bus.mtx) must be locked */
1058
1059	std->prev->next = std->next;
1060	std->prev->itd_next = std->itd_next;
1061
1062	usb_pc_cpu_flush(std->prev->page_cache);
1063
1064	if (std->next) {
1065	std->next->prev = std->prev;
1066	usb_pc_cpu_flush(std->next->page_cache);
1067	}
1068	return ((last == std) ? std->prev : last);
1069	}
1070
1071	#define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last)
1072	static ehci_qh_t *
1073	_ehci_remove_qh(ehci_qh_t sqh, ehci_qh_t last)
1074	{
1075	DPRINTFN(11, "%p from %p\n", sqh, last);
1076
1077	/* (sc->sc_bus.mtx) must be locked */
1078
1079	/* only remove if not removed from a queue */
1080	if (sqh->prev) {
1081
1082	sqh->prev->next = sqh->next;
1083	sqh->prev->qh_link = sqh->qh_link;
1084
1085	usb_pc_cpu_flush(sqh->prev->page_cache);
1086
1087	if (sqh->next) {
1088	sqh->next->prev = sqh->prev;
1089	usb_pc_cpu_flush(sqh->next->page_cache);
1090	}
1091	last = ((last == sqh) ? sqh->prev : last);
1092
1093	sqh->prev = 0;
1094
1095	usb_pc_cpu_flush(sqh->page_cache);
1096	}
1097	return (last);
1098	}
1099
1100	static void
1101	ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen)
1102	{
1103	uint16_t rem;
1104	uint8_t dt;
1105
1106	/* count number of full packets */
1107	dt = (actlen / xfer->max_packet_size) & 1;
1108
1109	/* compute remainder */
1110	rem = actlen % xfer->max_packet_size;
1111
1112	if (rem > 0)
1113	dt ^= 1; /* short packet at the end */
1114	else if (actlen != xlen)
1115	dt ^= 1; /* zero length packet at the end */
1116	else if (xlen == 0)
1117	dt ^= 1; /* zero length transfer */
1118
1119	xfer->endpoint->toggle_next ^= dt;
1120	}
1121
1122	static usb_error_t
1123	ehci_non_isoc_done_sub(struct usb_xfer *xfer)
1124	{
1125	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1126	ehci_qtd_t *td;
1127	ehci_qtd_t *td_alt_next;
1128	uint32_t status;
1129	uint16_t len;
1130
1131	td = xfer->td_transfer_cache;
1132	td_alt_next = td->alt_next;
1133
1134	if (xfer->aframes != xfer->nframes) {
1135	usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1136	}
1137	while (1) {
1138
1139	usb_pc_cpu_invalidate(td->page_cache);
1140	status = hc32toh(sc, td->qtd_status);
1141
1142	len = EHCI_QTD_GET_BYTES(status);
1143
1144	/*
1145	* Verify the status length and
1146	* add the length to "frlengths[]":
1147	*/
1148	if (len > td->len) {
1149	/* should not happen */
1150	DPRINTF("Invalid status length, "
1151	"0x%04x/0x%04x bytes\n", len, td->len);
1152	status \|= EHCI_QTD_HALTED;
1153	} else if (xfer->aframes != xfer->nframes) {
1154	xfer->frlengths[xfer->aframes] += td->len - len;
1155	/* manually update data toggle */
1156	ehci_data_toggle_update(xfer, td->len - len, td->len);
1157	}
1158
1159	/* Check for last transfer */
1160	if (((void *)td) == xfer->td_transfer_last) {
1161	td = NULL;
1162	break;
1163	}
1164	/* Check for transfer error */
1165	if (status & EHCI_QTD_HALTED) {
1166	/* the transfer is finished */
1167	td = NULL;
1168	break;
1169	}
1170	/* Check for short transfer */
1171	if (len > 0) {
1172	if (xfer->flags_int.short_frames_ok) {
1173	/* follow alt next */
1174	td = td->alt_next;
1175	} else {
1176	/* the transfer is finished */
1177	td = NULL;
1178	}
1179	break;
1180	}
1181	td = td->obj_next;
1182
1183	if (td->alt_next != td_alt_next) {
1184	/* this USB frame is complete */
1185	break;
1186	}
1187	}
1188
1189	/* update transfer cache */
1190
1191	xfer->td_transfer_cache = td;
1192
1193	#ifdef USB_DEBUG
1194	if (status & EHCI_QTD_STATERRS) {
1195	DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x"
1196	"status=%s%s%s%s%s%s%s%s\n",
1197	xfer->address, xfer->endpointno, xfer->aframes,
1198	(status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1199	(status & EHCI_QTD_HALTED) ? "[HALTED]" : "",
1200	(status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "",
1201	(status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "",
1202	(status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "",
1203	(status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "",
1204	(status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "",
1205	(status & EHCI_QTD_PINGSTATE) ? "[PING]" : "");
1206	}
1207	#endif
1208	if (status & EHCI_QTD_HALTED) {
1209	if ((xfer->xroot->udev->parent_hs_hub != NULL) \|\|
1210	(xfer->xroot->udev->address != 0)) {
1211	/* try to separate I/O errors from STALL */
1212	if (EHCI_QTD_GET_CERR(status) == 0)
1213	return (USB_ERR_IOERROR);
1214	}
1215	return (USB_ERR_STALLED);
1216	}
1217	return (USB_ERR_NORMAL_COMPLETION);
1218	}
1219
1220	static void
1221	ehci_non_isoc_done(struct usb_xfer *xfer)
1222	{
1223	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1224	ehci_qh_t *qh;
1225	uint32_t status;
1226	usb_error_t err = 0;
1227
1228	DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1229	xfer, xfer->endpoint);
1230
1231	#ifdef USB_DEBUG
1232	if (ehcidebug > 10) {
1233	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1234
1235	ehci_dump_sqtds(sc, xfer->td_transfer_first);
1236	}
1237	#endif
1238
1239	/* extract data toggle directly from the QH's overlay area */
1240
1241	qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1242
1243	usb_pc_cpu_invalidate(qh->page_cache);
1244
1245	status = hc32toh(sc, qh->qh_qtd.qtd_status);
1246
1247	/* reset scanner */
1248
1249	xfer->td_transfer_cache = xfer->td_transfer_first;
1250
1251	if (xfer->flags_int.control_xfr) {
1252
1253	if (xfer->flags_int.control_hdr) {
1254
1255	err = ehci_non_isoc_done_sub(xfer);
1256	}
1257	xfer->aframes = 1;
1258
1259	if (xfer->td_transfer_cache == NULL) {
1260	goto done;
1261	}
1262	}
1263	while (xfer->aframes != xfer->nframes) {
1264
1265	err = ehci_non_isoc_done_sub(xfer);
1266	xfer->aframes++;
1267
1268	if (xfer->td_transfer_cache == NULL) {
1269	goto done;
1270	}
1271	}
1272
1273	if (xfer->flags_int.control_xfr &&
1274	!xfer->flags_int.control_act) {
1275
1276	err = ehci_non_isoc_done_sub(xfer);
1277	}
1278	done:
1279	ehci_device_done(xfer, err);
1280	}
1281
1282	/------------------------------------------------------------------------
1283	* ehci_check_transfer
1284	*
1285	* Return values:
1286	* 0: USB transfer is not finished
1287	* Else: USB transfer is finished
1288	------------------------------------------------------------------------/
1289	static uint8_t
1290	ehci_check_transfer(struct usb_xfer *xfer)
1291	{
1292	struct usb_pipe_methods *methods = xfer->endpoint->methods;
1293	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1294
1295	uint32_t status;
1296
1297	DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1298
1299	if (methods == &ehci_device_isoc_fs_methods) {
1300	ehci_sitd_t *td;
1301
1302	/* isochronous full speed transfer */
1303
1304	td = xfer->td_transfer_last;
1305	usb_pc_cpu_invalidate(td->page_cache);
1306	status = hc32toh(sc, td->sitd_status);
1307
1308	/* also check if first is complete */
1309
1310	td = xfer->td_transfer_first;
1311	usb_pc_cpu_invalidate(td->page_cache);
1312	status \|= hc32toh(sc, td->sitd_status);
1313
1314	if (!(status & EHCI_SITD_ACTIVE)) {
1315	ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1316	goto transferred;
1317	}
1318	} else if (methods == &ehci_device_isoc_hs_methods) {
1319	ehci_itd_t *td;
1320
1321	/* isochronous high speed transfer */
1322
1323	/* check last transfer */
1324	td = xfer->td_transfer_last;
1325	usb_pc_cpu_invalidate(td->page_cache);
1326	status = td->itd_status[0];
1327	status \|= td->itd_status[1];
1328	status \|= td->itd_status[2];
1329	status \|= td->itd_status[3];
1330	status \|= td->itd_status[4];
1331	status \|= td->itd_status[5];
1332	status \|= td->itd_status[6];
1333	status \|= td->itd_status[7];
1334
1335	/* also check first transfer */
1336	td = xfer->td_transfer_first;
1337	usb_pc_cpu_invalidate(td->page_cache);
1338	status \|= td->itd_status[0];
1339	status \|= td->itd_status[1];
1340	status \|= td->itd_status[2];
1341	status \|= td->itd_status[3];
1342	status \|= td->itd_status[4];
1343	status \|= td->itd_status[5];
1344	status \|= td->itd_status[6];
1345	status \|= td->itd_status[7];
1346
1347	/* if no transactions are active we continue */
1348	if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) {
1349	ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1350	goto transferred;
1351	}
1352	} else {
1353	ehci_qtd_t *td;
1354	ehci_qh_t *qh;
1355
1356	/* non-isochronous transfer */
1357
1358	/*
1359	* check whether there is an error somewhere in the middle,
1360	* or whether there was a short packet (SPD and not ACTIVE)
1361	*/
1362	td = xfer->td_transfer_cache;
1363
1364	qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1365
1366	usb_pc_cpu_invalidate(qh->page_cache);
1367
1368	status = hc32toh(sc, qh->qh_qtd.qtd_status);
1369	if (status & EHCI_QTD_ACTIVE) {
1370	/* transfer is pending */
1371	goto done;
1372	}
1373
1374	while (1) {
1375	usb_pc_cpu_invalidate(td->page_cache);
1376	status = hc32toh(sc, td->qtd_status);
1377
1378	/*
1379	* Check if there is an active TD which
1380	* indicates that the transfer isn't done.
1381	*/
1382	if (status & EHCI_QTD_ACTIVE) {
1383	/* update cache */
1384	xfer->td_transfer_cache = td;
1385	goto done;
1386	}
1387	/*
1388	* last transfer descriptor makes the transfer done
1389	*/
1390	if (((void *)td) == xfer->td_transfer_last) {
1391	break;
1392	}
1393	/*
1394	* any kind of error makes the transfer done
1395	*/
1396	if (status & EHCI_QTD_HALTED) {
1397	break;
1398	}
1399	/*
1400	* if there is no alternate next transfer, a short
1401	* packet also makes the transfer done
1402	*/
1403	if (EHCI_QTD_GET_BYTES(status)) {
1404	if (xfer->flags_int.short_frames_ok) {
1405	/* follow alt next */
1406	if (td->alt_next) {
1407	td = td->alt_next;
1408	continue;
1409	}
1410	}
1411	/* transfer is done */
1412	break;
1413	}
1414	td = td->obj_next;
1415	}
1416	ehci_non_isoc_done(xfer);
1417	goto transferred;
1418	}
1419
1420	done:
1421	DPRINTFN(13, "xfer=%p is still active\n", xfer);
1422	return (0);
1423
1424	transferred:
1425	return (1);
1426	}
1427
1428	static void
1429	ehci_pcd_enable(ehci_softc_t *sc)
1430	{
1431	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1432
1433	sc->sc_eintrs \|= EHCI_STS_PCD;
1434	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1435
1436	/* acknowledge any PCD interrupt */
1437	EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD);
1438
1439	ehci_root_intr(sc);
1440	}
1441
1442	static void
1443	ehci_interrupt_poll(ehci_softc_t *sc)
1444	{
1445	struct usb_xfer *xfer;
1446
1447	repeat:
1448	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1449	/*
1450	* check if transfer is transferred
1451	*/
1452	if (ehci_check_transfer(xfer)) {
1453	/* queue has been modified */
1454	goto repeat;
1455	}
1456	}
1457	}
1458
1459	/*
1460	* Some EHCI chips from VIA / ATI seem to trigger interrupts before
1461	* writing back the qTD status, or miss signalling occasionally under
1462	* heavy load. If the host machine is too fast, we can miss
1463	* transaction completion - when we scan the active list the
1464	* transaction still seems to be active. This generally exhibits
1465	* itself as a umass stall that never recovers.
1466	*
1467	* We work around this behaviour by setting up this callback after any
1468	* softintr that completes with transactions still pending, giving us
1469	* another chance to check for completion after the writeback has
1470	* taken place.
1471	*/
1472	static void
1473	ehci_poll_timeout(void *arg)
1474	{
1475	ehci_softc_t *sc = arg;
1476
1477	DPRINTFN(3, "\n");
1478	ehci_interrupt_poll(sc);
1479	}
1480
1481	/------------------------------------------------------------------------
1482	* ehci_interrupt - EHCI interrupt handler
1483	*
1484	* NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1485	* hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1486	* is present !
1487	------------------------------------------------------------------------/
1488	void
1489	ehci_interrupt(ehci_softc_t *sc)
1490	{
1491	uint32_t status;
1492
1493	USB_BUS_LOCK(&sc->sc_bus);
1494
1495	DPRINTFN(16, "real interrupt\n");
1496
1497	#ifdef USB_DEBUG
1498	if (ehcidebug > 15) {
1499	ehci_dump_regs(sc);
1500	}
1501	#endif
1502
1503	status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1504	if (status == 0) {
1505	/* the interrupt was not for us */
1506	goto done;
1507	}
1508	if (!(status & sc->sc_eintrs)) {
1509	goto done;
1510	}
1511	EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */
1512
1513	status &= sc->sc_eintrs;
1514
1515	if (status & EHCI_STS_HSE) {
1516	printf("%s: unrecoverable error, "
1517	"controller halted\n", __FUNCTION__);
1518	#ifdef USB_DEBUG
1519	ehci_dump_regs(sc);
1520	ehci_dump_isoc(sc);
1521	#endif
1522	}
1523	if (status & EHCI_STS_PCD) {
1524	/*
1525	* Disable PCD interrupt for now, because it will be
1526	* on until the port has been reset.
1527	*/
1528	sc->sc_eintrs &= ~EHCI_STS_PCD;
1529	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1530
1531	ehci_root_intr(sc);
1532
1533	/* do not allow RHSC interrupts > 1 per second */
1534	usb_callout_reset(&sc->sc_tmo_pcd, hz,
1535	(void *)&ehci_pcd_enable, sc);
1536	}
1537	status &= ~(EHCI_STS_INT \| EHCI_STS_ERRINT \| EHCI_STS_PCD \| EHCI_STS_IAA);
1538
1539	if (status != 0) {
1540	/* block unprocessed interrupts */
1541	sc->sc_eintrs &= ~status;
1542	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1543	printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status);
1544	}
1545	/* poll all the USB transfers */
1546	ehci_interrupt_poll(sc);
1547
1548	if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) {
1549	usb_callout_reset(&sc->sc_tmo_poll, hz / 128,
1550	(void *)&ehci_poll_timeout, sc);
1551	}
1552
1553	done:
1554	USB_BUS_UNLOCK(&sc->sc_bus);
1555	}
1556
1557	/*
1558	* called when a request does not complete
1559	*/
1560	static void
1561	ehci_timeout(void *arg)
1562	{
1563	struct usb_xfer *xfer = arg;
1564
1565	DPRINTF("xfer=%p\n", xfer);
1566
1567	USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1568
1569	/* transfer is transferred */
1570	ehci_device_done(xfer, USB_ERR_TIMEOUT);
1571	}
1572
1573	static void
1574	ehci_do_poll(struct usb_bus *bus)
1575	{
1576	ehci_softc_t *sc = EHCI_BUS2SC(bus);
1577
1578	USB_BUS_LOCK(&sc->sc_bus);
1579	ehci_interrupt_poll(sc);
1580	USB_BUS_UNLOCK(&sc->sc_bus);
1581	}
1582
1583	static void
1584	ehci_setup_standard_chain_sub(struct ehci_std_temp *temp)
1585	{
1586	struct usb_page_search buf_res;
1587	ehci_qtd_t *td;
1588	ehci_qtd_t *td_next;
1589	ehci_qtd_t *td_alt_next;
1590	uint32_t buf_offset;
1591	uint32_t average;
1592	uint32_t len_old;
1593	uint32_t terminate;
1594	uint32_t qtd_altnext;
1595	uint8_t shortpkt_old;
1596	uint8_t precompute;
1597
1598	terminate = temp->sc->sc_terminate_self;
1599	qtd_altnext = temp->sc->sc_terminate_self;
1600	td_alt_next = NULL;
1601	buf_offset = 0;
1602	shortpkt_old = temp->shortpkt;
1603	len_old = temp->len;
1604	precompute = 1;
1605
1606	restart:
1607
1608	td = temp->td;
1609	td_next = temp->td_next;
1610
1611	while (1) {
1612
1613	if (temp->len == 0) {
1614
1615	if (temp->shortpkt) {
1616	break;
1617	}
1618	/* send a Zero Length Packet, ZLP, last */
1619
1620	temp->shortpkt = 1;
1621	average = 0;
1622
1623	} else {
1624
1625	average = temp->average;
1626
1627	if (temp->len < average) {
1628	if (temp->len % temp->max_frame_size) {
1629	temp->shortpkt = 1;
1630	}
1631	average = temp->len;
1632	}
1633	}
1634
1635	if (td_next == NULL) {
1636	panic("%s: out of EHCI transfer descriptors!", __FUNCTION__);
1637	}
1638	/* get next TD */
1639
1640	td = td_next;
1641	td_next = td->obj_next;
1642
1643	/* check if we are pre-computing */
1644
1645	if (precompute) {
1646
1647	/* update remaining length */
1648
1649	temp->len -= average;
1650
1651	continue;
1652	}
1653	/* fill out current TD */
1654
1655	td->qtd_status =
1656	temp->qtd_status \|
1657	htohc32(temp->sc, EHCI_QTD_IOC \|
1658	EHCI_QTD_SET_BYTES(average));
1659
1660	if (average == 0) {
1661
1662	if (temp->auto_data_toggle == 0) {
1663
1664	/* update data toggle, ZLP case */
1665
1666	temp->qtd_status ^=
1667	htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1668	}
1669	td->len = 0;
1670
1671	/* properly reset reserved fields */
1672	td->qtd_buffer[0] = 0;
1673	td->qtd_buffer[1] = 0;
1674	td->qtd_buffer[2] = 0;
1675	td->qtd_buffer[3] = 0;
1676	td->qtd_buffer[4] = 0;
1677	td->qtd_buffer_hi[0] = 0;
1678	td->qtd_buffer_hi[1] = 0;
1679	td->qtd_buffer_hi[2] = 0;
1680	td->qtd_buffer_hi[3] = 0;
1681	td->qtd_buffer_hi[4] = 0;
1682	} else {
1683
1684	uint8_t x;
1685
1686	if (temp->auto_data_toggle == 0) {
1687
1688	/* update data toggle */
1689
1690	if (((average + temp->max_frame_size - 1) /
1691	temp->max_frame_size) & 1) {
1692	temp->qtd_status ^=
1693	htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1694	}
1695	}
1696	td->len = average;
1697
1698	/* update remaining length */
1699
1700	temp->len -= average;
1701
1702	/* fill out buffer pointers */
1703
1704	usbd_get_page(temp->pc, buf_offset, &buf_res);
1705	td->qtd_buffer[0] =
1706	htohc32(temp->sc, buf_res.physaddr);
1707	td->qtd_buffer_hi[0] = 0;
1708
1709	x = 1;
1710
1711	while (average > EHCI_PAGE_SIZE) {
1712	average -= EHCI_PAGE_SIZE;
1713	buf_offset += EHCI_PAGE_SIZE;
1714	usbd_get_page(temp->pc, buf_offset, &buf_res);
1715	td->qtd_buffer[x] =
1716	htohc32(temp->sc,
1717	buf_res.physaddr & (~0xFFF));
1718	td->qtd_buffer_hi[x] = 0;
1719	x++;
1720	}
1721
1722	/*
1723	* NOTE: The "average" variable is never zero after
1724	* exiting the loop above !
1725	*
1726	* NOTE: We have to subtract one from the offset to
1727	* ensure that we are computing the physical address
1728	* of a valid page !
1729	*/
1730	buf_offset += average;
1731	usbd_get_page(temp->pc, buf_offset - 1, &buf_res);
1732	td->qtd_buffer[x] =
1733	htohc32(temp->sc,
1734	buf_res.physaddr & (~0xFFF));
1735	td->qtd_buffer_hi[x] = 0;
1736
1737	/* properly reset reserved fields */
1738	while (++x < EHCI_QTD_NBUFFERS) {
1739	td->qtd_buffer[x] = 0;
1740	td->qtd_buffer_hi[x] = 0;
1741	}
1742	}
1743
1744	if (td_next) {
1745	/* link the current TD with the next one */
1746	td->qtd_next = td_next->qtd_self;
1747	}
1748	td->qtd_altnext = qtd_altnext;
1749	td->alt_next = td_alt_next;
1750
1751	usb_pc_cpu_flush(td->page_cache);
1752	}
1753
1754	if (precompute) {
1755	precompute = 0;
1756
1757	/* setup alt next pointer, if any */
1758	if (temp->last_frame) {
1759	td_alt_next = NULL;
1760	qtd_altnext = terminate;
1761	} else {
1762	/* we use this field internally */
1763	td_alt_next = td_next;
1764	if (temp->setup_alt_next) {
1765	qtd_altnext = td_next->qtd_self;
1766	} else {
1767	qtd_altnext = terminate;
1768	}
1769	}
1770
1771	/* restore */
1772	temp->shortpkt = shortpkt_old;
1773	temp->len = len_old;
1774	goto restart;
1775	}
1776	temp->td = td;
1777	temp->td_next = td_next;
1778	}
1779
1780	static void
1781	ehci_setup_standard_chain(struct usb_xfer xfer, ehci_qh_t *qh_last)
1782	{
1783	struct ehci_std_temp temp;
1784	struct usb_pipe_methods *methods;
1785	ehci_qh_t *qh;
1786	ehci_qtd_t *td;
1787	uint32_t qh_endp;
1788	uint32_t qh_endphub;
1789	uint32_t x;
1790
1791	DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1792	xfer->address, UE_GET_ADDR(xfer->endpointno),
1793	xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1794
1795	temp.average = xfer->max_hc_frame_size;
1796	temp.max_frame_size = xfer->max_frame_size;
1797	temp.sc = EHCI_BUS2SC(xfer->xroot->bus);
1798
1799	/* toggle the DMA set we are using */
1800	xfer->flags_int.curr_dma_set ^= 1;
1801
1802	/* get next DMA set */
1803	td = xfer->td_start[xfer->flags_int.curr_dma_set];
1804
1805	xfer->td_transfer_first = td;
1806	xfer->td_transfer_cache = td;
1807
1808	temp.td = NULL;
1809	temp.td_next = td;
1810	temp.qtd_status = 0;
1811	temp.last_frame = 0;
1812	temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1813
1814	if (xfer->flags_int.control_xfr) {
1815	if (xfer->endpoint->toggle_next) {
1816	/* DATA1 is next */
1817	temp.qtd_status \|=
1818	htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1819	}
1820	temp.auto_data_toggle = 0;
1821	} else {
1822	temp.auto_data_toggle = 1;
1823	}
1824
1825	if ((xfer->xroot->udev->parent_hs_hub != NULL) \|\|
1826	(xfer->xroot->udev->address != 0)) {
1827	/* max 3 retries */
1828	temp.qtd_status \|=
1829	htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1830	}
1831	/* check if we should prepend a setup message */
1832
1833	if (xfer->flags_int.control_xfr) {
1834	if (xfer->flags_int.control_hdr) {
1835
1836	xfer->endpoint->toggle_next = 0;
1837
1838	temp.qtd_status &=
1839	htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1840	temp.qtd_status \|= htohc32(temp.sc,
1841	EHCI_QTD_ACTIVE \|
1842	EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) \|
1843	EHCI_QTD_SET_TOGGLE(0));
1844
1845	temp.len = xfer->frlengths[0];
1846	temp.pc = xfer->frbuffers + 0;
1847	temp.shortpkt = temp.len ? 1 : 0;
1848	/* check for last frame */
1849	if (xfer->nframes == 1) {
1850	/* no STATUS stage yet, SETUP is last */
1851	if (xfer->flags_int.control_act) {
1852	temp.last_frame = 1;
1853	temp.setup_alt_next = 0;
1854	}
1855	}
1856	ehci_setup_standard_chain_sub(&temp);
1857	}
1858	x = 1;
1859	} else {
1860	x = 0;
1861	}
1862
1863	while (x != xfer->nframes) {
1864
1865	/* DATA0 / DATA1 message */
1866
1867	temp.len = xfer->frlengths[x];
1868	temp.pc = xfer->frbuffers + x;
1869
1870	x++;
1871
1872	if (x == xfer->nframes) {
1873	if (xfer->flags_int.control_xfr) {
1874	/* no STATUS stage yet, DATA is last */
1875	if (xfer->flags_int.control_act) {
1876	temp.last_frame = 1;
1877	temp.setup_alt_next = 0;
1878	}
1879	} else {
1880	temp.last_frame = 1;
1881	temp.setup_alt_next = 0;
1882	}
1883	}
1884	/* keep previous data toggle and error count */
1885
1886	temp.qtd_status &=
1887	htohc32(temp.sc, EHCI_QTD_SET_CERR(3) \|
1888	EHCI_QTD_SET_TOGGLE(1));
1889
1890	if (temp.len == 0) {
1891
1892	/* make sure that we send an USB packet */
1893
1894	temp.shortpkt = 0;
1895
1896	} else {
1897
1898	/* regular data transfer */
1899
1900	temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1901	}
1902
1903	/* set endpoint direction */
1904
1905	temp.qtd_status \|=
1906	(UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1907	htohc32(temp.sc, EHCI_QTD_ACTIVE \|
1908	EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) :
1909	htohc32(temp.sc, EHCI_QTD_ACTIVE \|
1910	EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT));
1911
1912	ehci_setup_standard_chain_sub(&temp);
1913	}
1914
1915	/* check if we should append a status stage */
1916
1917	if (xfer->flags_int.control_xfr &&
1918	!xfer->flags_int.control_act) {
1919
1920	/*
1921	* Send a DATA1 message and invert the current endpoint
1922	* direction.
1923	*/
1924
1925	temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) \|
1926	EHCI_QTD_SET_TOGGLE(1));
1927	temp.qtd_status \|=
1928	(UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1929	htohc32(temp.sc, EHCI_QTD_ACTIVE \|
1930	EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) \|
1931	EHCI_QTD_SET_TOGGLE(1)) :
1932	htohc32(temp.sc, EHCI_QTD_ACTIVE \|
1933	EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) \|
1934	EHCI_QTD_SET_TOGGLE(1));
1935
1936	temp.len = 0;
1937	temp.pc = NULL;
1938	temp.shortpkt = 0;
1939	temp.last_frame = 1;
1940	temp.setup_alt_next = 0;
1941
1942	ehci_setup_standard_chain_sub(&temp);
1943	}
1944	td = temp.td;
1945
1946	/* the last TD terminates the transfer: */
1947	td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1948	td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1949
1950	usb_pc_cpu_flush(td->page_cache);
1951
1952	/* must have at least one frame! */
1953
1954	xfer->td_transfer_last = td;
1955
1956	#ifdef USB_DEBUG
1957	if (ehcidebug > 8) {
1958	DPRINTF("nexttog=%d; data before transfer:\n",
1959	xfer->endpoint->toggle_next);
1960	ehci_dump_sqtds(temp.sc,
1961	xfer->td_transfer_first);
1962	}
1963	#endif
1964
1965	methods = xfer->endpoint->methods;
1966
1967	qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1968
1969	/* the "qh_link" field is filled when the QH is added */
1970
1971	qh_endp =
1972	(EHCI_QH_SET_ADDR(xfer->address) \|
1973	EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) \|
1974	EHCI_QH_SET_MPL(xfer->max_packet_size));
1975
1976	if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
1977	qh_endp \|= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH);
1978	if (methods != &ehci_device_intr_methods)
1979	qh_endp \|= EHCI_QH_SET_NRL(8);
1980	} else {
1981
1982	if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) {
1983	qh_endp \|= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL);
1984	} else {
1985	qh_endp \|= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW);
1986	}
1987
1988	if (methods == &ehci_device_ctrl_methods) {
1989	qh_endp \|= EHCI_QH_CTL;
1990	}
1991	if (methods != &ehci_device_intr_methods) {
1992	/* Only try one time per microframe! */
1993	qh_endp \|= EHCI_QH_SET_NRL(1);
1994	}
1995	}
1996
1997	if (temp.auto_data_toggle == 0) {
1998	/* software computes the data toggle */
1999	qh_endp \|= EHCI_QH_DTC;
2000	}
2001
2002	qh->qh_endp = htohc32(temp.sc, qh_endp);
2003
2004	qh_endphub =
2005	(EHCI_QH_SET_MULT(xfer->max_packet_count & 3) \|
2006	EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) \|
2007	EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) \|
2008	EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) \|
2009	EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no));
2010
2011	qh->qh_endphub = htohc32(temp.sc, qh_endphub);
2012	qh->qh_curqtd = 0;
2013
2014	/* fill the overlay qTD */
2015
2016	if (temp.auto_data_toggle && xfer->endpoint->toggle_next) {
2017	/* DATA1 is next */
2018	qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
2019	} else {
2020	qh->qh_qtd.qtd_status = 0;
2021	}
2022
2023	td = xfer->td_transfer_first;
2024
2025	qh->qh_qtd.qtd_next = td->qtd_self;
2026	qh->qh_qtd.qtd_altnext =
2027	htohc32(temp.sc, EHCI_LINK_TERMINATE);
2028
2029	/* properly reset reserved fields */
2030	qh->qh_qtd.qtd_buffer[0] = 0;
2031	qh->qh_qtd.qtd_buffer[1] = 0;
2032	qh->qh_qtd.qtd_buffer[2] = 0;
2033	qh->qh_qtd.qtd_buffer[3] = 0;
2034	qh->qh_qtd.qtd_buffer[4] = 0;
2035	qh->qh_qtd.qtd_buffer_hi[0] = 0;
2036	qh->qh_qtd.qtd_buffer_hi[1] = 0;
2037	qh->qh_qtd.qtd_buffer_hi[2] = 0;
2038	qh->qh_qtd.qtd_buffer_hi[3] = 0;
2039	qh->qh_qtd.qtd_buffer_hi[4] = 0;
2040
2041	usb_pc_cpu_flush(qh->page_cache);
2042
2043	if (xfer->xroot->udev->flags.self_suspended == 0) {
2044	EHCI_APPEND_QH(qh, *qh_last);
2045	}
2046	}
2047
2048	static void
2049	ehci_root_intr(ehci_softc_t *sc)
2050	{
2051	uint16_t i;
2052	uint16_t m;
2053
2054	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2055
2056	/* clear any old interrupt data */
2057	memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2058
2059	/* set bits */
2060	m = (sc->sc_noport + 1);
2061	if (m > (8 * sizeof(sc->sc_hub_idata))) {
2062	m = (8 * sizeof(sc->sc_hub_idata));
2063	}
2064	for (i = 1; i < m; i++) {
2065	/* pick out CHANGE bits from the status register */
2066	if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) {
2067	sc->sc_hub_idata[i / 8] \|= 1 << (i % 8);
2068	DPRINTF("port %d changed\n", i);
2069	}
2070	}
2071	uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2072	sizeof(sc->sc_hub_idata));
2073	}
2074
2075	static void
2076	ehci_isoc_fs_done(ehci_softc_t sc, struct usb_xfer xfer)
2077	{
2078	uint32_t nframes = xfer->nframes;
2079	uint32_t status;
2080	uint32_t *plen = xfer->frlengths;
2081	uint16_t len = 0;
2082	ehci_sitd_t *td = xfer->td_transfer_first;
2083	ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos];
2084
2085	DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2086	xfer, xfer->endpoint);
2087
2088	while (nframes--) {
2089	if (td == NULL) {
2090	panic("%s:%d: out of TD's\n",
2091	__FUNCTION__, __LINE__);
2092	}
2093	if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2094	pp_last = &sc->sc_isoc_fs_p_last[0];
2095	}
2096	#ifdef USB_DEBUG
2097	if (ehcidebug > 15) {
2098	DPRINTF("isoc FS-TD\n");
2099	ehci_dump_sitd(sc, td);
2100	}
2101	#endif
2102	usb_pc_cpu_invalidate(td->page_cache);
2103	status = hc32toh(sc, td->sitd_status);
2104
2105	len = EHCI_SITD_GET_LEN(status);
2106
2107	DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len);
2108
2109	if (*plen >= len) {
2110	len = *plen - len;
2111	} else {
2112	len = 0;
2113	}
2114
2115	*plen = len;
2116
2117	/* remove FS-TD from schedule */
2118	EHCI_REMOVE_FS_TD(td, *pp_last);
2119
2120	pp_last++;
2121	plen++;
2122	td = td->obj_next;
2123	}
2124
2125	xfer->aframes = xfer->nframes;
2126	}
2127
2128	static void
2129	ehci_isoc_hs_done(ehci_softc_t sc, struct usb_xfer xfer)
2130	{
2131	uint32_t nframes = xfer->nframes;
2132	uint32_t status;
2133	uint32_t *plen = xfer->frlengths;
2134	uint16_t len = 0;
2135	uint8_t td_no = 0;
2136	ehci_itd_t *td = xfer->td_transfer_first;
2137	ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos];
2138
2139	DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2140	xfer, xfer->endpoint);
2141
2142	while (nframes) {
2143	if (td == NULL) {
2144	panic("%s:%d: out of TD's\n",
2145	__FUNCTION__, __LINE__);
2146	}
2147	if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2148	pp_last = &sc->sc_isoc_hs_p_last[0];
2149	}
2150	#ifdef USB_DEBUG
2151	if (ehcidebug > 15) {
2152	DPRINTF("isoc HS-TD\n");
2153	ehci_dump_itd(sc, td);
2154	}
2155	#endif
2156
2157	usb_pc_cpu_invalidate(td->page_cache);
2158	status = hc32toh(sc, td->itd_status[td_no]);
2159
2160	len = EHCI_ITD_GET_LEN(status);
2161
2162	DPRINTFN(2, "status=0x%08x, len=%u\n", status, len);
2163
2164	if (xfer->endpoint->usb_smask & (1 << td_no)) {
2165
2166	if (*plen >= len) {
2167	/*
2168	* The length is valid. NOTE: The
2169	* complete length is written back
2170	* into the status field, and not the
2171	* remainder like with other transfer
2172	* descriptor types.
2173	*/
2174	} else {
2175	/* Invalid length - truncate */
2176	len = 0;
2177	}
2178
2179	*plen = len;
2180	plen++;
2181	nframes--;
2182	}
2183
2184	td_no++;
2185
2186	if ((td_no == 8) \|\| (nframes == 0)) {
2187	/* remove HS-TD from schedule */
2188	EHCI_REMOVE_HS_TD(td, *pp_last);
2189	pp_last++;
2190
2191	td_no = 0;
2192	td = td->obj_next;
2193	}
2194	}
2195	xfer->aframes = xfer->nframes;
2196	}
2197
2198	/* NOTE: "done" can be run two times in a row,
2199	* from close and from interrupt
2200	*/
2201	static void
2202	ehci_device_done(struct usb_xfer *xfer, usb_error_t error)
2203	{
2204	struct usb_pipe_methods *methods = xfer->endpoint->methods;
2205	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2206
2207	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2208
2209	DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2210	xfer, xfer->endpoint, error);
2211
2212	if ((methods == &ehci_device_bulk_methods) \|\|
2213	(methods == &ehci_device_ctrl_methods)) {
2214	#ifdef USB_DEBUG
2215	if (ehcidebug > 8) {
2216	DPRINTF("nexttog=%d; data after transfer:\n",
2217	xfer->endpoint->toggle_next);
2218	ehci_dump_sqtds(sc,
2219	xfer->td_transfer_first);
2220	}
2221	#endif
2222
2223	EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2224	sc->sc_async_p_last);
2225	}
2226	if (methods == &ehci_device_intr_methods) {
2227	EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2228	sc->sc_intr_p_last[xfer->qh_pos]);
2229	}
2230	/*
2231	* Only finish isochronous transfers once which will update
2232	* "xfer->frlengths".
2233	*/
2234	if (xfer->td_transfer_first &&
2235	xfer->td_transfer_last) {
2236	if (methods == &ehci_device_isoc_fs_methods) {
2237	ehci_isoc_fs_done(sc, xfer);
2238	}
2239	if (methods == &ehci_device_isoc_hs_methods) {
2240	ehci_isoc_hs_done(sc, xfer);
2241	}
2242	xfer->td_transfer_first = NULL;
2243	xfer->td_transfer_last = NULL;
2244	}
2245	/* dequeue transfer and start next transfer */
2246	usbd_transfer_done(xfer, error);
2247	}
2248
2249	/------------------------------------------------------------------------
2250	* ehci bulk support
2251	------------------------------------------------------------------------/
2252	static void
2253	ehci_device_bulk_open(struct usb_xfer *xfer)
2254	{
2255	return;
2256	}
2257
2258	static void
2259	ehci_device_bulk_close(struct usb_xfer *xfer)
2260	{
2261	ehci_device_done(xfer, USB_ERR_CANCELLED);
2262	}
2263
2264	static void
2265	ehci_device_bulk_enter(struct usb_xfer *xfer)
2266	{
2267	return;
2268	}
2269
2270	static void
2271	ehci_doorbell_async(struct ehci_softc *sc)
2272	{
2273	uint32_t temp;
2274
2275	/*
2276	* XXX Performance quirk: Some Host Controllers have a too low
2277	* interrupt rate. Issue an IAAD to stimulate the Host
2278	* Controller after queueing the BULK transfer.
2279	*
2280	* XXX Force the host controller to refresh any QH caches.
2281	*/
2282	temp = EOREAD4(sc, EHCI_USBCMD);
2283	if (!(temp & EHCI_CMD_IAAD))
2284	EOWRITE4(sc, EHCI_USBCMD, temp \| EHCI_CMD_IAAD);
2285	}
2286
2287	static void
2288	ehci_device_bulk_start(struct usb_xfer *xfer)
2289	{
2290	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2291
2292	/* setup TD's and QH */
2293	ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2294
2295	/* put transfer on interrupt queue */
2296	ehci_transfer_intr_enqueue(xfer);
2297
2298	/*
2299	* XXX Certain nVidia chipsets choke when using the IAAD
2300	* feature too frequently.
2301	*/
2302	if (sc->sc_flags & EHCI_SCFLG_IAADBUG)
2303	return;
2304
2305	ehci_doorbell_async(sc);
2306	}
2307
2308	struct usb_pipe_methods ehci_device_bulk_methods =
2309	{
2310	.open = ehci_device_bulk_open,
2311	.close = ehci_device_bulk_close,
2312	.enter = ehci_device_bulk_enter,
2313	.start = ehci_device_bulk_start,
2314	};
2315
2316	/------------------------------------------------------------------------
2317	* ehci control support
2318	------------------------------------------------------------------------/
2319	static void
2320	ehci_device_ctrl_open(struct usb_xfer *xfer)
2321	{
2322	return;
2323	}
2324
2325	static void
2326	ehci_device_ctrl_close(struct usb_xfer *xfer)
2327	{
2328	ehci_device_done(xfer, USB_ERR_CANCELLED);
2329	}
2330
2331	static void
2332	ehci_device_ctrl_enter(struct usb_xfer *xfer)
2333	{
2334	return;
2335	}
2336
2337	static void
2338	ehci_device_ctrl_start(struct usb_xfer *xfer)
2339	{
2340	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2341
2342	/* setup TD's and QH */
2343	ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2344
2345	/* put transfer on interrupt queue */
2346	ehci_transfer_intr_enqueue(xfer);
2347	}
2348
2349	struct usb_pipe_methods ehci_device_ctrl_methods =
2350	{
2351	.open = ehci_device_ctrl_open,
2352	.close = ehci_device_ctrl_close,
2353	.enter = ehci_device_ctrl_enter,
2354	.start = ehci_device_ctrl_start,
2355	};
2356
2357	/------------------------------------------------------------------------
2358	* ehci interrupt support
2359	------------------------------------------------------------------------/
2360	static void
2361	ehci_device_intr_open(struct usb_xfer *xfer)
2362	{
2363	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2364	uint16_t best;
2365	uint16_t bit;
2366	uint16_t x;
2367
2368	usb_hs_bandwidth_alloc(xfer);
2369
2370	/*
2371	* Find the best QH position corresponding to the given interval:
2372	*/
2373
2374	best = 0;
2375	bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
2376	while (bit) {
2377	if (xfer->interval >= bit) {
2378	x = bit;
2379	best = bit;
2380	while (x & bit) {
2381	if (sc->sc_intr_stat[x] <
2382	sc->sc_intr_stat[best]) {
2383	best = x;
2384	}
2385	x++;
2386	}
2387	break;
2388	}
2389	bit >>= 1;
2390	}
2391
2392	sc->sc_intr_stat[best]++;
2393	xfer->qh_pos = best;
2394
2395	DPRINTFN(3, "best=%d interval=%d\n",
2396	best, xfer->interval);
2397	}
2398
2399	static void
2400	ehci_device_intr_close(struct usb_xfer *xfer)
2401	{
2402	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2403
2404	sc->sc_intr_stat[xfer->qh_pos]--;
2405
2406	ehci_device_done(xfer, USB_ERR_CANCELLED);
2407
2408	/* bandwidth must be freed after device done */
2409	usb_hs_bandwidth_free(xfer);
2410	}
2411
2412	static void
2413	ehci_device_intr_enter(struct usb_xfer *xfer)
2414	{
2415	return;
2416	}
2417
2418	static void
2419	ehci_device_intr_start(struct usb_xfer *xfer)
2420	{
2421	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2422
2423	/* setup TD's and QH */
2424	ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
2425
2426	/* put transfer on interrupt queue */
2427	ehci_transfer_intr_enqueue(xfer);
2428	}
2429
2430	struct usb_pipe_methods ehci_device_intr_methods =
2431	{
2432	.open = ehci_device_intr_open,
2433	.close = ehci_device_intr_close,
2434	.enter = ehci_device_intr_enter,
2435	.start = ehci_device_intr_start,
2436	};
2437
2438	/------------------------------------------------------------------------
2439	* ehci full speed isochronous support
2440	------------------------------------------------------------------------/
2441	static void
2442	ehci_device_isoc_fs_open(struct usb_xfer *xfer)
2443	{
2444	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2445	ehci_sitd_t *td;
2446	uint32_t sitd_portaddr;
2447	uint8_t ds;
2448
2449	sitd_portaddr =
2450	EHCI_SITD_SET_ADDR(xfer->address) \|
2451	EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) \|
2452	EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) \|
2453	EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no);
2454
2455	if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN)
2456	sitd_portaddr \|= EHCI_SITD_SET_DIR_IN;
2457
2458	sitd_portaddr = htohc32(sc, sitd_portaddr);
2459
2460	/* initialize all TD's */
2461
2462	for (ds = 0; ds != 2; ds++) {
2463
2464	for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2465
2466	td->sitd_portaddr = sitd_portaddr;
2467
2468	/*
2469	* TODO: make some kind of automatic
2470	* SMASK/CMASK selection based on micro-frame
2471	* usage
2472	*
2473	* micro-frame usage (8 microframes per 1ms)
2474	*/
2475	td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE);
2476
2477	usb_pc_cpu_flush(td->page_cache);
2478	}
2479	}
2480	}
2481
2482	static void
2483	ehci_device_isoc_fs_close(struct usb_xfer *xfer)
2484	{
2485	ehci_device_done(xfer, USB_ERR_CANCELLED);
2486	}
2487
2488	static void
2489	ehci_device_isoc_fs_enter(struct usb_xfer *xfer)
2490	{
2491	struct usb_page_search buf_res;
2492	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2493	ehci_sitd_t *td;
2494	ehci_sitd_t *td_last = NULL;
2495	ehci_sitd_t **pp_last;
2496	uint32_t *plen;
2497	uint32_t buf_offset;
2498	uint32_t nframes;
2499	uint32_t temp;
2500	uint32_t sitd_mask;
2501	uint16_t tlen;
2502	uint8_t sa;
2503	uint8_t sb;
2504
2505	#ifdef USB_DEBUG
2506	uint8_t once = 1;
2507
2508	#endif
2509
2510	DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2511	xfer, xfer->endpoint->isoc_next, xfer->nframes);
2512
2513	/* get the current frame index */
2514
2515	nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2516
2517	/*
2518	* check if the frame index is within the window where the frames
2519	* will be inserted
2520	*/
2521	buf_offset = (nframes - xfer->endpoint->isoc_next) &
2522	(EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2523
2524	if ((xfer->endpoint->is_synced == 0) \|\|
2525	(buf_offset < xfer->nframes)) {
2526	/*
2527	* If there is data underflow or the pipe queue is empty we
2528	* schedule the transfer a few frames ahead of the current
2529	* frame position. Else two isochronous transfers might
2530	* overlap.
2531	*/
2532	xfer->endpoint->isoc_next = (nframes + 3) &
2533	(EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2534	xfer->endpoint->is_synced = 1;
2535	DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2536	}
2537	/*
2538	* compute how many milliseconds the insertion is ahead of the
2539	* current frame position:
2540	*/
2541	buf_offset = (xfer->endpoint->isoc_next - nframes) &
2542	(EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2543
2544	/*
2545	* pre-compute when the isochronous transfer will be finished:
2546	*/
2547	xfer->isoc_time_complete =
2548	usb_isoc_time_expand(&sc->sc_bus, nframes) +
2549	buf_offset + xfer->nframes;
2550
2551	/* get the real number of frames */
2552
2553	nframes = xfer->nframes;
2554
2555	buf_offset = 0;
2556
2557	plen = xfer->frlengths;
2558
2559	/* toggle the DMA set we are using */
2560	xfer->flags_int.curr_dma_set ^= 1;
2561
2562	/* get next DMA set */
2563	td = xfer->td_start[xfer->flags_int.curr_dma_set];
2564	xfer->td_transfer_first = td;
2565
2566	pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next];
2567
2568	/* store starting position */
2569
2570	xfer->qh_pos = xfer->endpoint->isoc_next;
2571
2572	while (nframes--) {
2573	if (td == NULL) {
2574	panic("%s:%d: out of TD's\n",
2575	__FUNCTION__, __LINE__);
2576	}
2577	if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT])
2578	pp_last = &sc->sc_isoc_fs_p_last[0];
2579
2580	/* reuse sitd_portaddr and sitd_back from last transfer */
2581
2582	if (*plen > xfer->max_frame_size) {
2583	#ifdef USB_DEBUG
2584	if (once) {
2585	once = 0;
2586	printf("%s: frame length(%d) exceeds %d "
2587	"bytes (frame truncated)\n",
2588	__FUNCTION__, *plen,
2589	xfer->max_frame_size);
2590	}
2591	#endif
2592	*plen = xfer->max_frame_size;
2593	}
2594
2595	/* allocate a slot */
2596
2597	sa = usbd_fs_isoc_schedule_alloc_slot(xfer,
2598	xfer->isoc_time_complete - nframes - 1);
2599
2600	if (sa == 255) {
2601	/*
2602	* Schedule is FULL, set length to zero:
2603	*/
2604
2605	*plen = 0;
2606	sa = USB_FS_ISOC_UFRAME_MAX - 1;
2607	}
2608	if (*plen) {
2609	/*
2610	* only call "usbd_get_page()" when we have a
2611	* non-zero length
2612	*/
2613	usbd_get_page(xfer->frbuffers, buf_offset, &buf_res);
2614	td->sitd_bp[0] = htohc32(sc, buf_res.physaddr);
2615	buf_offset += *plen;
2616	/*
2617	* NOTE: We need to subtract one from the offset so
2618	* that we are on a valid page!
2619	*/
2620	usbd_get_page(xfer->frbuffers, buf_offset - 1,
2621	&buf_res);
2622	temp = buf_res.physaddr & ~0xFFF;
2623	} else {
2624	td->sitd_bp[0] = 0;
2625	temp = 0;
2626	}
2627
2628	if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) {
2629	tlen = *plen;
2630	if (tlen <= 188) {
2631	temp \|= 1; /* T-count = 1, TP = ALL */
2632	tlen = 1;
2633	} else {
2634	tlen += 187;
2635	tlen /= 188;
2636	temp \|= tlen; /* T-count = [1..6] */
2637	temp \|= 8; /* TP = Begin */
2638	}
2639
2640	tlen += sa;
2641
2642	if (tlen >= 8) {
2643	sb = 0;
2644	} else {
2645	sb = (1 << tlen);
2646	}
2647
2648	sa = (1 << sa);
2649	sa = (sb - sa) & 0x3F;
2650	sb = 0;
2651	} else {
2652	sb = (-(4 << sa)) & 0xFE;
2653	sa = (1 << sa) & 0x3F;
2654	}
2655
2656	sitd_mask = (EHCI_SITD_SET_SMASK(sa) \|
2657	EHCI_SITD_SET_CMASK(sb));
2658
2659	td->sitd_bp[1] = htohc32(sc, temp);
2660
2661	td->sitd_mask = htohc32(sc, sitd_mask);
2662
2663	if (nframes == 0) {
2664	td->sitd_status = htohc32(sc,
2665	EHCI_SITD_IOC \|
2666	EHCI_SITD_ACTIVE \|
2667	EHCI_SITD_SET_LEN(*plen));
2668	} else {
2669	td->sitd_status = htohc32(sc,
2670	EHCI_SITD_ACTIVE \|
2671	EHCI_SITD_SET_LEN(*plen));
2672	}
2673	usb_pc_cpu_flush(td->page_cache);
2674
2675	#ifdef USB_DEBUG
2676	if (ehcidebug > 15) {
2677	DPRINTF("FS-TD %d\n", nframes);
2678	ehci_dump_sitd(sc, td);
2679	}
2680	#endif
2681	/* insert TD into schedule */
2682	EHCI_APPEND_FS_TD(td, *pp_last);
2683	pp_last++;
2684
2685	plen++;
2686	td_last = td;
2687	td = td->obj_next;
2688	}
2689
2690	xfer->td_transfer_last = td_last;
2691
2692	/* update isoc_next */
2693	xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) &
2694	(EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2695
2696	/*
2697	* We don't allow cancelling of the SPLIT transaction USB FULL
2698	* speed transfer, because it disturbs the bandwidth
2699	* computation algorithm.
2700	*/
2701	xfer->flags_int.can_cancel_immed = 0;
2702	}
2703
2704	static void
2705	ehci_device_isoc_fs_start(struct usb_xfer *xfer)
2706	{
2707	/*
2708	* We don't allow cancelling of the SPLIT transaction USB FULL
2709	* speed transfer, because it disturbs the bandwidth
2710	* computation algorithm.
2711	*/
2712	xfer->flags_int.can_cancel_immed = 0;
2713
2714	/* set a default timeout */
2715	if (xfer->timeout == 0)
2716	xfer->timeout = 500; /* ms */
2717
2718	/* put transfer on interrupt queue */
2719	ehci_transfer_intr_enqueue(xfer);
2720	}
2721
2722	struct usb_pipe_methods ehci_device_isoc_fs_methods =
2723	{
2724	.open = ehci_device_isoc_fs_open,
2725	.close = ehci_device_isoc_fs_close,
2726	.enter = ehci_device_isoc_fs_enter,
2727	.start = ehci_device_isoc_fs_start,
2728	};
2729
2730	/------------------------------------------------------------------------
2731	* ehci high speed isochronous support
2732	------------------------------------------------------------------------/
2733	static void
2734	ehci_device_isoc_hs_open(struct usb_xfer *xfer)
2735	{
2736	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2737	ehci_itd_t *td;
2738	uint32_t temp;
2739	uint8_t ds;
2740
2741	usb_hs_bandwidth_alloc(xfer);
2742
2743	/* initialize all TD's */
2744
2745	for (ds = 0; ds != 2; ds++) {
2746
2747	for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2748
2749	/* set TD inactive */
2750	td->itd_status[0] = 0;
2751	td->itd_status[1] = 0;
2752	td->itd_status[2] = 0;
2753	td->itd_status[3] = 0;
2754	td->itd_status[4] = 0;
2755	td->itd_status[5] = 0;
2756	td->itd_status[6] = 0;
2757	td->itd_status[7] = 0;
2758
2759	/* set endpoint and address */
2760	td->itd_bp[0] = htohc32(sc,
2761	EHCI_ITD_SET_ADDR(xfer->address) \|
2762	EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)));
2763
2764	temp =
2765	EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF);
2766
2767	/* set direction */
2768	if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2769	temp \|= EHCI_ITD_SET_DIR_IN;
2770	}
2771	/* set maximum packet size */
2772	td->itd_bp[1] = htohc32(sc, temp);
2773
2774	/* set transfer multiplier */
2775	td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3);
2776
2777	usb_pc_cpu_flush(td->page_cache);
2778	}
2779	}
2780	}
2781
2782	static void
2783	ehci_device_isoc_hs_close(struct usb_xfer *xfer)
2784	{
2785	ehci_device_done(xfer, USB_ERR_CANCELLED);
2786
2787	/* bandwidth must be freed after device done */
2788	usb_hs_bandwidth_free(xfer);
2789	}
2790
2791	static void
2792	ehci_device_isoc_hs_enter(struct usb_xfer *xfer)
2793	{
2794	struct usb_page_search buf_res;
2795	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2796	ehci_itd_t *td;
2797	ehci_itd_t *td_last = NULL;
2798	ehci_itd_t **pp_last;
2799	bus_size_t page_addr;
2800	uint32_t *plen;
2801	uint32_t status;
2802	uint32_t buf_offset;
2803	uint32_t nframes;
2804	uint32_t itd_offset[8 + 1];
2805	uint8_t x;
2806	uint8_t td_no;
2807	uint8_t page_no;
2808	uint8_t shift = usbd_xfer_get_fps_shift(xfer);
2809
2810	#ifdef USB_DEBUG
2811	uint8_t once = 1;
2812
2813	#endif
2814
2815	DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n",
2816	xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift);
2817
2818	/* get the current frame index */
2819
2820	nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2821
2822	/*
2823	* check if the frame index is within the window where the frames
2824	* will be inserted
2825	*/
2826	buf_offset = (nframes - xfer->endpoint->isoc_next) &
2827	(EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2828
2829	if ((xfer->endpoint->is_synced == 0) \|\|
2830	(buf_offset < (((xfer->nframes << shift) + 7) / 8))) {
2831	/*
2832	* If there is data underflow or the pipe queue is empty we
2833	* schedule the transfer a few frames ahead of the current
2834	* frame position. Else two isochronous transfers might
2835	* overlap.
2836	*/
2837	xfer->endpoint->isoc_next = (nframes + 3) &
2838	(EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2839	xfer->endpoint->is_synced = 1;
2840	DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2841	}
2842	/*
2843	* compute how many milliseconds the insertion is ahead of the
2844	* current frame position:
2845	*/
2846	buf_offset = (xfer->endpoint->isoc_next - nframes) &
2847	(EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2848
2849	/*
2850	* pre-compute when the isochronous transfer will be finished:
2851	*/
2852	xfer->isoc_time_complete =
2853	usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
2854	(((xfer->nframes << shift) + 7) / 8);
2855
2856	/* get the real number of frames */
2857
2858	nframes = xfer->nframes;
2859
2860	buf_offset = 0;
2861	td_no = 0;
2862
2863	plen = xfer->frlengths;
2864
2865	/* toggle the DMA set we are using */
2866	xfer->flags_int.curr_dma_set ^= 1;
2867
2868	/* get next DMA set */
2869	td = xfer->td_start[xfer->flags_int.curr_dma_set];
2870	xfer->td_transfer_first = td;
2871
2872	pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next];
2873
2874	/* store starting position */
2875
2876	xfer->qh_pos = xfer->endpoint->isoc_next;
2877
2878	while (nframes) {
2879	if (td == NULL) {
2880	panic("%s:%d: out of TD's\n",
2881	__FUNCTION__, __LINE__);
2882	}
2883	if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2884	pp_last = &sc->sc_isoc_hs_p_last[0];
2885	}
2886	/* range check */
2887	if (*plen > xfer->max_frame_size) {
2888	#ifdef USB_DEBUG
2889	if (once) {
2890	once = 0;
2891	printf("%s: frame length(%d) exceeds %d bytes "
2892	"(frame truncated)\n",
2893	__FUNCTION__, *plen, xfer->max_frame_size);
2894	}
2895	#endif
2896	*plen = xfer->max_frame_size;
2897	}
2898
2899	if (xfer->endpoint->usb_smask & (1 << td_no)) {
2900	status = (EHCI_ITD_SET_LEN(*plen) \|
2901	EHCI_ITD_ACTIVE \|
2902	EHCI_ITD_SET_PG(0));
2903	td->itd_status[td_no] = htohc32(sc, status);
2904	itd_offset[td_no] = buf_offset;
2905	buf_offset += *plen;
2906	plen++;
2907	nframes --;
2908	} else {
2909	td->itd_status[td_no] = 0; /* not active */
2910	itd_offset[td_no] = buf_offset;
2911	}
2912
2913	td_no++;
2914
2915	if ((td_no == 8) \|\| (nframes == 0)) {
2916
2917	/* the rest of the transfers are not active, if any */
2918	for (x = td_no; x != 8; x++) {
2919	td->itd_status[x] = 0; /* not active */
2920	}
2921
2922	/* check if there is any data to be transferred */
2923	if (itd_offset[0] != buf_offset) {
2924	page_no = 0;
2925	itd_offset[td_no] = buf_offset;
2926
2927	/* get first page offset */
2928	usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res);
2929	/* get page address */
2930	page_addr = buf_res.physaddr & ~0xFFF;
2931	/* update page address */
2932	td->itd_bp[0] &= htohc32(sc, 0xFFF);
2933	td->itd_bp[0] \|= htohc32(sc, page_addr);
2934
2935	for (x = 0; x != td_no; x++) {
2936	/* set page number and page offset */
2937	status = (EHCI_ITD_SET_PG(page_no) \|
2938	(buf_res.physaddr & 0xFFF));
2939	td->itd_status[x] \|= htohc32(sc, status);
2940
2941	/* get next page offset */
2942	if (itd_offset[x + 1] == buf_offset) {
2943	/*
2944	* We subtract one so that
2945	* we don't go off the last
2946	* page!
2947	*/
2948	usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
2949	} else {
2950	usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res);
2951	}
2952
2953	/* check if we need a new page */
2954	if ((buf_res.physaddr ^ page_addr) & ~0xFFF) {
2955	/* new page needed */
2956	page_addr = buf_res.physaddr & ~0xFFF;
2957	if (page_no == 6) {
2958	panic("%s: too many pages\n", __FUNCTION__);
2959	}
2960	page_no++;
2961	/* update page address */
2962	td->itd_bp[page_no] &= htohc32(sc, 0xFFF);
2963	td->itd_bp[page_no] \|= htohc32(sc, page_addr);
2964	}
2965	}
2966	}
2967	/* set IOC bit if we are complete */
2968	if (nframes == 0) {
2969	td->itd_status[td_no - 1] \|= htohc32(sc, EHCI_ITD_IOC);
2970	}
2971	usb_pc_cpu_flush(td->page_cache);
2972	#ifdef USB_DEBUG
2973	if (ehcidebug > 15) {
2974	DPRINTF("HS-TD %d\n", nframes);
2975	ehci_dump_itd(sc, td);
2976	}
2977	#endif
2978	/* insert TD into schedule */
2979	EHCI_APPEND_HS_TD(td, *pp_last);
2980	pp_last++;
2981
2982	td_no = 0;
2983	td_last = td;
2984	td = td->obj_next;
2985	}
2986	}
2987
2988	xfer->td_transfer_last = td_last;
2989
2990	/* update isoc_next */
2991	xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) &
2992	(EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2993	}
2994
2995	static void
2996	ehci_device_isoc_hs_start(struct usb_xfer *xfer)
2997	{
2998	/* put transfer on interrupt queue */
2999	ehci_transfer_intr_enqueue(xfer);
3000	}
3001
3002	struct usb_pipe_methods ehci_device_isoc_hs_methods =
3003	{
3004	.open = ehci_device_isoc_hs_open,
3005	.close = ehci_device_isoc_hs_close,
3006	.enter = ehci_device_isoc_hs_enter,
3007	.start = ehci_device_isoc_hs_start,
3008	};
3009
3010	/------------------------------------------------------------------------
3011	* ehci root control support
3012	------------------------------------------------------------------------
3013	* Simulate a hardware hub by handling all the necessary requests.
3014	------------------------------------------------------------------------/
3015
3016	static const
3017	struct usb_device_descriptor ehci_devd =
3018	{
3019	sizeof(struct usb_device_descriptor),
3020	UDESC_DEVICE, /* type */
3021	{0x00, 0x02}, /* USB version */
3022	UDCLASS_HUB, /* class */
3023	UDSUBCLASS_HUB, /* subclass */
3024	UDPROTO_HSHUBSTT, /* protocol */
3025	64, /* max packet */
3026	{0}, {0}, {0x00, 0x01}, /* device id */
3027	1, 2, 0, /* string indicies */
3028	1 /* # of configurations */
3029	};
3030
3031	static const
3032	struct usb_device_qualifier ehci_odevd =
3033	{
3034	sizeof(struct usb_device_qualifier),
3035	UDESC_DEVICE_QUALIFIER, /* type */
3036	{0x00, 0x02}, /* USB version */
3037	UDCLASS_HUB, /* class */
3038	UDSUBCLASS_HUB, /* subclass */
3039	UDPROTO_FSHUB, /* protocol */
3040	0, /* max packet */
3041	0, /* # of configurations */
3042	0
3043	};
3044
3045	static const struct ehci_config_desc ehci_confd = {
3046	.confd = {
3047	.bLength = sizeof(struct usb_config_descriptor),
3048	.bDescriptorType = UDESC_CONFIG,
3049	.wTotalLength[0] = sizeof(ehci_confd),
3050	.bNumInterface = 1,
3051	.bConfigurationValue = 1,
3052	.iConfiguration = 0,
3053	.bmAttributes = UC_SELF_POWERED,
3054	.bMaxPower = 0 /* max power */
3055	},
3056	.ifcd = {
3057	.bLength = sizeof(struct usb_interface_descriptor),
3058	.bDescriptorType = UDESC_INTERFACE,
3059	.bNumEndpoints = 1,
3060	.bInterfaceClass = UICLASS_HUB,
3061	.bInterfaceSubClass = UISUBCLASS_HUB,
3062	.bInterfaceProtocol = 0,
3063	},
3064	.endpd = {
3065	.bLength = sizeof(struct usb_endpoint_descriptor),
3066	.bDescriptorType = UDESC_ENDPOINT,
3067	.bEndpointAddress = UE_DIR_IN \| EHCI_INTR_ENDPT,
3068	.bmAttributes = UE_INTERRUPT,
3069	.wMaxPacketSize[0] = 8, /* max packet (63 ports) */
3070	.bInterval = 255,
3071	},
3072	};
3073
3074	static const
3075	struct usb_hub_descriptor ehci_hubd =
3076	{
3077	.bDescLength = 0, /* dynamic length */
3078	.bDescriptorType = UDESC_HUB,
3079	};
3080
3081	static void
3082	ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed)
3083	{
3084	uint32_t port;
3085	uint32_t v;
3086
3087	DPRINTF("index=%d lowspeed=%d\n", index, lowspeed);
3088
3089	port = EHCI_PORTSC(index);
3090	v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3091	EOWRITE4(sc, port, v \| EHCI_PS_PO);
3092	}
3093
3094	static usb_error_t
3095	ehci_roothub_exec(struct usb_device *udev,
3096	struct usb_device_request req, const void pptr, uint16_t plength)
3097	{
3098	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3099	const char *str_ptr;
3100	const void *ptr;
3101	uint32_t port;
3102	uint32_t v;
3103	uint16_t len;
3104	uint16_t i;
3105	uint16_t value;
3106	uint16_t index;
3107	usb_error_t err;
3108
3109	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3110
3111	/* buffer reset */
3112	ptr = (const void *)&sc->sc_hub_desc;
3113	len = 0;
3114	err = 0;
3115
3116	value = UGETW(req->wValue);
3117	index = UGETW(req->wIndex);
3118
3119	DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3120	"wValue=0x%04x wIndex=0x%04x\n",
3121	req->bmRequestType, req->bRequest,
3122	UGETW(req->wLength), value, index);
3123
3124	#define C(x,y) ((x) \| ((y) << 8))
3125	switch (C(req->bRequest, req->bmRequestType)) {
3126	case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3127	case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3128	case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3129	/*
3130	* DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3131	* for the integrated root hub.
3132	*/
3133	break;
3134	case C(UR_GET_CONFIG, UT_READ_DEVICE):
3135	len = 1;
3136	sc->sc_hub_desc.temp[0] = sc->sc_conf;
3137	break;
3138	case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3139	switch (value >> 8) {
3140	case UDESC_DEVICE:
3141	if ((value & 0xff) != 0) {
3142	err = USB_ERR_IOERROR;
3143	goto done;
3144	}
3145	len = sizeof(ehci_devd);
3146	ptr = (const void *)&ehci_devd;
3147	break;
3148	/*
3149	* We can't really operate at another speed,
3150	* but the specification says we need this
3151	* descriptor:
3152	*/
3153	case UDESC_DEVICE_QUALIFIER:
3154	if ((value & 0xff) != 0) {
3155	err = USB_ERR_IOERROR;
3156	goto done;
3157	}
3158	len = sizeof(ehci_odevd);
3159	ptr = (const void *)&ehci_odevd;
3160	break;
3161
3162	case UDESC_CONFIG:
3163	if ((value & 0xff) != 0) {
3164	err = USB_ERR_IOERROR;
3165	goto done;
3166	}
3167	len = sizeof(ehci_confd);
3168	ptr = (const void *)&ehci_confd;
3169	break;
3170
3171	case UDESC_STRING:
3172	switch (value & 0xff) {
3173	case 0: /* Language table */
3174	str_ptr = "\001";
3175	break;
3176
3177	case 1: /* Vendor */
3178	str_ptr = sc->sc_vendor;
3179	break;
3180
3181	case 2: /* Product */
3182	str_ptr = "EHCI root HUB";
3183	break;
3184
3185	default:
3186	str_ptr = "";
3187	break;
3188	}
3189
3190	len = usb_make_str_desc(
3191	sc->sc_hub_desc.temp,
3192	sizeof(sc->sc_hub_desc.temp),
3193	str_ptr);
3194	break;
3195	default:
3196	err = USB_ERR_IOERROR;
3197	goto done;
3198	}
3199	break;
3200	case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3201	len = 1;
3202	sc->sc_hub_desc.temp[0] = 0;
3203	break;
3204	case C(UR_GET_STATUS, UT_READ_DEVICE):
3205	len = 2;
3206	USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3207	break;
3208	case C(UR_GET_STATUS, UT_READ_INTERFACE):
3209	case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3210	len = 2;
3211	USETW(sc->sc_hub_desc.stat.wStatus, 0);
3212	break;
3213	case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3214	if (value >= EHCI_MAX_DEVICES) {
3215	err = USB_ERR_IOERROR;
3216	goto done;
3217	}
3218	sc->sc_addr = value;
3219	break;
3220	case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3221	if ((value != 0) && (value != 1)) {
3222	err = USB_ERR_IOERROR;
3223	goto done;
3224	}
3225	sc->sc_conf = value;
3226	break;
3227	case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3228	break;
3229	case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3230	case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3231	case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3232	err = USB_ERR_IOERROR;
3233	goto done;
3234	case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3235	break;
3236	case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3237	break;
3238	/* Hub requests */
3239	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3240	break;
3241	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3242	DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3243
3244	if ((index < 1) \|\|
3245	(index > sc->sc_noport)) {
3246	err = USB_ERR_IOERROR;
3247	goto done;
3248	}
3249	port = EHCI_PORTSC(index);
3250	v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3251	switch (value) {
3252	case UHF_PORT_ENABLE:
3253	EOWRITE4(sc, port, v & ~EHCI_PS_PE);
3254	break;
3255	case UHF_PORT_SUSPEND:
3256	if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) {
3257
3258	/*
3259	* waking up a High Speed device is rather
3260	* complicated if
3261	*/
3262	EOWRITE4(sc, port, v \| EHCI_PS_FPR);
3263	}
3264	/* wait 20ms for resume sequence to complete */
3265	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3266
3267	EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP \|
3268	EHCI_PS_FPR \| (3 << 10) /* High Speed */ ));
3269
3270	/* 4ms settle time */
3271	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3272	break;
3273	case UHF_PORT_POWER:
3274	EOWRITE4(sc, port, v & ~EHCI_PS_PP);
3275	break;
3276	case UHF_PORT_TEST:
3277	DPRINTFN(3, "clear port test "
3278	"%d\n", index);
3279	break;
3280	case UHF_PORT_INDICATOR:
3281	DPRINTFN(3, "clear port ind "
3282	"%d\n", index);
3283	EOWRITE4(sc, port, v & ~EHCI_PS_PIC);
3284	break;
3285	case UHF_C_PORT_CONNECTION:
3286	EOWRITE4(sc, port, v \| EHCI_PS_CSC);
3287	break;
3288	case UHF_C_PORT_ENABLE:
3289	EOWRITE4(sc, port, v \| EHCI_PS_PEC);
3290	break;
3291	case UHF_C_PORT_SUSPEND:
3292	EOWRITE4(sc, port, v \| EHCI_PS_SUSP);
3293	break;
3294	case UHF_C_PORT_OVER_CURRENT:
3295	EOWRITE4(sc, port, v \| EHCI_PS_OCC);
3296	break;
3297	case UHF_C_PORT_RESET:
3298	sc->sc_isreset = 0;
3299	break;
3300	default:
3301	err = USB_ERR_IOERROR;
3302	goto done;
3303	}
3304	break;
3305	case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3306	if ((value & 0xff) != 0) {
3307	err = USB_ERR_IOERROR;
3308	goto done;
3309	}
3310	v = EREAD4(sc, EHCI_HCSPARAMS);
3311
3312	sc->sc_hub_desc.hubd = ehci_hubd;
3313	sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3314
3315	if (EHCI_HCS_PPC(v))
3316	i = UHD_PWR_INDIVIDUAL;
3317	else
3318	i = UHD_PWR_NO_SWITCH;
3319
3320	if (EHCI_HCS_P_INDICATOR(v))
3321	i \|= UHD_PORT_IND;
3322
3323	USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3324	/* XXX can't find out? */
3325	sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200;
3326	/* XXX don't know if ports are removable or not */
3327	sc->sc_hub_desc.hubd.bDescLength =
3328	8 + ((sc->sc_noport + 7) / 8);
3329	len = sc->sc_hub_desc.hubd.bDescLength;
3330	break;
3331	case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3332	len = 16;
3333	memset(sc->sc_hub_desc.temp, 0, 16);
3334	break;
3335	case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3336	DPRINTFN(9, "get port status i=%d\n",
3337	index);
3338	if ((index < 1) \|\|
3339	(index > sc->sc_noport)) {
3340	err = USB_ERR_IOERROR;
3341	goto done;
3342	}
3343	v = EOREAD4(sc, EHCI_PORTSC(index));
3344	DPRINTFN(9, "port status=0x%04x\n", v);
3345	if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED \| EHCI_SCFLG_TT)) {
3346	if ((v & 0xc000000) == 0x8000000)
3347	i = UPS_HIGH_SPEED;
3348	else if ((v & 0xc000000) == 0x4000000)
3349	i = UPS_LOW_SPEED;
3350	else
3351	i = 0;
3352	} else {
3353	i = UPS_HIGH_SPEED;
3354	}
3355	if (v & EHCI_PS_CS)
3356	i \|= UPS_CURRENT_CONNECT_STATUS;
3357	if (v & EHCI_PS_PE)
3358	i \|= UPS_PORT_ENABLED;
3359	if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR))
3360	i \|= UPS_SUSPEND;
3361	if (v & EHCI_PS_OCA)
3362	i \|= UPS_OVERCURRENT_INDICATOR;
3363	if (v & EHCI_PS_PR)
3364	i \|= UPS_RESET;
3365	if (v & EHCI_PS_PP)
3366	i \|= UPS_PORT_POWER;
3367	USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3368	i = 0;
3369	if (v & EHCI_PS_CSC)
3370	i \|= UPS_C_CONNECT_STATUS;
3371	if (v & EHCI_PS_PEC)
3372	i \|= UPS_C_PORT_ENABLED;
3373	if (v & EHCI_PS_OCC)
3374	i \|= UPS_C_OVERCURRENT_INDICATOR;
3375	if (v & EHCI_PS_FPR)
3376	i \|= UPS_C_SUSPEND;
3377	if (sc->sc_isreset)
3378	i \|= UPS_C_PORT_RESET;
3379	USETW(sc->sc_hub_desc.ps.wPortChange, i);
3380	len = sizeof(sc->sc_hub_desc.ps);
3381	break;
3382	case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3383	err = USB_ERR_IOERROR;
3384	goto done;
3385	case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3386	break;
3387	case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3388	if ((index < 1) \|\|
3389	(index > sc->sc_noport)) {
3390	err = USB_ERR_IOERROR;
3391	goto done;
3392	}
3393	port = EHCI_PORTSC(index);
3394	v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3395	switch (value) {
3396	case UHF_PORT_ENABLE:
3397	EOWRITE4(sc, port, v \| EHCI_PS_PE);
3398	break;
3399	case UHF_PORT_SUSPEND:
3400	EOWRITE4(sc, port, v \| EHCI_PS_SUSP);
3401	break;
3402	case UHF_PORT_RESET:
3403	DPRINTFN(6, "reset port %d\n", index);
3404	#ifdef USB_DEBUG
3405	if (ehcinohighspeed) {
3406	/*
3407	* Connect USB device to companion
3408	* controller.
3409	*/
3410	ehci_disown(sc, index, 1);
3411	break;
3412	}
3413	#endif
3414	if (EHCI_PS_IS_LOWSPEED(v) &&
3415	(sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3416	/* Low speed device, give up ownership. */
3417	ehci_disown(sc, index, 1);
3418	break;
3419	}
3420	/* Start reset sequence. */
3421	v &= ~(EHCI_PS_PE \| EHCI_PS_PR);
3422	EOWRITE4(sc, port, v \| EHCI_PS_PR);
3423
3424	/* Wait for reset to complete. */
3425	usb_pause_mtx(&sc->sc_bus.bus_mtx,
3426	USB_MS_TO_TICKS(usb_port_root_reset_delay));
3427
3428	/* Terminate reset sequence. */
3429	if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
3430	EOWRITE4(sc, port, v);
3431
3432	/* Wait for HC to complete reset. */
3433	usb_pause_mtx(&sc->sc_bus.bus_mtx,
3434	USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
3435
3436	v = EOREAD4(sc, port);
3437	DPRINTF("ehci after reset, status=0x%08x\n", v);
3438	if (v & EHCI_PS_PR) {
3439	device_printf(sc->sc_bus.bdev,
3440	"port reset timeout\n");
3441	err = USB_ERR_TIMEOUT;
3442	goto done;
3443	}
3444	if (!(v & EHCI_PS_PE) &&
3445	(sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3446	/* Not a high speed device, give up ownership.*/
3447	ehci_disown(sc, index, 0);
3448	break;
3449	}
3450	sc->sc_isreset = 1;
3451	DPRINTF("ehci port %d reset, status = 0x%08x\n",
3452	index, v);
3453	break;
3454
3455	case UHF_PORT_POWER:
3456	DPRINTFN(3, "set port power %d\n", index);
3457	EOWRITE4(sc, port, v \| EHCI_PS_PP);
3458	break;
3459
3460	case UHF_PORT_TEST:
3461	DPRINTFN(3, "set port test %d\n", index);
3462	break;
3463
3464	case UHF_PORT_INDICATOR:
3465	DPRINTFN(3, "set port ind %d\n", index);
3466	EOWRITE4(sc, port, v \| EHCI_PS_PIC);
3467	break;
3468
3469	default:
3470	err = USB_ERR_IOERROR;
3471	goto done;
3472	}
3473	break;
3474	case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3475	case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3476	case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3477	case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3478	break;
3479	default:
3480	err = USB_ERR_IOERROR;
3481	goto done;
3482	}
3483	done:
3484	*plength = len;
3485	*pptr = ptr;
3486	return (err);
3487	}
3488
3489	static void
3490	ehci_xfer_setup(struct usb_setup_params *parm)
3491	{
3492	struct usb_page_search page_info;
3493	struct usb_page_cache *pc;
3494	ehci_softc_t *sc;
3495	struct usb_xfer *xfer;
3496	void *last_obj;
3497	uint32_t nqtd;
3498	uint32_t nqh;
3499	uint32_t nsitd;
3500	uint32_t nitd;
3501	uint32_t n;
3502
3503	sc = EHCI_BUS2SC(parm->udev->bus);
3504	xfer = parm->curr_xfer;
3505
3506	nqtd = 0;
3507	nqh = 0;
3508	nsitd = 0;
3509	nitd = 0;
3510
3511	/*
3512	* compute maximum number of some structures
3513	*/
3514	if (parm->methods == &ehci_device_ctrl_methods) {
3515
3516	/*
3517	* The proof for the "nqtd" formula is illustrated like
3518	* this:
3519	*
3520	* +------------------------------------+
3521	* \| \|
3522	* \| \|remainder -> \|
3523	* \| +-----+---+ \|
3524	* \| \| xxx \| x \| frm 0 \|
3525	* \| +-----+---++ \|
3526	* \| \| xxx \| xx \| frm 1 \|
3527	* \| +-----+----+ \|
3528	* \| ... \|
3529	* +------------------------------------+
3530	*
3531	* "xxx" means a completely full USB transfer descriptor
3532	*
3533	* "x" and "xx" means a short USB packet
3534	*
3535	* For the remainder of an USB transfer modulo
3536	* "max_data_length" we need two USB transfer descriptors.
3537	* One to transfer the remaining data and one to finalise
3538	* with a zero length packet in case the "force_short_xfer"
3539	* flag is set. We only need two USB transfer descriptors in
3540	* the case where the transfer length of the first one is a
3541	* factor of "max_frame_size". The rest of the needed USB
3542	* transfer descriptors is given by the buffer size divided
3543	* by the maximum data payload.
3544	*/
3545	parm->hc_max_packet_size = 0x400;
3546	parm->hc_max_packet_count = 1;
3547	parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3548	xfer->flags_int.bdma_enable = 1;
3549
3550	usbd_transfer_setup_sub(parm);
3551
3552	nqh = 1;
3553	nqtd = ((2 * xfer->nframes) + 1 /* STATUS */
3554	+ (xfer->max_data_length / xfer->max_hc_frame_size));
3555
3556	} else if (parm->methods == &ehci_device_bulk_methods) {
3557
3558	parm->hc_max_packet_size = 0x400;
3559	parm->hc_max_packet_count = 1;
3560	parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3561	xfer->flags_int.bdma_enable = 1;
3562
3563	usbd_transfer_setup_sub(parm);
3564
3565	nqh = 1;
3566	nqtd = ((2 * xfer->nframes)
3567	+ (xfer->max_data_length / xfer->max_hc_frame_size));
3568
3569	} else if (parm->methods == &ehci_device_intr_methods) {
3570
3571	if (parm->speed == USB_SPEED_HIGH) {
3572	parm->hc_max_packet_size = 0x400;
3573	parm->hc_max_packet_count = 3;
3574	} else if (parm->speed == USB_SPEED_FULL) {
3575	parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME;
3576	parm->hc_max_packet_count = 1;
3577	} else {
3578	parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8;
3579	parm->hc_max_packet_count = 1;
3580	}
3581
3582	parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3583	xfer->flags_int.bdma_enable = 1;
3584
3585	usbd_transfer_setup_sub(parm);
3586
3587	nqh = 1;
3588	nqtd = ((2 * xfer->nframes)
3589	+ (xfer->max_data_length / xfer->max_hc_frame_size));
3590
3591	} else if (parm->methods == &ehci_device_isoc_fs_methods) {
3592
3593	parm->hc_max_packet_size = 0x3FF;
3594	parm->hc_max_packet_count = 1;
3595	parm->hc_max_frame_size = 0x3FF;
3596	xfer->flags_int.bdma_enable = 1;
3597
3598	usbd_transfer_setup_sub(parm);
3599
3600	nsitd = xfer->nframes;
3601
3602	} else if (parm->methods == &ehci_device_isoc_hs_methods) {
3603
3604	parm->hc_max_packet_size = 0x400;
3605	parm->hc_max_packet_count = 3;
3606	parm->hc_max_frame_size = 0xC00;
3607	xfer->flags_int.bdma_enable = 1;
3608
3609	usbd_transfer_setup_sub(parm);
3610
3611	nitd = ((xfer->nframes + 7) / 8) <<
3612	usbd_xfer_get_fps_shift(xfer);
3613
3614	} else {
3615
3616	parm->hc_max_packet_size = 0x400;
3617	parm->hc_max_packet_count = 1;
3618	parm->hc_max_frame_size = 0x400;
3619
3620	usbd_transfer_setup_sub(parm);
3621	}
3622
3623	alloc_dma_set:
3624
3625	if (parm->err) {
3626	return;
3627	}
3628	/*
3629	* Allocate queue heads and transfer descriptors
3630	*/
3631	last_obj = NULL;
3632
3633	if (usbd_transfer_setup_sub_malloc(
3634	parm, &pc, sizeof(ehci_itd_t),
3635	EHCI_ITD_ALIGN, nitd)) {
3636	parm->err = USB_ERR_NOMEM;
3637	return;
3638	}
3639	if (parm->buf) {
3640	for (n = 0; n != nitd; n++) {
3641	ehci_itd_t *td;
3642
3643	usbd_get_page(pc + n, 0, &page_info);
3644
3645	td = page_info.buffer;
3646
3647	/* init TD */
3648	td->itd_self = htohc32(sc, page_info.physaddr \| EHCI_LINK_ITD);
3649	td->obj_next = last_obj;
3650	td->page_cache = pc + n;
3651
3652	last_obj = td;
3653
3654	usb_pc_cpu_flush(pc + n);
3655	}
3656	}
3657	if (usbd_transfer_setup_sub_malloc(
3658	parm, &pc, sizeof(ehci_sitd_t),
3659	EHCI_SITD_ALIGN, nsitd)) {
3660	parm->err = USB_ERR_NOMEM;
3661	return;
3662	}
3663	if (parm->buf) {
3664	for (n = 0; n != nsitd; n++) {
3665	ehci_sitd_t *td;
3666
3667	usbd_get_page(pc + n, 0, &page_info);
3668
3669	td = page_info.buffer;
3670
3671	/* init TD */
3672	td->sitd_self = htohc32(sc, page_info.physaddr \| EHCI_LINK_SITD);
3673	td->obj_next = last_obj;
3674	td->page_cache = pc + n;
3675
3676	last_obj = td;
3677
3678	usb_pc_cpu_flush(pc + n);
3679	}
3680	}
3681	if (usbd_transfer_setup_sub_malloc(
3682	parm, &pc, sizeof(ehci_qtd_t),
3683	EHCI_QTD_ALIGN, nqtd)) {
3684	parm->err = USB_ERR_NOMEM;
3685	return;
3686	}
3687	if (parm->buf) {
3688	for (n = 0; n != nqtd; n++) {
3689	ehci_qtd_t *qtd;
3690
3691	usbd_get_page(pc + n, 0, &page_info);
3692
3693	qtd = page_info.buffer;
3694
3695	/* init TD */
3696	qtd->qtd_self = htohc32(sc, page_info.physaddr);
3697	qtd->obj_next = last_obj;
3698	qtd->page_cache = pc + n;
3699
3700	last_obj = qtd;
3701
3702	usb_pc_cpu_flush(pc + n);
3703	}
3704	}
3705	xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3706
3707	last_obj = NULL;
3708
3709	if (usbd_transfer_setup_sub_malloc(
3710	parm, &pc, sizeof(ehci_qh_t),
3711	EHCI_QH_ALIGN, nqh)) {
3712	parm->err = USB_ERR_NOMEM;
3713	return;
3714	}
3715	if (parm->buf) {
3716	for (n = 0; n != nqh; n++) {
3717	ehci_qh_t *qh;
3718
3719	usbd_get_page(pc + n, 0, &page_info);
3720
3721	qh = page_info.buffer;
3722
3723	/* init QH */
3724	qh->qh_self = htohc32(sc, page_info.physaddr \| EHCI_LINK_QH);
3725	qh->obj_next = last_obj;
3726	qh->page_cache = pc + n;
3727
3728	last_obj = qh;
3729
3730	usb_pc_cpu_flush(pc + n);
3731	}
3732	}
3733	xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3734
3735	if (!xfer->flags_int.curr_dma_set) {
3736	xfer->flags_int.curr_dma_set = 1;
3737	goto alloc_dma_set;
3738	}
3739	}
3740
3741	static void
3742	ehci_xfer_unsetup(struct usb_xfer *xfer)
3743	{
3744	return;
3745	}
3746
3747	static void
3748	ehci_ep_init(struct usb_device udev, struct usb_endpoint_descriptor edesc,
3749	struct usb_endpoint *ep)
3750	{
3751	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3752
3753	DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3754	ep, udev->address,
3755	edesc->bEndpointAddress, udev->flags.usb_mode,
3756	sc->sc_addr);
3757
3758	if (udev->device_index != sc->sc_addr) {
3759
3760	if ((udev->speed != USB_SPEED_HIGH) &&
3761	((udev->hs_hub_addr == 0) \|\|
3762	(udev->hs_port_no == 0) \|\|
3763	(udev->parent_hs_hub == NULL) \|\|
3764	(udev->parent_hs_hub->hub == NULL))) {
3765	/* We need a transaction translator */
3766	goto done;
3767	}
3768	switch (edesc->bmAttributes & UE_XFERTYPE) {
3769	case UE_CONTROL:
3770	ep->methods = &ehci_device_ctrl_methods;
3771	break;
3772	case UE_INTERRUPT:
3773	ep->methods = &ehci_device_intr_methods;
3774	break;
3775	case UE_ISOCHRONOUS:
3776	if (udev->speed == USB_SPEED_HIGH) {
3777	ep->methods = &ehci_device_isoc_hs_methods;
3778	} else if (udev->speed == USB_SPEED_FULL) {
3779	ep->methods = &ehci_device_isoc_fs_methods;
3780	}
3781	break;
3782	case UE_BULK:
3783	ep->methods = &ehci_device_bulk_methods;
3784	break;
3785	default:
3786	/* do nothing */
3787	break;
3788	}
3789	}
3790	done:
3791	return;
3792	}
3793
3794	static void
3795	ehci_get_dma_delay(struct usb_device udev, uint32_t pus)
3796	{
3797	/*
3798	* Wait until the hardware has finished any possible use of
3799	* the transfer descriptor(s) and QH
3800	*/
3801	pus = (1125); / microseconds */
3802	}
3803
3804	static void
3805	ehci_device_resume(struct usb_device *udev)
3806	{
3807	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3808	struct usb_xfer *xfer;
3809	struct usb_pipe_methods *methods;
3810
3811	DPRINTF("\n");
3812
3813	USB_BUS_LOCK(udev->bus);
3814
3815	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3816
3817	if (xfer->xroot->udev == udev) {
3818
3819	methods = xfer->endpoint->methods;
3820
3821	if ((methods == &ehci_device_bulk_methods) \|\|
3822	(methods == &ehci_device_ctrl_methods)) {
3823	EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3824	sc->sc_async_p_last);
3825	}
3826	if (methods == &ehci_device_intr_methods) {
3827	EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3828	sc->sc_intr_p_last[xfer->qh_pos]);
3829	}
3830	}
3831	}
3832
3833	USB_BUS_UNLOCK(udev->bus);
3834
3835	return;
3836	}
3837
3838	static void
3839	ehci_device_suspend(struct usb_device *udev)
3840	{
3841	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3842	struct usb_xfer *xfer;
3843	struct usb_pipe_methods *methods;
3844
3845	DPRINTF("\n");
3846
3847	USB_BUS_LOCK(udev->bus);
3848
3849	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3850
3851	if (xfer->xroot->udev == udev) {
3852
3853	methods = xfer->endpoint->methods;
3854
3855	if ((methods == &ehci_device_bulk_methods) \|\|
3856	(methods == &ehci_device_ctrl_methods)) {
3857	EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3858	sc->sc_async_p_last);
3859	}
3860	if (methods == &ehci_device_intr_methods) {
3861	EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3862	sc->sc_intr_p_last[xfer->qh_pos]);
3863	}
3864	}
3865	}
3866
3867	USB_BUS_UNLOCK(udev->bus);
3868	}
3869
3870	static void
3871	ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3872	{
3873	struct ehci_softc *sc = EHCI_BUS2SC(bus);
3874
3875	switch (state) {
3876	case USB_HW_POWER_SUSPEND:
3877	case USB_HW_POWER_SHUTDOWN:
3878	ehci_suspend(sc);
3879	break;
3880	case USB_HW_POWER_RESUME:
3881	ehci_resume(sc);
3882	break;
3883	default:
3884	break;
3885	}
3886	}
3887
3888	static void
3889	ehci_set_hw_power(struct usb_bus *bus)
3890	{
3891	ehci_softc_t *sc = EHCI_BUS2SC(bus);
3892	uint32_t temp;
3893	uint32_t flags;
3894
3895	DPRINTF("\n");
3896
3897	USB_BUS_LOCK(bus);
3898
3899	flags = bus->hw_power_state;
3900
3901	temp = EOREAD4(sc, EHCI_USBCMD);
3902
3903	temp &= ~(EHCI_CMD_ASE \| EHCI_CMD_PSE);
3904
3905	if (flags & (USB_HW_POWER_CONTROL \|
3906	USB_HW_POWER_BULK)) {
3907	DPRINTF("Async is active\n");
3908	temp \|= EHCI_CMD_ASE;
3909	}
3910	if (flags & (USB_HW_POWER_INTERRUPT \|
3911	USB_HW_POWER_ISOC)) {
3912	DPRINTF("Periodic is active\n");
3913	temp \|= EHCI_CMD_PSE;
3914	}
3915	EOWRITE4(sc, EHCI_USBCMD, temp);
3916
3917	USB_BUS_UNLOCK(bus);
3918
3919	return;
3920	}
3921
3922	static void
3923	ehci_start_dma_delay_second(struct usb_xfer *xfer)
3924	{
3925	struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus);
3926
3927	DPRINTF("\n");
3928
3929	/* trigger doorbell */
3930	ehci_doorbell_async(sc);
3931
3932	/* give the doorbell 4ms */
3933	usbd_transfer_timeout_ms(xfer,
3934	(void ()(void ))&usb_dma_delay_done_cb, 4);
3935	}
3936
3937	/*
3938	* Ring the doorbell twice before freeing any DMA descriptors. Some host
3939	* controllers apparently cache the QH descriptors and need a message
3940	* that the cache needs to be discarded.
3941	*/
3942	static void
3943	ehci_start_dma_delay(struct usb_xfer *xfer)
3944	{
3945	struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus);
3946
3947	DPRINTF("\n");
3948
3949	/* trigger doorbell */
3950	ehci_doorbell_async(sc);
3951
3952	/* give the doorbell 4ms */
3953	usbd_transfer_timeout_ms(xfer,
3954	(void ()(void ))&ehci_start_dma_delay_second, 4);
3955	}
3956
3957	struct usb_bus_methods ehci_bus_methods =
3958	{
3959	.endpoint_init = ehci_ep_init,
3960	.xfer_setup = ehci_xfer_setup,
3961	.xfer_unsetup = ehci_xfer_unsetup,
3962	.get_dma_delay = ehci_get_dma_delay,
3963	.device_resume = ehci_device_resume,
3964	.device_suspend = ehci_device_suspend,
3965	.set_hw_power = ehci_set_hw_power,
3966	.set_hw_power_sleep = ehci_set_hw_power_sleep,
3967	.roothub_exec = ehci_roothub_exec,
3968	.xfer_poll = ehci_do_poll,
3969	.start_dma_delay = ehci_start_dma_delay,
3970	};

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