| 1 | /*- |
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| 2 | * Copyright (C) 2008-2009 Semihalf, Piotr Ziecik |
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| 3 | * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski |
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| 4 | * All rights reserved. |
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| 5 | * |
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| 6 | * Redistribution and use in source and binary forms, with or without |
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| 7 | * modification, are permitted provided that the following conditions |
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| 8 | * are met: |
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| 9 | * 1. Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * |
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| 15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
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| 18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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| 19 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED |
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| 20 | * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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| 21 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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| 22 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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| 23 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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| 24 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 25 | * |
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| 26 | * $FreeBSD$ |
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| 27 | */ |
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| 28 | |
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| 29 | #define TSEC_REG_ID 0x000 /* Controller ID register #1. */ |
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| 30 | #define TSEC_REG_ID2 0x004 /* Controller ID register #2. */ |
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| 31 | |
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| 32 | /* TSEC General Control and Status Registers */ |
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| 33 | #define TSEC_REG_IEVENT 0x010 /* Interrupt event register */ |
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| 34 | #define TSEC_REG_IMASK 0x014 /* Interrupt mask register */ |
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| 35 | #define TSEC_REG_EDIS 0x018 /* Error disabled register */ |
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| 36 | #define TSEC_REG_ECNTRL 0x020 /* Ethernet control register */ |
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| 37 | #define TSEC_REG_MINFLR 0x024 /* Minimum frame length register */ |
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| 38 | #define TSEC_REG_PTV 0x028 /* Pause time value register */ |
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| 39 | #define TSEC_REG_DMACTRL 0x02c /* DMA control register */ |
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| 40 | #define TSEC_REG_TBIPA 0x030 /* TBI PHY address register */ |
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| 41 | |
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| 42 | /* TSEC FIFO Control and Status Registers */ |
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| 43 | #define TSEC_REG_FIFO_PAUSE_CTRL 0x04c /* FIFO pause control register */ |
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| 44 | #define TSEC_REG_FIFO_TX_THR 0x08c /* FIFO transmit threshold register */ |
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| 45 | #define TSEC_REG_FIFO_TX_STARVE 0x098 /* FIFO transmit starve register */ |
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| 46 | #define TSEC_REG_FIFO_TX_STARVE_SHUTOFF 0x09c /* FIFO transmit starve shutoff |
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| 47 | * register */ |
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| 48 | |
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| 49 | /* TSEC Transmit Control and Status Registers */ |
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| 50 | #define TSEC_REG_TCTRL 0x100 /* Transmit control register */ |
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| 51 | #define TSEC_REG_TSTAT 0x104 /* Transmit Status Register */ |
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| 52 | #define TSEC_REG_TBDLEN 0x10c /* TxBD data length register */ |
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| 53 | #define TSEC_REG_TXIC 0x110 /* Transmit interrupt coalescing |
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| 54 | * configuration register */ |
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| 55 | #define TSEC_REG_CTBPTR 0x124 /* Current TxBD pointer register */ |
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| 56 | #define TSEC_REG_TBPTR 0x184 /* TxBD pointer register */ |
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| 57 | #define TSEC_REG_TBASE 0x204 /* TxBD base address register */ |
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| 58 | #define TSEC_REG_OSTBD 0x2b0 /* Out-of-sequence TxBD register */ |
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| 59 | #define TSEC_REG_OSTBDP 0x2b4 /* Out-of-sequence Tx data buffer pointer |
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| 60 | * register */ |
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| 61 | |
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| 62 | /* TSEC Receive Control and Status Registers */ |
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| 63 | #define TSEC_REG_RCTRL 0x300 /* Receive control register */ |
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| 64 | #define TSEC_REG_RSTAT 0x304 /* Receive status register */ |
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| 65 | #define TSEC_REG_RBDLEN 0x30c /* RxBD data length register */ |
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| 66 | #define TSEC_REG_RXIC 0x310 /* Receive interrupt coalescing |
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| 67 | * configuration register */ |
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| 68 | #define TSEC_REG_CRBPTR 0x324 /* Current RxBD pointer register */ |
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| 69 | #define TSEC_REG_MRBLR 0x340 /* Maximum receive buffer length register */ |
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| 70 | #define TSEC_REG_RBPTR 0x384 /* RxBD pointer register */ |
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| 71 | #define TSEC_REG_RBASE 0x404 /* RxBD base address register */ |
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| 72 | |
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| 73 | /* TSEC MAC Registers */ |
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| 74 | #define TSEC_REG_MACCFG1 0x500 /* MAC configuration 1 register */ |
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| 75 | #define TSEC_REG_MACCFG2 0x504 /* MAC configuration 2 register */ |
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| 76 | #define TSEC_REG_IPGIFG 0x508 /* Inter-packet gap/inter-frame gap |
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| 77 | * register */ |
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| 78 | #define TSEC_REG_HAFDUP 0x50c /* Half-duplex register */ |
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| 79 | #define TSEC_REG_MAXFRM 0x510 /* Maximum frame length register */ |
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| 80 | #define TSEC_REG_MIIMCFG 0x520 /* MII Management configuration register */ |
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| 81 | #define TSEC_REG_MIIMCOM 0x524 /* MII Management command register */ |
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| 82 | #define TSEC_REG_MIIMADD 0x528 /* MII Management address register */ |
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| 83 | #define TSEC_REG_MIIMCON 0x52c /* MII Management control register */ |
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| 84 | #define TSEC_REG_MIIMSTAT 0x530 /* MII Management status register */ |
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| 85 | #define TSEC_REG_MIIMIND 0x534 /* MII Management indicator register */ |
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| 86 | #define TSEC_REG_IFSTAT 0x53c /* Interface status register */ |
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| 87 | #define TSEC_REG_MACSTNADDR1 0x540 /* Station address register, part 1 */ |
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| 88 | #define TSEC_REG_MACSTNADDR2 0x544 /* Station address register, part 2 */ |
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| 89 | |
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| 90 | /* TSEC Transmit and Receive Counters */ |
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| 91 | #define TSEC_REG_MON_TR64 0x680 /* Transmit and receive 64-byte |
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| 92 | * frame counter register */ |
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| 93 | #define TSEC_REG_MON_TR127 0x684 /* Transmit and receive 65-127 byte |
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| 94 | * frame counter register */ |
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| 95 | #define TSEC_REG_MON_TR255 0x688 /* Transmit and receive 128-255 byte |
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| 96 | * frame counter register */ |
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| 97 | #define TSEC_REG_MON_TR511 0x68c /* Transmit and receive 256-511 byte |
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| 98 | * frame counter register */ |
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| 99 | #define TSEC_REG_MON_TR1K 0x690 /* Transmit and receive 512-1023 byte |
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| 100 | * frame counter register */ |
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| 101 | #define TSEC_REG_MON_TRMAX 0x694 /* Transmit and receive 1024-1518 byte |
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| 102 | * frame counter register */ |
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| 103 | #define TSEC_REG_MON_TRMGV 0x698 /* Transmit and receive 1519-1522 byte |
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| 104 | * good VLAN frame counter register */ |
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| 105 | |
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| 106 | /* TSEC Receive Counters */ |
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| 107 | #define TSEC_REG_MON_RBYT 0x69c /* Receive byte counter register */ |
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| 108 | #define TSEC_REG_MON_RPKT 0x6a0 /* Receive packet counter register */ |
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| 109 | #define TSEC_REG_MON_RFCS 0x6a4 /* Receive FCS error counter register */ |
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| 110 | #define TSEC_REG_MON_RMCA 0x6a8 /* Receive multicast packet counter |
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| 111 | * register */ |
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| 112 | #define TSEC_REG_MON_RBCA 0x6ac /* Receive broadcast packet counter |
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| 113 | * register */ |
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| 114 | #define TSEC_REG_MON_RXCF 0x6b0 /* Receive control frame packet counter |
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| 115 | * register */ |
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| 116 | #define TSEC_REG_MON_RXPF 0x6b4 /* Receive pause frame packet counter |
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| 117 | * register */ |
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| 118 | #define TSEC_REG_MON_RXUO 0x6b8 /* Receive unknown OP code counter |
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| 119 | * register */ |
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| 120 | #define TSEC_REG_MON_RALN 0x6bc /* Receive alignment error counter |
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| 121 | * register */ |
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| 122 | #define TSEC_REG_MON_RFLR 0x6c0 /* Receive frame length error counter |
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| 123 | * register */ |
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| 124 | #define TSEC_REG_MON_RCDE 0x6c4 /* Receive code error counter register */ |
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| 125 | #define TSEC_REG_MON_RCSE 0x6c8 /* Receive carrier sense error counter |
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| 126 | * register */ |
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| 127 | #define TSEC_REG_MON_RUND 0x6cc /* Receive undersize packet counter |
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| 128 | * register */ |
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| 129 | #define TSEC_REG_MON_ROVR 0x6d0 /* Receive oversize packet counter |
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| 130 | * register */ |
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| 131 | #define TSEC_REG_MON_RFRG 0x6d4 /* Receive fragments counter register */ |
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| 132 | #define TSEC_REG_MON_RJBR 0x6d8 /* Receive jabber counter register */ |
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| 133 | #define TSEC_REG_MON_RDRP 0x6dc /* Receive drop counter register */ |
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| 134 | |
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| 135 | /* TSEC Transmit Counters */ |
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| 136 | #define TSEC_REG_MON_TBYT 0x6e0 /* Transmit byte counter register */ |
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| 137 | #define TSEC_REG_MON_TPKT 0x6e4 /* Transmit packet counter register */ |
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| 138 | #define TSEC_REG_MON_TMCA 0x6e8 /* Transmit multicast packet counter |
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| 139 | * register */ |
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| 140 | #define TSEC_REG_MON_TBCA 0x6ec /* Transmit broadcast packet counter |
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| 141 | * register */ |
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| 142 | #define TSEC_REG_MON_TXPF 0x6f0 /* Transmit PAUSE control frame counter |
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| 143 | * register */ |
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| 144 | #define TSEC_REG_MON_TDFR 0x6f4 /* Transmit deferral packet counter |
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| 145 | * register */ |
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| 146 | #define TSEC_REG_MON_TEDF 0x6f8 /* Transmit excessive deferral packet |
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| 147 | * counter register */ |
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| 148 | #define TSEC_REG_MON_TSCL 0x6fc /* Transmit single collision packet counter |
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| 149 | * register */ |
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| 150 | #define TSEC_REG_MON_TMCL 0x700 /* Transmit multiple collision packet counter |
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| 151 | * register */ |
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| 152 | #define TSEC_REG_MON_TLCL 0x704 /* Transmit late collision packet counter |
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| 153 | * register */ |
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| 154 | #define TSEC_REG_MON_TXCL 0x708 /* Transmit excessive collision packet |
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| 155 | * counter register */ |
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| 156 | #define TSEC_REG_MON_TNCL 0x70c /* Transmit total collision counter |
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| 157 | * register */ |
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| 158 | #define TSEC_REG_MON_TDRP 0x714 /* Transmit drop frame counter register */ |
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| 159 | #define TSEC_REG_MON_TJBR 0x718 /* Transmit jabber frame counter register */ |
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| 160 | #define TSEC_REG_MON_TFCS 0x71c /* Transmit FCS error counter register */ |
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| 161 | #define TSEC_REG_MON_TXCF 0x720 /* Transmit control frame counter register */ |
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| 162 | #define TSEC_REG_MON_TOVR 0x724 /* Transmit oversize frame counter |
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| 163 | * register */ |
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| 164 | #define TSEC_REG_MON_TUND 0x728 /* Transmit undersize frame counter |
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| 165 | * register */ |
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| 166 | #define TSEC_REG_MON_TFRG 0x72c /* Transmit fragments frame counter |
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| 167 | * register */ |
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| 168 | |
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| 169 | /* TSEC General Registers */ |
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| 170 | #define TSEC_REG_MON_CAR1 0x730 /* Carry register one register */ |
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| 171 | #define TSEC_REG_MON_CAR2 0x734 /* Carry register two register */ |
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| 172 | #define TSEC_REG_MON_CAM1 0x738 /* Carry register one mask register */ |
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| 173 | #define TSEC_REG_MON_CAM2 0x73c /* Carry register two mask register */ |
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| 174 | |
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| 175 | /* TSEC Hash Function Registers */ |
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| 176 | #define TSEC_REG_IADDR0 0x800 /* Indivdual address register 0 */ |
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| 177 | #define TSEC_REG_IADDR1 0x804 /* Indivdual address register 1 */ |
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| 178 | #define TSEC_REG_IADDR2 0x808 /* Indivdual address register 2 */ |
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| 179 | #define TSEC_REG_IADDR3 0x80c /* Indivdual address register 3 */ |
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| 180 | #define TSEC_REG_IADDR4 0x810 /* Indivdual address register 4 */ |
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| 181 | #define TSEC_REG_IADDR5 0x814 /* Indivdual address register 5 */ |
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| 182 | #define TSEC_REG_IADDR6 0x818 /* Indivdual address register 6 */ |
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| 183 | #define TSEC_REG_IADDR7 0x81c /* Indivdual address register 7 */ |
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| 184 | #define TSEC_REG_GADDR0 0x880 /* Group address register 0 */ |
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| 185 | #define TSEC_REG_GADDR1 0x884 /* Group address register 1 */ |
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| 186 | #define TSEC_REG_GADDR2 0x888 /* Group address register 2 */ |
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| 187 | #define TSEC_REG_GADDR3 0x88c /* Group address register 3 */ |
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| 188 | #define TSEC_REG_GADDR4 0x890 /* Group address register 4 */ |
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| 189 | #define TSEC_REG_GADDR5 0x894 /* Group address register 5 */ |
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| 190 | #define TSEC_REG_GADDR6 0x898 /* Group address register 6 */ |
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| 191 | #define TSEC_REG_GADDR7 0x89c /* Group address register 7 */ |
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| 192 | #define TSEC_REG_IADDR(n) (TSEC_REG_IADDR0 + (n << 2)) |
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| 193 | #define TSEC_REG_GADDR(n) (TSEC_REG_GADDR0 + (n << 2)) |
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| 194 | |
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| 195 | /* TSEC attribute registers */ |
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| 196 | #define TSEC_REG_ATTR 0xbf8 /* Attributes Register */ |
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| 197 | #define TSEC_REG_ATTRELI 0xbfc /* Attributes EL & EI register */ |
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| 198 | |
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| 199 | /* Size of TSEC registers area */ |
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| 200 | #define TSEC_IO_SIZE 0x1000 |
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| 201 | |
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| 202 | /* reg bits */ |
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| 203 | #define TSEC_FIFO_PAUSE_CTRL_EN 0x0002 |
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| 204 | |
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| 205 | #define TSEC_DMACTRL_TDSEN 0x00000080 /* Tx Data snoop enable */ |
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| 206 | #define TSEC_DMACTRL_TBDSEN 0x00000040 /* TxBD snoop enable */ |
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| 207 | #define TSEC_DMACTRL_GRS 0x00000010 /* Graceful receive stop */ |
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| 208 | #define TSEC_DMACTRL_GTS 0x00000008 /* Graceful transmit stop */ |
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| 209 | #define DMACTRL_WWR 0x00000002 /* Write with response */ |
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| 210 | #define DMACTRL_WOP 0x00000001 /* Wait or poll */ |
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| 211 | |
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| 212 | #define TSEC_RCTRL_VLEX 0x00002000 /* Enable automatic VLAN tag |
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| 213 | * extraction and deletion |
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| 214 | * from Ethernet frames */ |
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| 215 | #define TSEC_RCTRL_IPCSEN 0x00000200 /* IP Checksum verification enable */ |
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| 216 | #define TSEC_RCTRL_TUCSEN 0x00000100 /* TCP or UDP Checksum verification enable */ |
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| 217 | #define TSEC_RCTRL_PRSDEP 0x000000C0 /* Parser control */ |
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| 218 | #define TSEC_RCRTL_PRSFM 0x00000020 /* FIFO-mode parsing */ |
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| 219 | #define TSEC_RCTRL_BC_REJ 0x00000010 /* Broadcast frame reject */ |
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| 220 | #define TSEC_RCTRL_PROM 0x00000008 /* Promiscuous mode */ |
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| 221 | #define TSEC_RCTRL_RSF 0x00000004 /* Receive short frame mode */ |
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| 222 | |
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| 223 | #define TSEC_RCTRL_PRSDEP_PARSER_OFF 0x00000000 /* Parser Disabled */ |
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| 224 | #define TSEC_RCTRL_PRSDEP_PARSE_L2 0x00000040 /* Parse L2 */ |
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| 225 | #define TSEC_RCTRL_PRSDEP_PARSE_L23 0x00000080 /* Parse L2 and L3 */ |
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| 226 | #define TSEC_RCTRL_PRSDEP_PARSE_L234 0x000000C0 /* Parse L2, L3 and L4 */ |
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| 227 | |
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| 228 | #define TSEC_TCTRL_IPCSEN 0x00004000 /* IP header checksum generation enable */ |
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| 229 | #define TSEC_TCTRL_TUCSEN 0x00002000 /* TCP/UDP header checksum generation enable */ |
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| 230 | |
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| 231 | #define TSEC_TSTAT_THLT 0x80000000 /* Transmit halt */ |
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| 232 | #define TSEC_RSTAT_QHLT 0x00800000 /* RxBD queue is halted */ |
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| 233 | |
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| 234 | #define TSEC_IEVENT_BABR 0x80000000 /* Babbling receive error */ |
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| 235 | #define TSEC_IEVENT_RXC 0x40000000 /* Receive control interrupt */ |
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| 236 | #define TSEC_IEVENT_BSY 0x20000000 /* Busy condition interrupt */ |
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| 237 | #define TSEC_IEVENT_EBERR 0x10000000 /* Ethernet bus error */ |
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| 238 | #define TSEC_IEVENT_MSRO 0x04000000 /* MSTAT Register Overflow */ |
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| 239 | #define TSEC_IEVENT_GTSC 0x02000000 /* Graceful transmit stop complete */ |
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| 240 | #define TSEC_IEVENT_BABT 0x01000000 /* Babbling transmit error */ |
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| 241 | #define TSEC_IEVENT_TXC 0x00800000 /* Transmit control interrupt */ |
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| 242 | #define TSEC_IEVENT_TXE 0x00400000 /* Transmit error */ |
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| 243 | #define TSEC_IEVENT_TXB 0x00200000 /* Transmit buffer */ |
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| 244 | #define TSEC_IEVENT_TXF 0x00100000 /* Transmit frame interrupt */ |
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| 245 | #define TSEC_IEVENT_LC 0x00040000 /* Late collision */ |
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| 246 | #define TSEC_IEVENT_CRL 0x00020000 /* Collision retry limit/excessive |
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| 247 | * defer abort */ |
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| 248 | #define TSEC_IEVENT_XFUN 0x00010000 /* Transmit FIFO underrun */ |
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| 249 | #define TSEC_IEVENT_RXB 0x00008000 /* Receive buffer */ |
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| 250 | #define TSEC_IEVENT_MMRD 0x00000400 /* MII management read completion */ |
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| 251 | #define TSEC_IEVENT_MMWR 0x00000200 /* MII management write completion */ |
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| 252 | #define TSEC_IEVENT_GRSC 0x00000100 /* Graceful receive stop complete */ |
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| 253 | #define TSEC_IEVENT_RXF 0x00000080 /* Receive frame interrupt */ |
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| 254 | |
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| 255 | #define TSEC_IMASK_BREN 0x80000000 /* Babbling receiver interrupt */ |
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| 256 | #define TSEC_IMASK_RXCEN 0x40000000 /* Receive control interrupt */ |
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| 257 | #define TSEC_IMASK_BSYEN 0x20000000 /* Busy interrupt */ |
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| 258 | #define TSEC_IMASK_EBERREN 0x10000000 /* Ethernet controller bus error */ |
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| 259 | #define TSEC_IMASK_MSROEN 0x04000000 /* MSTAT register overflow interrupt */ |
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| 260 | #define TSEC_IMASK_GTSCEN 0x02000000 /* Graceful transmit stop complete interrupt */ |
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| 261 | #define TSEC_IMASK_BTEN 0x01000000 /* Babbling transmitter interrupt */ |
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| 262 | #define TSEC_IMASK_TXCEN 0x00800000 /* Transmit control interrupt */ |
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| 263 | #define TSEC_IMASK_TXEEN 0x00400000 /* Transmit error interrupt */ |
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| 264 | #define TSEC_IMASK_TXBEN 0x00200000 /* Transmit buffer interrupt */ |
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| 265 | #define TSEC_IMASK_TXFEN 0x00100000 /* Transmit frame interrupt */ |
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| 266 | #define TSEC_IMASK_LCEN 0x00040000 /* Late collision */ |
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| 267 | #define TSEC_IMASK_CRLEN 0x00020000 /* Collision retry limit/excessive defer */ |
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| 268 | #define TSEC_IMASK_XFUNEN 0x00010000 /* Transmit FIFO underrun */ |
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| 269 | #define TSEC_IMASK_RXBEN 0x00008000 /* Receive buffer interrupt */ |
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| 270 | #define TSEC_IMASK_MMRD 0x00000400 /* MII management read completion */ |
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| 271 | #define TSEC_IMASK_MMWR 0x00000200 /* MII management write completion */ |
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| 272 | #define TSEC_IMASK_GRSCEN 0x00000100 /* Graceful receive stop complete interrupt */ |
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| 273 | #define TSEC_IMASK_RXFEN 0x00000080 /* Receive frame interrupt */ |
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| 274 | |
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| 275 | #define TSEC_ATTR_ELCWT 0x00004000 /* Write extracted data to L2 cache */ |
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| 276 | #define TSEC_ATTR_BDLWT 0x00000800 /* Write buffer descriptor to L2 cache */ |
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| 277 | #define TSEC_ATTR_RDSEN 0x00000080 /* Rx data snoop enable */ |
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| 278 | #define TSEC_ATTR_RBDSEN 0x00000040 /* RxBD snoop enable */ |
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| 279 | |
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| 280 | #define TSEC_MACCFG1_SOFT_RESET 0x80000000 /* Soft reset */ |
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| 281 | #define TSEC_MACCFG1_RESET_RX_MC 0x00080000 /* Reset receive MAC control block */ |
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| 282 | #define TSEC_MACCFG1_RESET_TX_MC 0x00040000 /* Reset transmit MAC control block */ |
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| 283 | #define TSEC_MACCFG1_RESET_RX_FUN 0x00020000 /* Reset receive function block */ |
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| 284 | #define TSEC_MACCFG1_RESET_TX_FUN 0x00010000 /* Reset transmit function block */ |
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| 285 | #define TSEC_MACCFG1_LOOPBACK 0x00000100 /* Loopback */ |
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| 286 | #define TSEC_MACCFG1_RX_FLOW 0x00000020 /* Receive flow */ |
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| 287 | #define TSEC_MACCFG1_TX_FLOW 0x00000010 /* Transmit flow */ |
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| 288 | #define TSEC_MACCFG1_SYNCD_RX_EN 0x00000008 /* Receive enable synchronized |
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| 289 | * to the receive stream (Read-only) */ |
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| 290 | #define TSEC_MACCFG1_RX_EN 0x00000004 /* Receive enable */ |
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| 291 | #define TSEC_MACCFG1_SYNCD_TX_EN 0x00000002 /* Transmit enable synchronized |
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| 292 | * to the transmit stream (Read-only) */ |
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| 293 | #define TSEC_MACCFG1_TX_EN 0x00000001 /* Transmit enable */ |
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| 294 | |
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| 295 | #define TSEC_MACCFG2_PRECNT 0x00007000 /* Preamble Length (0x7) */ |
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| 296 | #define TSEC_MACCFG2_IF 0x00000300 /* Determines the type of interface |
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| 297 | * to which the MAC is connected */ |
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| 298 | #define TSEC_MACCFG2_MII 0x00000100 /* Nibble mode (MII) */ |
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| 299 | #define TSEC_MACCFG2_GMII 0x00000200 /* Byte mode (GMII/TBI) */ |
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| 300 | #define TSEC_MACCFG2_HUGEFRAME 0x00000020 /* Huge frame enable */ |
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| 301 | #define TSEC_MACCFG2_LENGTHCHECK 0x00000010 /* Length check */ |
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| 302 | #define TSEC_MACCFG2_PADCRC 0x00000004 /* Pad and append CRC */ |
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| 303 | #define TSEC_MACCFG2_CRCEN 0x00000002 /* CRC enable */ |
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| 304 | #define TSEC_MACCFG2_FULLDUPLEX 0x00000001 /* Full duplex configure */ |
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| 305 | |
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| 306 | #define TSEC_ECNTRL_STEN 0x00001000 /* Statistics enabled */ |
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| 307 | #define TSEC_ECNTRL_GMIIM 0x00000040 /* GMII I/F mode */ |
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| 308 | #define TSEC_ECNTRL_TBIM 0x00000020 /* Ten-bit I/F mode */ |
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| 309 | #define TSEC_ECNTRL_R100M 0x00000008 /* RGMII/RMII 100 mode */ |
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| 310 | #define TSEC_ECNTRL_RMM 0x00000004 /* Reduced-pin mode */ |
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| 311 | #define TSEC_ECNTRL_SGMIIM 0x00000002 /* Serial GMII mode */ |
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| 312 | |
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| 313 | #define TSEC_MIIMCFG_RESETMGMT 0x80000000 /* Reset management */ |
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| 314 | #define TSEC_MIIMCFG_NOPRE 0x00000010 /* Preamble suppress */ |
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| 315 | #define TSEC_MIIMCFG_CLKDIV28 0x00000007 /* source clock divided by 28 */ |
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| 316 | #define TSEC_MIIMCFG_CLKDIV20 0x00000006 /* source clock divided by 20 */ |
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| 317 | #define TSEC_MIIMCFG_CLKDIV14 0x00000005 /* source clock divided by 14 */ |
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| 318 | #define TSEC_MIIMCFG_CLKDIV10 0x00000004 /* source clock divided by 10 */ |
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| 319 | #define TSEC_MIIMCFG_CLKDIV8 0x00000003 /* source clock divided by 8 */ |
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| 320 | #define TSEC_MIIMCFG_CLKDIV6 0x00000002 /* source clock divided by 6 */ |
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| 321 | #define TSEC_MIIMCFG_CLKDIV4 0x00000001 /* source clock divided by 4 */ |
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| 322 | |
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| 323 | #define TSEC_MIIMIND_NOTVALID 0x00000004 /* Not valid */ |
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| 324 | #define TSEC_MIIMIND_SCAN 0x00000002 /* Scan in progress */ |
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| 325 | #define TSEC_MIIMIND_BUSY 0x00000001 /* Busy */ |
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| 326 | |
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| 327 | #define TSEC_MIIMCOM_SCANCYCLE 0x00000002 /* Scan cycle */ |
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| 328 | #define TSEC_MIIMCOM_READCYCLE 0x00000001 /* Read cycle */ |
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| 329 | |
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| 330 | /* Transmit Data Buffer Descriptor (TxBD) Field Descriptions */ |
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| 331 | #define TSEC_TXBD_R 0x8000 /* Ready */ |
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| 332 | #define TSEC_TXBD_PADCRC 0x4000 /* PAD/CRC */ |
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| 333 | #define TSEC_TXBD_W 0x2000 /* Wrap */ |
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| 334 | #define TSEC_TXBD_I 0x1000 /* Interrupt */ |
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| 335 | #define TSEC_TXBD_L 0x0800 /* Last in frame */ |
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| 336 | #define TSEC_TXBD_TC 0x0400 /* Tx CRC */ |
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| 337 | #define TSEC_TXBD_DEF 0x0200 /* Defer indication */ |
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| 338 | #define TSEC_TXBD_TO1 0x0100 /* Transmit software ownership */ |
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| 339 | #define TSEC_TXBD_HFE 0x0080 /* Huge frame enable (written by user) */ |
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| 340 | #define TSEC_TXBD_LC 0x0080 /* Late collision (written by TSEC) */ |
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| 341 | #define TSEC_TXBD_RL 0x0040 /* Retransmission Limit */ |
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| 342 | #define TSEC_TXBD_TOE 0x0002 /* TCP/IP Offload Enable */ |
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| 343 | #define TSEC_TXBD_UN 0x0002 /* Underrun */ |
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| 344 | #define TSEC_TXBD_TXTRUNC 0x0001 /* TX truncation */ |
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| 345 | |
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| 346 | /* Receive Data Buffer Descriptor (RxBD) Field Descriptions */ |
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| 347 | #define TSEC_RXBD_E 0x8000 /* Empty */ |
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| 348 | #define TSEC_RXBD_RO1 0x4000 /* Receive software ownership bit */ |
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| 349 | #define TSEC_RXBD_W 0x2000 /* Wrap */ |
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| 350 | #define TSEC_RXBD_I 0x1000 /* Interrupt */ |
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| 351 | #define TSEC_RXBD_L 0x0800 /* Last in frame */ |
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| 352 | #define TSEC_RXBD_F 0x0400 /* First in frame */ |
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| 353 | #define TSEC_RXBD_M 0x0100 /* Miss - The frame was received because |
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| 354 | * of promiscuous mode. */ |
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| 355 | #define TSEC_RXBD_B 0x0080 /* Broadcast */ |
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| 356 | #define TSEC_RXBD_MC 0x0040 /* Multicast */ |
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| 357 | #define TSEC_RXBD_LG 0x0020 /* Large - Rx frame length violation */ |
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| 358 | #define TSEC_RXBD_NO 0x0010 /* Rx non-octet aligned frame */ |
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| 359 | #define TSEC_RXBD_SH 0x0008 /* Short frame */ |
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| 360 | #define TSEC_RXBD_CR 0x0004 /* Rx CRC error */ |
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| 361 | #define TSEC_RXBD_OV 0x0002 /* Overrun */ |
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| 362 | #define TSEC_RXBD_TR 0x0001 /* Truncation */ |
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| 363 | #define TSEC_RXBD_ZEROONINIT (TSEC_RXBD_TR | TSEC_RXBD_OV | TSEC_RXBD_CR | \ |
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| 364 | TSEC_RXBD_SH | TSEC_RXBD_NO | TSEC_RXBD_LG | TSEC_RXBD_MC | \ |
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| 365 | TSEC_RXBD_B | TSEC_RXBD_M) |
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| 366 | |
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| 367 | #define TSEC_TXBUFFER_ALIGNMENT 64 |
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| 368 | #define TSEC_RXBUFFER_ALIGNMENT 64 |
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| 369 | |
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| 370 | /* Transmit Path Off-Load Frame Control Block flags */ |
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| 371 | #define TSEC_TX_FCB_VLAN 0x8000 /* VLAN control word valid */ |
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| 372 | #define TSEC_TX_FCB_L3_IS_IP 0x4000 /* Layer 3 header is an IP header */ |
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| 373 | #define TSEC_TX_FCB_L3_IS_IP6 0x2000 /* IP header is IP version 6 */ |
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| 374 | #define TSEC_TX_FCB_L4_IS_TCP_UDP 0x1000 /* Layer 4 header is a TCP or UDP header */ |
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| 375 | #define TSEC_TX_FCB_L4_IS_UDP 0x0800 /* UDP protocol at layer 4 */ |
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| 376 | #define TSEC_TX_FCB_CSUM_IP 0x0400 /* Checksum IP header enable */ |
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| 377 | #define TSEC_TX_FCB_CSUM_TCP_UDP 0x0200 /* Checksum TCP or UDP header enable */ |
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| 378 | #define TSEC_TX_FCB_FLAG_NO_PH_CSUM 0x0100 /* Disable pseudo-header checksum */ |
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| 379 | #define TSEC_TX_FCB_FLAG_PTP 0x0001 /* This is a PTP packet */ |
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| 380 | |
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| 381 | /* Receive Path Off-Load Frame Control Block flags */ |
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| 382 | #define TSEC_RX_FCB_VLAN 0x8000 /* VLAN tag recognized */ |
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| 383 | #define TSEC_RX_FCB_IP_FOUND 0x4000 /* IP header found at layer 3 */ |
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| 384 | #define TSEC_RX_FCB_IP6_FOUND 0x2000 /* IP version 6 header found at layer 3 */ |
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| 385 | #define TSEC_RX_FCB_TCP_UDP_FOUND 0x1000 /* TCP or UDP header found at layer 4 */ |
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| 386 | #define TSEC_RX_FCB_IP_CSUM 0x0800 /* IPv4 header checksum checked */ |
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| 387 | #define TSEC_RX_FCB_TCP_UDP_CSUM 0x0400 /* TCP or UDP header checksum checked */ |
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| 388 | #define TSEC_RX_FCB_IP_CSUM_ERROR 0x0200 /* IPv4 header checksum verification error */ |
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| 389 | #define TSEC_RX_FCB_TCP_UDP_CSUM_ERROR 0x0100 /* TCP or UDP header checksum verification error */ |
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| 390 | #define TSEC_RX_FCB_PARSE_ERROR 0x000C /* Parse error */ |
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