[70bb42b] | 1 | /*- |
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| 2 | * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * 1. Redistributions of source code must retain the above copyright |
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| 9 | * notice, this list of conditions and the following disclaimer. |
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| 10 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 11 | * notice, this list of conditions and the following disclaimer in the |
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| 12 | * documentation and/or other materials provided with the distribution. |
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| 13 | * |
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| 14 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 15 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 16 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
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| 17 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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| 18 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED |
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| 19 | * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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| 20 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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| 21 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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| 22 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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| 23 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 24 | * |
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| 25 | * $FreeBSD$ |
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| 26 | */ |
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| 27 | |
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| 28 | #ifndef _IF_TSEC_H |
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| 29 | #define _IF_TSEC_H |
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| 30 | |
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| 31 | #include <dev/ofw/openfirm.h> |
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| 32 | |
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| 33 | #define TSEC_RX_NUM_DESC 256 |
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| 34 | #define TSEC_TX_NUM_DESC 256 |
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| 35 | |
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| 36 | /* Interrupt Coalescing types */ |
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| 37 | #define TSEC_IC_RX 0 |
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| 38 | #define TSEC_IC_TX 1 |
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| 39 | |
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| 40 | /* eTSEC ID */ |
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| 41 | #define TSEC_ETSEC_ID 0x0124 |
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| 42 | |
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| 43 | /* Frame sizes */ |
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| 44 | #define TSEC_MIN_FRAME_SIZE 64 |
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| 45 | #define TSEC_MAX_FRAME_SIZE 9600 |
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| 46 | |
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| 47 | struct tsec_softc { |
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| 48 | /* XXX MII bus requires that struct ifnet is first!!! */ |
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| 49 | struct ifnet *tsec_ifp; |
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| 50 | |
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| 51 | struct mtx transmit_lock; /* transmitter lock */ |
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| 52 | struct mtx receive_lock; /* receiver lock */ |
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| 53 | |
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[8fe59fe] | 54 | #ifndef __rtems__ |
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[70bb42b] | 55 | phandle_t node; |
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[8fe59fe] | 56 | #endif /* __rtems__ */ |
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[70bb42b] | 57 | device_t dev; |
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| 58 | device_t tsec_miibus; |
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| 59 | struct mii_data *tsec_mii; /* MII media control */ |
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| 60 | int tsec_link; |
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| 61 | |
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| 62 | bus_dma_tag_t tsec_tx_dtag; /* TX descriptors tag */ |
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| 63 | bus_dmamap_t tsec_tx_dmap; /* TX descriptors map */ |
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| 64 | struct tsec_desc *tsec_tx_vaddr;/* vadress of TX descriptors */ |
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| 65 | uint32_t tsec_tx_raddr; /* real adress of TX descriptors */ |
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| 66 | |
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| 67 | bus_dma_tag_t tsec_rx_dtag; /* RX descriptors tag */ |
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| 68 | bus_dmamap_t tsec_rx_dmap; /* RX descriptors map */ |
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| 69 | struct tsec_desc *tsec_rx_vaddr; /* vadress of RX descriptors */ |
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| 70 | uint32_t tsec_rx_raddr; /* real adress of RX descriptors */ |
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| 71 | |
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| 72 | bus_dma_tag_t tsec_tx_mtag; /* TX mbufs tag */ |
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| 73 | bus_dma_tag_t tsec_rx_mtag; /* TX mbufs tag */ |
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| 74 | |
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| 75 | struct rx_data_type { |
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| 76 | bus_dmamap_t map; /* mbuf map */ |
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| 77 | struct mbuf *mbuf; |
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| 78 | uint32_t paddr; /* DMA addres of buffer */ |
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| 79 | } rx_data[TSEC_RX_NUM_DESC]; |
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| 80 | |
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| 81 | uint32_t tx_cur_desc_cnt; |
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| 82 | uint32_t tx_dirty_desc_cnt; |
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| 83 | uint32_t rx_cur_desc_cnt; |
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| 84 | |
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| 85 | struct resource *sc_rres; /* register resource */ |
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| 86 | int sc_rrid; /* register rid */ |
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| 87 | struct { |
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| 88 | bus_space_tag_t bst; |
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| 89 | bus_space_handle_t bsh; |
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| 90 | } sc_bas; |
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| 91 | |
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| 92 | struct resource *sc_transmit_ires; |
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| 93 | void *sc_transmit_ihand; |
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| 94 | int sc_transmit_irid; |
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| 95 | struct resource *sc_receive_ires; |
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| 96 | void *sc_receive_ihand; |
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| 97 | int sc_receive_irid; |
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| 98 | struct resource *sc_error_ires; |
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| 99 | void *sc_error_ihand; |
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| 100 | int sc_error_irid; |
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| 101 | |
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| 102 | int tsec_if_flags; |
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| 103 | int is_etsec; |
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| 104 | |
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| 105 | /* Watchdog and MII tick related */ |
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| 106 | struct callout tsec_callout; |
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| 107 | int tsec_watchdog; |
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| 108 | |
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| 109 | /* TX maps */ |
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| 110 | bus_dmamap_t tx_map_data[TSEC_TX_NUM_DESC]; |
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| 111 | |
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| 112 | /* unused TX maps data */ |
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| 113 | uint32_t tx_map_unused_get_cnt; |
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| 114 | uint32_t tx_map_unused_put_cnt; |
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| 115 | bus_dmamap_t *tx_map_unused_data[TSEC_TX_NUM_DESC]; |
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| 116 | |
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| 117 | /* used TX maps data */ |
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| 118 | uint32_t tx_map_used_get_cnt; |
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| 119 | uint32_t tx_map_used_put_cnt; |
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| 120 | bus_dmamap_t *tx_map_used_data[TSEC_TX_NUM_DESC]; |
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| 121 | |
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| 122 | /* mbufs in TX queue */ |
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| 123 | uint32_t tx_mbuf_used_get_cnt; |
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| 124 | uint32_t tx_mbuf_used_put_cnt; |
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| 125 | struct mbuf *tx_mbuf_used_data[TSEC_TX_NUM_DESC]; |
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| 126 | |
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| 127 | /* interrupt coalescing */ |
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| 128 | struct mtx ic_lock; |
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| 129 | uint32_t rx_ic_time; /* RW, valid values 0..65535 */ |
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| 130 | uint32_t rx_ic_count; /* RW, valid values 0..255 */ |
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| 131 | uint32_t tx_ic_time; |
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| 132 | uint32_t tx_ic_count; |
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| 133 | |
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| 134 | /* currently received frame */ |
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| 135 | struct mbuf *frame; |
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| 136 | |
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| 137 | int phyaddr; |
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| 138 | struct tsec_softc *phy_sc; |
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| 139 | }; |
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| 140 | |
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| 141 | /* interface to get/put generic objects */ |
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| 142 | #define TSEC_CNT_INIT(cnt, wrap) ((cnt) = ((wrap) - 1)) |
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| 143 | |
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| 144 | #define TSEC_INC(count, wrap) (count = ((count) + 1) & ((wrap) - 1)) |
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| 145 | |
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| 146 | #define TSEC_GET_GENERIC(hand, tab, count, wrap) \ |
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| 147 | ((hand)->tab[TSEC_INC((hand)->count, wrap)]) |
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| 148 | |
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| 149 | #define TSEC_PUT_GENERIC(hand, tab, count, wrap, val) \ |
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| 150 | ((hand)->tab[TSEC_INC((hand)->count, wrap)] = val) |
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| 151 | |
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| 152 | #define TSEC_BACK_GENERIC(sc, count, wrap) do { \ |
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| 153 | if ((sc)->count > 0) \ |
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| 154 | (sc)->count--; \ |
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| 155 | else \ |
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| 156 | (sc)->count = (wrap) - 1; \ |
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| 157 | } while (0) |
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| 158 | |
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| 159 | /* TX maps interface */ |
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| 160 | #define TSEC_TX_MAP_CNT_INIT(sc) do { \ |
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| 161 | TSEC_CNT_INIT((sc)->tx_map_unused_get_cnt, TSEC_TX_NUM_DESC); \ |
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| 162 | TSEC_CNT_INIT((sc)->tx_map_unused_put_cnt, TSEC_TX_NUM_DESC); \ |
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| 163 | TSEC_CNT_INIT((sc)->tx_map_used_get_cnt, TSEC_TX_NUM_DESC); \ |
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| 164 | TSEC_CNT_INIT((sc)->tx_map_used_put_cnt, TSEC_TX_NUM_DESC); \ |
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| 165 | } while (0) |
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| 166 | |
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| 167 | /* interface to get/put unused TX maps */ |
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| 168 | #define TSEC_ALLOC_TX_MAP(sc) \ |
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| 169 | TSEC_GET_GENERIC(sc, tx_map_unused_data, tx_map_unused_get_cnt, \ |
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| 170 | TSEC_TX_NUM_DESC) |
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| 171 | |
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| 172 | #define TSEC_FREE_TX_MAP(sc, val) \ |
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| 173 | TSEC_PUT_GENERIC(sc, tx_map_unused_data, tx_map_unused_put_cnt, \ |
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| 174 | TSEC_TX_NUM_DESC, val) |
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| 175 | |
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| 176 | /* interface to get/put used TX maps */ |
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| 177 | #define TSEC_GET_TX_MAP(sc) \ |
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| 178 | TSEC_GET_GENERIC(sc, tx_map_used_data, tx_map_used_get_cnt, \ |
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| 179 | TSEC_TX_NUM_DESC) |
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| 180 | |
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| 181 | #define TSEC_PUT_TX_MAP(sc, val) \ |
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| 182 | TSEC_PUT_GENERIC(sc, tx_map_used_data, tx_map_used_put_cnt, \ |
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| 183 | TSEC_TX_NUM_DESC, val) |
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| 184 | |
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| 185 | /* interface to get/put TX mbufs in send queue */ |
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| 186 | #define TSEC_TX_MBUF_CNT_INIT(sc) do { \ |
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| 187 | TSEC_CNT_INIT((sc)->tx_mbuf_used_get_cnt, TSEC_TX_NUM_DESC); \ |
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| 188 | TSEC_CNT_INIT((sc)->tx_mbuf_used_put_cnt, TSEC_TX_NUM_DESC); \ |
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| 189 | } while (0) |
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| 190 | |
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| 191 | #define TSEC_GET_TX_MBUF(sc) \ |
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| 192 | TSEC_GET_GENERIC(sc, tx_mbuf_used_data, tx_mbuf_used_get_cnt, \ |
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| 193 | TSEC_TX_NUM_DESC) |
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| 194 | |
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| 195 | #define TSEC_PUT_TX_MBUF(sc, val) \ |
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| 196 | TSEC_PUT_GENERIC(sc, tx_mbuf_used_data, tx_mbuf_used_put_cnt, \ |
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| 197 | TSEC_TX_NUM_DESC, val) |
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| 198 | |
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| 199 | #define TSEC_EMPTYQ_TX_MBUF(sc) \ |
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| 200 | ((sc)->tx_mbuf_used_get_cnt == (sc)->tx_mbuf_used_put_cnt) |
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| 201 | |
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| 202 | /* interface for manage tx tsec_desc */ |
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| 203 | #define TSEC_TX_DESC_CNT_INIT(sc) do { \ |
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| 204 | TSEC_CNT_INIT((sc)->tx_cur_desc_cnt, TSEC_TX_NUM_DESC); \ |
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| 205 | TSEC_CNT_INIT((sc)->tx_dirty_desc_cnt, TSEC_TX_NUM_DESC); \ |
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| 206 | } while (0) |
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| 207 | |
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| 208 | #define TSEC_GET_CUR_TX_DESC(sc) \ |
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| 209 | &TSEC_GET_GENERIC(sc, tsec_tx_vaddr, tx_cur_desc_cnt, \ |
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| 210 | TSEC_TX_NUM_DESC) |
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| 211 | |
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| 212 | #define TSEC_GET_DIRTY_TX_DESC(sc) \ |
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| 213 | &TSEC_GET_GENERIC(sc, tsec_tx_vaddr, tx_dirty_desc_cnt, \ |
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| 214 | TSEC_TX_NUM_DESC) |
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| 215 | |
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| 216 | #define TSEC_BACK_DIRTY_TX_DESC(sc) \ |
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| 217 | TSEC_BACK_GENERIC(sc, tx_dirty_desc_cnt, TSEC_TX_NUM_DESC) |
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| 218 | |
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| 219 | #define TSEC_CUR_DIFF_DIRTY_TX_DESC(sc) \ |
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| 220 | ((sc)->tx_cur_desc_cnt != (sc)->tx_dirty_desc_cnt) |
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| 221 | |
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| 222 | #define TSEC_FREE_TX_DESC(sc) \ |
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| 223 | (((sc)->tx_cur_desc_cnt < (sc)->tx_dirty_desc_cnt) ? \ |
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| 224 | ((sc)->tx_dirty_desc_cnt - (sc)->tx_cur_desc_cnt - 1) \ |
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| 225 | : \ |
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| 226 | (TSEC_TX_NUM_DESC - (sc)->tx_cur_desc_cnt \ |
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| 227 | + (sc)->tx_dirty_desc_cnt - 1)) |
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| 228 | |
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| 229 | /* interface for manage rx tsec_desc */ |
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| 230 | #define TSEC_RX_DESC_CNT_INIT(sc) do { \ |
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| 231 | TSEC_CNT_INIT((sc)->rx_cur_desc_cnt, TSEC_RX_NUM_DESC); \ |
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| 232 | } while (0) |
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| 233 | |
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| 234 | #define TSEC_GET_CUR_RX_DESC(sc) \ |
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| 235 | &TSEC_GET_GENERIC(sc, tsec_rx_vaddr, rx_cur_desc_cnt, \ |
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| 236 | TSEC_RX_NUM_DESC) |
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| 237 | |
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| 238 | #define TSEC_BACK_CUR_RX_DESC(sc) \ |
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| 239 | TSEC_BACK_GENERIC(sc, rx_cur_desc_cnt, TSEC_RX_NUM_DESC) |
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| 240 | |
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| 241 | #define TSEC_GET_CUR_RX_DESC_CNT(sc) \ |
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| 242 | ((sc)->rx_cur_desc_cnt) |
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| 243 | |
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| 244 | /* init all counters (for init only!) */ |
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| 245 | #define TSEC_TX_RX_COUNTERS_INIT(sc) do { \ |
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| 246 | TSEC_TX_MAP_CNT_INIT(sc); \ |
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| 247 | TSEC_TX_MBUF_CNT_INIT(sc); \ |
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| 248 | TSEC_TX_DESC_CNT_INIT(sc); \ |
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| 249 | TSEC_RX_DESC_CNT_INIT(sc); \ |
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| 250 | } while (0) |
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| 251 | |
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| 252 | /* read/write bus functions */ |
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| 253 | #define TSEC_READ(sc, reg) \ |
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| 254 | bus_space_read_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg)) |
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| 255 | #define TSEC_WRITE(sc, reg, val) \ |
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| 256 | bus_space_write_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg), (val)) |
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| 257 | |
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| 258 | /* Lock for transmitter */ |
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| 259 | #define TSEC_TRANSMIT_LOCK(sc) do { \ |
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| 260 | mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \ |
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| 261 | mtx_lock(&(sc)->transmit_lock); \ |
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| 262 | } while (0) |
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| 263 | |
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| 264 | #define TSEC_TRANSMIT_UNLOCK(sc) mtx_unlock(&(sc)->transmit_lock) |
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| 265 | #define TSEC_TRANSMIT_LOCK_ASSERT(sc) mtx_assert(&(sc)->transmit_lock, MA_OWNED) |
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| 266 | |
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| 267 | /* Lock for receiver */ |
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| 268 | #define TSEC_RECEIVE_LOCK(sc) do { \ |
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| 269 | mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \ |
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| 270 | mtx_lock(&(sc)->receive_lock); \ |
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| 271 | } while (0) |
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| 272 | |
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| 273 | #define TSEC_RECEIVE_UNLOCK(sc) mtx_unlock(&(sc)->receive_lock) |
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| 274 | #define TSEC_RECEIVE_LOCK_ASSERT(sc) mtx_assert(&(sc)->receive_lock, MA_OWNED) |
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| 275 | |
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| 276 | /* Lock for interrupts coalescing */ |
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| 277 | #define TSEC_IC_LOCK(sc) do { \ |
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| 278 | mtx_assert(&(sc)->ic_lock, MA_NOTOWNED); \ |
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| 279 | mtx_lock(&(sc)->ic_lock); \ |
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| 280 | } while (0) |
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| 281 | |
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| 282 | #define TSEC_IC_UNLOCK(sc) mtx_unlock(&(sc)->ic_lock) |
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| 283 | #define TSEC_IC_LOCK_ASSERT(sc) mtx_assert(&(sc)->ic_lock, MA_OWNED) |
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| 284 | |
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| 285 | /* Global tsec lock (with all locks) */ |
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| 286 | #define TSEC_GLOBAL_LOCK(sc) do { \ |
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| 287 | if ((mtx_owned(&(sc)->transmit_lock) ? 1 : 0) != \ |
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| 288 | (mtx_owned(&(sc)->receive_lock) ? 1 : 0)) { \ |
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| 289 | panic("tsec deadlock possibility detection!"); \ |
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| 290 | } \ |
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| 291 | mtx_lock(&(sc)->transmit_lock); \ |
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| 292 | mtx_lock(&(sc)->receive_lock); \ |
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| 293 | } while (0) |
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| 294 | |
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| 295 | #define TSEC_GLOBAL_UNLOCK(sc) do { \ |
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| 296 | TSEC_RECEIVE_UNLOCK(sc); \ |
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| 297 | TSEC_TRANSMIT_UNLOCK(sc); \ |
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| 298 | } while (0) |
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| 299 | |
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| 300 | #define TSEC_GLOBAL_LOCK_ASSERT(sc) do { \ |
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| 301 | TSEC_TRANSMIT_LOCK_ASSERT(sc); \ |
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| 302 | TSEC_RECEIVE_LOCK_ASSERT(sc); \ |
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| 303 | } while (0) |
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| 304 | |
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| 305 | /* From global to {transmit,receive} */ |
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| 306 | #define TSEC_GLOBAL_TO_TRANSMIT_LOCK(sc) do { \ |
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| 307 | mtx_unlock(&(sc)->receive_lock);\ |
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| 308 | } while (0) |
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| 309 | |
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| 310 | #define TSEC_GLOBAL_TO_RECEIVE_LOCK(sc) do { \ |
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| 311 | mtx_unlock(&(sc)->transmit_lock);\ |
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| 312 | } while (0) |
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| 313 | |
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| 314 | struct tsec_desc { |
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| 315 | volatile uint16_t flags; /* descriptor flags */ |
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| 316 | volatile uint16_t length; /* buffer length */ |
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| 317 | volatile uint32_t bufptr; /* buffer pointer */ |
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| 318 | }; |
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| 319 | |
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| 320 | #define TSEC_READ_RETRY 10000 |
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| 321 | #define TSEC_READ_DELAY 100 |
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| 322 | |
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| 323 | /* Structures and defines for TCP/IP Off-load */ |
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| 324 | struct tsec_tx_fcb { |
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| 325 | volatile uint16_t flags; |
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| 326 | volatile uint8_t l4_offset; |
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| 327 | volatile uint8_t l3_offset; |
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| 328 | volatile uint16_t ph_chsum; |
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| 329 | volatile uint16_t vlan; |
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| 330 | }; |
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| 331 | |
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| 332 | struct tsec_rx_fcb { |
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| 333 | volatile uint16_t flags; |
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| 334 | volatile uint8_t rq_index; |
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| 335 | volatile uint8_t protocol; |
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| 336 | volatile uint16_t unused; |
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| 337 | volatile uint16_t vlan; |
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| 338 | }; |
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| 339 | |
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| 340 | #define TSEC_CHECKSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) |
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| 341 | |
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| 342 | #define TSEC_TX_FCB_IP4 TSEC_TX_FCB_L3_IS_IP |
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| 343 | #define TSEC_TX_FCB_IP6 (TSEC_TX_FCB_L3_IS_IP | TSEC_TX_FCB_L3_IS_IP6) |
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| 344 | |
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| 345 | #define TSEC_TX_FCB_TCP TSEC_TX_FCB_L4_IS_TCP_UDP |
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| 346 | #define TSEC_TX_FCB_UDP (TSEC_TX_FCB_L4_IS_TCP_UDP | TSEC_TX_FCB_L4_IS_UDP) |
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| 347 | |
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| 348 | #define TSEC_RX_FCB_IP_CSUM_CHECKED(flags) \ |
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| 349 | ((flags & (TSEC_RX_FCB_IP_FOUND | TSEC_RX_FCB_IP6_FOUND | \ |
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| 350 | TSEC_RX_FCB_IP_CSUM | TSEC_RX_FCB_PARSE_ERROR)) \ |
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| 351 | == (TSEC_RX_FCB_IP_FOUND | TSEC_RX_FCB_IP_CSUM)) |
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| 352 | |
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| 353 | #define TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) \ |
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| 354 | ((flags & (TSEC_RX_FCB_TCP_UDP_FOUND | TSEC_RX_FCB_TCP_UDP_CSUM \ |
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| 355 | | TSEC_RX_FCB_PARSE_ERROR)) \ |
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| 356 | == (TSEC_RX_FCB_TCP_UDP_FOUND | TSEC_RX_FCB_TCP_UDP_CSUM)) |
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| 357 | |
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| 358 | /* Prototypes */ |
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| 359 | extern devclass_t tsec_devclass; |
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| 360 | |
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| 361 | int tsec_attach(struct tsec_softc *sc); |
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| 362 | int tsec_detach(struct tsec_softc *sc); |
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| 363 | |
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| 364 | void tsec_error_intr(void *arg); |
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| 365 | void tsec_receive_intr(void *arg); |
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| 366 | void tsec_transmit_intr(void *arg); |
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| 367 | |
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| 368 | int tsec_miibus_readreg(device_t dev, int phy, int reg); |
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| 369 | int tsec_miibus_writereg(device_t dev, int phy, int reg, int value); |
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| 370 | void tsec_miibus_statchg(device_t dev); |
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| 371 | int tsec_resume(device_t dev); /* XXX */ |
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| 372 | int tsec_shutdown(device_t dev); |
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| 373 | int tsec_suspend(device_t dev); /* XXX */ |
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| 374 | |
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| 375 | void tsec_get_hwaddr(struct tsec_softc *sc, uint8_t *addr); |
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| 376 | |
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| 377 | #endif /* _IF_TSEC_H */ |
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