source: rtems-libbsd/freebsd/sys/dev/rtwn/rtl8812a/r12a_init.c @ 0cbb715

55-freebsd-126-freebsd-12
Last change on this file since 0cbb715 was 0cbb715, checked in by Christian Mauderer <Christian.Mauderer@…>, on 11/22/16 at 09:41:47

rtwn: Import from FreeBSD.
  • Property mode set to 100644
File size: 12.6 KB
Line 
1#include <machine/rtems-bsd-kernel-space.h>
2
3/*-
4 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD$");
31
32#include <rtems/bsd/local/opt_wlan.h>
33
34#include <rtems/bsd/sys/param.h>
35#include <rtems/bsd/sys/lock.h>
36#include <sys/mutex.h>
37#include <sys/mbuf.h>
38#include <sys/kernel.h>
39#include <sys/socket.h>
40#include <sys/systm.h>
41#include <sys/malloc.h>
42#include <sys/queue.h>
43#include <sys/taskqueue.h>
44#include <sys/bus.h>
45#include <sys/endian.h>
46#include <sys/linker.h>
47
48#include <net/if.h>
49#include <net/ethernet.h>
50#include <net/if_media.h>
51
52#include <net80211/ieee80211_var.h>
53#include <net80211/ieee80211_radiotap.h>
54
55#include <dev/rtwn/if_rtwnreg.h>
56#include <dev/rtwn/if_rtwnvar.h>
57
58#include <dev/rtwn/if_rtwn_debug.h>
59
60#include <dev/rtwn/rtl8192c/r92c.h>
61
62#include <dev/rtwn/rtl8812a/r12a.h>
63#include <dev/rtwn/rtl8812a/r12a_priv.h>
64#include <dev/rtwn/rtl8812a/r12a_reg.h>
65#include <dev/rtwn/rtl8812a/r12a_var.h>
66
67
68int
69r12a_check_condition(struct rtwn_softc *sc, const uint8_t cond[])
70{
71        struct r12a_softc *rs = sc->sc_priv;
72        uint8_t mask[4];
73        int i, j, nmasks;
74
75        RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
76            "%s: condition byte 0: %02X; ext PA/LNA: %d/%d (2 GHz), "
77            "%d/%d (5 GHz)\n", __func__, cond[0], rs->ext_pa_2g,
78            rs->ext_lna_2g, rs->ext_pa_5g, rs->ext_lna_5g);
79
80        if (cond[0] == 0)
81                return (1);
82
83        if (!rs->ext_pa_2g && !rs->ext_lna_2g &&
84            !rs->ext_pa_5g && !rs->ext_lna_5g)
85                return (0);
86
87        nmasks = 0;
88        if (rs->ext_pa_2g) {
89                mask[nmasks] = R12A_COND_GPA;
90                mask[nmasks] |= R12A_COND_TYPE(rs->type_pa_2g);
91                nmasks++;
92        }
93        if (rs->ext_pa_5g) {
94                mask[nmasks] = R12A_COND_APA;
95                mask[nmasks] |= R12A_COND_TYPE(rs->type_pa_5g);
96                nmasks++;
97        }
98        if (rs->ext_lna_2g) {
99                mask[nmasks] = R12A_COND_GLNA;
100                mask[nmasks] |= R12A_COND_TYPE(rs->type_lna_2g);
101                nmasks++;
102        }
103        if (rs->ext_lna_5g) {
104                mask[nmasks] = R12A_COND_ALNA;
105                mask[nmasks] |= R12A_COND_TYPE(rs->type_lna_5g);
106                nmasks++;
107        }
108
109        for (i = 0; i < RTWN_MAX_CONDITIONS && cond[i] != 0; i++)
110                for (j = 0; j < nmasks; j++)
111                        if ((cond[i] & mask[j]) == mask[j])
112                                return (1);
113
114        return (0);
115}
116
117int
118r12a_set_page_size(struct rtwn_softc *sc)
119{
120        return (rtwn_setbits_1(sc, R92C_PBP, R92C_PBP_PSTX_M,
121            R92C_PBP_512 << R92C_PBP_PSTX_S) == 0);
122}
123
124void
125r12a_init_edca(struct rtwn_softc *sc)
126{
127        r92c_init_edca(sc);
128
129        /* 80 MHz clock */
130        rtwn_write_1(sc, R92C_USTIME_TSF, 0x50);
131        rtwn_write_1(sc, R92C_USTIME_EDCA, 0x50);
132}
133
134void
135r12a_init_bb(struct rtwn_softc *sc)
136{
137        int i, j;
138
139        rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, R92C_SYS_FUNC_EN_USBA);
140
141        /* Enable BB and RF. */
142        rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0,
143            R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST);
144
145        /* PathA RF Power On. */
146        rtwn_write_1(sc, R92C_RF_CTRL,
147            R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
148
149        /* PathB RF Power On. */
150        rtwn_write_1(sc, R12A_RF_B_CTRL,
151            R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
152
153        /* Write BB initialization values. */
154        for (i = 0; i < sc->bb_size; i++) {
155                const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i];
156
157                while (!rtwn_check_condition(sc, bb_prog->cond)) {
158                        KASSERT(bb_prog->next != NULL,
159                            ("%s: wrong condition value (i %d)\n",
160                            __func__, i));
161                        bb_prog = bb_prog->next;
162                }
163
164                for (j = 0; j < bb_prog->count; j++) {
165                        RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
166                            "BB: reg 0x%03x, val 0x%08x\n",
167                            bb_prog->reg[j], bb_prog->val[j]);
168
169                        rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]);
170                        rtwn_delay(sc, 1);
171                }
172        }
173
174        /* XXX meshpoint mode? */
175
176        /* Write AGC values. */
177        for (i = 0; i < sc->agc_size; i++) {
178                const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i];
179
180                while (!rtwn_check_condition(sc, agc_prog->cond)) {
181                        KASSERT(agc_prog->next != NULL,
182                            ("%s: wrong condition value (2) (i %d)\n",
183                            __func__, i));
184                        agc_prog = agc_prog->next;
185                }
186
187                for (j = 0; j < agc_prog->count; j++) {
188                        RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
189                            "AGC: val 0x%08x\n", agc_prog->val[j]);
190
191                        rtwn_bb_write(sc, 0x81c, agc_prog->val[j]);
192                        rtwn_delay(sc, 1);
193                }
194        }
195
196        for (i = 0; i < sc->nrxchains; i++) {
197                rtwn_bb_write(sc, R12A_INITIAL_GAIN(i), 0x22);
198                rtwn_delay(sc, 1);
199                rtwn_bb_write(sc, R12A_INITIAL_GAIN(i), 0x20);
200                rtwn_delay(sc, 1);
201        }
202
203        rtwn_r12a_crystalcap_write(sc);
204
205        if (rtwn_bb_read(sc, R12A_CCK_RPT_FORMAT) & R12A_CCK_RPT_FORMAT_HIPWR)
206                sc->sc_flags |= RTWN_FLAG_CCK_HIPWR;
207}
208
209void
210r12a_init_rf(struct rtwn_softc *sc)
211{
212        int chain, i;
213
214        for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) {
215                /* Write RF initialization values for this chain. */
216                i += r92c_init_rf_chain(sc, &sc->rf_prog[i], chain);
217        }
218}
219
220void
221r12a_crystalcap_write(struct rtwn_softc *sc)
222{
223        struct r12a_softc *rs = sc->sc_priv;
224        uint32_t reg;
225        uint8_t val;
226
227        val = rs->crystalcap & 0x3f;
228        reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL);
229        reg = RW(reg, R12A_MAC_PHY_CRYSTALCAP, val | (val << 6));
230        rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg);
231}
232
233static void
234r12a_rf_init_workaround(struct rtwn_softc *sc)
235{
236
237        rtwn_write_1(sc, R92C_RF_CTRL,
238            R92C_RF_CTRL_EN | R92C_RF_CTRL_SDMRSTB);
239        rtwn_write_1(sc, R92C_RF_CTRL,
240            R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB |
241            R92C_RF_CTRL_SDMRSTB);
242        rtwn_write_1(sc, R12A_RF_B_CTRL,
243            R92C_RF_CTRL_EN | R92C_RF_CTRL_SDMRSTB);
244        rtwn_write_1(sc, R12A_RF_B_CTRL,
245            R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB |
246            R92C_RF_CTRL_SDMRSTB);
247}
248
249int
250r12a_power_on(struct rtwn_softc *sc)
251{
252#define RTWN_CHK(res) do {      \
253        if (res != 0)           \
254                return (EIO);   \
255} while(0)
256        int ntries;
257
258        r12a_rf_init_workaround(sc);
259
260        /* Force PWM mode. */
261        RTWN_CHK(rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0, 0x01));
262
263        /* Turn off ZCD. */
264        RTWN_CHK(rtwn_setbits_2(sc, 0x014, 0x0180, 0));
265
266        /* Enable LDO normal mode. */
267        RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP,
268            0));
269
270        /* GPIO 0...7 input mode. */
271        RTWN_CHK(rtwn_write_1(sc, R92C_GPIO_IOSEL, 0));
272
273        /* GPIO 11...8 input mode. */
274        RTWN_CHK(rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0));
275
276        /* Enable WL suspend. */
277        RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
278            R92C_APS_FSMCO_AFSM_HSUS, 0, 1));
279
280        /* Enable 8051. */
281        RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
282            0, R92C_SYS_FUNC_EN_CPUEN, 1));
283
284        /* Disable SW LPS. */
285        RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
286            R92C_APS_FSMCO_APFM_RSM, 0, 1));
287
288        /* Wait for power ready bit. */
289        for (ntries = 0; ntries < 5000; ntries++) {
290                if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
291                        break;
292                rtwn_delay(sc, 10);
293        }
294        if (ntries == 5000) {
295                device_printf(sc->sc_dev,
296                    "timeout waiting for chip power up\n");
297                return (ETIMEDOUT);
298        }
299
300        /* Disable WL suspend. */
301        RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
302            R92C_APS_FSMCO_AFSM_HSUS, 0, 1));
303
304        RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
305            R92C_APS_FSMCO_APFM_ONMAC, 1));
306        for (ntries = 0; ntries < 5000; ntries++) {
307                if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
308                    R92C_APS_FSMCO_APFM_ONMAC))
309                        break;
310                rtwn_delay(sc, 10);
311        }
312        if (ntries == 5000)
313                return (ETIMEDOUT);
314
315        /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
316        RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000));
317        RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
318            R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
319            R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
320            R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
321            ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
322            R92C_CR_CALTMR_EN));
323
324        return (0);
325}
326
327void
328r12a_power_off(struct rtwn_softc *sc)
329{
330        struct r12a_softc *rs = sc->sc_priv;
331        int error, ntries;
332
333        /* Stop Rx. */
334        error = rtwn_write_1(sc, R92C_CR, 0);
335        if (error == ENXIO)     /* hardware gone */
336                return;
337
338        /* Move card to Low Power state. */
339        /* Block all Tx queues. */
340        rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
341
342        for (ntries = 0; ntries < 10; ntries++) {
343                /* Should be zero if no packet is transmitting. */
344                if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
345                        break;
346
347                rtwn_delay(sc, 5000);
348        }
349        if (ntries == 10) {
350                device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
351                    __func__);
352                return;
353        }
354
355        /* Turn off 3-wire. */
356        rtwn_write_1(sc, R12A_HSSI_PARAM1(0), 0x04);
357        rtwn_write_1(sc, R12A_HSSI_PARAM1(1), 0x04);
358
359        /* CCK and OFDM are disabled, and clock are gated. */
360        rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
361
362        rtwn_delay(sc, 1);
363
364        /* Reset whole BB. */
365        rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
366
367        /* Reset MAC TRX. */
368        rtwn_write_1(sc, R92C_CR,
369            R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN);
370
371        /* check if removed later. (?) */
372        rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
373
374        /* Respond TxOK to scheduler */
375        rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK);
376
377        /* If firmware in ram code, do reset. */
378#ifndef RTWN_WITHOUT_UCODE
379        if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
380                r12a_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
381#endif
382
383        /* Reset MCU. */
384        rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN,
385            0, 1);
386        rtwn_write_1(sc, R92C_MCUFWDL, 0);
387
388        /* Move card to Disabled state. */
389        /* Turn off 3-wire. */
390        rtwn_write_1(sc, R12A_HSSI_PARAM1(0), 0x04);
391        rtwn_write_1(sc, R12A_HSSI_PARAM1(1), 0x04);
392
393        /* Reset BB, close RF. */
394        rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
395
396        rtwn_delay(sc, 1);
397
398        /* SPS PWM mode. */
399        rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
400            R92C_APS_FSMCO_SOP_RCK | R92C_APS_FSMCO_SOP_ABG, 3);
401
402        /* ANA clock = 500k. */
403        rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0);
404
405        /* Turn off MAC by HW state machine */
406        rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
407            1);
408        for (ntries = 0; ntries < 10; ntries++) {
409                /* Wait until it will be disabled. */
410                if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
411                    R92C_APS_FSMCO_APFM_OFF) == 0)
412                        break;
413
414                rtwn_delay(sc, 5000);
415        }
416        if (ntries == 10) {
417                device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
418                    __func__);
419                return;
420        }
421
422        /* Reset 8051. */
423        rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN,
424            0, 1);
425
426        /* Fill the default value of host_CPU handshake field. */
427        rtwn_write_1(sc, R92C_MCUFWDL,
428            R92C_MCUFWDL_EN | R92C_MCUFWDL_CHKSUM_RPT);
429
430        rtwn_setbits_1(sc, R92C_GPIO_IO_SEL, 0xf0, 0xc0);
431
432        /* GPIO 11 input mode, 10...8 output mode. */
433        rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x07);
434
435        /* GPIO 7...0, output = input */
436        rtwn_write_1(sc, R92C_GPIO_OUT, 0);
437
438        /* GPIO 7...0 output mode. */
439        rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
440
441        rtwn_write_1(sc, R92C_GPIO_MOD, 0);
442
443        /* Turn on ZCD. */
444        rtwn_setbits_2(sc, 0x014, 0, 0x0180);
445
446        /* Force PFM mode. */
447        rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0x01, 0);
448
449        /* LDO sleep mode. */
450        rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
451
452        /* ANA clock = 500k. */
453        rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0);
454
455        /* SOP option to disable BG/MB. */
456        rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
457            R92C_APS_FSMCO_SOP_RCK, 3);
458
459        /* Disable RFC_0. */
460        rtwn_setbits_1(sc, R92C_RF_CTRL, R92C_RF_CTRL_RSTB, 0);
461
462        /* Disable RFC_1. */
463        rtwn_setbits_1(sc, R12A_RF_B_CTRL, R92C_RF_CTRL_RSTB, 0);
464
465        /* Enable WL suspend. */
466        rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_AFSM_HSUS,
467            1);
468
469        rs->rs_flags &= ~R12A_IQK_RUNNING;
470}
471
472void
473r12a_init_intr(struct rtwn_softc *sc)
474{
475        rtwn_write_4(sc, R88E_HIMR, 0);
476        rtwn_write_4(sc, R88E_HIMRE, 0);
477}
478
479void
480r12a_init_antsel(struct rtwn_softc *sc)
481{
482        uint32_t reg;
483
484        rtwn_write_1(sc, R92C_LEDCFG2, 0x82);
485        rtwn_bb_setbits(sc, R92C_FPGA0_RFPARAM(0), 0, 0x2000);
486        reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));
487        sc->sc_ant = MS(reg, R92C_FPGA0_RFIFACEOE0_ANT);
488}
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