1 | /* $OpenBSD: if_rtwnreg.h,v 1.3 2015/06/14 08:02:47 stsp Exp $ */ |
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2 | |
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3 | /*- |
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4 | * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> |
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5 | * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> |
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6 | * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> |
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7 | * |
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8 | * Permission to use, copy, modify, and distribute this software for any |
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9 | * purpose with or without fee is hereby granted, provided that the above |
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10 | * copyright notice and this permission notice appear in all copies. |
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11 | * |
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12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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19 | * |
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20 | * $FreeBSD$ |
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21 | */ |
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22 | |
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23 | #ifndef R92CE_REG_H |
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24 | #define R92CE_REG_H |
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25 | |
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26 | #include <dev/rtwn/rtl8192c/r92c_reg.h> |
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27 | |
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28 | /* |
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29 | * MAC registers. |
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30 | */ |
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31 | /* System Configuration. */ |
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32 | #define R92C_PCIE_MIO_INTF 0x0e4 |
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33 | #define R92C_PCIE_MIO_INTD 0x0e8 |
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34 | /* PCIe Configuration. */ |
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35 | #define R92C_PCIE_CTRL_REG 0x300 |
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36 | #define R92C_INT_MIG 0x304 |
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37 | #define R92C_BCNQ_DESA 0x308 |
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38 | #define R92C_HQ_DESA 0x310 |
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39 | #define R92C_MGQ_DESA 0x318 |
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40 | #define R92C_VOQ_DESA 0x320 |
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41 | #define R92C_VIQ_DESA 0x328 |
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42 | #define R92C_BEQ_DESA 0x330 |
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43 | #define R92C_BKQ_DESA 0x338 |
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44 | #define R92C_RX_DESA 0x340 |
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45 | #define R92C_DBI 0x348 |
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46 | #define R92C_MDIO 0x354 |
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47 | #define R92C_DBG_SEL 0x360 |
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48 | #define R92C_PCIE_HRPWM 0x361 |
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49 | #define R92C_PCIE_HCPWM 0x363 |
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50 | #define R92C_UART_CTRL 0x364 |
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51 | #define R92C_UART_TX_DES 0x370 |
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52 | #define R92C_UART_RX_DES 0x378 |
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53 | |
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54 | |
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55 | /* Bits for R92C_GPIO_MUXCFG. */ |
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56 | #define R92C_GPIO_MUXCFG_RFKILL 0x0008 |
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57 | |
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58 | /* Bits for R92C_GPIO_IO_SEL. */ |
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59 | #define R92C_GPIO_IO_SEL_RFKILL 0x0008 |
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60 | |
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61 | /* Bits for R92C_LEDCFG2. */ |
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62 | #define R92C_LEDCFG2_EN 0x60 |
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63 | #define R92C_LEDCFG2_DIS 0x68 |
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64 | |
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65 | /* Bits for R92C_HIMR. */ |
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66 | #define R92C_IMR_ROK 0x00000001 /* receive DMA OK */ |
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67 | #define R92C_IMR_VODOK 0x00000002 /* AC_VO DMA OK */ |
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68 | #define R92C_IMR_VIDOK 0x00000004 /* AC_VI DMA OK */ |
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69 | #define R92C_IMR_BEDOK 0x00000008 /* AC_BE DMA OK */ |
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70 | #define R92C_IMR_BKDOK 0x00000010 /* AC_BK DMA OK */ |
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71 | #define R92C_IMR_TXBDER 0x00000020 /* beacon transmit error */ |
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72 | #define R92C_IMR_MGNTDOK 0x00000040 /* management queue DMA OK */ |
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73 | #define R92C_IMR_TBDOK 0x00000080 /* beacon transmit OK */ |
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74 | #define R92C_IMR_HIGHDOK 0x00000100 /* high queue DMA OK */ |
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75 | #define R92C_IMR_BDOK 0x00000200 /* beacon queue DMA OK */ |
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76 | #define R92C_IMR_ATIMEND 0x00000400 /* ATIM window end interrupt */ |
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77 | #define R92C_IMR_RDU 0x00000800 /* Rx descriptor unavailable */ |
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78 | #define R92C_IMR_RXFOVW 0x00001000 /* receive FIFO overflow */ |
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79 | #define R92C_IMR_BCNINT 0x00002000 /* beacon DMA interrupt 0 */ |
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80 | #define R92C_IMR_PSTIMEOUT 0x00004000 /* powersave timeout */ |
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81 | #define R92C_IMR_TXFOVW 0x00008000 /* transmit FIFO overflow */ |
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82 | #define R92C_IMR_TIMEOUT1 0x00010000 /* timeout interrupt 1 */ |
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83 | #define R92C_IMR_TIMEOUT2 0x00020000 /* timeout interrupt 2 */ |
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84 | #define R92C_IMR_BCNDOK1 0x00040000 /* beacon queue DMA OK (1) */ |
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85 | #define R92C_IMR_BCNDOK2 0x00080000 /* beacon queue DMA OK (2) */ |
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86 | #define R92C_IMR_BCNDOK3 0x00100000 /* beacon queue DMA OK (3) */ |
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87 | #define R92C_IMR_BCNDOK4 0x00200000 /* beacon queue DMA OK (4) */ |
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88 | #define R92C_IMR_BCNDOK5 0x00400000 /* beacon queue DMA OK (5) */ |
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89 | #define R92C_IMR_BCNDOK6 0x00800000 /* beacon queue DMA OK (6) */ |
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90 | #define R92C_IMR_BCNDOK7 0x01000000 /* beacon queue DMA OK (7) */ |
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91 | #define R92C_IMR_BCNDOK8 0x02000000 /* beacon queue DMA OK (8) */ |
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92 | #define R92C_IMR_BCNDMAINT1 0x04000000 /* beacon DMA interrupt 1 */ |
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93 | #define R92C_IMR_BCNDMAINT2 0x08000000 /* beacon DMA interrupt 2 */ |
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94 | #define R92C_IMR_BCNDMAINT3 0x10000000 /* beacon DMA interrupt 3 */ |
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95 | #define R92C_IMR_BCNDMAINT4 0x20000000 /* beacon DMA interrupt 4 */ |
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96 | #define R92C_IMR_BCNDMAINT5 0x40000000 /* beacon DMA interrupt 5 */ |
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97 | #define R92C_IMR_BCNDMAINT6 0x80000000 /* beacon DMA interrupt 6 */ |
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98 | |
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99 | /* Shortcut. */ |
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100 | #define R92C_IBSS_INT_MASK \ |
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101 | (R92C_IMR_BCNINT | R92C_IMR_TBDOK | R92C_IMR_TBDER) |
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102 | |
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103 | #endif /* R92CE_REG_H */ |
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