source: rtems-libbsd/freebsd/sys/dev/mmc/mmcreg.h @ de8a76d

5-freebsd-12
Last change on this file since de8a76d was de8a76d, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 4, 2017 at 7:36:57 AM

Update to FreeBSD head 2017-04-04

Git mirror commit 642b174daddbd0efd9bb5f242c43f4ab4db6869f.

  • Property mode set to 100644
File size: 18.8 KB
Line 
1/*-
2 * Copyright (c) 2006 M. Warner Losh.  All rights reserved.
3 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * Portions of this software may have been developed with reference to
26 * the SD Simplified Specification.  The following disclaimer may apply:
27 *
28 * The following conditions apply to the release of the simplified
29 * specification ("Simplified Specification") by the SD Card Association and
30 * the SD Group. The Simplified Specification is a subset of the complete SD
31 * Specification which is owned by the SD Card Association and the SD
32 * Group. This Simplified Specification is provided on a non-confidential
33 * basis subject to the disclaimers below. Any implementation of the
34 * Simplified Specification may require a license from the SD Card
35 * Association, SD Group, SD-3C LLC or other third parties.
36 *
37 * Disclaimers:
38 *
39 * The information contained in the Simplified Specification is presented only
40 * as a standard specification for SD Cards and SD Host/Ancillary products and
41 * is provided "AS-IS" without any representations or warranties of any
42 * kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD
43 * Card Association for any damages, any infringements of patents or other
44 * right of the SD Group, SD-3C LLC, the SD Card Association or any third
45 * parties, which may result from its use. No license is granted by
46 * implication, estoppel or otherwise under any patent or other rights of the
47 * SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing
48 * herein shall be construed as an obligation by the SD Group, the SD-3C LLC
49 * or the SD Card Association to disclose or distribute any technical
50 * information, know-how or other confidential information to any third party.
51 *
52 * $FreeBSD$
53 */
54
55#ifndef DEV_MMC_MMCREG_H
56#define DEV_MMC_MMCREG_H
57
58/*
59 * This file contains the register definitions for the mmc and sd buses.
60 * They are taken from publicly available sources.
61 */
62
63struct mmc_data;
64struct mmc_request;
65
66struct mmc_command {
67        uint32_t        opcode;
68        uint32_t        arg;
69        uint32_t        resp[4];
70        uint32_t        flags;          /* Expected responses */
71#define MMC_RSP_PRESENT (1ul << 0)      /* Response */
72#define MMC_RSP_136     (1ul << 1)      /* 136 bit response */
73#define MMC_RSP_CRC     (1ul << 2)      /* Expect valid crc */
74#define MMC_RSP_BUSY    (1ul << 3)      /* Card may send busy */
75#define MMC_RSP_OPCODE  (1ul << 4)      /* Response include opcode */
76#define MMC_RSP_MASK    0x1ful
77#define MMC_CMD_AC      (0ul << 5)      /* Addressed Command, no data */
78#define MMC_CMD_ADTC    (1ul << 5)      /* Addressed Data transfer cmd */
79#define MMC_CMD_BC      (2ul << 5)      /* Broadcast command, no response */
80#define MMC_CMD_BCR     (3ul << 5)      /* Broadcast command with response */
81#define MMC_CMD_MASK    (3ul << 5)
82
83/* Possible response types defined in the standard: */
84#define MMC_RSP_NONE    (0)
85#define MMC_RSP_R1      (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
86#define MMC_RSP_R1B     (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
87#define MMC_RSP_R2      (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
88#define MMC_RSP_R3      (MMC_RSP_PRESENT)
89#define MMC_RSP_R4      (MMC_RSP_PRESENT)
90#define MMC_RSP_R5      (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
91#define MMC_RSP_R5B     (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
92#define MMC_RSP_R6      (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
93#define MMC_RSP_R7      (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
94#define MMC_RSP(x)      ((x) & MMC_RSP_MASK)
95        uint32_t        retries;
96        uint32_t        error;
97#define MMC_ERR_NONE    0
98#define MMC_ERR_TIMEOUT 1
99#define MMC_ERR_BADCRC  2
100#define MMC_ERR_FIFO    3
101#define MMC_ERR_FAILED  4
102#define MMC_ERR_INVALID 5
103#define MMC_ERR_NO_MEMORY 6
104#define MMC_ERR_MAX     6
105        struct mmc_data *data;          /* Data segment with cmd */
106        struct mmc_request *mrq;        /* backpointer to request */
107};
108
109/*
110 * R1 responses
111 *
112 * Types (per SD 2.0 standard)
113 *      e : error bit
114 *      s : status bit
115 *      r : detected and set for the actual command response
116 *      x : Detected and set during command execution.  The host can get
117 *          the status by issuing a command with R1 response.
118 *
119 * Clear Condition (per SD 2.0 standard)
120 *      a : according to the card current state.
121 *      b : always related to the previous command.  reception of a valid
122 *          command will clear it (with a delay of one command).
123 *      c : clear by read
124 */
125#define R1_OUT_OF_RANGE (1u << 31)              /* erx, c */
126#define R1_ADDRESS_ERROR (1u << 30)             /* erx, c */
127#define R1_BLOCK_LEN_ERROR (1u << 29)           /* erx, c */
128#define R1_ERASE_SEQ_ERROR (1u << 28)           /* er, c */
129#define R1_ERASE_PARAM (1u << 27)               /* erx, c */
130#define R1_WP_VIOLATION (1u << 26)              /* erx, c */
131#define R1_CARD_IS_LOCKED (1u << 25)            /* sx, a */
132#define R1_LOCK_UNLOCK_FAILED (1u << 24)        /* erx, c */
133#define R1_COM_CRC_ERROR (1u << 23)             /* er, b */
134#define R1_ILLEGAL_COMMAND (1u << 22)           /* er, b */
135#define R1_CARD_ECC_FAILED (1u << 21)           /* erx, c */
136#define R1_CC_ERROR (1u << 20)                  /* erx, c */
137#define R1_ERROR (1u << 19)                     /* erx, c */
138#define R1_CSD_OVERWRITE (1u << 16)             /* erx, c */
139#define R1_WP_ERASE_SKIP (1u << 15)             /* erx, c */
140#define R1_CARD_ECC_DISABLED (1u << 14)         /* sx, a */
141#define R1_ERASE_RESET (1u << 13)               /* sr, c */
142#define R1_CURRENT_STATE_MASK (0xfu << 9)       /* sx, b */
143#define R1_READY_FOR_DATA (1u << 8)             /* sx, a */
144#define R1_SWITCH_ERROR (1u << 7)               /* sx, c */
145#define R1_APP_CMD (1u << 5)                    /* sr, c */
146#define R1_AKE_SEQ_ERROR (1u << 3)              /* er, c */
147#define R1_STATUS(x)            ((x) & 0xFFFFE000)
148#define R1_CURRENT_STATE(x)     (((x) & R1_CURRENT_STATE_MASK) >> 9)
149#define R1_STATE_IDLE   0
150#define R1_STATE_READY  1
151#define R1_STATE_IDENT  2
152#define R1_STATE_STBY   3
153#define R1_STATE_TRAN   4
154#define R1_STATE_DATA   5
155#define R1_STATE_RCV    6
156#define R1_STATE_PRG    7
157#define R1_STATE_DIS    8
158
159struct mmc_data {
160        size_t len;             /* size of the data */
161        size_t xfer_len;
162        void *data;             /* data buffer */
163        uint32_t        flags;
164#define MMC_DATA_WRITE  (1UL << 0)
165#define MMC_DATA_READ   (1UL << 1)
166#define MMC_DATA_STREAM (1UL << 2)
167#define MMC_DATA_MULTI  (1UL << 3)
168        struct mmc_request *mrq;
169};
170
171struct mmc_request {
172        struct mmc_command *cmd;
173        struct mmc_command *stop;
174        void (*done)(struct mmc_request *); /* Completion function */
175        void *done_data;                /* requestor set data */
176        uint32_t flags;
177#define MMC_REQ_DONE    1
178};
179
180/* Command definitions */
181
182/* Class 0 and 1: Basic commands & read stream commands */
183#define MMC_GO_IDLE_STATE       0
184#define MMC_SEND_OP_COND        1
185#define MMC_ALL_SEND_CID        2
186#define MMC_SET_RELATIVE_ADDR   3
187#define SD_SEND_RELATIVE_ADDR   3
188#define MMC_SET_DSR             4
189#define MMC_SLEEP_AWAKE         5
190#define MMC_SWITCH_FUNC         6
191#define  MMC_SWITCH_FUNC_CMDS    0
192#define  MMC_SWITCH_FUNC_SET     1
193#define  MMC_SWITCH_FUNC_CLR     2
194#define  MMC_SWITCH_FUNC_WR      3
195#define MMC_SELECT_CARD         7
196#define MMC_DESELECT_CARD       7
197#define MMC_SEND_EXT_CSD        8
198#define SD_SEND_IF_COND         8
199#define MMC_SEND_CSD            9
200#define MMC_SEND_CID            10
201#define MMC_READ_DAT_UNTIL_STOP 11
202#define MMC_STOP_TRANSMISSION   12
203#define MMC_SEND_STATUS         13
204#define MMC_BUSTEST_R           14
205#define MMC_GO_INACTIVE_STATE   15
206#define MMC_BUSTEST_W           19
207
208/* Class 2: Block oriented read commands */
209#define MMC_SET_BLOCKLEN        16
210#define MMC_READ_SINGLE_BLOCK   17
211#define MMC_READ_MULTIPLE_BLOCK 18
212#define MMC_SEND_TUNING_BLOCK   19
213#define MMC_SEND_TUNING_BLOCK_HS200 21
214
215/* Class 3: Stream write commands */
216#define MMC_WRITE_DAT_UNTIL_STOP 20
217                        /* reserved: 22 */
218
219/* Class 4: Block oriented write commands */
220#define MMC_SET_BLOCK_COUNT     23
221#define MMC_WRITE_BLOCK         24
222#define MMC_WRITE_MULTIPLE_BLOCK 25
223#define MMC_PROGARM_CID         26
224#define MMC_PROGRAM_CSD         27
225
226/* Class 6: Block oriented write protection commands */
227#define MMC_SET_WRITE_PROT      28
228#define MMC_CLR_WRITE_PROT      29
229#define MMC_SEND_WRITE_PROT     30
230                        /* reserved: 31 */
231
232/* Class 5: Erase commands */
233#define SD_ERASE_WR_BLK_START   32
234#define SD_ERASE_WR_BLK_END     33
235                        /* 34 -- reserved old command */
236#define MMC_ERASE_GROUP_START   35
237#define MMC_ERASE_GROUP_END     36
238                        /* 37 -- reserved old command */
239#define MMC_ERASE               38
240
241/* Class 9: I/O mode commands */
242#define MMC_FAST_IO             39
243#define MMC_GO_IRQ_STATE        40
244                        /* reserved: 41 */
245
246/* Class 7: Lock card */
247#define MMC_LOCK_UNLOCK         42
248                        /* reserved: 43 */
249                        /* reserved: 44 */
250                        /* reserved: 45 */
251                        /* reserved: 46 */
252                        /* reserved: 47 */
253                        /* reserved: 48 */
254                        /* reserved: 49 */
255                        /* reserved: 50 */
256                        /* reserved: 51 */
257                        /* reserved: 54 */
258
259/* Class 8: Application specific commands */
260#define MMC_APP_CMD             55
261#define MMC_GEN_CMD             56
262                        /* reserved: 57 */
263                        /* reserved: 58 */
264                        /* reserved: 59 */
265                        /* reserved for mfg: 60 */
266                        /* reserved for mfg: 61 */
267                        /* reserved for mfg: 62 */
268                        /* reserved for mfg: 63 */
269
270/* Class 9: I/O cards (sd) */
271#define SD_IO_RW_DIRECT         52
272#define SD_IO_RW_EXTENDED       53
273
274/* Class 10: Switch function commands */
275#define SD_SWITCH_FUNC          6
276                        /* reserved: 34 */
277                        /* reserved: 35 */
278                        /* reserved: 36 */
279                        /* reserved: 37 */
280                        /* reserved: 50 */
281                        /* reserved: 57 */
282
283/* Application specific commands for SD */
284#define ACMD_SET_BUS_WIDTH      6
285#define ACMD_SD_STATUS          13
286#define ACMD_SEND_NUM_WR_BLOCKS 22
287#define ACMD_SET_WR_BLK_ERASE_COUNT 23
288#define ACMD_SD_SEND_OP_COND    41
289#define ACMD_SET_CLR_CARD_DETECT 42
290#define ACMD_SEND_SCR           51
291
292/*
293 * EXT_CSD fields
294 */
295#define EXT_CSD_EXT_PART_ATTR   52      /* R/W, 2 bytes */
296#define EXT_CSD_ENH_START_ADDR  136     /* R/W, 4 bytes */
297#define EXT_CSD_ENH_SIZE_MULT   140     /* R/W, 3 bytes */
298#define EXT_CSD_GP_SIZE_MULT    143     /* R/W, 12 bytes */
299#define EXT_CSD_PART_SET        155     /* R/W */
300#define EXT_CSD_PART_ATTR       156     /* R/W */
301#define EXT_CSD_PART_SUPPORT    160     /* RO */
302#define EXT_CSD_RPMB_MULT       168     /* RO */
303#define EXT_CSD_BOOT_WP_STATUS  174     /* RO */
304#define EXT_CSD_ERASE_GRP_DEF   175     /* R/W */
305#define EXT_CSD_PART_CONFIG     179     /* R/W */
306#define EXT_CSD_BUS_WIDTH       183     /* R/W */
307#define EXT_CSD_STROBE_SUPPORT  184     /* RO */
308#define EXT_CSD_HS_TIMING       185     /* R/W */
309#define EXT_CSD_POWER_CLASS     187     /* R/W */
310#define EXT_CSD_CARD_TYPE       196     /* RO */
311#define EXT_CSD_DRIVER_STRENGTH 197     /* RO */
312#define EXT_CSD_REV             192     /* RO */
313#define EXT_CSD_PART_SWITCH_TO  199     /* RO */
314#define EXT_CSD_PWR_CL_52_195   200     /* RO */
315#define EXT_CSD_PWR_CL_26_195   201     /* RO */
316#define EXT_CSD_PWR_CL_52_360   202     /* RO */
317#define EXT_CSD_PWR_CL_26_360   203     /* RO */
318#define EXT_CSD_SEC_CNT         212     /* RO, 4 bytes */
319#define EXT_CSD_HC_WP_GRP_SIZE  221     /* RO */
320#define EXT_CSD_ERASE_TO_MULT   223     /* RO */
321#define EXT_CSD_ERASE_GRP_SIZE  224     /* RO */
322#define EXT_CSD_BOOT_SIZE_MULT  226     /* RO */
323#define EXT_CSD_PWR_CL_200_195  236     /* RO */
324#define EXT_CSD_PWR_CL_200_360  237     /* RO */
325#define EXT_CSD_PWR_CL_52_195_DDR 238   /* RO */
326#define EXT_CSD_PWR_CL_52_360_DDR 239   /* RO */
327#define EXT_CSD_GEN_CMD6_TIME   248     /* RO */
328#define EXT_CSD_PWR_CL_200_360_DDR 253  /* RO */
329
330/*
331 * EXT_CSD field definitions
332 */
333#define EXT_CSD_EXT_PART_ATTR_DEFAULT           0x0
334#define EXT_CSD_EXT_PART_ATTR_SYSTEMCODE        0x1
335#define EXT_CSD_EXT_PART_ATTR_NPERSISTENT       0x2
336
337#define EXT_CSD_PART_SET_COMPLETED              0x01
338
339#define EXT_CSD_PART_ATTR_ENH_USR               0x01
340#define EXT_CSD_PART_ATTR_ENH_GP0               0x02
341#define EXT_CSD_PART_ATTR_ENH_GP1               0x04
342#define EXT_CSD_PART_ATTR_ENH_GP2               0x08
343#define EXT_CSD_PART_ATTR_ENH_GP3               0x10
344#define EXT_CSD_PART_ATTR_ENH_MASK              0x1f
345
346#define EXT_CSD_PART_SUPPORT_EN                 0x01
347#define EXT_CSD_PART_SUPPORT_ENH_ATTR_EN        0x02
348#define EXT_CSD_PART_SUPPORT_EXT_ATTR_EN        0x04
349
350#define EXT_CSD_BOOT_WP_STATUS_BOOT0_PWR        0x01
351#define EXT_CSD_BOOT_WP_STATUS_BOOT0_PERM       0x02
352#define EXT_CSD_BOOT_WP_STATUS_BOOT0_MASK       0x03
353#define EXT_CSD_BOOT_WP_STATUS_BOOT1_PWR        0x04
354#define EXT_CSD_BOOT_WP_STATUS_BOOT1_PERM       0x08
355#define EXT_CSD_BOOT_WP_STATUS_BOOT1_MASK       0x0c
356
357#define EXT_CSD_ERASE_GRP_DEF_EN        0x01
358
359#define EXT_CSD_PART_CONFIG_ACC_DEFAULT 0x00
360#define EXT_CSD_PART_CONFIG_ACC_BOOT0   0x01
361#define EXT_CSD_PART_CONFIG_ACC_BOOT1   0x02
362#define EXT_CSD_PART_CONFIG_ACC_RPMB    0x03
363#define EXT_CSD_PART_CONFIG_ACC_GP0     0x04
364#define EXT_CSD_PART_CONFIG_ACC_GP1     0x05
365#define EXT_CSD_PART_CONFIG_ACC_GP2     0x06
366#define EXT_CSD_PART_CONFIG_ACC_GP3     0x07
367#define EXT_CSD_PART_CONFIG_ACC_MASK    0x07
368#define EXT_CSD_PART_CONFIG_BOOT0       0x08
369#define EXT_CSD_PART_CONFIG_BOOT1       0x10
370#define EXT_CSD_PART_CONFIG_BOOT_USR    0x38
371#define EXT_CSD_PART_CONFIG_BOOT_MASK   0x38
372#define EXT_CSD_PART_CONFIG_BOOT_ACK    0x40
373
374#define EXT_CSD_CMD_SET_NORMAL          1
375#define EXT_CSD_CMD_SET_SECURE          2
376#define EXT_CSD_CMD_SET_CPSECURE        4
377
378#define EXT_CSD_HS_TIMING_BC            0
379#define EXT_CSD_HS_TIMING_HS            1
380#define EXT_CSD_HS_TIMING_DDR200        2
381#define EXT_CSD_HS_TIMING_DDR400        3
382#define EXT_CSD_HS_TIMING_DRV_STR_SHIFT 4
383
384#define EXT_CSD_POWER_CLASS_8BIT_MASK   0xf0
385#define EXT_CSD_POWER_CLASS_8BIT_SHIFT  4
386#define EXT_CSD_POWER_CLASS_4BIT_MASK   0x0f
387#define EXT_CSD_POWER_CLASS_4BIT_SHIFT  0
388
389#define EXT_CSD_CARD_TYPE_HS_26         0x0001
390#define EXT_CSD_CARD_TYPE_HS_52         0x0002
391#define EXT_CSD_CARD_TYPE_DDR_52_1_8V   0x0004
392#define EXT_CSD_CARD_TYPE_DDR_52_1_2V   0x0008
393#define EXT_CSD_CARD_TYPE_HS200_1_8V    0x0010
394#define EXT_CSD_CARD_TYPE_HS200_1_2V    0x0020
395#define EXT_CSD_CARD_TYPE_HS400_1_8V    0x0040
396#define EXT_CSD_CARD_TYPE_HS400_1_2V    0x0080
397#define EXT_CSD_CARD_TYPE_HS400ES       0x0100
398
399#define EXT_CSD_BUS_WIDTH_1     0
400#define EXT_CSD_BUS_WIDTH_4     1
401#define EXT_CSD_BUS_WIDTH_8     2
402#define EXT_CSD_BUS_WIDTH_4_DDR 5
403#define EXT_CSD_BUS_WIDTH_8_DDR 6
404#define EXT_CSD_BUS_WIDTH_ES    0x80
405
406#define MMC_TYPE_HS_26_MAX              26000000
407#define MMC_TYPE_HS_52_MAX              52000000
408#define MMC_TYPE_DDR52_MAX              52000000
409#define MMC_TYPE_HS200_HS400ES_MAX      200000000
410
411/*
412 * SD bus widths
413 */
414#define SD_BUS_WIDTH_1          0
415#define SD_BUS_WIDTH_4          2
416
417/*
418 * SD Switch
419 */
420#define SD_SWITCH_MODE_CHECK    0
421#define SD_SWITCH_MODE_SET      1
422#define SD_SWITCH_GROUP1        0
423#define SD_SWITCH_NORMAL_MODE   0
424#define SD_SWITCH_HS_MODE       1
425#define SD_SWITCH_SDR50_MODE    2
426#define SD_SWITCH_SDR104_MODE   3
427#define SD_SWITCH_DDR50         4
428#define SD_SWITCH_NOCHANGE      0xF
429
430#define SD_CLR_CARD_DETECT      0
431#define SD_SET_CARD_DETECT      1
432
433#define SD_HS_MAX               50000000
434#define SD_DDR50_MAX            50000000
435#define SD_SDR12_MAX            25000000
436#define SD_SDR25_MAX            50000000
437#define SD_SDR50_MAX            100000000
438#define SD_SDR104_MAX           208000000
439
440/* Specifications require 400 kHz max. during ID phase. */
441#define SD_MMC_CARD_ID_FREQUENCY        400000
442
443/* OCR bits */
444
445/*
446 * in SD 2.0 spec, bits 8-14 are now marked reserved
447 * Low voltage in SD2.0 spec is bit 7, TBD voltage
448 * Low voltage in MC 3.31 spec is bit 7, 1.65-1.95V
449 * Specs prior to  MMC 3.31 defined bits 0-7 as voltages down to 1.5V.
450 * 3.31 redefined them to be reserved and also said that cards had to
451 * support the 2.7-3.6V and fixed the OCR to be 0xfff8000 for high voltage
452 * cards.  MMC 4.0 says that a dual voltage card responds with 0xfff8080.
453 * Looks like the fine-grained control of the voltage tolerance ranges
454 * was abandoned.
455 *
456 * The MMC_OCR_CCS appears to be valid for only SD cards.
457 */
458#define MMC_OCR_VOLTAGE 0x3fffffffU     /* Vdd Voltage mask */
459#define MMC_OCR_LOW_VOLTAGE (1u << 7)   /* Low Voltage Range -- tbd */
460#define MMC_OCR_MIN_VOLTAGE_SHIFT       7
461#define MMC_OCR_200_210 (1U << 8)       /* Vdd voltage 2.00 ~ 2.10 */
462#define MMC_OCR_210_220 (1U << 9)       /* Vdd voltage 2.10 ~ 2.20 */
463#define MMC_OCR_220_230 (1U << 10)      /* Vdd voltage 2.20 ~ 2.30 */
464#define MMC_OCR_230_240 (1U << 11)      /* Vdd voltage 2.30 ~ 2.40 */
465#define MMC_OCR_240_250 (1U << 12)      /* Vdd voltage 2.40 ~ 2.50 */
466#define MMC_OCR_250_260 (1U << 13)      /* Vdd voltage 2.50 ~ 2.60 */
467#define MMC_OCR_260_270 (1U << 14)      /* Vdd voltage 2.60 ~ 2.70 */
468#define MMC_OCR_270_280 (1U << 15)      /* Vdd voltage 2.70 ~ 2.80 */
469#define MMC_OCR_280_290 (1U << 16)      /* Vdd voltage 2.80 ~ 2.90 */
470#define MMC_OCR_290_300 (1U << 17)      /* Vdd voltage 2.90 ~ 3.00 */
471#define MMC_OCR_300_310 (1U << 18)      /* Vdd voltage 3.00 ~ 3.10 */
472#define MMC_OCR_310_320 (1U << 19)      /* Vdd voltage 3.10 ~ 3.20 */
473#define MMC_OCR_320_330 (1U << 20)      /* Vdd voltage 3.20 ~ 3.30 */
474#define MMC_OCR_330_340 (1U << 21)      /* Vdd voltage 3.30 ~ 3.40 */
475#define MMC_OCR_340_350 (1U << 22)      /* Vdd voltage 3.40 ~ 3.50 */
476#define MMC_OCR_350_360 (1U << 23)      /* Vdd voltage 3.50 ~ 3.60 */
477#define MMC_OCR_MAX_VOLTAGE_SHIFT       23
478#define MMC_OCR_S18R    (1U << 24)      /* Switching to 1.8 V requested (SD) */
479#define MMC_OCR_S18A    MMC_OCR_S18R    /* Switching to 1.8 V accepted (SD) */
480#define MMC_OCR_XPC     (1U << 28)      /* SDXC Power Control */
481#define MMC_OCR_ACCESS_MODE_BYTE (0U << 29) /* Access Mode Byte (MMC) */
482#define MMC_OCR_ACCESS_MODE_SECT (1U << 29) /* Access Mode Sector (MMC) */
483#define MMC_OCR_ACCESS_MODE_MASK (3U << 29)
484#define MMC_OCR_CCS     (1u << 30)      /* Card Capacity status (SD vs SDHC) */
485#define MMC_OCR_CARD_BUSY (1U << 31)    /* Card Power up status */
486
487/* CSD -- decoded structure */
488struct mmc_cid {
489        uint32_t mid;
490        char pnm[8];
491        uint32_t psn;
492        uint16_t oid;
493        uint16_t mdt_year;
494        uint8_t mdt_month;
495        uint8_t prv;
496        uint8_t fwrev;
497};
498
499struct mmc_csd
500{
501        uint8_t csd_structure;
502        uint8_t spec_vers;
503        uint16_t ccc;
504        uint16_t tacc;
505        uint32_t nsac;
506        uint32_t r2w_factor;
507        uint32_t tran_speed;
508        uint32_t read_bl_len;
509        uint32_t write_bl_len;
510        uint32_t vdd_r_curr_min;
511        uint32_t vdd_r_curr_max;
512        uint32_t vdd_w_curr_min;
513        uint32_t vdd_w_curr_max;
514        uint32_t wp_grp_size;
515        uint32_t erase_sector;
516        uint64_t capacity;
517        unsigned int read_bl_partial:1,
518            read_blk_misalign:1,
519            write_bl_partial:1,
520            write_blk_misalign:1,
521            dsr_imp:1,
522            erase_blk_en:1,
523            wp_grp_enable:1;
524};
525
526struct mmc_scr
527{
528        unsigned char           sda_vsn;
529        unsigned char           bus_widths;
530#define SD_SCR_BUS_WIDTH_1      (1 << 0)
531#define SD_SCR_BUS_WIDTH_4      (1 << 2)
532};
533
534struct mmc_sd_status
535{
536        uint8_t                 bus_width;
537        uint8_t                 secured_mode;
538        uint16_t                card_type;
539        uint16_t                prot_area;
540        uint8_t                 speed_class;
541        uint8_t                 perf_move;
542        uint8_t                 au_size;
543        uint16_t                erase_size;
544        uint8_t                 erase_timeout;
545        uint8_t                 erase_offset;
546};
547
548/*
549 * Various MMC/SD constants
550 */
551#define MMC_BOOT_RPMB_BLOCK_SIZE        (128 * 1024)
552
553#define MMC_EXTCSD_SIZE 512
554
555#define MMC_PART_GP_MAX 4
556#define MMC_PART_MAX    8
557
558/*
559 * Older versions of the MMC standard had a variable sector size.  However,
560 * I've been able to find no old MMC or SD cards that have a non 512
561 * byte sector size anywhere, so we assume that such cards are very rare
562 * and only note their existence in passing here...
563 */
564#define MMC_SECTOR_SIZE 512
565
566#endif /* DEV_MMCREG_H */
Note: See TracBrowser for help on using the repository browser.