source: rtems-libbsd/freebsd/sys/dev/mmc/mmcreg.h @ c7e162a

5-freebsd-12
Last change on this file since c7e162a was c7e162a, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 26, 2018 at 1:19:42 PM

mmc: Optimize mmc_wait_for_req()

Use a self-contained RTEMS binary semaphore instead of msleep() and
wakeup(). This is itself more efficient and in addition allows the use
of mmc_wakeup() in interrupt context.

  • Property mode set to 100644
File size: 19.0 KB
Line 
1/*-
2 * Copyright (c) 2006 M. Warner Losh.  All rights reserved.
3 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * Portions of this software may have been developed with reference to
26 * the SD Simplified Specification.  The following disclaimer may apply:
27 *
28 * The following conditions apply to the release of the simplified
29 * specification ("Simplified Specification") by the SD Card Association and
30 * the SD Group. The Simplified Specification is a subset of the complete SD
31 * Specification which is owned by the SD Card Association and the SD
32 * Group. This Simplified Specification is provided on a non-confidential
33 * basis subject to the disclaimers below. Any implementation of the
34 * Simplified Specification may require a license from the SD Card
35 * Association, SD Group, SD-3C LLC or other third parties.
36 *
37 * Disclaimers:
38 *
39 * The information contained in the Simplified Specification is presented only
40 * as a standard specification for SD Cards and SD Host/Ancillary products and
41 * is provided "AS-IS" without any representations or warranties of any
42 * kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD
43 * Card Association for any damages, any infringements of patents or other
44 * right of the SD Group, SD-3C LLC, the SD Card Association or any third
45 * parties, which may result from its use. No license is granted by
46 * implication, estoppel or otherwise under any patent or other rights of the
47 * SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing
48 * herein shall be construed as an obligation by the SD Group, the SD-3C LLC
49 * or the SD Card Association to disclose or distribute any technical
50 * information, know-how or other confidential information to any third party.
51 *
52 * $FreeBSD$
53 */
54
55#ifndef DEV_MMC_MMCREG_H
56#define DEV_MMC_MMCREG_H
57#ifdef __rtems__
58#include <rtems/thread.h>
59#endif /* __rtems__ */
60
61/*
62 * This file contains the register definitions for the mmc and sd buses.
63 * They are taken from publicly available sources.
64 */
65
66struct mmc_data;
67struct mmc_request;
68
69struct mmc_command {
70        uint32_t        opcode;
71        uint32_t        arg;
72        uint32_t        resp[4];
73        uint32_t        flags;          /* Expected responses */
74#define MMC_RSP_PRESENT (1ul << 0)      /* Response */
75#define MMC_RSP_136     (1ul << 1)      /* 136 bit response */
76#define MMC_RSP_CRC     (1ul << 2)      /* Expect valid crc */
77#define MMC_RSP_BUSY    (1ul << 3)      /* Card may send busy */
78#define MMC_RSP_OPCODE  (1ul << 4)      /* Response include opcode */
79#define MMC_RSP_MASK    0x1ful
80#define MMC_CMD_AC      (0ul << 5)      /* Addressed Command, no data */
81#define MMC_CMD_ADTC    (1ul << 5)      /* Addressed Data transfer cmd */
82#define MMC_CMD_BC      (2ul << 5)      /* Broadcast command, no response */
83#define MMC_CMD_BCR     (3ul << 5)      /* Broadcast command with response */
84#define MMC_CMD_MASK    (3ul << 5)
85
86/* Possible response types defined in the standard: */
87#define MMC_RSP_NONE    (0)
88#define MMC_RSP_R1      (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
89#define MMC_RSP_R1B     (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
90#define MMC_RSP_R2      (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
91#define MMC_RSP_R3      (MMC_RSP_PRESENT)
92#define MMC_RSP_R4      (MMC_RSP_PRESENT)
93#define MMC_RSP_R5      (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
94#define MMC_RSP_R5B     (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
95#define MMC_RSP_R6      (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
96#define MMC_RSP_R7      (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
97#define MMC_RSP(x)      ((x) & MMC_RSP_MASK)
98        uint32_t        retries;
99        uint32_t        error;
100#define MMC_ERR_NONE    0
101#define MMC_ERR_TIMEOUT 1
102#define MMC_ERR_BADCRC  2
103#define MMC_ERR_FIFO    3
104#define MMC_ERR_FAILED  4
105#define MMC_ERR_INVALID 5
106#define MMC_ERR_NO_MEMORY 6
107#define MMC_ERR_MAX     6
108        struct mmc_data *data;          /* Data segment with cmd */
109        struct mmc_request *mrq;        /* backpointer to request */
110};
111
112/*
113 * R1 responses
114 *
115 * Types (per SD 2.0 standard)
116 *      e : error bit
117 *      s : status bit
118 *      r : detected and set for the actual command response
119 *      x : Detected and set during command execution.  The host can get
120 *          the status by issuing a command with R1 response.
121 *
122 * Clear Condition (per SD 2.0 standard)
123 *      a : according to the card current state.
124 *      b : always related to the previous command.  reception of a valid
125 *          command will clear it (with a delay of one command).
126 *      c : clear by read
127 */
128#define R1_OUT_OF_RANGE (1u << 31)              /* erx, c */
129#define R1_ADDRESS_ERROR (1u << 30)             /* erx, c */
130#define R1_BLOCK_LEN_ERROR (1u << 29)           /* erx, c */
131#define R1_ERASE_SEQ_ERROR (1u << 28)           /* er, c */
132#define R1_ERASE_PARAM (1u << 27)               /* erx, c */
133#define R1_WP_VIOLATION (1u << 26)              /* erx, c */
134#define R1_CARD_IS_LOCKED (1u << 25)            /* sx, a */
135#define R1_LOCK_UNLOCK_FAILED (1u << 24)        /* erx, c */
136#define R1_COM_CRC_ERROR (1u << 23)             /* er, b */
137#define R1_ILLEGAL_COMMAND (1u << 22)           /* er, b */
138#define R1_CARD_ECC_FAILED (1u << 21)           /* erx, c */
139#define R1_CC_ERROR (1u << 20)                  /* erx, c */
140#define R1_ERROR (1u << 19)                     /* erx, c */
141#define R1_CSD_OVERWRITE (1u << 16)             /* erx, c */
142#define R1_WP_ERASE_SKIP (1u << 15)             /* erx, c */
143#define R1_CARD_ECC_DISABLED (1u << 14)         /* sx, a */
144#define R1_ERASE_RESET (1u << 13)               /* sr, c */
145#define R1_CURRENT_STATE_MASK (0xfu << 9)       /* sx, b */
146#define R1_READY_FOR_DATA (1u << 8)             /* sx, a */
147#define R1_SWITCH_ERROR (1u << 7)               /* sx, c */
148#define R1_APP_CMD (1u << 5)                    /* sr, c */
149#define R1_AKE_SEQ_ERROR (1u << 3)              /* er, c */
150#define R1_STATUS(x)            ((x) & 0xFFFFE000)
151#define R1_CURRENT_STATE(x)     (((x) & R1_CURRENT_STATE_MASK) >> 9)
152#define R1_STATE_IDLE   0
153#define R1_STATE_READY  1
154#define R1_STATE_IDENT  2
155#define R1_STATE_STBY   3
156#define R1_STATE_TRAN   4
157#define R1_STATE_DATA   5
158#define R1_STATE_RCV    6
159#define R1_STATE_PRG    7
160#define R1_STATE_DIS    8
161
162struct mmc_data {
163        size_t len;             /* size of the data */
164        size_t xfer_len;
165        void *data;             /* data buffer */
166        uint32_t        flags;
167#define MMC_DATA_WRITE  (1UL << 0)
168#define MMC_DATA_READ   (1UL << 1)
169#define MMC_DATA_STREAM (1UL << 2)
170#define MMC_DATA_MULTI  (1UL << 3)
171        struct mmc_request *mrq;
172};
173
174struct mmc_request {
175        struct mmc_command *cmd;
176        struct mmc_command *stop;
177        void (*done)(struct mmc_request *); /* Completion function */
178        void *done_data;                /* requestor set data */
179#ifndef __rtems__
180        uint32_t flags;
181#define MMC_REQ_DONE    1
182#else /* __rtems__ */
183        rtems_binary_semaphore req_done;
184#endif /* __rtems__ */
185};
186
187/* Command definitions */
188
189/* Class 0 and 1: Basic commands & read stream commands */
190#define MMC_GO_IDLE_STATE       0
191#define MMC_SEND_OP_COND        1
192#define MMC_ALL_SEND_CID        2
193#define MMC_SET_RELATIVE_ADDR   3
194#define SD_SEND_RELATIVE_ADDR   3
195#define MMC_SET_DSR             4
196#define MMC_SLEEP_AWAKE         5
197#define MMC_SWITCH_FUNC         6
198#define  MMC_SWITCH_FUNC_CMDS    0
199#define  MMC_SWITCH_FUNC_SET     1
200#define  MMC_SWITCH_FUNC_CLR     2
201#define  MMC_SWITCH_FUNC_WR      3
202#define MMC_SELECT_CARD         7
203#define MMC_DESELECT_CARD       7
204#define MMC_SEND_EXT_CSD        8
205#define SD_SEND_IF_COND         8
206#define MMC_SEND_CSD            9
207#define MMC_SEND_CID            10
208#define MMC_READ_DAT_UNTIL_STOP 11
209#define MMC_STOP_TRANSMISSION   12
210#define MMC_SEND_STATUS         13
211#define MMC_BUSTEST_R           14
212#define MMC_GO_INACTIVE_STATE   15
213#define MMC_BUSTEST_W           19
214
215/* Class 2: Block oriented read commands */
216#define MMC_SET_BLOCKLEN        16
217#define MMC_READ_SINGLE_BLOCK   17
218#define MMC_READ_MULTIPLE_BLOCK 18
219#define MMC_SEND_TUNING_BLOCK   19
220#define MMC_SEND_TUNING_BLOCK_HS200 21
221
222/* Class 3: Stream write commands */
223#define MMC_WRITE_DAT_UNTIL_STOP 20
224                        /* reserved: 22 */
225
226/* Class 4: Block oriented write commands */
227#define MMC_SET_BLOCK_COUNT     23
228#define MMC_WRITE_BLOCK         24
229#define MMC_WRITE_MULTIPLE_BLOCK 25
230#define MMC_PROGARM_CID         26
231#define MMC_PROGRAM_CSD         27
232
233/* Class 6: Block oriented write protection commands */
234#define MMC_SET_WRITE_PROT      28
235#define MMC_CLR_WRITE_PROT      29
236#define MMC_SEND_WRITE_PROT     30
237                        /* reserved: 31 */
238
239/* Class 5: Erase commands */
240#define SD_ERASE_WR_BLK_START   32
241#define SD_ERASE_WR_BLK_END     33
242                        /* 34 -- reserved old command */
243#define MMC_ERASE_GROUP_START   35
244#define MMC_ERASE_GROUP_END     36
245                        /* 37 -- reserved old command */
246#define MMC_ERASE               38
247
248/* Class 9: I/O mode commands */
249#define MMC_FAST_IO             39
250#define MMC_GO_IRQ_STATE        40
251                        /* reserved: 41 */
252
253/* Class 7: Lock card */
254#define MMC_LOCK_UNLOCK         42
255                        /* reserved: 43 */
256                        /* reserved: 44 */
257                        /* reserved: 45 */
258                        /* reserved: 46 */
259                        /* reserved: 47 */
260                        /* reserved: 48 */
261                        /* reserved: 49 */
262                        /* reserved: 50 */
263                        /* reserved: 51 */
264                        /* reserved: 54 */
265
266/* Class 8: Application specific commands */
267#define MMC_APP_CMD             55
268#define MMC_GEN_CMD             56
269                        /* reserved: 57 */
270                        /* reserved: 58 */
271                        /* reserved: 59 */
272                        /* reserved for mfg: 60 */
273                        /* reserved for mfg: 61 */
274                        /* reserved for mfg: 62 */
275                        /* reserved for mfg: 63 */
276
277/* Class 9: I/O cards (sd) */
278#define SD_IO_RW_DIRECT         52
279#define SD_IO_RW_EXTENDED       53
280
281/* Class 10: Switch function commands */
282#define SD_SWITCH_FUNC          6
283                        /* reserved: 34 */
284                        /* reserved: 35 */
285                        /* reserved: 36 */
286                        /* reserved: 37 */
287                        /* reserved: 50 */
288                        /* reserved: 57 */
289
290/* Application specific commands for SD */
291#define ACMD_SET_BUS_WIDTH      6
292#define ACMD_SD_STATUS          13
293#define ACMD_SEND_NUM_WR_BLOCKS 22
294#define ACMD_SET_WR_BLK_ERASE_COUNT 23
295#define ACMD_SD_SEND_OP_COND    41
296#define ACMD_SET_CLR_CARD_DETECT 42
297#define ACMD_SEND_SCR           51
298
299/*
300 * EXT_CSD fields
301 */
302#define EXT_CSD_EXT_PART_ATTR   52      /* R/W, 2 bytes */
303#define EXT_CSD_ENH_START_ADDR  136     /* R/W, 4 bytes */
304#define EXT_CSD_ENH_SIZE_MULT   140     /* R/W, 3 bytes */
305#define EXT_CSD_GP_SIZE_MULT    143     /* R/W, 12 bytes */
306#define EXT_CSD_PART_SET        155     /* R/W */
307#define EXT_CSD_PART_ATTR       156     /* R/W */
308#define EXT_CSD_PART_SUPPORT    160     /* RO */
309#define EXT_CSD_RPMB_MULT       168     /* RO */
310#define EXT_CSD_BOOT_WP_STATUS  174     /* RO */
311#define EXT_CSD_ERASE_GRP_DEF   175     /* R/W */
312#define EXT_CSD_PART_CONFIG     179     /* R/W */
313#define EXT_CSD_BUS_WIDTH       183     /* R/W */
314#define EXT_CSD_STROBE_SUPPORT  184     /* RO */
315#define EXT_CSD_HS_TIMING       185     /* R/W */
316#define EXT_CSD_POWER_CLASS     187     /* R/W */
317#define EXT_CSD_CARD_TYPE       196     /* RO */
318#define EXT_CSD_DRIVER_STRENGTH 197     /* RO */
319#define EXT_CSD_REV             192     /* RO */
320#define EXT_CSD_PART_SWITCH_TO  199     /* RO */
321#define EXT_CSD_PWR_CL_52_195   200     /* RO */
322#define EXT_CSD_PWR_CL_26_195   201     /* RO */
323#define EXT_CSD_PWR_CL_52_360   202     /* RO */
324#define EXT_CSD_PWR_CL_26_360   203     /* RO */
325#define EXT_CSD_SEC_CNT         212     /* RO, 4 bytes */
326#define EXT_CSD_HC_WP_GRP_SIZE  221     /* RO */
327#define EXT_CSD_ERASE_TO_MULT   223     /* RO */
328#define EXT_CSD_ERASE_GRP_SIZE  224     /* RO */
329#define EXT_CSD_BOOT_SIZE_MULT  226     /* RO */
330#define EXT_CSD_PWR_CL_200_195  236     /* RO */
331#define EXT_CSD_PWR_CL_200_360  237     /* RO */
332#define EXT_CSD_PWR_CL_52_195_DDR 238   /* RO */
333#define EXT_CSD_PWR_CL_52_360_DDR 239   /* RO */
334#define EXT_CSD_GEN_CMD6_TIME   248     /* RO */
335#define EXT_CSD_PWR_CL_200_360_DDR 253  /* RO */
336
337/*
338 * EXT_CSD field definitions
339 */
340#define EXT_CSD_EXT_PART_ATTR_DEFAULT           0x0
341#define EXT_CSD_EXT_PART_ATTR_SYSTEMCODE        0x1
342#define EXT_CSD_EXT_PART_ATTR_NPERSISTENT       0x2
343
344#define EXT_CSD_PART_SET_COMPLETED              0x01
345
346#define EXT_CSD_PART_ATTR_ENH_USR               0x01
347#define EXT_CSD_PART_ATTR_ENH_GP0               0x02
348#define EXT_CSD_PART_ATTR_ENH_GP1               0x04
349#define EXT_CSD_PART_ATTR_ENH_GP2               0x08
350#define EXT_CSD_PART_ATTR_ENH_GP3               0x10
351#define EXT_CSD_PART_ATTR_ENH_MASK              0x1f
352
353#define EXT_CSD_PART_SUPPORT_EN                 0x01
354#define EXT_CSD_PART_SUPPORT_ENH_ATTR_EN        0x02
355#define EXT_CSD_PART_SUPPORT_EXT_ATTR_EN        0x04
356
357#define EXT_CSD_BOOT_WP_STATUS_BOOT0_PWR        0x01
358#define EXT_CSD_BOOT_WP_STATUS_BOOT0_PERM       0x02
359#define EXT_CSD_BOOT_WP_STATUS_BOOT0_MASK       0x03
360#define EXT_CSD_BOOT_WP_STATUS_BOOT1_PWR        0x04
361#define EXT_CSD_BOOT_WP_STATUS_BOOT1_PERM       0x08
362#define EXT_CSD_BOOT_WP_STATUS_BOOT1_MASK       0x0c
363
364#define EXT_CSD_ERASE_GRP_DEF_EN        0x01
365
366#define EXT_CSD_PART_CONFIG_ACC_DEFAULT 0x00
367#define EXT_CSD_PART_CONFIG_ACC_BOOT0   0x01
368#define EXT_CSD_PART_CONFIG_ACC_BOOT1   0x02
369#define EXT_CSD_PART_CONFIG_ACC_RPMB    0x03
370#define EXT_CSD_PART_CONFIG_ACC_GP0     0x04
371#define EXT_CSD_PART_CONFIG_ACC_GP1     0x05
372#define EXT_CSD_PART_CONFIG_ACC_GP2     0x06
373#define EXT_CSD_PART_CONFIG_ACC_GP3     0x07
374#define EXT_CSD_PART_CONFIG_ACC_MASK    0x07
375#define EXT_CSD_PART_CONFIG_BOOT0       0x08
376#define EXT_CSD_PART_CONFIG_BOOT1       0x10
377#define EXT_CSD_PART_CONFIG_BOOT_USR    0x38
378#define EXT_CSD_PART_CONFIG_BOOT_MASK   0x38
379#define EXT_CSD_PART_CONFIG_BOOT_ACK    0x40
380
381#define EXT_CSD_CMD_SET_NORMAL          1
382#define EXT_CSD_CMD_SET_SECURE          2
383#define EXT_CSD_CMD_SET_CPSECURE        4
384
385#define EXT_CSD_HS_TIMING_BC            0
386#define EXT_CSD_HS_TIMING_HS            1
387#define EXT_CSD_HS_TIMING_DDR200        2
388#define EXT_CSD_HS_TIMING_DDR400        3
389#define EXT_CSD_HS_TIMING_DRV_STR_SHIFT 4
390
391#define EXT_CSD_POWER_CLASS_8BIT_MASK   0xf0
392#define EXT_CSD_POWER_CLASS_8BIT_SHIFT  4
393#define EXT_CSD_POWER_CLASS_4BIT_MASK   0x0f
394#define EXT_CSD_POWER_CLASS_4BIT_SHIFT  0
395
396#define EXT_CSD_CARD_TYPE_HS_26         0x0001
397#define EXT_CSD_CARD_TYPE_HS_52         0x0002
398#define EXT_CSD_CARD_TYPE_DDR_52_1_8V   0x0004
399#define EXT_CSD_CARD_TYPE_DDR_52_1_2V   0x0008
400#define EXT_CSD_CARD_TYPE_HS200_1_8V    0x0010
401#define EXT_CSD_CARD_TYPE_HS200_1_2V    0x0020
402#define EXT_CSD_CARD_TYPE_HS400_1_8V    0x0040
403#define EXT_CSD_CARD_TYPE_HS400_1_2V    0x0080
404#define EXT_CSD_CARD_TYPE_HS400ES       0x0100
405
406#define EXT_CSD_BUS_WIDTH_1     0
407#define EXT_CSD_BUS_WIDTH_4     1
408#define EXT_CSD_BUS_WIDTH_8     2
409#define EXT_CSD_BUS_WIDTH_4_DDR 5
410#define EXT_CSD_BUS_WIDTH_8_DDR 6
411#define EXT_CSD_BUS_WIDTH_ES    0x80
412
413#define MMC_TYPE_HS_26_MAX              26000000
414#define MMC_TYPE_HS_52_MAX              52000000
415#define MMC_TYPE_DDR52_MAX              52000000
416#define MMC_TYPE_HS200_HS400ES_MAX      200000000
417
418/*
419 * SD bus widths
420 */
421#define SD_BUS_WIDTH_1          0
422#define SD_BUS_WIDTH_4          2
423
424/*
425 * SD Switch
426 */
427#define SD_SWITCH_MODE_CHECK    0
428#define SD_SWITCH_MODE_SET      1
429#define SD_SWITCH_GROUP1        0
430#define SD_SWITCH_NORMAL_MODE   0
431#define SD_SWITCH_HS_MODE       1
432#define SD_SWITCH_SDR50_MODE    2
433#define SD_SWITCH_SDR104_MODE   3
434#define SD_SWITCH_DDR50         4
435#define SD_SWITCH_NOCHANGE      0xF
436
437#define SD_CLR_CARD_DETECT      0
438#define SD_SET_CARD_DETECT      1
439
440#define SD_HS_MAX               50000000
441#define SD_DDR50_MAX            50000000
442#define SD_SDR12_MAX            25000000
443#define SD_SDR25_MAX            50000000
444#define SD_SDR50_MAX            100000000
445#define SD_SDR104_MAX           208000000
446
447/* Specifications require 400 kHz max. during ID phase. */
448#define SD_MMC_CARD_ID_FREQUENCY        400000
449
450/* OCR bits */
451
452/*
453 * in SD 2.0 spec, bits 8-14 are now marked reserved
454 * Low voltage in SD2.0 spec is bit 7, TBD voltage
455 * Low voltage in MC 3.31 spec is bit 7, 1.65-1.95V
456 * Specs prior to  MMC 3.31 defined bits 0-7 as voltages down to 1.5V.
457 * 3.31 redefined them to be reserved and also said that cards had to
458 * support the 2.7-3.6V and fixed the OCR to be 0xfff8000 for high voltage
459 * cards.  MMC 4.0 says that a dual voltage card responds with 0xfff8080.
460 * Looks like the fine-grained control of the voltage tolerance ranges
461 * was abandoned.
462 *
463 * The MMC_OCR_CCS appears to be valid for only SD cards.
464 */
465#define MMC_OCR_VOLTAGE 0x3fffffffU     /* Vdd Voltage mask */
466#define MMC_OCR_LOW_VOLTAGE (1u << 7)   /* Low Voltage Range -- tbd */
467#define MMC_OCR_MIN_VOLTAGE_SHIFT       7
468#define MMC_OCR_200_210 (1U << 8)       /* Vdd voltage 2.00 ~ 2.10 */
469#define MMC_OCR_210_220 (1U << 9)       /* Vdd voltage 2.10 ~ 2.20 */
470#define MMC_OCR_220_230 (1U << 10)      /* Vdd voltage 2.20 ~ 2.30 */
471#define MMC_OCR_230_240 (1U << 11)      /* Vdd voltage 2.30 ~ 2.40 */
472#define MMC_OCR_240_250 (1U << 12)      /* Vdd voltage 2.40 ~ 2.50 */
473#define MMC_OCR_250_260 (1U << 13)      /* Vdd voltage 2.50 ~ 2.60 */
474#define MMC_OCR_260_270 (1U << 14)      /* Vdd voltage 2.60 ~ 2.70 */
475#define MMC_OCR_270_280 (1U << 15)      /* Vdd voltage 2.70 ~ 2.80 */
476#define MMC_OCR_280_290 (1U << 16)      /* Vdd voltage 2.80 ~ 2.90 */
477#define MMC_OCR_290_300 (1U << 17)      /* Vdd voltage 2.90 ~ 3.00 */
478#define MMC_OCR_300_310 (1U << 18)      /* Vdd voltage 3.00 ~ 3.10 */
479#define MMC_OCR_310_320 (1U << 19)      /* Vdd voltage 3.10 ~ 3.20 */
480#define MMC_OCR_320_330 (1U << 20)      /* Vdd voltage 3.20 ~ 3.30 */
481#define MMC_OCR_330_340 (1U << 21)      /* Vdd voltage 3.30 ~ 3.40 */
482#define MMC_OCR_340_350 (1U << 22)      /* Vdd voltage 3.40 ~ 3.50 */
483#define MMC_OCR_350_360 (1U << 23)      /* Vdd voltage 3.50 ~ 3.60 */
484#define MMC_OCR_MAX_VOLTAGE_SHIFT       23
485#define MMC_OCR_S18R    (1U << 24)      /* Switching to 1.8 V requested (SD) */
486#define MMC_OCR_S18A    MMC_OCR_S18R    /* Switching to 1.8 V accepted (SD) */
487#define MMC_OCR_XPC     (1U << 28)      /* SDXC Power Control */
488#define MMC_OCR_ACCESS_MODE_BYTE (0U << 29) /* Access Mode Byte (MMC) */
489#define MMC_OCR_ACCESS_MODE_SECT (1U << 29) /* Access Mode Sector (MMC) */
490#define MMC_OCR_ACCESS_MODE_MASK (3U << 29)
491#define MMC_OCR_CCS     (1u << 30)      /* Card Capacity status (SD vs SDHC) */
492#define MMC_OCR_CARD_BUSY (1U << 31)    /* Card Power up status */
493
494/* CSD -- decoded structure */
495struct mmc_cid {
496        uint32_t mid;
497        char pnm[8];
498        uint32_t psn;
499        uint16_t oid;
500        uint16_t mdt_year;
501        uint8_t mdt_month;
502        uint8_t prv;
503        uint8_t fwrev;
504};
505
506struct mmc_csd
507{
508        uint8_t csd_structure;
509        uint8_t spec_vers;
510        uint16_t ccc;
511        uint16_t tacc;
512        uint32_t nsac;
513        uint32_t r2w_factor;
514        uint32_t tran_speed;
515        uint32_t read_bl_len;
516        uint32_t write_bl_len;
517        uint32_t vdd_r_curr_min;
518        uint32_t vdd_r_curr_max;
519        uint32_t vdd_w_curr_min;
520        uint32_t vdd_w_curr_max;
521        uint32_t wp_grp_size;
522        uint32_t erase_sector;
523        uint64_t capacity;
524        unsigned int read_bl_partial:1,
525            read_blk_misalign:1,
526            write_bl_partial:1,
527            write_blk_misalign:1,
528            dsr_imp:1,
529            erase_blk_en:1,
530            wp_grp_enable:1;
531};
532
533struct mmc_scr
534{
535        unsigned char           sda_vsn;
536        unsigned char           bus_widths;
537#define SD_SCR_BUS_WIDTH_1      (1 << 0)
538#define SD_SCR_BUS_WIDTH_4      (1 << 2)
539};
540
541struct mmc_sd_status
542{
543        uint8_t                 bus_width;
544        uint8_t                 secured_mode;
545        uint16_t                card_type;
546        uint16_t                prot_area;
547        uint8_t                 speed_class;
548        uint8_t                 perf_move;
549        uint8_t                 au_size;
550        uint16_t                erase_size;
551        uint8_t                 erase_timeout;
552        uint8_t                 erase_offset;
553};
554
555/*
556 * Various MMC/SD constants
557 */
558#define MMC_BOOT_RPMB_BLOCK_SIZE        (128 * 1024)
559
560#define MMC_EXTCSD_SIZE 512
561
562#define MMC_PART_GP_MAX 4
563#define MMC_PART_MAX    8
564
565/*
566 * Older versions of the MMC standard had a variable sector size.  However,
567 * I've been able to find no old MMC or SD cards that have a non 512
568 * byte sector size anywhere, so we assume that such cards are very rare
569 * and only note their existence in passing here...
570 */
571#define MMC_SECTOR_SIZE 512
572
573#endif /* DEV_MMCREG_H */
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