| 1 | /*- |
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| 2 | * SPDX-License-Identifier: BSD-2-Clause-FreeBSD |
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| 3 | * |
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| 4 | * Copyright (c) 2006 M. Warner Losh. All rights reserved. |
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| 5 | * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org> |
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| 6 | * Copyright (c) 2015-2016 Ilya Bakulin <kibab@FreeBSD.org> |
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| 7 | * |
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| 8 | * Redistribution and use in source and binary forms, with or without |
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| 9 | * modification, are permitted provided that the following conditions |
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| 10 | * are met: |
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| 11 | * 1. Redistributions of source code must retain the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer. |
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| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 14 | * notice, this list of conditions and the following disclaimer in the |
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| 15 | * documentation and/or other materials provided with the distribution. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | * |
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| 28 | * Portions of this software may have been developed with reference to |
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| 29 | * the SD Simplified Specification. The following disclaimer may apply: |
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| 30 | * |
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| 31 | * The following conditions apply to the release of the simplified |
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| 32 | * specification ("Simplified Specification") by the SD Card Association and |
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| 33 | * the SD Group. The Simplified Specification is a subset of the complete SD |
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| 34 | * Specification which is owned by the SD Card Association and the SD |
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| 35 | * Group. This Simplified Specification is provided on a non-confidential |
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| 36 | * basis subject to the disclaimers below. Any implementation of the |
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| 37 | * Simplified Specification may require a license from the SD Card |
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| 38 | * Association, SD Group, SD-3C LLC or other third parties. |
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| 39 | * |
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| 40 | * Disclaimers: |
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| 41 | * |
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| 42 | * The information contained in the Simplified Specification is presented only |
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| 43 | * as a standard specification for SD Cards and SD Host/Ancillary products and |
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| 44 | * is provided "AS-IS" without any representations or warranties of any |
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| 45 | * kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD |
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| 46 | * Card Association for any damages, any infringements of patents or other |
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| 47 | * right of the SD Group, SD-3C LLC, the SD Card Association or any third |
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| 48 | * parties, which may result from its use. No license is granted by |
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| 49 | * implication, estoppel or otherwise under any patent or other rights of the |
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| 50 | * SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing |
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| 51 | * herein shall be construed as an obligation by the SD Group, the SD-3C LLC |
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| 52 | * or the SD Card Association to disclose or distribute any technical |
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| 53 | * information, know-how or other confidential information to any third party. |
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| 54 | * |
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| 55 | * $FreeBSD$ |
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| 56 | */ |
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| 57 | |
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| 58 | #ifndef DEV_MMC_MMCREG_H |
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| 59 | #define DEV_MMC_MMCREG_H |
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| 60 | #ifdef __rtems__ |
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| 61 | #include <rtems/thread.h> |
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| 62 | #endif /* __rtems__ */ |
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| 63 | |
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| 64 | /* |
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| 65 | * This file contains the register definitions for the mmc and sd buses. |
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| 66 | * They are taken from publicly available sources. |
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| 67 | */ |
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| 68 | |
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| 69 | struct mmc_data; |
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| 70 | struct mmc_request; |
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| 71 | |
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| 72 | struct mmc_command { |
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| 73 | uint32_t opcode; |
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| 74 | uint32_t arg; |
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| 75 | uint32_t resp[4]; |
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| 76 | uint32_t flags; /* Expected responses */ |
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| 77 | #define MMC_RSP_PRESENT (1ul << 0) /* Response */ |
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| 78 | #define MMC_RSP_136 (1ul << 1) /* 136 bit response */ |
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| 79 | #define MMC_RSP_CRC (1ul << 2) /* Expect valid crc */ |
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| 80 | #define MMC_RSP_BUSY (1ul << 3) /* Card may send busy */ |
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| 81 | #define MMC_RSP_OPCODE (1ul << 4) /* Response include opcode */ |
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| 82 | #define MMC_RSP_MASK 0x1ful |
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| 83 | #define MMC_CMD_AC (0ul << 5) /* Addressed Command, no data */ |
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| 84 | #define MMC_CMD_ADTC (1ul << 5) /* Addressed Data transfer cmd */ |
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| 85 | #define MMC_CMD_BC (2ul << 5) /* Broadcast command, no response */ |
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| 86 | #define MMC_CMD_BCR (3ul << 5) /* Broadcast command with response */ |
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| 87 | #define MMC_CMD_MASK (3ul << 5) |
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| 88 | |
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| 89 | /* Possible response types defined in the standard: */ |
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| 90 | #define MMC_RSP_NONE (0) |
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| 91 | #define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) |
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| 92 | #define MMC_RSP_R1B (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY) |
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| 93 | #define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC) |
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| 94 | #define MMC_RSP_R3 (MMC_RSP_PRESENT) |
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| 95 | #define MMC_RSP_R4 (MMC_RSP_PRESENT) |
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| 96 | #define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) |
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| 97 | #define MMC_RSP_R5B (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY) |
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| 98 | #define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) |
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| 99 | #define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) |
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| 100 | #define MMC_RSP(x) ((x) & MMC_RSP_MASK) |
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| 101 | uint32_t retries; |
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| 102 | uint32_t error; |
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| 103 | #define MMC_ERR_NONE 0 |
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| 104 | #define MMC_ERR_TIMEOUT 1 |
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| 105 | #define MMC_ERR_BADCRC 2 |
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| 106 | #define MMC_ERR_FIFO 3 |
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| 107 | #define MMC_ERR_FAILED 4 |
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| 108 | #define MMC_ERR_INVALID 5 |
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| 109 | #define MMC_ERR_NO_MEMORY 6 |
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| 110 | #define MMC_ERR_MAX 6 |
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| 111 | struct mmc_data *data; /* Data segment with cmd */ |
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| 112 | struct mmc_request *mrq; /* backpointer to request */ |
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| 113 | }; |
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| 114 | |
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| 115 | /* |
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| 116 | * R1 responses |
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| 117 | * |
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| 118 | * Types (per SD 2.0 standard) |
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| 119 | * e : error bit |
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| 120 | * s : status bit |
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| 121 | * r : detected and set for the actual command response |
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| 122 | * x : Detected and set during command execution. The host can get |
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| 123 | * the status by issuing a command with R1 response. |
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| 124 | * |
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| 125 | * Clear Condition (per SD 2.0 standard) |
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| 126 | * a : according to the card current state. |
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| 127 | * b : always related to the previous command. reception of a valid |
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| 128 | * command will clear it (with a delay of one command). |
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| 129 | * c : clear by read |
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| 130 | */ |
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| 131 | #define R1_OUT_OF_RANGE (1u << 31) /* erx, c */ |
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| 132 | #define R1_ADDRESS_ERROR (1u << 30) /* erx, c */ |
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| 133 | #define R1_BLOCK_LEN_ERROR (1u << 29) /* erx, c */ |
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| 134 | #define R1_ERASE_SEQ_ERROR (1u << 28) /* er, c */ |
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| 135 | #define R1_ERASE_PARAM (1u << 27) /* erx, c */ |
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| 136 | #define R1_WP_VIOLATION (1u << 26) /* erx, c */ |
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| 137 | #define R1_CARD_IS_LOCKED (1u << 25) /* sx, a */ |
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| 138 | #define R1_LOCK_UNLOCK_FAILED (1u << 24) /* erx, c */ |
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| 139 | #define R1_COM_CRC_ERROR (1u << 23) /* er, b */ |
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| 140 | #define R1_ILLEGAL_COMMAND (1u << 22) /* er, b */ |
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| 141 | #define R1_CARD_ECC_FAILED (1u << 21) /* erx, c */ |
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| 142 | #define R1_CC_ERROR (1u << 20) /* erx, c */ |
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| 143 | #define R1_ERROR (1u << 19) /* erx, c */ |
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| 144 | #define R1_CSD_OVERWRITE (1u << 16) /* erx, c */ |
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| 145 | #define R1_WP_ERASE_SKIP (1u << 15) /* erx, c */ |
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| 146 | #define R1_CARD_ECC_DISABLED (1u << 14) /* sx, a */ |
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| 147 | #define R1_ERASE_RESET (1u << 13) /* sr, c */ |
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| 148 | #define R1_CURRENT_STATE_MASK (0xfu << 9) /* sx, b */ |
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| 149 | #define R1_READY_FOR_DATA (1u << 8) /* sx, a */ |
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| 150 | #define R1_SWITCH_ERROR (1u << 7) /* sx, c */ |
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| 151 | #define R1_APP_CMD (1u << 5) /* sr, c */ |
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| 152 | #define R1_AKE_SEQ_ERROR (1u << 3) /* er, c */ |
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| 153 | #define R1_STATUS(x) ((x) & 0xFFFFE000) |
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| 154 | #define R1_CURRENT_STATE(x) (((x) & R1_CURRENT_STATE_MASK) >> 9) |
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| 155 | #define R1_STATE_IDLE 0 |
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| 156 | #define R1_STATE_READY 1 |
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| 157 | #define R1_STATE_IDENT 2 |
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| 158 | #define R1_STATE_STBY 3 |
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| 159 | #define R1_STATE_TRAN 4 |
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| 160 | #define R1_STATE_DATA 5 |
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| 161 | #define R1_STATE_RCV 6 |
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| 162 | #define R1_STATE_PRG 7 |
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| 163 | #define R1_STATE_DIS 8 |
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| 164 | |
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| 165 | /* R4 responses (SDIO) */ |
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| 166 | #define R4_IO_NUM_FUNCTIONS(ocr) (((ocr) >> 28) & 0x3) |
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| 167 | #define R4_IO_MEM_PRESENT (0x1 << 27) |
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| 168 | #define R4_IO_OCR_MASK 0x00fffff0 |
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| 169 | |
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| 170 | /* |
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| 171 | * R5 responses |
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| 172 | * |
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| 173 | * Types (per SD 2.0 standard) |
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| 174 | * e : error bit |
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| 175 | * s : status bit |
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| 176 | * r : detected and set for the actual command response |
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| 177 | * x : Detected and set during command execution. The host can get |
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| 178 | * the status by issuing a command with R1 response. |
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| 179 | * |
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| 180 | * Clear Condition (per SD 2.0 standard) |
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| 181 | * a : according to the card current state. |
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| 182 | * b : always related to the previous command. reception of a valid |
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| 183 | * command will clear it (with a delay of one command). |
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| 184 | * c : clear by read |
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| 185 | */ |
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| 186 | #define R5_COM_CRC_ERROR (1u << 15) /* er, b */ |
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| 187 | #define R5_ILLEGAL_COMMAND (1u << 14) /* er, b */ |
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| 188 | #define R5_IO_CURRENT_STATE_MASK (3u << 12) /* s, b */ |
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| 189 | #define R5_IO_CURRENT_STATE(x) (((x) & R5_IO_CURRENT_STATE_MASK) >> 12) |
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| 190 | #define R5_ERROR (1u << 11) /* erx, c */ |
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| 191 | #define R5_FUNCTION_NUMBER (1u << 9) /* er, c */ |
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| 192 | #define R5_OUT_OF_RANGE (1u << 8) /* er, c */ |
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| 193 | |
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| 194 | struct mmc_data { |
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| 195 | size_t len; /* size of the data */ |
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| 196 | size_t xfer_len; |
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| 197 | void *data; /* data buffer */ |
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| 198 | uint32_t flags; |
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| 199 | #define MMC_DATA_WRITE (1UL << 0) |
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| 200 | #define MMC_DATA_READ (1UL << 1) |
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| 201 | #define MMC_DATA_STREAM (1UL << 2) |
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| 202 | #define MMC_DATA_MULTI (1UL << 3) |
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| 203 | struct mmc_request *mrq; |
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| 204 | }; |
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| 205 | |
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| 206 | struct mmc_request { |
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| 207 | struct mmc_command *cmd; |
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| 208 | struct mmc_command *stop; |
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| 209 | void (*done)(struct mmc_request *); /* Completion function */ |
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| 210 | void *done_data; /* requestor set data */ |
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| 211 | uint32_t flags; |
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| 212 | #ifndef __rtems__ |
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| 213 | #define MMC_REQ_DONE 1 |
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| 214 | #endif /* __rtems__ */ |
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| 215 | #define MMC_TUNE_DONE 2 |
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| 216 | #ifdef __rtems__ |
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| 217 | rtems_binary_semaphore req_done; |
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| 218 | #endif /* __rtems__ */ |
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| 219 | }; |
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| 220 | |
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| 221 | /* Command definitions */ |
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| 222 | |
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| 223 | /* Class 0 and 1: Basic commands & read stream commands */ |
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| 224 | #define MMC_GO_IDLE_STATE 0 |
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| 225 | #define MMC_SEND_OP_COND 1 |
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| 226 | #define MMC_ALL_SEND_CID 2 |
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| 227 | #define MMC_SET_RELATIVE_ADDR 3 |
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| 228 | #define SD_SEND_RELATIVE_ADDR 3 |
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| 229 | #define MMC_SET_DSR 4 |
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| 230 | #define MMC_SLEEP_AWAKE 5 |
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| 231 | #define IO_SEND_OP_COND 5 |
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| 232 | #define MMC_SWITCH_FUNC 6 |
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| 233 | #define MMC_SWITCH_FUNC_CMDS 0 |
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| 234 | #define MMC_SWITCH_FUNC_SET 1 |
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| 235 | #define MMC_SWITCH_FUNC_CLR 2 |
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| 236 | #define MMC_SWITCH_FUNC_WR 3 |
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| 237 | #define MMC_SELECT_CARD 7 |
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| 238 | #define MMC_DESELECT_CARD 7 |
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| 239 | #define MMC_SEND_EXT_CSD 8 |
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| 240 | #define SD_SEND_IF_COND 8 |
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| 241 | #define MMC_SEND_CSD 9 |
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| 242 | #define MMC_SEND_CID 10 |
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| 243 | #define MMC_READ_DAT_UNTIL_STOP 11 |
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| 244 | #define MMC_STOP_TRANSMISSION 12 |
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| 245 | #define MMC_SEND_STATUS 13 |
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| 246 | #define MMC_BUSTEST_R 14 |
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| 247 | #define MMC_GO_INACTIVE_STATE 15 |
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| 248 | #define MMC_BUSTEST_W 19 |
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| 249 | |
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| 250 | /* Class 2: Block oriented read commands */ |
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| 251 | #define MMC_SET_BLOCKLEN 16 |
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| 252 | #define MMC_READ_SINGLE_BLOCK 17 |
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| 253 | #define MMC_READ_MULTIPLE_BLOCK 18 |
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| 254 | #define MMC_SEND_TUNING_BLOCK 19 |
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| 255 | #define MMC_SEND_TUNING_BLOCK_HS200 21 |
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| 256 | |
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| 257 | /* Class 3: Stream write commands */ |
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| 258 | #define MMC_WRITE_DAT_UNTIL_STOP 20 |
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| 259 | /* reserved: 22 */ |
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| 260 | |
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| 261 | /* Class 4: Block oriented write commands */ |
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| 262 | #define MMC_SET_BLOCK_COUNT 23 |
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| 263 | #define MMC_WRITE_BLOCK 24 |
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| 264 | #define MMC_WRITE_MULTIPLE_BLOCK 25 |
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| 265 | #define MMC_PROGARM_CID 26 |
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| 266 | #define MMC_PROGRAM_CSD 27 |
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| 267 | |
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| 268 | /* Class 6: Block oriented write protection commands */ |
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| 269 | #define MMC_SET_WRITE_PROT 28 |
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| 270 | #define MMC_CLR_WRITE_PROT 29 |
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| 271 | #define MMC_SEND_WRITE_PROT 30 |
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| 272 | /* reserved: 31 */ |
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| 273 | |
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| 274 | /* Class 5: Erase commands */ |
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| 275 | #define SD_ERASE_WR_BLK_START 32 |
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| 276 | #define SD_ERASE_WR_BLK_END 33 |
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| 277 | /* 34 -- reserved old command */ |
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| 278 | #define MMC_ERASE_GROUP_START 35 |
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| 279 | #define MMC_ERASE_GROUP_END 36 |
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| 280 | /* 37 -- reserved old command */ |
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| 281 | #define MMC_ERASE 38 |
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| 282 | #define MMC_ERASE_ERASE 0x00000000 |
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| 283 | #define MMC_ERASE_TRIM 0x00000001 |
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| 284 | #define MMC_ERASE_FULE 0x00000002 |
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| 285 | #define MMC_ERASE_DISCARD 0x00000003 |
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| 286 | #define MMC_ERASE_SECURE_ERASE 0x80000000 |
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| 287 | #define MMC_ERASE_SECURE_TRIM1 0x80000001 |
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| 288 | #define MMC_ERASE_SECURE_TRIM2 0x80008000 |
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| 289 | |
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| 290 | /* Class 9: I/O mode commands */ |
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| 291 | #define MMC_FAST_IO 39 |
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| 292 | #define MMC_GO_IRQ_STATE 40 |
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| 293 | /* reserved: 41 */ |
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| 294 | |
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| 295 | /* Class 7: Lock card */ |
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| 296 | #define MMC_LOCK_UNLOCK 42 |
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| 297 | /* reserved: 43 */ |
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| 298 | /* reserved: 44 */ |
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| 299 | /* reserved: 45 */ |
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| 300 | /* reserved: 46 */ |
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| 301 | /* reserved: 47 */ |
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| 302 | /* reserved: 48 */ |
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| 303 | /* reserved: 49 */ |
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| 304 | /* reserved: 50 */ |
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| 305 | /* reserved: 51 */ |
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| 306 | /* reserved: 54 */ |
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| 307 | |
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| 308 | /* Class 8: Application specific commands */ |
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| 309 | #define MMC_APP_CMD 55 |
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| 310 | #define MMC_GEN_CMD 56 |
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| 311 | /* reserved: 57 */ |
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| 312 | /* reserved: 58 */ |
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| 313 | /* reserved: 59 */ |
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| 314 | /* reserved for mfg: 60 */ |
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| 315 | /* reserved for mfg: 61 */ |
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| 316 | /* reserved for mfg: 62 */ |
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| 317 | /* reserved for mfg: 63 */ |
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| 318 | |
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| 319 | /* Class 9: I/O cards (sd) */ |
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| 320 | #define SD_IO_RW_DIRECT 52 |
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| 321 | /* CMD52 arguments */ |
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| 322 | #define SD_ARG_CMD52_READ (0 << 31) |
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| 323 | #define SD_ARG_CMD52_WRITE (1 << 31) |
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| 324 | #define SD_ARG_CMD52_FUNC_SHIFT 28 |
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| 325 | #define SD_ARG_CMD52_FUNC_MASK 0x7 |
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| 326 | #define SD_ARG_CMD52_EXCHANGE (1 << 27) |
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| 327 | #define SD_ARG_CMD52_REG_SHIFT 9 |
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| 328 | #define SD_ARG_CMD52_REG_MASK 0x1ffff |
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| 329 | #define SD_ARG_CMD52_DATA_SHIFT 0 |
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| 330 | #define SD_ARG_CMD52_DATA_MASK 0xff |
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| 331 | #define SD_R5_DATA(resp) ((resp)[0] & 0xff) |
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| 332 | |
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| 333 | #define SD_IO_RW_EXTENDED 53 |
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| 334 | /* CMD53 arguments */ |
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| 335 | #define SD_ARG_CMD53_READ (0 << 31) |
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| 336 | #define SD_ARG_CMD53_WRITE (1 << 31) |
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| 337 | #define SD_ARG_CMD53_FUNC_SHIFT 28 |
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| 338 | #define SD_ARG_CMD53_FUNC_MASK 0x7 |
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| 339 | #define SD_ARG_CMD53_BLOCK_MODE (1 << 27) |
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| 340 | #define SD_ARG_CMD53_INCREMENT (1 << 26) |
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| 341 | #define SD_ARG_CMD53_REG_SHIFT 9 |
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| 342 | #define SD_ARG_CMD53_REG_MASK 0x1ffff |
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| 343 | #define SD_ARG_CMD53_LENGTH_SHIFT 0 |
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| 344 | #define SD_ARG_CMD53_LENGTH_MASK 0x1ff |
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| 345 | #define SD_ARG_CMD53_LENGTH_MAX 64 /* XXX should be 511? */ |
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| 346 | |
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| 347 | /* Class 10: Switch function commands */ |
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| 348 | #define SD_SWITCH_FUNC 6 |
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| 349 | /* reserved: 34 */ |
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| 350 | /* reserved: 35 */ |
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| 351 | /* reserved: 36 */ |
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| 352 | /* reserved: 37 */ |
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| 353 | /* reserved: 50 */ |
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| 354 | /* reserved: 57 */ |
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| 355 | |
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| 356 | /* Application specific commands for SD */ |
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| 357 | #define ACMD_SET_BUS_WIDTH 6 |
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| 358 | #define ACMD_SD_STATUS 13 |
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| 359 | #define ACMD_SEND_NUM_WR_BLOCKS 22 |
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| 360 | #define ACMD_SET_WR_BLK_ERASE_COUNT 23 |
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| 361 | #define ACMD_SD_SEND_OP_COND 41 |
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| 362 | #define ACMD_SET_CLR_CARD_DETECT 42 |
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| 363 | #define ACMD_SEND_SCR 51 |
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| 364 | |
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| 365 | /* |
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| 366 | * EXT_CSD fields |
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| 367 | */ |
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| 368 | #define EXT_CSD_FLUSH_CACHE 32 /* W/E */ |
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| 369 | #define EXT_CSD_CACHE_CTRL 33 /* R/W/E */ |
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| 370 | #define EXT_CSD_EXT_PART_ATTR 52 /* R/W, 2 bytes */ |
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| 371 | #define EXT_CSD_ENH_START_ADDR 136 /* R/W, 4 bytes */ |
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| 372 | #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W, 3 bytes */ |
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| 373 | #define EXT_CSD_GP_SIZE_MULT 143 /* R/W, 12 bytes */ |
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| 374 | #define EXT_CSD_PART_SET 155 /* R/W */ |
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| 375 | #define EXT_CSD_PART_ATTR 156 /* R/W */ |
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| 376 | #define EXT_CSD_PART_SUPPORT 160 /* RO */ |
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| 377 | #define EXT_CSD_RPMB_MULT 168 /* RO */ |
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| 378 | #define EXT_CSD_BOOT_WP_STATUS 174 /* RO */ |
|---|
| 379 | #define EXT_CSD_ERASE_GRP_DEF 175 /* R/W */ |
|---|
| 380 | #define EXT_CSD_PART_CONFIG 179 /* R/W */ |
|---|
| 381 | #define EXT_CSD_BUS_WIDTH 183 /* R/W */ |
|---|
| 382 | #define EXT_CSD_STROBE_SUPPORT 184 /* RO */ |
|---|
| 383 | #define EXT_CSD_HS_TIMING 185 /* R/W */ |
|---|
| 384 | #define EXT_CSD_POWER_CLASS 187 /* R/W */ |
|---|
| 385 | #define EXT_CSD_CARD_TYPE 196 /* RO */ |
|---|
| 386 | #define EXT_CSD_DRIVER_STRENGTH 197 /* RO */ |
|---|
| 387 | #define EXT_CSD_REV 192 /* RO */ |
|---|
| 388 | #define EXT_CSD_PART_SWITCH_TO 199 /* RO */ |
|---|
| 389 | #define EXT_CSD_PWR_CL_52_195 200 /* RO */ |
|---|
| 390 | #define EXT_CSD_PWR_CL_26_195 201 /* RO */ |
|---|
| 391 | #define EXT_CSD_PWR_CL_52_360 202 /* RO */ |
|---|
| 392 | #define EXT_CSD_PWR_CL_26_360 203 /* RO */ |
|---|
| 393 | #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ |
|---|
| 394 | #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ |
|---|
| 395 | #define EXT_CSD_ERASE_TO_MULT 223 /* RO */ |
|---|
| 396 | #define EXT_CSD_ERASE_GRP_SIZE 224 /* RO */ |
|---|
| 397 | #define EXT_CSD_BOOT_SIZE_MULT 226 /* RO */ |
|---|
| 398 | #define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ |
|---|
| 399 | #define EXT_CSD_PWR_CL_200_195 236 /* RO */ |
|---|
| 400 | #define EXT_CSD_PWR_CL_200_360 237 /* RO */ |
|---|
| 401 | #define EXT_CSD_PWR_CL_52_195_DDR 238 /* RO */ |
|---|
| 402 | #define EXT_CSD_PWR_CL_52_360_DDR 239 /* RO */ |
|---|
| 403 | #define EXT_CSD_CACHE_FLUSH_POLICY 249 /* RO */ |
|---|
| 404 | #define EXT_CSD_GEN_CMD6_TIME 248 /* RO */ |
|---|
| 405 | #define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ |
|---|
| 406 | #define EXT_CSD_PWR_CL_200_360_DDR 253 /* RO */ |
|---|
| 407 | |
|---|
| 408 | /* |
|---|
| 409 | * EXT_CSD field definitions |
|---|
| 410 | */ |
|---|
| 411 | #define EXT_CSD_FLUSH_CACHE_FLUSH 0x01 |
|---|
| 412 | #define EXT_CSD_FLUSH_CACHE_BARRIER 0x02 |
|---|
| 413 | |
|---|
| 414 | #define EXT_CSD_CACHE_CTRL_CACHE_EN 0x01 |
|---|
| 415 | |
|---|
| 416 | #define EXT_CSD_EXT_PART_ATTR_DEFAULT 0x0 |
|---|
| 417 | #define EXT_CSD_EXT_PART_ATTR_SYSTEMCODE 0x1 |
|---|
| 418 | #define EXT_CSD_EXT_PART_ATTR_NPERSISTENT 0x2 |
|---|
| 419 | |
|---|
| 420 | #define EXT_CSD_PART_SET_COMPLETED 0x01 |
|---|
| 421 | |
|---|
| 422 | #define EXT_CSD_PART_ATTR_ENH_USR 0x01 |
|---|
| 423 | #define EXT_CSD_PART_ATTR_ENH_GP0 0x02 |
|---|
| 424 | #define EXT_CSD_PART_ATTR_ENH_GP1 0x04 |
|---|
| 425 | #define EXT_CSD_PART_ATTR_ENH_GP2 0x08 |
|---|
| 426 | #define EXT_CSD_PART_ATTR_ENH_GP3 0x10 |
|---|
| 427 | #define EXT_CSD_PART_ATTR_ENH_MASK 0x1f |
|---|
| 428 | |
|---|
| 429 | #define EXT_CSD_PART_SUPPORT_EN 0x01 |
|---|
| 430 | #define EXT_CSD_PART_SUPPORT_ENH_ATTR_EN 0x02 |
|---|
| 431 | #define EXT_CSD_PART_SUPPORT_EXT_ATTR_EN 0x04 |
|---|
| 432 | |
|---|
| 433 | #define EXT_CSD_BOOT_WP_STATUS_BOOT0_PWR 0x01 |
|---|
| 434 | #define EXT_CSD_BOOT_WP_STATUS_BOOT0_PERM 0x02 |
|---|
| 435 | #define EXT_CSD_BOOT_WP_STATUS_BOOT0_MASK 0x03 |
|---|
| 436 | #define EXT_CSD_BOOT_WP_STATUS_BOOT1_PWR 0x04 |
|---|
| 437 | #define EXT_CSD_BOOT_WP_STATUS_BOOT1_PERM 0x08 |
|---|
| 438 | #define EXT_CSD_BOOT_WP_STATUS_BOOT1_MASK 0x0c |
|---|
| 439 | |
|---|
| 440 | #define EXT_CSD_ERASE_GRP_DEF_EN 0x01 |
|---|
| 441 | |
|---|
| 442 | #define EXT_CSD_PART_CONFIG_ACC_DEFAULT 0x00 |
|---|
| 443 | #define EXT_CSD_PART_CONFIG_ACC_BOOT0 0x01 |
|---|
| 444 | #define EXT_CSD_PART_CONFIG_ACC_BOOT1 0x02 |
|---|
| 445 | #define EXT_CSD_PART_CONFIG_ACC_RPMB 0x03 |
|---|
| 446 | #define EXT_CSD_PART_CONFIG_ACC_GP0 0x04 |
|---|
| 447 | #define EXT_CSD_PART_CONFIG_ACC_GP1 0x05 |
|---|
| 448 | #define EXT_CSD_PART_CONFIG_ACC_GP2 0x06 |
|---|
| 449 | #define EXT_CSD_PART_CONFIG_ACC_GP3 0x07 |
|---|
| 450 | #define EXT_CSD_PART_CONFIG_ACC_MASK 0x07 |
|---|
| 451 | #define EXT_CSD_PART_CONFIG_BOOT0 0x08 |
|---|
| 452 | #define EXT_CSD_PART_CONFIG_BOOT1 0x10 |
|---|
| 453 | #define EXT_CSD_PART_CONFIG_BOOT_USR 0x38 |
|---|
| 454 | #define EXT_CSD_PART_CONFIG_BOOT_MASK 0x38 |
|---|
| 455 | #define EXT_CSD_PART_CONFIG_BOOT_ACK 0x40 |
|---|
| 456 | |
|---|
| 457 | #define EXT_CSD_CMD_SET_NORMAL 1 |
|---|
| 458 | #define EXT_CSD_CMD_SET_SECURE 2 |
|---|
| 459 | #define EXT_CSD_CMD_SET_CPSECURE 4 |
|---|
| 460 | |
|---|
| 461 | #define EXT_CSD_HS_TIMING_BC 0 |
|---|
| 462 | #define EXT_CSD_HS_TIMING_HS 1 |
|---|
| 463 | #define EXT_CSD_HS_TIMING_HS200 2 |
|---|
| 464 | #define EXT_CSD_HS_TIMING_HS400 3 |
|---|
| 465 | #define EXT_CSD_HS_TIMING_DRV_STR_SHIFT 4 |
|---|
| 466 | |
|---|
| 467 | #define EXT_CSD_POWER_CLASS_8BIT_MASK 0xf0 |
|---|
| 468 | #define EXT_CSD_POWER_CLASS_8BIT_SHIFT 4 |
|---|
| 469 | #define EXT_CSD_POWER_CLASS_4BIT_MASK 0x0f |
|---|
| 470 | #define EXT_CSD_POWER_CLASS_4BIT_SHIFT 0 |
|---|
| 471 | |
|---|
| 472 | #define EXT_CSD_CARD_TYPE_HS_26 0x0001 |
|---|
| 473 | #define EXT_CSD_CARD_TYPE_HS_52 0x0002 |
|---|
| 474 | #define EXT_CSD_CARD_TYPE_DDR_52_1_8V 0x0004 |
|---|
| 475 | #define EXT_CSD_CARD_TYPE_DDR_52_1_2V 0x0008 |
|---|
| 476 | #define EXT_CSD_CARD_TYPE_HS200_1_8V 0x0010 |
|---|
| 477 | #define EXT_CSD_CARD_TYPE_HS200_1_2V 0x0020 |
|---|
| 478 | #define EXT_CSD_CARD_TYPE_HS400_1_8V 0x0040 |
|---|
| 479 | #define EXT_CSD_CARD_TYPE_HS400_1_2V 0x0080 |
|---|
| 480 | |
|---|
| 481 | #define EXT_CSD_BUS_WIDTH_1 0 |
|---|
| 482 | #define EXT_CSD_BUS_WIDTH_4 1 |
|---|
| 483 | #define EXT_CSD_BUS_WIDTH_8 2 |
|---|
| 484 | #define EXT_CSD_BUS_WIDTH_4_DDR 5 |
|---|
| 485 | #define EXT_CSD_BUS_WIDTH_8_DDR 6 |
|---|
| 486 | #define EXT_CSD_BUS_WIDTH_ES 0x80 |
|---|
| 487 | |
|---|
| 488 | #define EXT_CSD_STROBE_SUPPORT_EN 0x01 |
|---|
| 489 | |
|---|
| 490 | #define EXT_CSD_SEC_FEATURE_SUPPORT_ER_EN 0x01 |
|---|
| 491 | #define EXT_CSD_SEC_FEATURE_SUPPORT_BD_BLK_EN 0x04 |
|---|
| 492 | #define EXT_CSD_SEC_FEATURE_SUPPORT_GB_CL_EN 0x10 |
|---|
| 493 | #define EXT_CSD_SEC_FEATURE_SUPPORT_SANITIZE 0x40 |
|---|
| 494 | |
|---|
| 495 | #define EXT_CSD_CACHE_FLUSH_POLICY_FIFO 0x01 |
|---|
| 496 | |
|---|
| 497 | /* |
|---|
| 498 | * Vendor specific EXT_CSD fields |
|---|
| 499 | */ |
|---|
| 500 | /* SanDisk iNAND */ |
|---|
| 501 | #define EXT_CSD_INAND_CMD38 113 |
|---|
| 502 | #define EXT_CSD_INAND_CMD38_ERASE 0x00 |
|---|
| 503 | #define EXT_CSD_INAND_CMD38_TRIM 0x01 |
|---|
| 504 | #define EXT_CSD_INAND_CMD38_SECURE_ERASE 0x80 |
|---|
| 505 | #define EXT_CSD_INAND_CMD38_SECURE_TRIM1 0x81 |
|---|
| 506 | #define EXT_CSD_INAND_CMD38_SECURE_TRIM2 0x82 |
|---|
| 507 | |
|---|
| 508 | #define MMC_TYPE_HS_26_MAX 26000000 |
|---|
| 509 | #define MMC_TYPE_HS_52_MAX 52000000 |
|---|
| 510 | #define MMC_TYPE_DDR52_MAX 52000000 |
|---|
| 511 | #define MMC_TYPE_HS200_HS400ES_MAX 200000000 |
|---|
| 512 | |
|---|
| 513 | /* |
|---|
| 514 | * SD bus widths |
|---|
| 515 | */ |
|---|
| 516 | #define SD_BUS_WIDTH_1 0 |
|---|
| 517 | #define SD_BUS_WIDTH_4 2 |
|---|
| 518 | |
|---|
| 519 | /* |
|---|
| 520 | * SD Switch |
|---|
| 521 | */ |
|---|
| 522 | #define SD_SWITCH_MODE_CHECK 0 |
|---|
| 523 | #define SD_SWITCH_MODE_SET 1 |
|---|
| 524 | #define SD_SWITCH_GROUP1 0 |
|---|
| 525 | #define SD_SWITCH_NORMAL_MODE 0 |
|---|
| 526 | #define SD_SWITCH_HS_MODE 1 |
|---|
| 527 | #define SD_SWITCH_SDR50_MODE 2 |
|---|
| 528 | #define SD_SWITCH_SDR104_MODE 3 |
|---|
| 529 | #define SD_SWITCH_DDR50 4 |
|---|
| 530 | #define SD_SWITCH_NOCHANGE 0xF |
|---|
| 531 | |
|---|
| 532 | #define SD_CLR_CARD_DETECT 0 |
|---|
| 533 | #define SD_SET_CARD_DETECT 1 |
|---|
| 534 | |
|---|
| 535 | #define SD_HS_MAX 50000000 |
|---|
| 536 | #define SD_DDR50_MAX 50000000 |
|---|
| 537 | #define SD_SDR12_MAX 25000000 |
|---|
| 538 | #define SD_SDR25_MAX 50000000 |
|---|
| 539 | #define SD_SDR50_MAX 100000000 |
|---|
| 540 | #define SD_SDR104_MAX 208000000 |
|---|
| 541 | |
|---|
| 542 | /* Specifications require 400 kHz max. during ID phase. */ |
|---|
| 543 | #define SD_MMC_CARD_ID_FREQUENCY 400000 |
|---|
| 544 | |
|---|
| 545 | /* |
|---|
| 546 | * SDIO Direct & Extended I/O |
|---|
| 547 | */ |
|---|
| 548 | #define SD_IO_RW_WR (1u << 31) |
|---|
| 549 | #define SD_IO_RW_FUNC(x) (((x) & 0x7) << 28) |
|---|
| 550 | #define SD_IO_RW_RAW (1u << 27) |
|---|
| 551 | #define SD_IO_RW_INCR (1u << 26) |
|---|
| 552 | #define SD_IO_RW_ADR(x) (((x) & 0x1FFFF) << 9) |
|---|
| 553 | #define SD_IO_RW_DAT(x) (((x) & 0xFF) << 0) |
|---|
| 554 | #define SD_IO_RW_LEN(x) (((x) & 0xFF) << 0) |
|---|
| 555 | |
|---|
| 556 | #define SD_IOE_RW_LEN(x) (((x) & 0x1FF) << 0) |
|---|
| 557 | #define SD_IOE_RW_BLK (1u << 27) |
|---|
| 558 | |
|---|
| 559 | /* Card Common Control Registers (CCCR) */ |
|---|
| 560 | #define SD_IO_CCCR_START 0x00000 |
|---|
| 561 | #define SD_IO_CCCR_SIZE 0x100 |
|---|
| 562 | #define SD_IO_CCCR_FN_ENABLE 0x02 |
|---|
| 563 | #define SD_IO_CCCR_FN_READY 0x03 |
|---|
| 564 | #define SD_IO_CCCR_INT_ENABLE 0x04 |
|---|
| 565 | #define SD_IO_CCCR_INT_PENDING 0x05 |
|---|
| 566 | #define SD_IO_CCCR_CTL 0x06 |
|---|
| 567 | #define CCCR_CTL_RES (1 << 3) |
|---|
| 568 | #define SD_IO_CCCR_BUS_WIDTH 0x07 |
|---|
| 569 | #define CCCR_BUS_WIDTH_4 (1 << 1) |
|---|
| 570 | #define CCCR_BUS_WIDTH_1 (1 << 0) |
|---|
| 571 | #define SD_IO_CCCR_CARDCAP 0x08 |
|---|
| 572 | #define SD_IO_CCCR_CISPTR 0x09 /* XXX 9-10, 10-11, or 9-12 */ |
|---|
| 573 | |
|---|
| 574 | /* Function Basic Registers (FBR) */ |
|---|
| 575 | #define SD_IO_FBR_START 0x00100 |
|---|
| 576 | #define SD_IO_FBR_SIZE 0x00700 |
|---|
| 577 | |
|---|
| 578 | /* Card Information Structure (CIS) */ |
|---|
| 579 | #define SD_IO_CIS_START 0x01000 |
|---|
| 580 | #define SD_IO_CIS_SIZE 0x17000 |
|---|
| 581 | |
|---|
| 582 | /* CIS tuple codes (based on PC Card 16) */ |
|---|
| 583 | #define SD_IO_CISTPL_VERS_1 0x15 |
|---|
| 584 | #define SD_IO_CISTPL_MANFID 0x20 |
|---|
| 585 | #define SD_IO_CISTPL_FUNCID 0x21 |
|---|
| 586 | #define SD_IO_CISTPL_FUNCE 0x22 |
|---|
| 587 | #define SD_IO_CISTPL_END 0xff |
|---|
| 588 | |
|---|
| 589 | /* CISTPL_FUNCID codes */ |
|---|
| 590 | /* OpenBSD incorrectly defines 0x0c as FUNCTION_WLAN */ |
|---|
| 591 | /* #define SDMMC_FUNCTION_WLAN 0x0c */ |
|---|
| 592 | |
|---|
| 593 | /* OCR bits */ |
|---|
| 594 | |
|---|
| 595 | /* |
|---|
| 596 | * in SD 2.0 spec, bits 8-14 are now marked reserved |
|---|
| 597 | * Low voltage in SD2.0 spec is bit 7, TBD voltage |
|---|
| 598 | * Low voltage in MC 3.31 spec is bit 7, 1.65-1.95V |
|---|
| 599 | * Specs prior to MMC 3.31 defined bits 0-7 as voltages down to 1.5V. |
|---|
| 600 | * 3.31 redefined them to be reserved and also said that cards had to |
|---|
| 601 | * support the 2.7-3.6V and fixed the OCR to be 0xfff8000 for high voltage |
|---|
| 602 | * cards. MMC 4.0 says that a dual voltage card responds with 0xfff8080. |
|---|
| 603 | * Looks like the fine-grained control of the voltage tolerance ranges |
|---|
| 604 | * was abandoned. |
|---|
| 605 | * |
|---|
| 606 | * The MMC_OCR_CCS appears to be valid for only SD cards. |
|---|
| 607 | */ |
|---|
| 608 | #define MMC_OCR_VOLTAGE 0x3fffffffU /* Vdd Voltage mask */ |
|---|
| 609 | #define MMC_OCR_LOW_VOLTAGE (1u << 7) /* Low Voltage Range -- tbd */ |
|---|
| 610 | #define MMC_OCR_MIN_VOLTAGE_SHIFT 7 |
|---|
| 611 | #define MMC_OCR_200_210 (1U << 8) /* Vdd voltage 2.00 ~ 2.10 */ |
|---|
| 612 | #define MMC_OCR_210_220 (1U << 9) /* Vdd voltage 2.10 ~ 2.20 */ |
|---|
| 613 | #define MMC_OCR_220_230 (1U << 10) /* Vdd voltage 2.20 ~ 2.30 */ |
|---|
| 614 | #define MMC_OCR_230_240 (1U << 11) /* Vdd voltage 2.30 ~ 2.40 */ |
|---|
| 615 | #define MMC_OCR_240_250 (1U << 12) /* Vdd voltage 2.40 ~ 2.50 */ |
|---|
| 616 | #define MMC_OCR_250_260 (1U << 13) /* Vdd voltage 2.50 ~ 2.60 */ |
|---|
| 617 | #define MMC_OCR_260_270 (1U << 14) /* Vdd voltage 2.60 ~ 2.70 */ |
|---|
| 618 | #define MMC_OCR_270_280 (1U << 15) /* Vdd voltage 2.70 ~ 2.80 */ |
|---|
| 619 | #define MMC_OCR_280_290 (1U << 16) /* Vdd voltage 2.80 ~ 2.90 */ |
|---|
| 620 | #define MMC_OCR_290_300 (1U << 17) /* Vdd voltage 2.90 ~ 3.00 */ |
|---|
| 621 | #define MMC_OCR_300_310 (1U << 18) /* Vdd voltage 3.00 ~ 3.10 */ |
|---|
| 622 | #define MMC_OCR_310_320 (1U << 19) /* Vdd voltage 3.10 ~ 3.20 */ |
|---|
| 623 | #define MMC_OCR_320_330 (1U << 20) /* Vdd voltage 3.20 ~ 3.30 */ |
|---|
| 624 | #define MMC_OCR_330_340 (1U << 21) /* Vdd voltage 3.30 ~ 3.40 */ |
|---|
| 625 | #define MMC_OCR_340_350 (1U << 22) /* Vdd voltage 3.40 ~ 3.50 */ |
|---|
| 626 | #define MMC_OCR_350_360 (1U << 23) /* Vdd voltage 3.50 ~ 3.60 */ |
|---|
| 627 | #define MMC_OCR_MAX_VOLTAGE_SHIFT 23 |
|---|
| 628 | #define MMC_OCR_S18R (1U << 24) /* Switching to 1.8 V requested (SD) */ |
|---|
| 629 | #define MMC_OCR_S18A MMC_OCR_S18R /* Switching to 1.8 V accepted (SD) */ |
|---|
| 630 | #define MMC_OCR_XPC (1U << 28) /* SDXC Power Control */ |
|---|
| 631 | #define MMC_OCR_ACCESS_MODE_BYTE (0U << 29) /* Access Mode Byte (MMC) */ |
|---|
| 632 | #define MMC_OCR_ACCESS_MODE_SECT (1U << 29) /* Access Mode Sector (MMC) */ |
|---|
| 633 | #define MMC_OCR_ACCESS_MODE_MASK (3U << 29) |
|---|
| 634 | #define MMC_OCR_CCS (1u << 30) /* Card Capacity status (SD vs SDHC) */ |
|---|
| 635 | #define MMC_OCR_CARD_BUSY (1U << 31) /* Card Power up status */ |
|---|
| 636 | |
|---|
| 637 | /* CSD -- decoded structure */ |
|---|
| 638 | struct mmc_cid { |
|---|
| 639 | uint32_t mid; |
|---|
| 640 | char pnm[8]; |
|---|
| 641 | uint32_t psn; |
|---|
| 642 | uint16_t oid; |
|---|
| 643 | uint16_t mdt_year; |
|---|
| 644 | uint8_t mdt_month; |
|---|
| 645 | uint8_t prv; |
|---|
| 646 | uint8_t fwrev; |
|---|
| 647 | }; |
|---|
| 648 | |
|---|
| 649 | struct mmc_csd { |
|---|
| 650 | uint8_t csd_structure; |
|---|
| 651 | uint8_t spec_vers; |
|---|
| 652 | uint16_t ccc; |
|---|
| 653 | uint16_t tacc; |
|---|
| 654 | uint32_t nsac; |
|---|
| 655 | uint32_t r2w_factor; |
|---|
| 656 | uint32_t tran_speed; |
|---|
| 657 | uint32_t read_bl_len; |
|---|
| 658 | uint32_t write_bl_len; |
|---|
| 659 | uint32_t vdd_r_curr_min; |
|---|
| 660 | uint32_t vdd_r_curr_max; |
|---|
| 661 | uint32_t vdd_w_curr_min; |
|---|
| 662 | uint32_t vdd_w_curr_max; |
|---|
| 663 | uint32_t wp_grp_size; |
|---|
| 664 | uint32_t erase_sector; |
|---|
| 665 | uint64_t capacity; |
|---|
| 666 | unsigned int read_bl_partial:1, |
|---|
| 667 | read_blk_misalign:1, |
|---|
| 668 | write_bl_partial:1, |
|---|
| 669 | write_blk_misalign:1, |
|---|
| 670 | dsr_imp:1, |
|---|
| 671 | erase_blk_en:1, |
|---|
| 672 | wp_grp_enable:1; |
|---|
| 673 | }; |
|---|
| 674 | |
|---|
| 675 | struct mmc_scr { |
|---|
| 676 | unsigned char sda_vsn; |
|---|
| 677 | unsigned char bus_widths; |
|---|
| 678 | #define SD_SCR_BUS_WIDTH_1 (1 << 0) |
|---|
| 679 | #define SD_SCR_BUS_WIDTH_4 (1 << 2) |
|---|
| 680 | }; |
|---|
| 681 | |
|---|
| 682 | struct mmc_sd_status { |
|---|
| 683 | uint8_t bus_width; |
|---|
| 684 | uint8_t secured_mode; |
|---|
| 685 | uint16_t card_type; |
|---|
| 686 | uint16_t prot_area; |
|---|
| 687 | uint8_t speed_class; |
|---|
| 688 | uint8_t perf_move; |
|---|
| 689 | uint8_t au_size; |
|---|
| 690 | uint16_t erase_size; |
|---|
| 691 | uint8_t erase_timeout; |
|---|
| 692 | uint8_t erase_offset; |
|---|
| 693 | }; |
|---|
| 694 | |
|---|
| 695 | struct mmc_quirk { |
|---|
| 696 | uint32_t mid; |
|---|
| 697 | #define MMC_QUIRK_MID_ANY ((uint32_t)-1) |
|---|
| 698 | uint16_t oid; |
|---|
| 699 | #define MMC_QUIRK_OID_ANY ((uint16_t)-1) |
|---|
| 700 | const char *pnm; |
|---|
| 701 | uint32_t quirks; |
|---|
| 702 | #define MMC_QUIRK_INAND_CMD38 0x0001 |
|---|
| 703 | #define MMC_QUIRK_BROKEN_TRIM 0x0002 |
|---|
| 704 | }; |
|---|
| 705 | |
|---|
| 706 | #define MMC_QUIRKS_FMT "\020" "\001INAND_CMD38" "\002BROKEN_TRIM" |
|---|
| 707 | |
|---|
| 708 | /* |
|---|
| 709 | * Various MMC/SD constants |
|---|
| 710 | */ |
|---|
| 711 | #define MMC_BOOT_RPMB_BLOCK_SIZE (128 * 1024) |
|---|
| 712 | |
|---|
| 713 | #define MMC_EXTCSD_SIZE 512 |
|---|
| 714 | |
|---|
| 715 | #define MMC_PART_GP_MAX 4 |
|---|
| 716 | #define MMC_PART_MAX 8 |
|---|
| 717 | |
|---|
| 718 | #define MMC_TUNING_MAX 64 /* Maximum tuning iterations */ |
|---|
| 719 | #define MMC_TUNING_LEN 64 /* Size of tuning data */ |
|---|
| 720 | #define MMC_TUNING_LEN_HS200 128 /* Size of tuning data in HS200 mode */ |
|---|
| 721 | |
|---|
| 722 | /* |
|---|
| 723 | * Older versions of the MMC standard had a variable sector size. However, |
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| 724 | * I've been able to find no old MMC or SD cards that have a non 512 |
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| 725 | * byte sector size anywhere, so we assume that such cards are very rare |
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| 726 | * and only note their existence in passing here... |
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| 727 | */ |
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| 728 | #define MMC_SECTOR_SIZE 512 |
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| 729 | |
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| 730 | #endif /* DEV_MMCREG_H */ |
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