1 | /*- |
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2 | * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * 1. Redistributions of source code must retain the above copyright |
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9 | * notice, this list of conditions and the following disclaimer. |
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10 | * 2. Redistributions in binary form must reproduce the above copyright |
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11 | * notice, this list of conditions and the following disclaimer in the |
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12 | * documentation and/or other materials provided with the distribution. |
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13 | * |
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14 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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16 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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17 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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18 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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19 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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20 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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21 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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22 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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23 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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24 | * SUCH DAMAGE. |
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25 | * |
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26 | */ |
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27 | |
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28 | #ifndef IF_FFECREG_H |
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29 | #define IF_FFECREG_H |
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30 | |
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31 | #include <sys/cdefs.h> |
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32 | __FBSDID("$FreeBSD$"); |
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33 | |
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34 | /* |
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35 | * Hardware defines for Freescale Fast Ethernet Controller. |
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36 | */ |
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37 | |
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38 | /* |
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39 | * MAC registers. |
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40 | */ |
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41 | #define FEC_IER_REG 0x0004 |
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42 | #define FEC_IEM_REG 0x0008 |
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43 | #define FEC_IER_HBERR (1U << 31) |
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44 | #define FEC_IER_BABR (1 << 30) |
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45 | #define FEC_IER_BABT (1 << 29) |
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46 | #define FEC_IER_GRA (1 << 28) |
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47 | #define FEC_IER_TXF (1 << 27) |
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48 | #define FEC_IER_TXB (1 << 26) |
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49 | #define FEC_IER_RXF (1 << 25) |
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50 | #define FEC_IER_RXB (1 << 24) |
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51 | #define FEC_IER_MII (1 << 23) |
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52 | #define FEC_IER_EBERR (1 << 22) |
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53 | #define FEC_IER_LC (1 << 21) |
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54 | #define FEC_IER_RL (1 << 20) |
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55 | #define FEC_IER_UN (1 << 19) |
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56 | #define FEC_IER_PLR (1 << 18) |
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57 | #define FEC_IER_WAKEUP (1 << 17) |
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58 | #define FEC_IER_AVAIL (1 << 16) |
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59 | #define FEC_IER_TIMER (1 << 15) |
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60 | |
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61 | #define FEC_RDAR_REG 0x0010 |
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62 | #define FEC_RDAR_RDAR (1 << 24) |
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63 | |
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64 | #define FEC_TDAR_REG 0x0014 |
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65 | #define FEC_TDAR_TDAR (1 << 24) |
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66 | |
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67 | #define FEC_ECR_REG 0x0024 |
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68 | #define FEC_ECR_DBSWP (1 << 8) |
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69 | #define FEC_ECR_STOPEN (1 << 7) |
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70 | #define FEC_ECR_DBGEN (1 << 6) |
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71 | #define FEC_ECR_SPEED (1 << 5) |
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72 | #define FEC_ECR_EN1588 (1 << 4) |
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73 | #define FEC_ECR_SLEEP (1 << 3) |
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74 | #define FEC_ECR_MAGICEN (1 << 2) |
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75 | #define FEC_ECR_ETHEREN (1 << 1) |
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76 | #define FEC_ECR_RESET (1 << 0) |
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77 | |
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78 | #define FEC_MMFR_REG 0x0040 |
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79 | #define FEC_MMFR_ST_SHIFT 30 |
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80 | #define FEC_MMFR_ST_VALUE (0x01 << FEC_MMFR_ST_SHIFT) |
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81 | #define FEC_MMFR_OP_SHIFT 28 |
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82 | #define FEC_MMFR_OP_WRITE (0x01 << FEC_MMFR_OP_SHIFT) |
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83 | #define FEC_MMFR_OP_READ (0x02 << FEC_MMFR_OP_SHIFT) |
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84 | #define FEC_MMFR_PA_SHIFT 23 |
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85 | #define FEC_MMFR_PA_MASK (0x1f << FEC_MMFR_PA_SHIFT) |
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86 | #define FEC_MMFR_RA_SHIFT 18 |
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87 | #define FEC_MMFR_RA_MASK (0x1f << FEC_MMFR_RA_SHIFT) |
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88 | #define FEC_MMFR_TA_SHIFT 16 |
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89 | #define FEC_MMFR_TA_VALUE (0x02 << FEC_MMFR_TA_SHIFT) |
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90 | #define FEC_MMFR_DATA_SHIFT 0 |
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91 | #define FEC_MMFR_DATA_MASK (0xffff << FEC_MMFR_DATA_SHIFT) |
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92 | |
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93 | #define FEC_MSCR_REG 0x0044 |
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94 | #define FEC_MSCR_HOLDTIME_SHIFT 8 |
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95 | #define FEC_MSCR_HOLDTIME_MASK (0x07 << FEC_MSCR_HOLDTIME_SHIFT) |
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96 | #define FEC_MSCR_DIS_PRE (1 << 7) |
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97 | #define FEC_MSCR_MII_SPEED_SHIFT 1 |
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98 | #define FEC_MSCR_MII_SPEED_MASk (0x3f << FEC_MSCR_MII_SPEED_SHIFT) |
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99 | |
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100 | #define FEC_MIBC_REG 0x0064 |
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101 | #define FEC_MIBC_DIS (1U << 31) |
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102 | #define FEC_MIBC_IDLE (1 << 30) |
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103 | #define FEC_MIBC_CLEAR (1 << 29) /* imx6 only */ |
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104 | |
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105 | #define FEC_RCR_REG 0x0084 |
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106 | #define FEC_RCR_GRS (1U << 31) |
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107 | #define FEC_RCR_NLC (1 << 30) |
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108 | #define FEC_RCR_MAX_FL_SHIFT 16 |
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109 | #define FEC_RCR_MAX_FL_MASK (0x3fff << FEC_RCR_MAX_FL_SHIFT) |
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110 | #define FEC_RCR_CFEN (1 << 15) |
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111 | #define FEC_RCR_CRCFWD (1 << 14) |
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112 | #define FEC_RCR_PAUFWD (1 << 13) |
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113 | #define FEC_RCR_PADEN (1 << 12) |
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114 | #define FEC_RCR_RMII_10T (1 << 9) |
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115 | #define FEC_RCR_RMII_MODE (1 << 8) |
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116 | #define FEC_RCR_RGMII_EN (1 << 6) |
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117 | #define FEC_RCR_FCE (1 << 5) |
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118 | #define FEC_RCR_BC_REJ (1 << 4) |
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119 | #define FEC_RCR_PROM (1 << 3) |
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120 | #define FEC_RCR_MII_MODE (1 << 2) |
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121 | #define FEC_RCR_DRT (1 << 1) |
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122 | #define FEC_RCR_LOOP (1 << 0) |
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123 | |
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124 | #define FEC_TCR_REG 0x00c4 |
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125 | #define FEC_TCR_ADDINS (1 << 9) |
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126 | #define FEC_TCR_ADDSEL_SHIFT 5 |
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127 | #define FEC_TCR_ADDSEL_MASK (0x07 << FEC_TCR_ADDSEL_SHIFT) |
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128 | #define FEC_TCR_RFC_PAUSE (1 << 4) |
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129 | #define FEC_TCR_TFC_PAUSE (1 << 3) |
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130 | #define FEC_TCR_FDEN (1 << 2) |
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131 | #define FEC_TCR_GTS (1 << 0) |
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132 | |
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133 | #define FEC_PALR_REG 0x00e4 |
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134 | #define FEC_PALR_PADDR1_SHIFT 0 |
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135 | #define FEC_PALR_PADDR1_MASK (0xffffffff << FEC_PALR_PADDR1_SHIFT) |
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136 | |
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137 | #define FEC_PAUR_REG 0x00e8 |
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138 | #define FEC_PAUR_PADDR2_SHIFT 16 |
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139 | #define FEC_PAUR_PADDR2_MASK (0xffff << FEC_PAUR_PADDR2_SHIFT) |
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140 | #define FEC_PAUR_TYPE_VALUE (0x8808) |
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141 | |
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142 | #define FEC_OPD_REG 0x00ec |
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143 | #define FEC_OPD_PAUSE_DUR_SHIFT 0 |
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144 | #define FEC_OPD_PAUSE_DUR_MASK (0xffff << FEC_OPD_PAUSE_DUR_SHIFT) |
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145 | |
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146 | #define FEC_TXIC0_REG 0x00f0 |
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147 | #define FEC_TXIC1_REG 0x00f4 |
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148 | #define FEC_TXIC2_REG 0x00f8 |
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149 | #define FEC_RXIC0_REG 0x0100 |
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150 | #define FEC_RXIC1_REG 0x0104 |
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151 | #define FEC_RXIC2_REG 0x0108 |
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152 | #define FEC_IC_ICEN (1 << 31) |
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153 | #define FEC_IC_ICCS (1 << 30) |
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154 | #define FEC_IC_ICFT(x) (((x) & 0xff) << 20) |
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155 | #define FEC_IC_ICTT(x) ((x) & 0xffff) |
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156 | |
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157 | #define FEC_IAUR_REG 0x0118 |
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158 | #define FEC_IALR_REG 0x011c |
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159 | |
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160 | #define FEC_GAUR_REG 0x0120 |
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161 | #define FEC_GALR_REG 0x0124 |
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162 | |
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163 | #define FEC_TFWR_REG 0x0144 |
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164 | #define FEC_TFWR_STRFWD (1 << 8) |
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165 | #define FEC_TFWR_TWFR_SHIFT 0 |
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166 | #define FEC_TFWR_TWFR_MASK (0x3f << FEC_TFWR_TWFR_SHIFT) |
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167 | #define FEC_TFWR_TWFR_128BYTE (0x02 << FEC_TFWR_TWFR_SHIFT) |
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168 | |
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169 | #define FEC_RDSR_REG 0x0180 |
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170 | |
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171 | #define FEC_TDSR_REG 0x0184 |
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172 | |
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173 | #define FEC_MRBR_REG 0x0188 |
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174 | #define FEC_MRBR_R_BUF_SIZE_SHIFT 0 |
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175 | #define FEC_MRBR_R_BUF_SIZE_MASK (0x3fff << FEC_MRBR_R_BUF_SIZE_SHIFT) |
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176 | |
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177 | #define FEC_RSFL_REG 0x0190 |
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178 | #define FEC_RSEM_REG 0x0194 |
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179 | #define FEC_RAEM_REG 0x0198 |
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180 | #define FEC_RAFL_REG 0x019c |
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181 | #define FEC_TSEM_REG 0x01a0 |
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182 | #define FEC_TAEM_REG 0x01a4 |
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183 | #define FEC_TAFL_REG 0x01a8 |
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184 | #define FEC_TIPG_REG 0x01ac |
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185 | #define FEC_FTRL_REG 0x01b0 |
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186 | |
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187 | #define FEC_TACC_REG 0x01c0 |
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188 | #define FEC_TACC_PROCHK (1 << 4) |
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189 | #define FEC_TACC_IPCHK (1 << 3) |
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190 | #define FEC_TACC_SHIFT16 (1 << 0) |
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191 | |
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192 | #define FEC_RACC_REG 0x01c4 |
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193 | #define FEC_RACC_SHIFT16 (1 << 7) |
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194 | #define FEC_RACC_LINEDIS (1 << 6) |
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195 | #define FEC_RACC_PRODIS (1 << 2) |
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196 | #define FEC_RACC_IPDIS (1 << 1) |
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197 | #define FEC_RACC_PADREM (1 << 0) |
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198 | |
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199 | /* |
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200 | * IEEE-1588 timer registers |
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201 | */ |
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202 | |
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203 | #define FEC_ATCR_REG 0x0400 |
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204 | #define FEC_ATCR_SLAVE (1u << 13) |
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205 | #define FEC_ATCR_CAPTURE (1u << 11) |
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206 | #define FEC_ATCR_RESTART (1u << 9) |
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207 | #define FEC_ATCR_PINPER (1u << 7) |
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208 | #define FEC_ATCR_PEREN (1u << 4) |
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209 | #define FEC_ATCR_OFFRST (1u << 3) |
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210 | #define FEC_ATCR_OFFEN (1u << 2) |
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211 | #define FEC_ATCR_EN (1u << 0) |
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212 | |
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213 | #define FEC_ATVR_REG 0x0404 |
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214 | #define FEC_ATOFF_REG 0x0408 |
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215 | #define FEC_ATPER_REG 0x040c |
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216 | #define FEC_ATCOR_REG 0x0410 |
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217 | #define FEC_ATINC_REG 0x0414 |
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218 | #define FEC_ATSTMP_REG 0x0418 |
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219 | |
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220 | /* |
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221 | * Statistics registers |
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222 | */ |
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223 | #define FEC_RMON_T_DROP 0x200 |
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224 | #define FEC_RMON_T_PACKETS 0x204 |
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225 | #define FEC_RMON_T_BC_PKT 0x208 |
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226 | #define FEC_RMON_T_MC_PKT 0x20C |
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227 | #define FEC_RMON_T_CRC_ALIGN 0x210 |
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228 | #define FEC_RMON_T_UNDERSIZE 0x214 |
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229 | #define FEC_RMON_T_OVERSIZE 0x218 |
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230 | #define FEC_RMON_T_FRAG 0x21C |
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231 | #define FEC_RMON_T_JAB 0x220 |
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232 | #define FEC_RMON_T_COL 0x224 |
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233 | #define FEC_RMON_T_P64 0x228 |
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234 | #define FEC_RMON_T_P65TO127 0x22C |
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235 | #define FEC_RMON_T_P128TO255 0x230 |
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236 | #define FEC_RMON_T_P256TO511 0x234 |
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237 | #define FEC_RMON_T_P512TO1023 0x238 |
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238 | #define FEC_RMON_T_P1024TO2047 0x23C |
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239 | #define FEC_RMON_T_P_GTE2048 0x240 |
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240 | #define FEC_RMON_T_OCTECTS 0x240 |
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241 | #define FEC_IEEE_T_DROP 0x248 |
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242 | #define FEC_IEEE_T_FRAME_OK 0x24C |
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243 | #define FEC_IEEE_T_1COL 0x250 |
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244 | #define FEC_IEEE_T_MCOL 0x254 |
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245 | #define FEC_IEEE_T_DEF 0x258 |
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246 | #define FEC_IEEE_T_LCOL 0x25C |
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247 | #define FEC_IEEE_T_EXCOL 0x260 |
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248 | #define FEC_IEEE_T_MACERR 0x264 |
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249 | #define FEC_IEEE_T_CSERR 0x268 |
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250 | #define FEC_IEEE_T_SQE 0x26C |
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251 | #define FEC_IEEE_T_FDXFC 0x270 |
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252 | #define FEC_IEEE_T_OCTETS_OK 0x274 |
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253 | #define FEC_RMON_R_PACKETS 0x284 |
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254 | #define FEC_RMON_R_BC_PKT 0x288 |
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255 | #define FEC_RMON_R_MC_PKT 0x28C |
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256 | #define FEC_RMON_R_CRC_ALIGN 0x290 |
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257 | #define FEC_RMON_R_UNDERSIZE 0x294 |
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258 | #define FEC_RMON_R_OVERSIZE 0x298 |
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259 | #define FEC_RMON_R_FRAG 0x29C |
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260 | #define FEC_RMON_R_JAB 0x2A0 |
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261 | #define FEC_RMON_R_RESVD_0 0x2A4 |
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262 | #define FEC_RMON_R_P64 0x2A8 |
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263 | #define FEC_RMON_R_P65TO127 0x2AC |
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264 | #define FEC_RMON_R_P128TO255 0x2B0 |
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265 | #define FEC_RMON_R_P256TO511 0x2B4 |
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266 | #define FEC_RMON_R_P512TO1023 0x2B8 |
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267 | #define FEC_RMON_R_P1024TO2047 0x2BC |
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268 | #define FEC_RMON_R_P_GTE2048 0x2C0 |
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269 | #define FEC_RMON_R_OCTETS 0x2C4 |
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270 | #define FEC_IEEE_R_DROP 0x2C8 |
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271 | #define FEC_IEEE_R_FRAME_OK 0x2CC |
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272 | #define FEC_IEEE_R_CRC 0x2D0 |
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273 | #define FEC_IEEE_R_ALIGN 0x2D4 |
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274 | #define FEC_IEEE_R_MACERR 0x2D8 |
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275 | #define FEC_IEEE_R_FDXFC 0x2DC |
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276 | #define FEC_IEEE_R_OCTETS_OK 0x2E0 |
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277 | |
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278 | #define FEC_MIIGSK_CFGR 0x300 |
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279 | #define FEC_MIIGSK_CFGR_FRCONT (1 << 6) /* Freq: 0=50MHz, 1=5MHz */ |
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280 | #define FEC_MIIGSK_CFGR_LBMODE (1 << 4) /* loopback mode */ |
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281 | #define FEC_MIIGSK_CFGR_EMODE (1 << 3) /* echo mode */ |
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282 | #define FEC_MIIGSK_CFGR_IF_MODE_MASK (0x3 << 0) |
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283 | #define FEC_MIIGSK_CFGR_IF_MODE_MII (0 << 0) |
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284 | #define FEC_MIIGSK_CFGR_IF_MODE_RMII (1 << 0) |
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285 | |
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286 | #define FEC_MIIGSK_ENR 0x308 |
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287 | #define FEC_MIIGSK_ENR_READY (1 << 2) |
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288 | #define FEC_MIIGSK_ENR_EN (1 << 1) |
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289 | |
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290 | /* |
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291 | * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor |
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292 | * layout, but the bits in the flags field have different meanings. |
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293 | */ |
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294 | struct ffec_hwdesc |
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295 | { |
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296 | uint32_t flags_len; |
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297 | uint32_t buf_paddr; |
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298 | uint32_t flags2; |
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299 | uint32_t hlen_proto; |
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300 | uint32_t bdu; |
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301 | uint32_t ts; |
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302 | uint32_t res[2]; |
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303 | }; |
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304 | |
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305 | #define FEC_TXDESC_READY (1U << 31) |
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306 | #define FEC_TXDESC_T01 (1 << 30) |
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307 | #define FEC_TXDESC_WRAP (1 << 29) |
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308 | #define FEC_TXDESC_T02 (1 << 28) |
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309 | #define FEC_TXDESC_L (1 << 27) |
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310 | #define FEC_TXDESC_TC (1 << 26) |
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311 | #define FEC_TXDESC_ABC (1 << 25) |
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312 | #define FEC_TXDESC_LEN_MASK (0xffff) |
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313 | |
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314 | #define FEC_TXDESC_INT (1 << 30) |
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315 | #define FEC_TXDESC_TS (1 << 29) |
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316 | #define FEC_TXDESC_PINS (1 << 28) |
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317 | #define FEC_TXDESC_IINS (1 << 27) |
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318 | |
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319 | #define FEC_RXDESC_EMPTY (1U << 31) |
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320 | #define FEC_RXDESC_R01 (1 << 30) |
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321 | #define FEC_RXDESC_WRAP (1 << 29) |
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322 | #define FEC_RXDESC_R02 (1 << 28) |
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323 | #define FEC_RXDESC_L (1 << 27) |
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324 | #define FEC_RXDESC_M (1 << 24) |
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325 | #define FEC_RXDESC_BC (1 << 23) |
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326 | #define FEC_RXDESC_MC (1 << 22) |
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327 | #define FEC_RXDESC_LG (1 << 21) |
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328 | #define FEC_RXDESC_NO (1 << 20) |
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329 | #define FEC_RXDESC_CR (1 << 18) |
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330 | #define FEC_RXDESC_OV (1 << 17) |
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331 | #define FEC_RXDESC_TR (1 << 16) |
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332 | #define FEC_RXDESC_LEN_MASK (0xffff) |
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333 | |
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334 | #define FEC_RXDESC_INT (1 << 23) |
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335 | #define FEC_RXDESC_ICE (1 << 5) |
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336 | #define FEC_RXDESC_PCR (1 << 4) |
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337 | |
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338 | #define FEC_RXDESC_ERROR_BITS (FEC_RXDESC_LG | FEC_RXDESC_NO | \ |
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339 | FEC_RXDESC_OV | FEC_RXDESC_TR) |
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340 | |
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341 | /* |
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342 | * The hardware imposes alignment restrictions on various objects involved in |
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343 | * DMA transfers. These values are expressed in bytes (not bits). |
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344 | */ |
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345 | #define FEC_DESC_RING_ALIGN 64 |
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346 | |
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347 | #endif /* IF_FFECREG_H */ |
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